1 //===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the declaration of the MachineInstr class, which is the 11 // basic representation for all target dependent machine instructions used by 12 // the back end. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H 17 #define LLVM_CODEGEN_MACHINEINSTR_H 18 19 #include "llvm/ADT/DenseMapInfo.h" 20 #include "llvm/ADT/PointerSumType.h" 21 #include "llvm/ADT/ilist.h" 22 #include "llvm/ADT/ilist_node.h" 23 #include "llvm/ADT/iterator_range.h" 24 #include "llvm/Analysis/AliasAnalysis.h" 25 #include "llvm/CodeGen/MachineMemOperand.h" 26 #include "llvm/CodeGen/MachineOperand.h" 27 #include "llvm/CodeGen/TargetOpcodes.h" 28 #include "llvm/IR/DebugLoc.h" 29 #include "llvm/IR/InlineAsm.h" 30 #include "llvm/MC/MCInstrDesc.h" 31 #include "llvm/MC/MCSymbol.h" 32 #include "llvm/Support/ArrayRecycler.h" 33 #include "llvm/Support/TrailingObjects.h" 34 #include <algorithm> 35 #include <cassert> 36 #include <cstdint> 37 #include <utility> 38 39 namespace llvm { 40 41 template <typename T> class ArrayRef; 42 class DIExpression; 43 class DILocalVariable; 44 class MachineBasicBlock; 45 class MachineFunction; 46 class MachineMemOperand; 47 class MachineRegisterInfo; 48 class ModuleSlotTracker; 49 class raw_ostream; 50 template <typename T> class SmallVectorImpl; 51 class SmallBitVector; 52 class StringRef; 53 class TargetInstrInfo; 54 class TargetRegisterClass; 55 class TargetRegisterInfo; 56 57 //===----------------------------------------------------------------------===// 58 /// Representation of each machine instruction. 59 /// 60 /// This class isn't a POD type, but it must have a trivial destructor. When a 61 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated 62 /// without having their destructor called. 63 /// 64 class MachineInstr 65 : public ilist_node_with_parent<MachineInstr, MachineBasicBlock, 66 ilist_sentinel_tracking<true>> { 67 public: 68 using mmo_iterator = ArrayRef<MachineMemOperand *>::iterator; 69 70 /// Flags to specify different kinds of comments to output in 71 /// assembly code. These flags carry semantic information not 72 /// otherwise easily derivable from the IR text. 73 /// 74 enum CommentFlag { 75 ReloadReuse = 0x1, // higher bits are reserved for target dep comments. 76 NoSchedComment = 0x2, 77 TAsmComments = 0x4 // Target Asm comments should start from this value. 78 }; 79 80 enum MIFlag { 81 NoFlags = 0, 82 FrameSetup = 1 << 0, // Instruction is used as a part of 83 // function frame setup code. 84 FrameDestroy = 1 << 1, // Instruction is used as a part of 85 // function frame destruction code. 86 BundledPred = 1 << 2, // Instruction has bundled predecessors. 87 BundledSucc = 1 << 3, // Instruction has bundled successors. 88 FmNoNans = 1 << 4, // Instruction does not support Fast 89 // math nan values. 90 FmNoInfs = 1 << 5, // Instruction does not support Fast 91 // math infinity values. 92 FmNsz = 1 << 6, // Instruction is not required to retain 93 // signed zero values. 94 FmArcp = 1 << 7, // Instruction supports Fast math 95 // reciprocal approximations. 96 FmContract = 1 << 8, // Instruction supports Fast math 97 // contraction operations like fma. 98 FmAfn = 1 << 9, // Instruction may map to Fast math 99 // instrinsic approximation. 100 FmReassoc = 1 << 10, // Instruction supports Fast math 101 // reassociation of operand order. 102 NoUWrap = 1 << 11, // Instruction supports binary operator 103 // no unsigned wrap. 104 NoSWrap = 1 << 12, // Instruction supports binary operator 105 // no signed wrap. 106 IsExact = 1 << 13 // Instruction supports division is 107 // known to be exact. 108 }; 109 110 private: 111 const MCInstrDesc *MCID; // Instruction descriptor. 112 MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block. 113 114 // Operands are allocated by an ArrayRecycler. 115 MachineOperand *Operands = nullptr; // Pointer to the first operand. 116 unsigned NumOperands = 0; // Number of operands on instruction. 117 using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity; 118 OperandCapacity CapOperands; // Capacity of the Operands array. 119 120 uint16_t Flags = 0; // Various bits of additional 121 // information about machine 122 // instruction. 123 124 uint8_t AsmPrinterFlags = 0; // Various bits of information used by 125 // the AsmPrinter to emit helpful 126 // comments. This is *not* semantic 127 // information. Do not use this for 128 // anything other than to convey comment 129 // information to AsmPrinter. 130 131 /// Internal implementation detail class that provides out-of-line storage for 132 /// extra info used by the machine instruction when this info cannot be stored 133 /// in-line within the instruction itself. 134 /// 135 /// This has to be defined eagerly due to the implementation constraints of 136 /// `PointerSumType` where it is used. 137 class ExtraInfo final 138 : TrailingObjects<ExtraInfo, MachineMemOperand *, MCSymbol *> { 139 public: 140 static ExtraInfo *create(BumpPtrAllocator &Allocator, 141 ArrayRef<MachineMemOperand *> MMOs, 142 MCSymbol *PreInstrSymbol = nullptr, 143 MCSymbol *PostInstrSymbol = nullptr) { 144 bool HasPreInstrSymbol = PreInstrSymbol != nullptr; 145 bool HasPostInstrSymbol = PostInstrSymbol != nullptr; 146 auto *Result = new (Allocator.Allocate( 147 totalSizeToAlloc<MachineMemOperand *, MCSymbol *>( 148 MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol), 149 alignof(ExtraInfo))) 150 ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol); 151 152 // Copy the actual data into the trailing objects. 153 std::copy(MMOs.begin(), MMOs.end(), 154 Result->getTrailingObjects<MachineMemOperand *>()); 155 156 if (HasPreInstrSymbol) 157 Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol; 158 if (HasPostInstrSymbol) 159 Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] = 160 PostInstrSymbol; 161 162 return Result; 163 } 164 getMMOs()165 ArrayRef<MachineMemOperand *> getMMOs() const { 166 return makeArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs); 167 } 168 getPreInstrSymbol()169 MCSymbol *getPreInstrSymbol() const { 170 return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr; 171 } 172 getPostInstrSymbol()173 MCSymbol *getPostInstrSymbol() const { 174 return HasPostInstrSymbol 175 ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] 176 : nullptr; 177 } 178 179 private: 180 friend TrailingObjects; 181 182 // Description of the extra info, used to interpret the actual optional 183 // data appended. 184 // 185 // Note that this is not terribly space optimized. This leaves a great deal 186 // of flexibility to fit more in here later. 187 const int NumMMOs; 188 const bool HasPreInstrSymbol; 189 const bool HasPostInstrSymbol; 190 191 // Implement the `TrailingObjects` internal API. numTrailingObjects(OverloadToken<MachineMemOperand * >)192 size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const { 193 return NumMMOs; 194 } numTrailingObjects(OverloadToken<MCSymbol * >)195 size_t numTrailingObjects(OverloadToken<MCSymbol *>) const { 196 return HasPreInstrSymbol + HasPostInstrSymbol; 197 } 198 199 // Just a boring constructor to allow us to initialize the sizes. Always use 200 // the `create` routine above. ExtraInfo(int NumMMOs,bool HasPreInstrSymbol,bool HasPostInstrSymbol)201 ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol) 202 : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol), 203 HasPostInstrSymbol(HasPostInstrSymbol) {} 204 }; 205 206 /// Enumeration of the kinds of inline extra info available. It is important 207 /// that the `MachineMemOperand` inline kind has a tag value of zero to make 208 /// it accessible as an `ArrayRef`. 209 enum ExtraInfoInlineKinds { 210 EIIK_MMO = 0, 211 EIIK_PreInstrSymbol, 212 EIIK_PostInstrSymbol, 213 EIIK_OutOfLine 214 }; 215 216 // We store extra information about the instruction here. The common case is 217 // expected to be nothing or a single pointer (typically a MMO or a symbol). 218 // We work to optimize this common case by storing it inline here rather than 219 // requiring a separate allocation, but we fall back to an allocation when 220 // multiple pointers are needed. 221 PointerSumType<ExtraInfoInlineKinds, 222 PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>, 223 PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>, 224 PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>, 225 PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>> 226 Info; 227 228 DebugLoc debugLoc; // Source line information. 229 230 // Intrusive list support 231 friend struct ilist_traits<MachineInstr>; 232 friend struct ilist_callback_traits<MachineBasicBlock>; 233 void setParent(MachineBasicBlock *P) { Parent = P; } 234 235 /// This constructor creates a copy of the given 236 /// MachineInstr in the given MachineFunction. 237 MachineInstr(MachineFunction &, const MachineInstr &); 238 239 /// This constructor create a MachineInstr and add the implicit operands. 240 /// It reserves space for number of operands specified by 241 /// MCInstrDesc. An explicit DebugLoc is supplied. 242 MachineInstr(MachineFunction &, const MCInstrDesc &tid, DebugLoc dl, 243 bool NoImp = false); 244 245 // MachineInstrs are pool-allocated and owned by MachineFunction. 246 friend class MachineFunction; 247 248 public: 249 MachineInstr(const MachineInstr &) = delete; 250 MachineInstr &operator=(const MachineInstr &) = delete; 251 // Use MachineFunction::DeleteMachineInstr() instead. 252 ~MachineInstr() = delete; 253 254 const MachineBasicBlock* getParent() const { return Parent; } 255 MachineBasicBlock* getParent() { return Parent; } 256 257 /// Return the function that contains the basic block that this instruction 258 /// belongs to. 259 /// 260 /// Note: this is undefined behaviour if the instruction does not have a 261 /// parent. 262 const MachineFunction *getMF() const; 263 MachineFunction *getMF() { 264 return const_cast<MachineFunction *>( 265 static_cast<const MachineInstr *>(this)->getMF()); 266 } 267 268 /// Return the asm printer flags bitvector. 269 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; } 270 271 /// Clear the AsmPrinter bitvector. 272 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; } 273 274 /// Return whether an AsmPrinter flag is set. 275 bool getAsmPrinterFlag(CommentFlag Flag) const { 276 return AsmPrinterFlags & Flag; 277 } 278 279 /// Set a flag for the AsmPrinter. 280 void setAsmPrinterFlag(uint8_t Flag) { 281 AsmPrinterFlags |= Flag; 282 } 283 284 /// Clear specific AsmPrinter flags. 285 void clearAsmPrinterFlag(CommentFlag Flag) { 286 AsmPrinterFlags &= ~Flag; 287 } 288 289 /// Return the MI flags bitvector. 290 uint16_t getFlags() const { 291 return Flags; 292 } 293 294 /// Return whether an MI flag is set. 295 bool getFlag(MIFlag Flag) const { 296 return Flags & Flag; 297 } 298 299 /// Set a MI flag. 300 void setFlag(MIFlag Flag) { 301 Flags |= (uint16_t)Flag; 302 } 303 304 void setFlags(unsigned flags) { 305 // Filter out the automatically maintained flags. 306 unsigned Mask = BundledPred | BundledSucc; 307 Flags = (Flags & Mask) | (flags & ~Mask); 308 } 309 310 /// clearFlag - Clear a MI flag. 311 void clearFlag(MIFlag Flag) { 312 Flags &= ~((uint16_t)Flag); 313 } 314 315 /// Return true if MI is in a bundle (but not the first MI in a bundle). 316 /// 317 /// A bundle looks like this before it's finalized: 318 /// ---------------- 319 /// | MI | 320 /// ---------------- 321 /// | 322 /// ---------------- 323 /// | MI * | 324 /// ---------------- 325 /// | 326 /// ---------------- 327 /// | MI * | 328 /// ---------------- 329 /// In this case, the first MI starts a bundle but is not inside a bundle, the 330 /// next 2 MIs are considered "inside" the bundle. 331 /// 332 /// After a bundle is finalized, it looks like this: 333 /// ---------------- 334 /// | Bundle | 335 /// ---------------- 336 /// | 337 /// ---------------- 338 /// | MI * | 339 /// ---------------- 340 /// | 341 /// ---------------- 342 /// | MI * | 343 /// ---------------- 344 /// | 345 /// ---------------- 346 /// | MI * | 347 /// ---------------- 348 /// The first instruction has the special opcode "BUNDLE". It's not "inside" 349 /// a bundle, but the next three MIs are. 350 bool isInsideBundle() const { 351 return getFlag(BundledPred); 352 } 353 354 /// Return true if this instruction part of a bundle. This is true 355 /// if either itself or its following instruction is marked "InsideBundle". 356 bool isBundled() const { 357 return isBundledWithPred() || isBundledWithSucc(); 358 } 359 360 /// Return true if this instruction is part of a bundle, and it is not the 361 /// first instruction in the bundle. 362 bool isBundledWithPred() const { return getFlag(BundledPred); } 363 364 /// Return true if this instruction is part of a bundle, and it is not the 365 /// last instruction in the bundle. 366 bool isBundledWithSucc() const { return getFlag(BundledSucc); } 367 368 /// Bundle this instruction with its predecessor. This can be an unbundled 369 /// instruction, or it can be the first instruction in a bundle. 370 void bundleWithPred(); 371 372 /// Bundle this instruction with its successor. This can be an unbundled 373 /// instruction, or it can be the last instruction in a bundle. 374 void bundleWithSucc(); 375 376 /// Break bundle above this instruction. 377 void unbundleFromPred(); 378 379 /// Break bundle below this instruction. 380 void unbundleFromSucc(); 381 382 /// Returns the debug location id of this MachineInstr. 383 const DebugLoc &getDebugLoc() const { return debugLoc; } 384 385 /// Return the debug variable referenced by 386 /// this DBG_VALUE instruction. 387 const DILocalVariable *getDebugVariable() const; 388 389 /// Return the complex address expression referenced by 390 /// this DBG_VALUE instruction. 391 const DIExpression *getDebugExpression() const; 392 393 /// Return the debug label referenced by 394 /// this DBG_LABEL instruction. 395 const DILabel *getDebugLabel() const; 396 397 /// Emit an error referring to the source location of this instruction. 398 /// This should only be used for inline assembly that is somehow 399 /// impossible to compile. Other errors should have been handled much 400 /// earlier. 401 /// 402 /// If this method returns, the caller should try to recover from the error. 403 void emitError(StringRef Msg) const; 404 405 /// Returns the target instruction descriptor of this MachineInstr. 406 const MCInstrDesc &getDesc() const { return *MCID; } 407 408 /// Returns the opcode of this MachineInstr. 409 unsigned getOpcode() const { return MCID->Opcode; } 410 411 /// Retuns the total number of operands. 412 unsigned getNumOperands() const { return NumOperands; } 413 414 const MachineOperand& getOperand(unsigned i) const { 415 assert(i < getNumOperands() && "getOperand() out of range!"); 416 return Operands[i]; 417 } 418 MachineOperand& getOperand(unsigned i) { 419 assert(i < getNumOperands() && "getOperand() out of range!"); 420 return Operands[i]; 421 } 422 423 /// Returns the total number of definitions. 424 unsigned getNumDefs() const { 425 return getNumExplicitDefs() + MCID->getNumImplicitDefs(); 426 } 427 428 /// Return true if operand \p OpIdx is a subregister index. 429 bool isOperandSubregIdx(unsigned OpIdx) const { 430 assert(getOperand(OpIdx).getType() == MachineOperand::MO_Immediate && 431 "Expected MO_Immediate operand type."); 432 if (isExtractSubreg() && OpIdx == 2) 433 return true; 434 if (isInsertSubreg() && OpIdx == 3) 435 return true; 436 if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0) 437 return true; 438 if (isSubregToReg() && OpIdx == 3) 439 return true; 440 return false; 441 } 442 443 /// Returns the number of non-implicit operands. 444 unsigned getNumExplicitOperands() const; 445 446 /// Returns the number of non-implicit definitions. 447 unsigned getNumExplicitDefs() const; 448 449 /// iterator/begin/end - Iterate over all operands of a machine instruction. 450 using mop_iterator = MachineOperand *; 451 using const_mop_iterator = const MachineOperand *; 452 453 mop_iterator operands_begin() { return Operands; } 454 mop_iterator operands_end() { return Operands + NumOperands; } 455 456 const_mop_iterator operands_begin() const { return Operands; } 457 const_mop_iterator operands_end() const { return Operands + NumOperands; } 458 459 iterator_range<mop_iterator> operands() { 460 return make_range(operands_begin(), operands_end()); 461 } 462 iterator_range<const_mop_iterator> operands() const { 463 return make_range(operands_begin(), operands_end()); 464 } 465 iterator_range<mop_iterator> explicit_operands() { 466 return make_range(operands_begin(), 467 operands_begin() + getNumExplicitOperands()); 468 } 469 iterator_range<const_mop_iterator> explicit_operands() const { 470 return make_range(operands_begin(), 471 operands_begin() + getNumExplicitOperands()); 472 } 473 iterator_range<mop_iterator> implicit_operands() { 474 return make_range(explicit_operands().end(), operands_end()); 475 } 476 iterator_range<const_mop_iterator> implicit_operands() const { 477 return make_range(explicit_operands().end(), operands_end()); 478 } 479 /// Returns a range over all explicit operands that are register definitions. 480 /// Implicit definition are not included! 481 iterator_range<mop_iterator> defs() { 482 return make_range(operands_begin(), 483 operands_begin() + getNumExplicitDefs()); 484 } 485 /// \copydoc defs() 486 iterator_range<const_mop_iterator> defs() const { 487 return make_range(operands_begin(), 488 operands_begin() + getNumExplicitDefs()); 489 } 490 /// Returns a range that includes all operands that are register uses. 491 /// This may include unrelated operands which are not register uses. 492 iterator_range<mop_iterator> uses() { 493 return make_range(operands_begin() + getNumExplicitDefs(), operands_end()); 494 } 495 /// \copydoc uses() 496 iterator_range<const_mop_iterator> uses() const { 497 return make_range(operands_begin() + getNumExplicitDefs(), operands_end()); 498 } 499 iterator_range<mop_iterator> explicit_uses() { 500 return make_range(operands_begin() + getNumExplicitDefs(), 501 operands_begin() + getNumExplicitOperands()); 502 } 503 iterator_range<const_mop_iterator> explicit_uses() const { 504 return make_range(operands_begin() + getNumExplicitDefs(), 505 operands_begin() + getNumExplicitOperands()); 506 } 507 508 /// Returns the number of the operand iterator \p I points to. 509 unsigned getOperandNo(const_mop_iterator I) const { 510 return I - operands_begin(); 511 } 512 513 /// Access to memory operands of the instruction. If there are none, that does 514 /// not imply anything about whether the function accesses memory. Instead, 515 /// the caller must behave conservatively. 516 ArrayRef<MachineMemOperand *> memoperands() const { 517 if (!Info) 518 return {}; 519 520 if (Info.is<EIIK_MMO>()) 521 return makeArrayRef(Info.getAddrOfZeroTagPointer(), 1); 522 523 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>()) 524 return EI->getMMOs(); 525 526 return {}; 527 } 528 529 /// Access to memory operands of the instruction. 530 /// 531 /// If `memoperands_begin() == memoperands_end()`, that does not imply 532 /// anything about whether the function accesses memory. Instead, the caller 533 /// must behave conservatively. 534 mmo_iterator memoperands_begin() const { return memoperands().begin(); } 535 536 /// Access to memory operands of the instruction. 537 /// 538 /// If `memoperands_begin() == memoperands_end()`, that does not imply 539 /// anything about whether the function accesses memory. Instead, the caller 540 /// must behave conservatively. 541 mmo_iterator memoperands_end() const { return memoperands().end(); } 542 543 /// Return true if we don't have any memory operands which described the 544 /// memory access done by this instruction. If this is true, calling code 545 /// must be conservative. 546 bool memoperands_empty() const { return memoperands().empty(); } 547 548 /// Return true if this instruction has exactly one MachineMemOperand. 549 bool hasOneMemOperand() const { return memoperands().size() == 1; } 550 551 /// Return the number of memory operands. 552 unsigned getNumMemOperands() const { return memoperands().size(); } 553 554 /// Helper to extract a pre-instruction symbol if one has been added. 555 MCSymbol *getPreInstrSymbol() const { 556 if (!Info) 557 return nullptr; 558 if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>()) 559 return S; 560 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>()) 561 return EI->getPreInstrSymbol(); 562 563 return nullptr; 564 } 565 566 /// Helper to extract a post-instruction symbol if one has been added. 567 MCSymbol *getPostInstrSymbol() const { 568 if (!Info) 569 return nullptr; 570 if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>()) 571 return S; 572 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>()) 573 return EI->getPostInstrSymbol(); 574 575 return nullptr; 576 } 577 578 /// API for querying MachineInstr properties. They are the same as MCInstrDesc 579 /// queries but they are bundle aware. 580 581 enum QueryType { 582 IgnoreBundle, // Ignore bundles 583 AnyInBundle, // Return true if any instruction in bundle has property 584 AllInBundle // Return true if all instructions in bundle have property 585 }; 586 587 /// Return true if the instruction (or in the case of a bundle, 588 /// the instructions inside the bundle) has the specified property. 589 /// The first argument is the property being queried. 590 /// The second argument indicates whether the query should look inside 591 /// instruction bundles. 592 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const { 593 assert(MCFlag < 64 && 594 "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle."); 595 // Inline the fast path for unbundled or bundle-internal instructions. 596 if (Type == IgnoreBundle || !isBundled() || isBundledWithPred()) 597 return getDesc().getFlags() & (1ULL << MCFlag); 598 599 // If this is the first instruction in a bundle, take the slow path. 600 return hasPropertyInBundle(1ULL << MCFlag, Type); 601 } 602 603 /// Return true if this instruction can have a variable number of operands. 604 /// In this case, the variable operands will be after the normal 605 /// operands but before the implicit definitions and uses (if any are 606 /// present). 607 bool isVariadic(QueryType Type = IgnoreBundle) const { 608 return hasProperty(MCID::Variadic, Type); 609 } 610 611 /// Set if this instruction has an optional definition, e.g. 612 /// ARM instructions which can set condition code if 's' bit is set. 613 bool hasOptionalDef(QueryType Type = IgnoreBundle) const { 614 return hasProperty(MCID::HasOptionalDef, Type); 615 } 616 617 /// Return true if this is a pseudo instruction that doesn't 618 /// correspond to a real machine instruction. 619 bool isPseudo(QueryType Type = IgnoreBundle) const { 620 return hasProperty(MCID::Pseudo, Type); 621 } 622 623 bool isReturn(QueryType Type = AnyInBundle) const { 624 return hasProperty(MCID::Return, Type); 625 } 626 627 /// Return true if this is an instruction that marks the end of an EH scope, 628 /// i.e., a catchpad or a cleanuppad instruction. 629 bool isEHScopeReturn(QueryType Type = AnyInBundle) const { 630 return hasProperty(MCID::EHScopeReturn, Type); 631 } 632 633 bool isCall(QueryType Type = AnyInBundle) const { 634 return hasProperty(MCID::Call, Type); 635 } 636 637 /// Returns true if the specified instruction stops control flow 638 /// from executing the instruction immediately following it. Examples include 639 /// unconditional branches and return instructions. 640 bool isBarrier(QueryType Type = AnyInBundle) const { 641 return hasProperty(MCID::Barrier, Type); 642 } 643 644 /// Returns true if this instruction part of the terminator for a basic block. 645 /// Typically this is things like return and branch instructions. 646 /// 647 /// Various passes use this to insert code into the bottom of a basic block, 648 /// but before control flow occurs. 649 bool isTerminator(QueryType Type = AnyInBundle) const { 650 return hasProperty(MCID::Terminator, Type); 651 } 652 653 /// Returns true if this is a conditional, unconditional, or indirect branch. 654 /// Predicates below can be used to discriminate between 655 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to 656 /// get more information. 657 bool isBranch(QueryType Type = AnyInBundle) const { 658 return hasProperty(MCID::Branch, Type); 659 } 660 661 /// Return true if this is an indirect branch, such as a 662 /// branch through a register. 663 bool isIndirectBranch(QueryType Type = AnyInBundle) const { 664 return hasProperty(MCID::IndirectBranch, Type); 665 } 666 667 /// Return true if this is a branch which may fall 668 /// through to the next instruction or may transfer control flow to some other 669 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more 670 /// information about this branch. 671 bool isConditionalBranch(QueryType Type = AnyInBundle) const { 672 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type); 673 } 674 675 /// Return true if this is a branch which always 676 /// transfers control flow to some other block. The 677 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information 678 /// about this branch. 679 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const { 680 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type); 681 } 682 683 /// Return true if this instruction has a predicate operand that 684 /// controls execution. It may be set to 'always', or may be set to other 685 /// values. There are various methods in TargetInstrInfo that can be used to 686 /// control and modify the predicate in this instruction. 687 bool isPredicable(QueryType Type = AllInBundle) const { 688 // If it's a bundle than all bundled instructions must be predicable for this 689 // to return true. 690 return hasProperty(MCID::Predicable, Type); 691 } 692 693 /// Return true if this instruction is a comparison. 694 bool isCompare(QueryType Type = IgnoreBundle) const { 695 return hasProperty(MCID::Compare, Type); 696 } 697 698 /// Return true if this instruction is a move immediate 699 /// (including conditional moves) instruction. 700 bool isMoveImmediate(QueryType Type = IgnoreBundle) const { 701 return hasProperty(MCID::MoveImm, Type); 702 } 703 704 /// Return true if this instruction is a register move. 705 /// (including moving values from subreg to reg) 706 bool isMoveReg(QueryType Type = IgnoreBundle) const { 707 return hasProperty(MCID::MoveReg, Type); 708 } 709 710 /// Return true if this instruction is a bitcast instruction. 711 bool isBitcast(QueryType Type = IgnoreBundle) const { 712 return hasProperty(MCID::Bitcast, Type); 713 } 714 715 /// Return true if this instruction is a select instruction. 716 bool isSelect(QueryType Type = IgnoreBundle) const { 717 return hasProperty(MCID::Select, Type); 718 } 719 720 /// Return true if this instruction cannot be safely duplicated. 721 /// For example, if the instruction has a unique labels attached 722 /// to it, duplicating it would cause multiple definition errors. 723 bool isNotDuplicable(QueryType Type = AnyInBundle) const { 724 return hasProperty(MCID::NotDuplicable, Type); 725 } 726 727 /// Return true if this instruction is convergent. 728 /// Convergent instructions can not be made control-dependent on any 729 /// additional values. 730 bool isConvergent(QueryType Type = AnyInBundle) const { 731 if (isInlineAsm()) { 732 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 733 if (ExtraInfo & InlineAsm::Extra_IsConvergent) 734 return true; 735 } 736 return hasProperty(MCID::Convergent, Type); 737 } 738 739 /// Returns true if the specified instruction has a delay slot 740 /// which must be filled by the code generator. 741 bool hasDelaySlot(QueryType Type = AnyInBundle) const { 742 return hasProperty(MCID::DelaySlot, Type); 743 } 744 745 /// Return true for instructions that can be folded as 746 /// memory operands in other instructions. The most common use for this 747 /// is instructions that are simple loads from memory that don't modify 748 /// the loaded value in any way, but it can also be used for instructions 749 /// that can be expressed as constant-pool loads, such as V_SETALLONES 750 /// on x86, to allow them to be folded when it is beneficial. 751 /// This should only be set on instructions that return a value in their 752 /// only virtual register definition. 753 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const { 754 return hasProperty(MCID::FoldableAsLoad, Type); 755 } 756 757 /// Return true if this instruction behaves 758 /// the same way as the generic REG_SEQUENCE instructions. 759 /// E.g., on ARM, 760 /// dX VMOVDRR rY, rZ 761 /// is equivalent to 762 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1. 763 /// 764 /// Note that for the optimizers to be able to take advantage of 765 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be 766 /// override accordingly. 767 bool isRegSequenceLike(QueryType Type = IgnoreBundle) const { 768 return hasProperty(MCID::RegSequence, Type); 769 } 770 771 /// Return true if this instruction behaves 772 /// the same way as the generic EXTRACT_SUBREG instructions. 773 /// E.g., on ARM, 774 /// rX, rY VMOVRRD dZ 775 /// is equivalent to two EXTRACT_SUBREG: 776 /// rX = EXTRACT_SUBREG dZ, ssub_0 777 /// rY = EXTRACT_SUBREG dZ, ssub_1 778 /// 779 /// Note that for the optimizers to be able to take advantage of 780 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be 781 /// override accordingly. 782 bool isExtractSubregLike(QueryType Type = IgnoreBundle) const { 783 return hasProperty(MCID::ExtractSubreg, Type); 784 } 785 786 /// Return true if this instruction behaves 787 /// the same way as the generic INSERT_SUBREG instructions. 788 /// E.g., on ARM, 789 /// dX = VSETLNi32 dY, rZ, Imm 790 /// is equivalent to a INSERT_SUBREG: 791 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm) 792 /// 793 /// Note that for the optimizers to be able to take advantage of 794 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be 795 /// override accordingly. 796 bool isInsertSubregLike(QueryType Type = IgnoreBundle) const { 797 return hasProperty(MCID::InsertSubreg, Type); 798 } 799 800 //===--------------------------------------------------------------------===// 801 // Side Effect Analysis 802 //===--------------------------------------------------------------------===// 803 804 /// Return true if this instruction could possibly read memory. 805 /// Instructions with this flag set are not necessarily simple load 806 /// instructions, they may load a value and modify it, for example. 807 bool mayLoad(QueryType Type = AnyInBundle) const { 808 if (isInlineAsm()) { 809 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 810 if (ExtraInfo & InlineAsm::Extra_MayLoad) 811 return true; 812 } 813 return hasProperty(MCID::MayLoad, Type); 814 } 815 816 /// Return true if this instruction could possibly modify memory. 817 /// Instructions with this flag set are not necessarily simple store 818 /// instructions, they may store a modified value based on their operands, or 819 /// may not actually modify anything, for example. 820 bool mayStore(QueryType Type = AnyInBundle) const { 821 if (isInlineAsm()) { 822 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 823 if (ExtraInfo & InlineAsm::Extra_MayStore) 824 return true; 825 } 826 return hasProperty(MCID::MayStore, Type); 827 } 828 829 /// Return true if this instruction could possibly read or modify memory. 830 bool mayLoadOrStore(QueryType Type = AnyInBundle) const { 831 return mayLoad(Type) || mayStore(Type); 832 } 833 834 //===--------------------------------------------------------------------===// 835 // Flags that indicate whether an instruction can be modified by a method. 836 //===--------------------------------------------------------------------===// 837 838 /// Return true if this may be a 2- or 3-address 839 /// instruction (of the form "X = op Y, Z, ..."), which produces the same 840 /// result if Y and Z are exchanged. If this flag is set, then the 841 /// TargetInstrInfo::commuteInstruction method may be used to hack on the 842 /// instruction. 843 /// 844 /// Note that this flag may be set on instructions that are only commutable 845 /// sometimes. In these cases, the call to commuteInstruction will fail. 846 /// Also note that some instructions require non-trivial modification to 847 /// commute them. 848 bool isCommutable(QueryType Type = IgnoreBundle) const { 849 return hasProperty(MCID::Commutable, Type); 850 } 851 852 /// Return true if this is a 2-address instruction 853 /// which can be changed into a 3-address instruction if needed. Doing this 854 /// transformation can be profitable in the register allocator, because it 855 /// means that the instruction can use a 2-address form if possible, but 856 /// degrade into a less efficient form if the source and dest register cannot 857 /// be assigned to the same register. For example, this allows the x86 858 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which 859 /// is the same speed as the shift but has bigger code size. 860 /// 861 /// If this returns true, then the target must implement the 862 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which 863 /// is allowed to fail if the transformation isn't valid for this specific 864 /// instruction (e.g. shl reg, 4 on x86). 865 /// 866 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const { 867 return hasProperty(MCID::ConvertibleTo3Addr, Type); 868 } 869 870 /// Return true if this instruction requires 871 /// custom insertion support when the DAG scheduler is inserting it into a 872 /// machine basic block. If this is true for the instruction, it basically 873 /// means that it is a pseudo instruction used at SelectionDAG time that is 874 /// expanded out into magic code by the target when MachineInstrs are formed. 875 /// 876 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method 877 /// is used to insert this into the MachineBasicBlock. 878 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const { 879 return hasProperty(MCID::UsesCustomInserter, Type); 880 } 881 882 /// Return true if this instruction requires *adjustment* 883 /// after instruction selection by calling a target hook. For example, this 884 /// can be used to fill in ARM 's' optional operand depending on whether 885 /// the conditional flag register is used. 886 bool hasPostISelHook(QueryType Type = IgnoreBundle) const { 887 return hasProperty(MCID::HasPostISelHook, Type); 888 } 889 890 /// Returns true if this instruction is a candidate for remat. 891 /// This flag is deprecated, please don't use it anymore. If this 892 /// flag is set, the isReallyTriviallyReMaterializable() method is called to 893 /// verify the instruction is really rematable. 894 bool isRematerializable(QueryType Type = AllInBundle) const { 895 // It's only possible to re-mat a bundle if all bundled instructions are 896 // re-materializable. 897 return hasProperty(MCID::Rematerializable, Type); 898 } 899 900 /// Returns true if this instruction has the same cost (or less) than a move 901 /// instruction. This is useful during certain types of optimizations 902 /// (e.g., remat during two-address conversion or machine licm) 903 /// where we would like to remat or hoist the instruction, but not if it costs 904 /// more than moving the instruction into the appropriate register. Note, we 905 /// are not marking copies from and to the same register class with this flag. 906 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const { 907 // Only returns true for a bundle if all bundled instructions are cheap. 908 return hasProperty(MCID::CheapAsAMove, Type); 909 } 910 911 /// Returns true if this instruction source operands 912 /// have special register allocation requirements that are not captured by the 913 /// operand register classes. e.g. ARM::STRD's two source registers must be an 914 /// even / odd pair, ARM::STM registers have to be in ascending order. 915 /// Post-register allocation passes should not attempt to change allocations 916 /// for sources of instructions with this flag. 917 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const { 918 return hasProperty(MCID::ExtraSrcRegAllocReq, Type); 919 } 920 921 /// Returns true if this instruction def operands 922 /// have special register allocation requirements that are not captured by the 923 /// operand register classes. e.g. ARM::LDRD's two def registers must be an 924 /// even / odd pair, ARM::LDM registers have to be in ascending order. 925 /// Post-register allocation passes should not attempt to change allocations 926 /// for definitions of instructions with this flag. 927 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const { 928 return hasProperty(MCID::ExtraDefRegAllocReq, Type); 929 } 930 931 enum MICheckType { 932 CheckDefs, // Check all operands for equality 933 CheckKillDead, // Check all operands including kill / dead markers 934 IgnoreDefs, // Ignore all definitions 935 IgnoreVRegDefs // Ignore virtual register definitions 936 }; 937 938 /// Return true if this instruction is identical to \p Other. 939 /// Two instructions are identical if they have the same opcode and all their 940 /// operands are identical (with respect to MachineOperand::isIdenticalTo()). 941 /// Note that this means liveness related flags (dead, undef, kill) do not 942 /// affect the notion of identical. 943 bool isIdenticalTo(const MachineInstr &Other, 944 MICheckType Check = CheckDefs) const; 945 946 /// Unlink 'this' from the containing basic block, and return it without 947 /// deleting it. 948 /// 949 /// This function can not be used on bundled instructions, use 950 /// removeFromBundle() to remove individual instructions from a bundle. 951 MachineInstr *removeFromParent(); 952 953 /// Unlink this instruction from its basic block and return it without 954 /// deleting it. 955 /// 956 /// If the instruction is part of a bundle, the other instructions in the 957 /// bundle remain bundled. 958 MachineInstr *removeFromBundle(); 959 960 /// Unlink 'this' from the containing basic block and delete it. 961 /// 962 /// If this instruction is the header of a bundle, the whole bundle is erased. 963 /// This function can not be used for instructions inside a bundle, use 964 /// eraseFromBundle() to erase individual bundled instructions. 965 void eraseFromParent(); 966 967 /// Unlink 'this' from the containing basic block and delete it. 968 /// 969 /// For all definitions mark their uses in DBG_VALUE nodes 970 /// as undefined. Otherwise like eraseFromParent(). 971 void eraseFromParentAndMarkDBGValuesForRemoval(); 972 973 /// Unlink 'this' form its basic block and delete it. 974 /// 975 /// If the instruction is part of a bundle, the other instructions in the 976 /// bundle remain bundled. 977 void eraseFromBundle(); 978 979 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; } 980 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; } 981 bool isAnnotationLabel() const { 982 return getOpcode() == TargetOpcode::ANNOTATION_LABEL; 983 } 984 985 /// Returns true if the MachineInstr represents a label. 986 bool isLabel() const { 987 return isEHLabel() || isGCLabel() || isAnnotationLabel(); 988 } 989 990 bool isCFIInstruction() const { 991 return getOpcode() == TargetOpcode::CFI_INSTRUCTION; 992 } 993 994 // True if the instruction represents a position in the function. 995 bool isPosition() const { return isLabel() || isCFIInstruction(); } 996 997 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; } 998 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; } 999 bool isDebugInstr() const { return isDebugValue() || isDebugLabel(); } 1000 1001 /// A DBG_VALUE is indirect iff the first operand is a register and 1002 /// the second operand is an immediate. 1003 bool isIndirectDebugValue() const { 1004 return isDebugValue() 1005 && getOperand(0).isReg() 1006 && getOperand(1).isImm(); 1007 } 1008 1009 bool isPHI() const { 1010 return getOpcode() == TargetOpcode::PHI || 1011 getOpcode() == TargetOpcode::G_PHI; 1012 } 1013 bool isKill() const { return getOpcode() == TargetOpcode::KILL; } 1014 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; } 1015 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; } 1016 1017 bool isMSInlineAsm() const { 1018 return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect(); 1019 } 1020 1021 bool isStackAligningInlineAsm() const; 1022 InlineAsm::AsmDialect getInlineAsmDialect() const; 1023 1024 bool isInsertSubreg() const { 1025 return getOpcode() == TargetOpcode::INSERT_SUBREG; 1026 } 1027 1028 bool isSubregToReg() const { 1029 return getOpcode() == TargetOpcode::SUBREG_TO_REG; 1030 } 1031 1032 bool isRegSequence() const { 1033 return getOpcode() == TargetOpcode::REG_SEQUENCE; 1034 } 1035 1036 bool isBundle() const { 1037 return getOpcode() == TargetOpcode::BUNDLE; 1038 } 1039 1040 bool isCopy() const { 1041 return getOpcode() == TargetOpcode::COPY; 1042 } 1043 1044 bool isFullCopy() const { 1045 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg(); 1046 } 1047 1048 bool isExtractSubreg() const { 1049 return getOpcode() == TargetOpcode::EXTRACT_SUBREG; 1050 } 1051 1052 /// Return true if the instruction behaves like a copy. 1053 /// This does not include native copy instructions. 1054 bool isCopyLike() const { 1055 return isCopy() || isSubregToReg(); 1056 } 1057 1058 /// Return true is the instruction is an identity copy. 1059 bool isIdentityCopy() const { 1060 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() && 1061 getOperand(0).getSubReg() == getOperand(1).getSubReg(); 1062 } 1063 1064 /// Return true if this instruction doesn't produce any output in the form of 1065 /// executable instructions. 1066 bool isMetaInstruction() const { 1067 switch (getOpcode()) { 1068 default: 1069 return false; 1070 case TargetOpcode::IMPLICIT_DEF: 1071 case TargetOpcode::KILL: 1072 case TargetOpcode::CFI_INSTRUCTION: 1073 case TargetOpcode::EH_LABEL: 1074 case TargetOpcode::GC_LABEL: 1075 case TargetOpcode::DBG_VALUE: 1076 case TargetOpcode::DBG_LABEL: 1077 case TargetOpcode::LIFETIME_START: 1078 case TargetOpcode::LIFETIME_END: 1079 return true; 1080 } 1081 } 1082 1083 /// Return true if this is a transient instruction that is either very likely 1084 /// to be eliminated during register allocation (such as copy-like 1085 /// instructions), or if this instruction doesn't have an execution-time cost. 1086 bool isTransient() const { 1087 switch (getOpcode()) { 1088 default: 1089 return isMetaInstruction(); 1090 // Copy-like instructions are usually eliminated during register allocation. 1091 case TargetOpcode::PHI: 1092 case TargetOpcode::G_PHI: 1093 case TargetOpcode::COPY: 1094 case TargetOpcode::INSERT_SUBREG: 1095 case TargetOpcode::SUBREG_TO_REG: 1096 case TargetOpcode::REG_SEQUENCE: 1097 return true; 1098 } 1099 } 1100 1101 /// Return the number of instructions inside the MI bundle, excluding the 1102 /// bundle header. 1103 /// 1104 /// This is the number of instructions that MachineBasicBlock::iterator 1105 /// skips, 0 for unbundled instructions. 1106 unsigned getBundleSize() const; 1107 1108 /// Return true if the MachineInstr reads the specified register. 1109 /// If TargetRegisterInfo is passed, then it also checks if there 1110 /// is a read of a super-register. 1111 /// This does not count partial redefines of virtual registers as reads: 1112 /// %reg1024:6 = OP. 1113 bool readsRegister(unsigned Reg, 1114 const TargetRegisterInfo *TRI = nullptr) const { 1115 return findRegisterUseOperandIdx(Reg, false, TRI) != -1; 1116 } 1117 1118 /// Return true if the MachineInstr reads the specified virtual register. 1119 /// Take into account that a partial define is a 1120 /// read-modify-write operation. 1121 bool readsVirtualRegister(unsigned Reg) const { 1122 return readsWritesVirtualRegister(Reg).first; 1123 } 1124 1125 /// Return a pair of bools (reads, writes) indicating if this instruction 1126 /// reads or writes Reg. This also considers partial defines. 1127 /// If Ops is not null, all operand indices for Reg are added. 1128 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg, 1129 SmallVectorImpl<unsigned> *Ops = nullptr) const; 1130 1131 /// Return true if the MachineInstr kills the specified register. 1132 /// If TargetRegisterInfo is passed, then it also checks if there is 1133 /// a kill of a super-register. 1134 bool killsRegister(unsigned Reg, 1135 const TargetRegisterInfo *TRI = nullptr) const { 1136 return findRegisterUseOperandIdx(Reg, true, TRI) != -1; 1137 } 1138 1139 /// Return true if the MachineInstr fully defines the specified register. 1140 /// If TargetRegisterInfo is passed, then it also checks 1141 /// if there is a def of a super-register. 1142 /// NOTE: It's ignoring subreg indices on virtual registers. 1143 bool definesRegister(unsigned Reg, 1144 const TargetRegisterInfo *TRI = nullptr) const { 1145 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1; 1146 } 1147 1148 /// Return true if the MachineInstr modifies (fully define or partially 1149 /// define) the specified register. 1150 /// NOTE: It's ignoring subreg indices on virtual registers. 1151 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const { 1152 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1; 1153 } 1154 1155 /// Returns true if the register is dead in this machine instruction. 1156 /// If TargetRegisterInfo is passed, then it also checks 1157 /// if there is a dead def of a super-register. 1158 bool registerDefIsDead(unsigned Reg, 1159 const TargetRegisterInfo *TRI = nullptr) const { 1160 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1; 1161 } 1162 1163 /// Returns true if the MachineInstr has an implicit-use operand of exactly 1164 /// the given register (not considering sub/super-registers). 1165 bool hasRegisterImplicitUseOperand(unsigned Reg) const; 1166 1167 /// Returns the operand index that is a use of the specific register or -1 1168 /// if it is not found. It further tightens the search criteria to a use 1169 /// that kills the register if isKill is true. 1170 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false, 1171 const TargetRegisterInfo *TRI = nullptr) const; 1172 1173 /// Wrapper for findRegisterUseOperandIdx, it returns 1174 /// a pointer to the MachineOperand rather than an index. 1175 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false, 1176 const TargetRegisterInfo *TRI = nullptr) { 1177 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI); 1178 return (Idx == -1) ? nullptr : &getOperand(Idx); 1179 } 1180 1181 const MachineOperand *findRegisterUseOperand( 1182 unsigned Reg, bool isKill = false, 1183 const TargetRegisterInfo *TRI = nullptr) const { 1184 return const_cast<MachineInstr *>(this)-> 1185 findRegisterUseOperand(Reg, isKill, TRI); 1186 } 1187 1188 /// Returns the operand index that is a def of the specified register or 1189 /// -1 if it is not found. If isDead is true, defs that are not dead are 1190 /// skipped. If Overlap is true, then it also looks for defs that merely 1191 /// overlap the specified register. If TargetRegisterInfo is non-null, 1192 /// then it also checks if there is a def of a super-register. 1193 /// This may also return a register mask operand when Overlap is true. 1194 int findRegisterDefOperandIdx(unsigned Reg, 1195 bool isDead = false, bool Overlap = false, 1196 const TargetRegisterInfo *TRI = nullptr) const; 1197 1198 /// Wrapper for findRegisterDefOperandIdx, it returns 1199 /// a pointer to the MachineOperand rather than an index. 1200 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false, 1201 const TargetRegisterInfo *TRI = nullptr) { 1202 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI); 1203 return (Idx == -1) ? nullptr : &getOperand(Idx); 1204 } 1205 1206 /// Find the index of the first operand in the 1207 /// operand list that is used to represent the predicate. It returns -1 if 1208 /// none is found. 1209 int findFirstPredOperandIdx() const; 1210 1211 /// Find the index of the flag word operand that 1212 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if 1213 /// getOperand(OpIdx) does not belong to an inline asm operand group. 1214 /// 1215 /// If GroupNo is not NULL, it will receive the number of the operand group 1216 /// containing OpIdx. 1217 /// 1218 /// The flag operand is an immediate that can be decoded with methods like 1219 /// InlineAsm::hasRegClassConstraint(). 1220 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const; 1221 1222 /// Compute the static register class constraint for operand OpIdx. 1223 /// For normal instructions, this is derived from the MCInstrDesc. 1224 /// For inline assembly it is derived from the flag words. 1225 /// 1226 /// Returns NULL if the static register class constraint cannot be 1227 /// determined. 1228 const TargetRegisterClass* 1229 getRegClassConstraint(unsigned OpIdx, 1230 const TargetInstrInfo *TII, 1231 const TargetRegisterInfo *TRI) const; 1232 1233 /// Applies the constraints (def/use) implied by this MI on \p Reg to 1234 /// the given \p CurRC. 1235 /// If \p ExploreBundle is set and MI is part of a bundle, all the 1236 /// instructions inside the bundle will be taken into account. In other words, 1237 /// this method accumulates all the constraints of the operand of this MI and 1238 /// the related bundle if MI is a bundle or inside a bundle. 1239 /// 1240 /// Returns the register class that satisfies both \p CurRC and the 1241 /// constraints set by MI. Returns NULL if such a register class does not 1242 /// exist. 1243 /// 1244 /// \pre CurRC must not be NULL. 1245 const TargetRegisterClass *getRegClassConstraintEffectForVReg( 1246 unsigned Reg, const TargetRegisterClass *CurRC, 1247 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, 1248 bool ExploreBundle = false) const; 1249 1250 /// Applies the constraints (def/use) implied by the \p OpIdx operand 1251 /// to the given \p CurRC. 1252 /// 1253 /// Returns the register class that satisfies both \p CurRC and the 1254 /// constraints set by \p OpIdx MI. Returns NULL if such a register class 1255 /// does not exist. 1256 /// 1257 /// \pre CurRC must not be NULL. 1258 /// \pre The operand at \p OpIdx must be a register. 1259 const TargetRegisterClass * 1260 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, 1261 const TargetInstrInfo *TII, 1262 const TargetRegisterInfo *TRI) const; 1263 1264 /// Add a tie between the register operands at DefIdx and UseIdx. 1265 /// The tie will cause the register allocator to ensure that the two 1266 /// operands are assigned the same physical register. 1267 /// 1268 /// Tied operands are managed automatically for explicit operands in the 1269 /// MCInstrDesc. This method is for exceptional cases like inline asm. 1270 void tieOperands(unsigned DefIdx, unsigned UseIdx); 1271 1272 /// Given the index of a tied register operand, find the 1273 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the 1274 /// index of the tied operand which must exist. 1275 unsigned findTiedOperandIdx(unsigned OpIdx) const; 1276 1277 /// Given the index of a register def operand, 1278 /// check if the register def is tied to a source operand, due to either 1279 /// two-address elimination or inline assembly constraints. Returns the 1280 /// first tied use operand index by reference if UseOpIdx is not null. 1281 bool isRegTiedToUseOperand(unsigned DefOpIdx, 1282 unsigned *UseOpIdx = nullptr) const { 1283 const MachineOperand &MO = getOperand(DefOpIdx); 1284 if (!MO.isReg() || !MO.isDef() || !MO.isTied()) 1285 return false; 1286 if (UseOpIdx) 1287 *UseOpIdx = findTiedOperandIdx(DefOpIdx); 1288 return true; 1289 } 1290 1291 /// Return true if the use operand of the specified index is tied to a def 1292 /// operand. It also returns the def operand index by reference if DefOpIdx 1293 /// is not null. 1294 bool isRegTiedToDefOperand(unsigned UseOpIdx, 1295 unsigned *DefOpIdx = nullptr) const { 1296 const MachineOperand &MO = getOperand(UseOpIdx); 1297 if (!MO.isReg() || !MO.isUse() || !MO.isTied()) 1298 return false; 1299 if (DefOpIdx) 1300 *DefOpIdx = findTiedOperandIdx(UseOpIdx); 1301 return true; 1302 } 1303 1304 /// Clears kill flags on all operands. 1305 void clearKillInfo(); 1306 1307 /// Replace all occurrences of FromReg with ToReg:SubIdx, 1308 /// properly composing subreg indices where necessary. 1309 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, 1310 const TargetRegisterInfo &RegInfo); 1311 1312 /// We have determined MI kills a register. Look for the 1313 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true, 1314 /// add a implicit operand if it's not found. Returns true if the operand 1315 /// exists / is added. 1316 bool addRegisterKilled(unsigned IncomingReg, 1317 const TargetRegisterInfo *RegInfo, 1318 bool AddIfNotFound = false); 1319 1320 /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes 1321 /// all aliasing registers. 1322 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo); 1323 1324 /// We have determined MI defined a register without a use. 1325 /// Look for the operand that defines it and mark it as IsDead. If 1326 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns 1327 /// true if the operand exists / is added. 1328 bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, 1329 bool AddIfNotFound = false); 1330 1331 /// Clear all dead flags on operands defining register @p Reg. 1332 void clearRegisterDeads(unsigned Reg); 1333 1334 /// Mark all subregister defs of register @p Reg with the undef flag. 1335 /// This function is used when we determined to have a subregister def in an 1336 /// otherwise undefined super register. 1337 void setRegisterDefReadUndef(unsigned Reg, bool IsUndef = true); 1338 1339 /// We have determined MI defines a register. Make sure there is an operand 1340 /// defining Reg. 1341 void addRegisterDefined(unsigned Reg, 1342 const TargetRegisterInfo *RegInfo = nullptr); 1343 1344 /// Mark every physreg used by this instruction as 1345 /// dead except those in the UsedRegs list. 1346 /// 1347 /// On instructions with register mask operands, also add implicit-def 1348 /// operands for all registers in UsedRegs. 1349 void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs, 1350 const TargetRegisterInfo &TRI); 1351 1352 /// Return true if it is safe to move this instruction. If 1353 /// SawStore is set to true, it means that there is a store (or call) between 1354 /// the instruction's location and its intended destination. 1355 bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const; 1356 1357 /// Returns true if this instruction's memory access aliases the memory 1358 /// access of Other. 1359 // 1360 /// Assumes any physical registers used to compute addresses 1361 /// have the same value for both instructions. Returns false if neither 1362 /// instruction writes to memory. 1363 /// 1364 /// @param AA Optional alias analysis, used to compare memory operands. 1365 /// @param Other MachineInstr to check aliasing against. 1366 /// @param UseTBAA Whether to pass TBAA information to alias analysis. 1367 bool mayAlias(AliasAnalysis *AA, MachineInstr &Other, bool UseTBAA); 1368 1369 /// Return true if this instruction may have an ordered 1370 /// or volatile memory reference, or if the information describing the memory 1371 /// reference is not available. Return false if it is known to have no 1372 /// ordered or volatile memory references. 1373 bool hasOrderedMemoryRef() const; 1374 1375 /// Return true if this load instruction never traps and points to a memory 1376 /// location whose value doesn't change during the execution of this function. 1377 /// 1378 /// Examples include loading a value from the constant pool or from the 1379 /// argument area of a function (if it does not change). If the instruction 1380 /// does multiple loads, this returns true only if all of the loads are 1381 /// dereferenceable and invariant. 1382 bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const; 1383 1384 /// If the specified instruction is a PHI that always merges together the 1385 /// same virtual register, return the register, otherwise return 0. 1386 unsigned isConstantValuePHI() const; 1387 1388 /// Return true if this instruction has side effects that are not modeled 1389 /// by mayLoad / mayStore, etc. 1390 /// For all instructions, the property is encoded in MCInstrDesc::Flags 1391 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is 1392 /// INLINEASM instruction, in which case the side effect property is encoded 1393 /// in one of its operands (see InlineAsm::Extra_HasSideEffect). 1394 /// 1395 bool hasUnmodeledSideEffects() const; 1396 1397 /// Returns true if it is illegal to fold a load across this instruction. 1398 bool isLoadFoldBarrier() const; 1399 1400 /// Return true if all the defs of this instruction are dead. 1401 bool allDefsAreDead() const; 1402 1403 /// Copy implicit register operands from specified 1404 /// instruction to this instruction. 1405 void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI); 1406 1407 /// Debugging support 1408 /// @{ 1409 /// Determine the generic type to be printed (if needed) on uses and defs. 1410 LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, 1411 const MachineRegisterInfo &MRI) const; 1412 1413 /// Return true when an instruction has tied register that can't be determined 1414 /// by the instruction's descriptor. This is useful for MIR printing, to 1415 /// determine whether we need to print the ties or not. 1416 bool hasComplexRegisterTies() const; 1417 1418 /// Print this MI to \p OS. 1419 /// Don't print information that can be inferred from other instructions if 1420 /// \p IsStandalone is false. It is usually true when only a fragment of the 1421 /// function is printed. 1422 /// Only print the defs and the opcode if \p SkipOpers is true. 1423 /// Otherwise, also print operands if \p SkipDebugLoc is true. 1424 /// Otherwise, also print the debug loc, with a terminating newline. 1425 /// \p TII is used to print the opcode name. If it's not present, but the 1426 /// MI is in a function, the opcode will be printed using the function's TII. 1427 void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false, 1428 bool SkipDebugLoc = false, bool AddNewLine = true, 1429 const TargetInstrInfo *TII = nullptr) const; 1430 void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true, 1431 bool SkipOpers = false, bool SkipDebugLoc = false, 1432 bool AddNewLine = true, 1433 const TargetInstrInfo *TII = nullptr) const; 1434 void dump() const; 1435 /// @} 1436 1437 //===--------------------------------------------------------------------===// 1438 // Accessors used to build up machine instructions. 1439 1440 /// Add the specified operand to the instruction. If it is an implicit 1441 /// operand, it is added to the end of the operand list. If it is an 1442 /// explicit operand it is added at the end of the explicit operand list 1443 /// (before the first implicit operand). 1444 /// 1445 /// MF must be the machine function that was used to allocate this 1446 /// instruction. 1447 /// 1448 /// MachineInstrBuilder provides a more convenient interface for creating 1449 /// instructions and adding operands. 1450 void addOperand(MachineFunction &MF, const MachineOperand &Op); 1451 1452 /// Add an operand without providing an MF reference. This only works for 1453 /// instructions that are inserted in a basic block. 1454 /// 1455 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be 1456 /// preferred. 1457 void addOperand(const MachineOperand &Op); 1458 1459 /// Replace the instruction descriptor (thus opcode) of 1460 /// the current instruction with a new one. 1461 void setDesc(const MCInstrDesc &tid) { MCID = &tid; } 1462 1463 /// Replace current source information with new such. 1464 /// Avoid using this, the constructor argument is preferable. 1465 void setDebugLoc(DebugLoc dl) { 1466 debugLoc = std::move(dl); 1467 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor"); 1468 } 1469 1470 /// Erase an operand from an instruction, leaving it with one 1471 /// fewer operand than it started with. 1472 void RemoveOperand(unsigned OpNo); 1473 1474 /// Clear this MachineInstr's memory reference descriptor list. This resets 1475 /// the memrefs to their most conservative state. This should be used only 1476 /// as a last resort since it greatly pessimizes our knowledge of the memory 1477 /// access performed by the instruction. 1478 void dropMemRefs(MachineFunction &MF); 1479 1480 /// Assign this MachineInstr's memory reference descriptor list. 1481 /// 1482 /// Unlike other methods, this *will* allocate them into a new array 1483 /// associated with the provided `MachineFunction`. 1484 void setMemRefs(MachineFunction &MF, ArrayRef<MachineMemOperand *> MemRefs); 1485 1486 /// Add a MachineMemOperand to the machine instruction. 1487 /// This function should be used only occasionally. The setMemRefs function 1488 /// is the primary method for setting up a MachineInstr's MemRefs list. 1489 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO); 1490 1491 /// Clone another MachineInstr's memory reference descriptor list and replace 1492 /// ours with it. 1493 /// 1494 /// Note that `*this` may be the incoming MI! 1495 /// 1496 /// Prefer this API whenever possible as it can avoid allocations in common 1497 /// cases. 1498 void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI); 1499 1500 /// Clone the merge of multiple MachineInstrs' memory reference descriptors 1501 /// list and replace ours with it. 1502 /// 1503 /// Note that `*this` may be one of the incoming MIs! 1504 /// 1505 /// Prefer this API whenever possible as it can avoid allocations in common 1506 /// cases. 1507 void cloneMergedMemRefs(MachineFunction &MF, 1508 ArrayRef<const MachineInstr *> MIs); 1509 1510 /// Set a symbol that will be emitted just prior to the instruction itself. 1511 /// 1512 /// Setting this to a null pointer will remove any such symbol. 1513 /// 1514 /// FIXME: This is not fully implemented yet. 1515 void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol); 1516 1517 /// Set a symbol that will be emitted just after the instruction itself. 1518 /// 1519 /// Setting this to a null pointer will remove any such symbol. 1520 /// 1521 /// FIXME: This is not fully implemented yet. 1522 void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol); 1523 1524 /// Return the MIFlags which represent both MachineInstrs. This 1525 /// should be used when merging two MachineInstrs into one. This routine does 1526 /// not modify the MIFlags of this MachineInstr. 1527 uint16_t mergeFlagsWith(const MachineInstr& Other) const; 1528 1529 /// Copy all flags to MachineInst MIFlags 1530 void copyIRFlags(const Instruction &I); 1531 1532 /// Break any tie involving OpIdx. 1533 void untieRegOperand(unsigned OpIdx) { 1534 MachineOperand &MO = getOperand(OpIdx); 1535 if (MO.isReg() && MO.isTied()) { 1536 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0; 1537 MO.TiedTo = 0; 1538 } 1539 } 1540 1541 /// Add all implicit def and use operands to this instruction. 1542 void addImplicitDefUseOperands(MachineFunction &MF); 1543 1544 /// Scan instructions following MI and collect any matching DBG_VALUEs. 1545 void collectDebugValues(SmallVectorImpl<MachineInstr *> &DbgValues); 1546 1547 /// Find all DBG_VALUEs immediately following this instruction that point 1548 /// to a register def in this instruction and point them to \p Reg instead. 1549 void changeDebugValuesDefReg(unsigned Reg); 1550 1551 private: 1552 /// If this instruction is embedded into a MachineFunction, return the 1553 /// MachineRegisterInfo object for the current function, otherwise 1554 /// return null. 1555 MachineRegisterInfo *getRegInfo(); 1556 1557 /// Unlink all of the register operands in this instruction from their 1558 /// respective use lists. This requires that the operands already be on their 1559 /// use lists. 1560 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&); 1561 1562 /// Add all of the register operands in this instruction from their 1563 /// respective use lists. This requires that the operands not be on their 1564 /// use lists yet. 1565 void AddRegOperandsToUseLists(MachineRegisterInfo&); 1566 1567 /// Slow path for hasProperty when we're dealing with a bundle. 1568 bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const; 1569 1570 /// Implements the logic of getRegClassConstraintEffectForVReg for the 1571 /// this MI and the given operand index \p OpIdx. 1572 /// If the related operand does not constrained Reg, this returns CurRC. 1573 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl( 1574 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC, 1575 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const; 1576 }; 1577 1578 /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the 1579 /// instruction rather than by pointer value. 1580 /// The hashing and equality testing functions ignore definitions so this is 1581 /// useful for CSE, etc. 1582 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> { 1583 static inline MachineInstr *getEmptyKey() { 1584 return nullptr; 1585 } 1586 1587 static inline MachineInstr *getTombstoneKey() { 1588 return reinterpret_cast<MachineInstr*>(-1); 1589 } 1590 1591 static unsigned getHashValue(const MachineInstr* const &MI); 1592 1593 static bool isEqual(const MachineInstr* const &LHS, 1594 const MachineInstr* const &RHS) { 1595 if (RHS == getEmptyKey() || RHS == getTombstoneKey() || 1596 LHS == getEmptyKey() || LHS == getTombstoneKey()) 1597 return LHS == RHS; 1598 return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs); 1599 } 1600 }; 1601 1602 //===----------------------------------------------------------------------===// 1603 // Debugging Support 1604 1605 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) { 1606 MI.print(OS); 1607 return OS; 1608 } 1609 1610 } // end namespace llvm 1611 1612 #endif // LLVM_CODEGEN_MACHINEINSTR_H 1613