1 //===--- ScheduleDAGSDNodes.cpp - Implement the ScheduleDAGSDNodes class --===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This implements the ScheduleDAG class, which is a base class used by
11 // scheduling implementation classes.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "ScheduleDAGSDNodes.h"
16 #include "InstrEmitter.h"
17 #include "SDNodeDbgValue.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallPtrSet.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/TargetInstrInfo.h"
27 #include "llvm/CodeGen/TargetLowering.h"
28 #include "llvm/CodeGen/TargetRegisterInfo.h"
29 #include "llvm/CodeGen/TargetSubtargetInfo.h"
30 #include "llvm/Config/llvm-config.h"
31 #include "llvm/MC/MCInstrItineraries.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/raw_ostream.h"
35 using namespace llvm;
36
37 #define DEBUG_TYPE "pre-RA-sched"
38
39 STATISTIC(LoadsClustered, "Number of loads clustered together");
40
41 // This allows the latency-based scheduler to notice high latency instructions
42 // without a target itinerary. The choice of number here has more to do with
43 // balancing scheduler heuristics than with the actual machine latency.
44 static cl::opt<int> HighLatencyCycles(
45 "sched-high-latency-cycles", cl::Hidden, cl::init(10),
46 cl::desc("Roughly estimate the number of cycles that 'long latency'"
47 "instructions take for targets with no itinerary"));
48
ScheduleDAGSDNodes(MachineFunction & mf)49 ScheduleDAGSDNodes::ScheduleDAGSDNodes(MachineFunction &mf)
50 : ScheduleDAG(mf), BB(nullptr), DAG(nullptr),
51 InstrItins(mf.getSubtarget().getInstrItineraryData()) {}
52
53 /// Run - perform scheduling.
54 ///
Run(SelectionDAG * dag,MachineBasicBlock * bb)55 void ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb) {
56 BB = bb;
57 DAG = dag;
58
59 // Clear the scheduler's SUnit DAG.
60 ScheduleDAG::clearDAG();
61 Sequence.clear();
62
63 // Invoke the target's selection of scheduler.
64 Schedule();
65 }
66
67 /// NewSUnit - Creates a new SUnit and return a ptr to it.
68 ///
newSUnit(SDNode * N)69 SUnit *ScheduleDAGSDNodes::newSUnit(SDNode *N) {
70 #ifndef NDEBUG
71 const SUnit *Addr = nullptr;
72 if (!SUnits.empty())
73 Addr = &SUnits[0];
74 #endif
75 SUnits.emplace_back(N, (unsigned)SUnits.size());
76 assert((Addr == nullptr || Addr == &SUnits[0]) &&
77 "SUnits std::vector reallocated on the fly!");
78 SUnits.back().OrigNode = &SUnits.back();
79 SUnit *SU = &SUnits.back();
80 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
81 if (!N ||
82 (N->isMachineOpcode() &&
83 N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF))
84 SU->SchedulingPref = Sched::None;
85 else
86 SU->SchedulingPref = TLI.getSchedulingPreference(N);
87 return SU;
88 }
89
Clone(SUnit * Old)90 SUnit *ScheduleDAGSDNodes::Clone(SUnit *Old) {
91 SUnit *SU = newSUnit(Old->getNode());
92 SU->OrigNode = Old->OrigNode;
93 SU->Latency = Old->Latency;
94 SU->isVRegCycle = Old->isVRegCycle;
95 SU->isCall = Old->isCall;
96 SU->isCallOp = Old->isCallOp;
97 SU->isTwoAddress = Old->isTwoAddress;
98 SU->isCommutable = Old->isCommutable;
99 SU->hasPhysRegDefs = Old->hasPhysRegDefs;
100 SU->hasPhysRegClobbers = Old->hasPhysRegClobbers;
101 SU->isScheduleHigh = Old->isScheduleHigh;
102 SU->isScheduleLow = Old->isScheduleLow;
103 SU->SchedulingPref = Old->SchedulingPref;
104 Old->isCloned = true;
105 return SU;
106 }
107
108 /// CheckForPhysRegDependency - Check if the dependency between def and use of
109 /// a specified operand is a physical register dependency. If so, returns the
110 /// register and the cost of copying the register.
CheckForPhysRegDependency(SDNode * Def,SDNode * User,unsigned Op,const TargetRegisterInfo * TRI,const TargetInstrInfo * TII,unsigned & PhysReg,int & Cost)111 static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op,
112 const TargetRegisterInfo *TRI,
113 const TargetInstrInfo *TII,
114 unsigned &PhysReg, int &Cost) {
115 if (Op != 2 || User->getOpcode() != ISD::CopyToReg)
116 return;
117
118 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
119 if (TargetRegisterInfo::isVirtualRegister(Reg))
120 return;
121
122 unsigned ResNo = User->getOperand(2).getResNo();
123 if (Def->getOpcode() == ISD::CopyFromReg &&
124 cast<RegisterSDNode>(Def->getOperand(1))->getReg() == Reg) {
125 PhysReg = Reg;
126 } else if (Def->isMachineOpcode()) {
127 const MCInstrDesc &II = TII->get(Def->getMachineOpcode());
128 if (ResNo >= II.getNumDefs() &&
129 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg)
130 PhysReg = Reg;
131 }
132
133 if (PhysReg != 0) {
134 const TargetRegisterClass *RC =
135 TRI->getMinimalPhysRegClass(Reg, Def->getSimpleValueType(ResNo));
136 Cost = RC->getCopyCost();
137 }
138 }
139
140 // Helper for AddGlue to clone node operands.
CloneNodeWithValues(SDNode * N,SelectionDAG * DAG,ArrayRef<EVT> VTs,SDValue ExtraOper=SDValue ())141 static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG, ArrayRef<EVT> VTs,
142 SDValue ExtraOper = SDValue()) {
143 SmallVector<SDValue, 8> Ops(N->op_begin(), N->op_end());
144 if (ExtraOper.getNode())
145 Ops.push_back(ExtraOper);
146
147 SDVTList VTList = DAG->getVTList(VTs);
148 MachineSDNode *MN = dyn_cast<MachineSDNode>(N);
149
150 // Store memory references.
151 SmallVector<MachineMemOperand *, 2> MMOs;
152 if (MN)
153 MMOs.assign(MN->memoperands_begin(), MN->memoperands_end());
154
155 DAG->MorphNodeTo(N, N->getOpcode(), VTList, Ops);
156
157 // Reset the memory references
158 if (MN)
159 DAG->setNodeMemRefs(MN, MMOs);
160 }
161
AddGlue(SDNode * N,SDValue Glue,bool AddGlue,SelectionDAG * DAG)162 static bool AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG) {
163 SDNode *GlueDestNode = Glue.getNode();
164
165 // Don't add glue from a node to itself.
166 if (GlueDestNode == N) return false;
167
168 // Don't add a glue operand to something that already uses glue.
169 if (GlueDestNode &&
170 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) {
171 return false;
172 }
173 // Don't add glue to something that already has a glue value.
174 if (N->getValueType(N->getNumValues() - 1) == MVT::Glue) return false;
175
176 SmallVector<EVT, 4> VTs(N->value_begin(), N->value_end());
177 if (AddGlue)
178 VTs.push_back(MVT::Glue);
179
180 CloneNodeWithValues(N, DAG, VTs, Glue);
181
182 return true;
183 }
184
185 // Cleanup after unsuccessful AddGlue. Use the standard method of morphing the
186 // node even though simply shrinking the value list is sufficient.
RemoveUnusedGlue(SDNode * N,SelectionDAG * DAG)187 static void RemoveUnusedGlue(SDNode *N, SelectionDAG *DAG) {
188 assert((N->getValueType(N->getNumValues() - 1) == MVT::Glue &&
189 !N->hasAnyUseOfValue(N->getNumValues() - 1)) &&
190 "expected an unused glue value");
191
192 CloneNodeWithValues(N, DAG,
193 makeArrayRef(N->value_begin(), N->getNumValues() - 1));
194 }
195
196 /// ClusterNeighboringLoads - Force nearby loads together by "gluing" them.
197 /// This function finds loads of the same base and different offsets. If the
198 /// offsets are not far apart (target specific), it add MVT::Glue inputs and
199 /// outputs to ensure they are scheduled together and in order. This
200 /// optimization may benefit some targets by improving cache locality.
ClusterNeighboringLoads(SDNode * Node)201 void ScheduleDAGSDNodes::ClusterNeighboringLoads(SDNode *Node) {
202 SDNode *Chain = nullptr;
203 unsigned NumOps = Node->getNumOperands();
204 if (Node->getOperand(NumOps-1).getValueType() == MVT::Other)
205 Chain = Node->getOperand(NumOps-1).getNode();
206 if (!Chain)
207 return;
208
209 // Look for other loads of the same chain. Find loads that are loading from
210 // the same base pointer and different offsets.
211 SmallPtrSet<SDNode*, 16> Visited;
212 SmallVector<int64_t, 4> Offsets;
213 DenseMap<long long, SDNode*> O2SMap; // Map from offset to SDNode.
214 bool Cluster = false;
215 SDNode *Base = Node;
216 // This algorithm requires a reasonably low use count before finding a match
217 // to avoid uselessly blowing up compile time in large blocks.
218 unsigned UseCount = 0;
219 for (SDNode::use_iterator I = Chain->use_begin(), E = Chain->use_end();
220 I != E && UseCount < 100; ++I, ++UseCount) {
221 SDNode *User = *I;
222 if (User == Node || !Visited.insert(User).second)
223 continue;
224 int64_t Offset1, Offset2;
225 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) ||
226 Offset1 == Offset2)
227 // FIXME: Should be ok if they addresses are identical. But earlier
228 // optimizations really should have eliminated one of the loads.
229 continue;
230 if (O2SMap.insert(std::make_pair(Offset1, Base)).second)
231 Offsets.push_back(Offset1);
232 O2SMap.insert(std::make_pair(Offset2, User));
233 Offsets.push_back(Offset2);
234 if (Offset2 < Offset1)
235 Base = User;
236 Cluster = true;
237 // Reset UseCount to allow more matches.
238 UseCount = 0;
239 }
240
241 if (!Cluster)
242 return;
243
244 // Sort them in increasing order.
245 llvm::sort(Offsets);
246
247 // Check if the loads are close enough.
248 SmallVector<SDNode*, 4> Loads;
249 unsigned NumLoads = 0;
250 int64_t BaseOff = Offsets[0];
251 SDNode *BaseLoad = O2SMap[BaseOff];
252 Loads.push_back(BaseLoad);
253 for (unsigned i = 1, e = Offsets.size(); i != e; ++i) {
254 int64_t Offset = Offsets[i];
255 SDNode *Load = O2SMap[Offset];
256 if (!TII->shouldScheduleLoadsNear(BaseLoad, Load, BaseOff, Offset,NumLoads))
257 break; // Stop right here. Ignore loads that are further away.
258 Loads.push_back(Load);
259 ++NumLoads;
260 }
261
262 if (NumLoads == 0)
263 return;
264
265 // Cluster loads by adding MVT::Glue outputs and inputs. This also
266 // ensure they are scheduled in order of increasing addresses.
267 SDNode *Lead = Loads[0];
268 SDValue InGlue = SDValue(nullptr, 0);
269 if (AddGlue(Lead, InGlue, true, DAG))
270 InGlue = SDValue(Lead, Lead->getNumValues() - 1);
271 for (unsigned I = 1, E = Loads.size(); I != E; ++I) {
272 bool OutGlue = I < E - 1;
273 SDNode *Load = Loads[I];
274
275 // If AddGlue fails, we could leave an unsused glue value. This should not
276 // cause any
277 if (AddGlue(Load, InGlue, OutGlue, DAG)) {
278 if (OutGlue)
279 InGlue = SDValue(Load, Load->getNumValues() - 1);
280
281 ++LoadsClustered;
282 }
283 else if (!OutGlue && InGlue.getNode())
284 RemoveUnusedGlue(InGlue.getNode(), DAG);
285 }
286 }
287
288 /// ClusterNodes - Cluster certain nodes which should be scheduled together.
289 ///
ClusterNodes()290 void ScheduleDAGSDNodes::ClusterNodes() {
291 for (SDNode &NI : DAG->allnodes()) {
292 SDNode *Node = &NI;
293 if (!Node || !Node->isMachineOpcode())
294 continue;
295
296 unsigned Opc = Node->getMachineOpcode();
297 const MCInstrDesc &MCID = TII->get(Opc);
298 if (MCID.mayLoad())
299 // Cluster loads from "near" addresses into combined SUnits.
300 ClusterNeighboringLoads(Node);
301 }
302 }
303
BuildSchedUnits()304 void ScheduleDAGSDNodes::BuildSchedUnits() {
305 // During scheduling, the NodeId field of SDNode is used to map SDNodes
306 // to their associated SUnits by holding SUnits table indices. A value
307 // of -1 means the SDNode does not yet have an associated SUnit.
308 unsigned NumNodes = 0;
309 for (SDNode &NI : DAG->allnodes()) {
310 NI.setNodeId(-1);
311 ++NumNodes;
312 }
313
314 // Reserve entries in the vector for each of the SUnits we are creating. This
315 // ensure that reallocation of the vector won't happen, so SUnit*'s won't get
316 // invalidated.
317 // FIXME: Multiply by 2 because we may clone nodes during scheduling.
318 // This is a temporary workaround.
319 SUnits.reserve(NumNodes * 2);
320
321 // Add all nodes in depth first order.
322 SmallVector<SDNode*, 64> Worklist;
323 SmallPtrSet<SDNode*, 32> Visited;
324 Worklist.push_back(DAG->getRoot().getNode());
325 Visited.insert(DAG->getRoot().getNode());
326
327 SmallVector<SUnit*, 8> CallSUnits;
328 while (!Worklist.empty()) {
329 SDNode *NI = Worklist.pop_back_val();
330
331 // Add all operands to the worklist unless they've already been added.
332 for (const SDValue &Op : NI->op_values())
333 if (Visited.insert(Op.getNode()).second)
334 Worklist.push_back(Op.getNode());
335
336 if (isPassiveNode(NI)) // Leaf node, e.g. a TargetImmediate.
337 continue;
338
339 // If this node has already been processed, stop now.
340 if (NI->getNodeId() != -1) continue;
341
342 SUnit *NodeSUnit = newSUnit(NI);
343
344 // See if anything is glued to this node, if so, add them to glued
345 // nodes. Nodes can have at most one glue input and one glue output. Glue
346 // is required to be the last operand and result of a node.
347
348 // Scan up to find glued preds.
349 SDNode *N = NI;
350 while (N->getNumOperands() &&
351 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) {
352 N = N->getOperand(N->getNumOperands()-1).getNode();
353 assert(N->getNodeId() == -1 && "Node already inserted!");
354 N->setNodeId(NodeSUnit->NodeNum);
355 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
356 NodeSUnit->isCall = true;
357 }
358
359 // Scan down to find any glued succs.
360 N = NI;
361 while (N->getValueType(N->getNumValues()-1) == MVT::Glue) {
362 SDValue GlueVal(N, N->getNumValues()-1);
363
364 // There are either zero or one users of the Glue result.
365 bool HasGlueUse = false;
366 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
367 UI != E; ++UI)
368 if (GlueVal.isOperandOf(*UI)) {
369 HasGlueUse = true;
370 assert(N->getNodeId() == -1 && "Node already inserted!");
371 N->setNodeId(NodeSUnit->NodeNum);
372 N = *UI;
373 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall())
374 NodeSUnit->isCall = true;
375 break;
376 }
377 if (!HasGlueUse) break;
378 }
379
380 if (NodeSUnit->isCall)
381 CallSUnits.push_back(NodeSUnit);
382
383 // Schedule zero-latency TokenFactor below any nodes that may increase the
384 // schedule height. Otherwise, ancestors of the TokenFactor may appear to
385 // have false stalls.
386 if (NI->getOpcode() == ISD::TokenFactor)
387 NodeSUnit->isScheduleLow = true;
388
389 // If there are glue operands involved, N is now the bottom-most node
390 // of the sequence of nodes that are glued together.
391 // Update the SUnit.
392 NodeSUnit->setNode(N);
393 assert(N->getNodeId() == -1 && "Node already inserted!");
394 N->setNodeId(NodeSUnit->NodeNum);
395
396 // Compute NumRegDefsLeft. This must be done before AddSchedEdges.
397 InitNumRegDefsLeft(NodeSUnit);
398
399 // Assign the Latency field of NodeSUnit using target-provided information.
400 computeLatency(NodeSUnit);
401 }
402
403 // Find all call operands.
404 while (!CallSUnits.empty()) {
405 SUnit *SU = CallSUnits.pop_back_val();
406 for (const SDNode *SUNode = SU->getNode(); SUNode;
407 SUNode = SUNode->getGluedNode()) {
408 if (SUNode->getOpcode() != ISD::CopyToReg)
409 continue;
410 SDNode *SrcN = SUNode->getOperand(2).getNode();
411 if (isPassiveNode(SrcN)) continue; // Not scheduled.
412 SUnit *SrcSU = &SUnits[SrcN->getNodeId()];
413 SrcSU->isCallOp = true;
414 }
415 }
416 }
417
AddSchedEdges()418 void ScheduleDAGSDNodes::AddSchedEdges() {
419 const TargetSubtargetInfo &ST = MF.getSubtarget();
420
421 // Check to see if the scheduler cares about latencies.
422 bool UnitLatencies = forceUnitLatencies();
423
424 // Pass 2: add the preds, succs, etc.
425 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
426 SUnit *SU = &SUnits[su];
427 SDNode *MainNode = SU->getNode();
428
429 if (MainNode->isMachineOpcode()) {
430 unsigned Opc = MainNode->getMachineOpcode();
431 const MCInstrDesc &MCID = TII->get(Opc);
432 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) {
433 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) {
434 SU->isTwoAddress = true;
435 break;
436 }
437 }
438 if (MCID.isCommutable())
439 SU->isCommutable = true;
440 }
441
442 // Find all predecessors and successors of the group.
443 for (SDNode *N = SU->getNode(); N; N = N->getGluedNode()) {
444 if (N->isMachineOpcode() &&
445 TII->get(N->getMachineOpcode()).getImplicitDefs()) {
446 SU->hasPhysRegClobbers = true;
447 unsigned NumUsed = InstrEmitter::CountResults(N);
448 while (NumUsed != 0 && !N->hasAnyUseOfValue(NumUsed - 1))
449 --NumUsed; // Skip over unused values at the end.
450 if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs())
451 SU->hasPhysRegDefs = true;
452 }
453
454 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
455 SDNode *OpN = N->getOperand(i).getNode();
456 if (isPassiveNode(OpN)) continue; // Not scheduled.
457 SUnit *OpSU = &SUnits[OpN->getNodeId()];
458 assert(OpSU && "Node has no SUnit!");
459 if (OpSU == SU) continue; // In the same group.
460
461 EVT OpVT = N->getOperand(i).getValueType();
462 assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!");
463 bool isChain = OpVT == MVT::Other;
464
465 unsigned PhysReg = 0;
466 int Cost = 1;
467 // Determine if this is a physical register dependency.
468 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
469 assert((PhysReg == 0 || !isChain) &&
470 "Chain dependence via physreg data?");
471 // FIXME: See ScheduleDAGSDNodes::EmitCopyFromReg. For now, scheduler
472 // emits a copy from the physical register to a virtual register unless
473 // it requires a cross class copy (cost < 0). That means we are only
474 // treating "expensive to copy" register dependency as physical register
475 // dependency. This may change in the future though.
476 if (Cost >= 0 && !StressSched)
477 PhysReg = 0;
478
479 // If this is a ctrl dep, latency is 1.
480 unsigned OpLatency = isChain ? 1 : OpSU->Latency;
481 // Special-case TokenFactor chains as zero-latency.
482 if(isChain && OpN->getOpcode() == ISD::TokenFactor)
483 OpLatency = 0;
484
485 SDep Dep = isChain ? SDep(OpSU, SDep::Barrier)
486 : SDep(OpSU, SDep::Data, PhysReg);
487 Dep.setLatency(OpLatency);
488 if (!isChain && !UnitLatencies) {
489 computeOperandLatency(OpN, N, i, Dep);
490 ST.adjustSchedDependency(OpSU, SU, Dep);
491 }
492
493 if (!SU->addPred(Dep) && !Dep.isCtrl() && OpSU->NumRegDefsLeft > 1) {
494 // Multiple register uses are combined in the same SUnit. For example,
495 // we could have a set of glued nodes with all their defs consumed by
496 // another set of glued nodes. Register pressure tracking sees this as
497 // a single use, so to keep pressure balanced we reduce the defs.
498 //
499 // We can't tell (without more book-keeping) if this results from
500 // glued nodes or duplicate operands. As long as we don't reduce
501 // NumRegDefsLeft to zero, we handle the common cases well.
502 --OpSU->NumRegDefsLeft;
503 }
504 }
505 }
506 }
507 }
508
509 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
510 /// are input. This SUnit graph is similar to the SelectionDAG, but
511 /// excludes nodes that aren't interesting to scheduling, and represents
512 /// glued together nodes with a single SUnit.
BuildSchedGraph(AliasAnalysis * AA)513 void ScheduleDAGSDNodes::BuildSchedGraph(AliasAnalysis *AA) {
514 // Cluster certain nodes which should be scheduled together.
515 ClusterNodes();
516 // Populate the SUnits array.
517 BuildSchedUnits();
518 // Compute all the scheduling dependencies between nodes.
519 AddSchedEdges();
520 }
521
522 // Initialize NumNodeDefs for the current Node's opcode.
InitNodeNumDefs()523 void ScheduleDAGSDNodes::RegDefIter::InitNodeNumDefs() {
524 // Check for phys reg copy.
525 if (!Node)
526 return;
527
528 if (!Node->isMachineOpcode()) {
529 if (Node->getOpcode() == ISD::CopyFromReg)
530 NodeNumDefs = 1;
531 else
532 NodeNumDefs = 0;
533 return;
534 }
535 unsigned POpc = Node->getMachineOpcode();
536 if (POpc == TargetOpcode::IMPLICIT_DEF) {
537 // No register need be allocated for this.
538 NodeNumDefs = 0;
539 return;
540 }
541 if (POpc == TargetOpcode::PATCHPOINT &&
542 Node->getValueType(0) == MVT::Other) {
543 // PATCHPOINT is defined to have one result, but it might really have none
544 // if we're not using CallingConv::AnyReg. Don't mistake the chain for a
545 // real definition.
546 NodeNumDefs = 0;
547 return;
548 }
549 unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs();
550 // Some instructions define regs that are not represented in the selection DAG
551 // (e.g. unused flags). See tMOVi8. Make sure we don't access past NumValues.
552 NodeNumDefs = std::min(Node->getNumValues(), NRegDefs);
553 DefIdx = 0;
554 }
555
556 // Construct a RegDefIter for this SUnit and find the first valid value.
RegDefIter(const SUnit * SU,const ScheduleDAGSDNodes * SD)557 ScheduleDAGSDNodes::RegDefIter::RegDefIter(const SUnit *SU,
558 const ScheduleDAGSDNodes *SD)
559 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) {
560 InitNodeNumDefs();
561 Advance();
562 }
563
564 // Advance to the next valid value defined by the SUnit.
Advance()565 void ScheduleDAGSDNodes::RegDefIter::Advance() {
566 for (;Node;) { // Visit all glued nodes.
567 for (;DefIdx < NodeNumDefs; ++DefIdx) {
568 if (!Node->hasAnyUseOfValue(DefIdx))
569 continue;
570 ValueType = Node->getSimpleValueType(DefIdx);
571 ++DefIdx;
572 return; // Found a normal regdef.
573 }
574 Node = Node->getGluedNode();
575 if (!Node) {
576 return; // No values left to visit.
577 }
578 InitNodeNumDefs();
579 }
580 }
581
InitNumRegDefsLeft(SUnit * SU)582 void ScheduleDAGSDNodes::InitNumRegDefsLeft(SUnit *SU) {
583 assert(SU->NumRegDefsLeft == 0 && "expect a new node");
584 for (RegDefIter I(SU, this); I.IsValid(); I.Advance()) {
585 assert(SU->NumRegDefsLeft < USHRT_MAX && "overflow is ok but unexpected");
586 ++SU->NumRegDefsLeft;
587 }
588 }
589
computeLatency(SUnit * SU)590 void ScheduleDAGSDNodes::computeLatency(SUnit *SU) {
591 SDNode *N = SU->getNode();
592
593 // TokenFactor operands are considered zero latency, and some schedulers
594 // (e.g. Top-Down list) may rely on the fact that operand latency is nonzero
595 // whenever node latency is nonzero.
596 if (N && N->getOpcode() == ISD::TokenFactor) {
597 SU->Latency = 0;
598 return;
599 }
600
601 // Check to see if the scheduler cares about latencies.
602 if (forceUnitLatencies()) {
603 SU->Latency = 1;
604 return;
605 }
606
607 if (!InstrItins || InstrItins->isEmpty()) {
608 if (N && N->isMachineOpcode() &&
609 TII->isHighLatencyDef(N->getMachineOpcode()))
610 SU->Latency = HighLatencyCycles;
611 else
612 SU->Latency = 1;
613 return;
614 }
615
616 // Compute the latency for the node. We use the sum of the latencies for
617 // all nodes glued together into this SUnit.
618 SU->Latency = 0;
619 for (SDNode *N = SU->getNode(); N; N = N->getGluedNode())
620 if (N->isMachineOpcode())
621 SU->Latency += TII->getInstrLatency(InstrItins, N);
622 }
623
computeOperandLatency(SDNode * Def,SDNode * Use,unsigned OpIdx,SDep & dep) const624 void ScheduleDAGSDNodes::computeOperandLatency(SDNode *Def, SDNode *Use,
625 unsigned OpIdx, SDep& dep) const{
626 // Check to see if the scheduler cares about latencies.
627 if (forceUnitLatencies())
628 return;
629
630 if (dep.getKind() != SDep::Data)
631 return;
632
633 unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
634 if (Use->isMachineOpcode())
635 // Adjust the use operand index by num of defs.
636 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs();
637 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
638 if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg &&
639 !BB->succ_empty()) {
640 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
641 if (TargetRegisterInfo::isVirtualRegister(Reg))
642 // This copy is a liveout value. It is likely coalesced, so reduce the
643 // latency so not to penalize the def.
644 // FIXME: need target specific adjustment here?
645 Latency = (Latency > 1) ? Latency - 1 : 1;
646 }
647 if (Latency >= 0)
648 dep.setLatency(Latency);
649 }
650
dumpNode(const SUnit & SU) const651 void ScheduleDAGSDNodes::dumpNode(const SUnit &SU) const {
652 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
653 dumpNodeName(SU);
654 dbgs() << ": ";
655
656 if (!SU.getNode()) {
657 dbgs() << "PHYS REG COPY\n";
658 return;
659 }
660
661 SU.getNode()->dump(DAG);
662 dbgs() << "\n";
663 SmallVector<SDNode *, 4> GluedNodes;
664 for (SDNode *N = SU.getNode()->getGluedNode(); N; N = N->getGluedNode())
665 GluedNodes.push_back(N);
666 while (!GluedNodes.empty()) {
667 dbgs() << " ";
668 GluedNodes.back()->dump(DAG);
669 dbgs() << "\n";
670 GluedNodes.pop_back();
671 }
672 #endif
673 }
674
dump() const675 void ScheduleDAGSDNodes::dump() const {
676 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
677 if (EntrySU.getNode() != nullptr)
678 dumpNodeAll(EntrySU);
679 for (const SUnit &SU : SUnits)
680 dumpNodeAll(SU);
681 if (ExitSU.getNode() != nullptr)
682 dumpNodeAll(ExitSU);
683 #endif
684 }
685
686 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
dumpSchedule() const687 void ScheduleDAGSDNodes::dumpSchedule() const {
688 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
689 if (SUnit *SU = Sequence[i])
690 dumpNode(*SU);
691 else
692 dbgs() << "**** NOOP ****\n";
693 }
694 }
695 #endif
696
697 #ifndef NDEBUG
698 /// VerifyScheduledSequence - Verify that all SUnits were scheduled and that
699 /// their state is consistent with the nodes listed in Sequence.
700 ///
VerifyScheduledSequence(bool isBottomUp)701 void ScheduleDAGSDNodes::VerifyScheduledSequence(bool isBottomUp) {
702 unsigned ScheduledNodes = ScheduleDAG::VerifyScheduledDAG(isBottomUp);
703 unsigned Noops = 0;
704 for (unsigned i = 0, e = Sequence.size(); i != e; ++i)
705 if (!Sequence[i])
706 ++Noops;
707 assert(Sequence.size() - Noops == ScheduledNodes &&
708 "The number of nodes scheduled doesn't match the expected number!");
709 }
710 #endif // NDEBUG
711
712 /// ProcessSDDbgValues - Process SDDbgValues associated with this node.
713 static void
ProcessSDDbgValues(SDNode * N,SelectionDAG * DAG,InstrEmitter & Emitter,SmallVectorImpl<std::pair<unsigned,MachineInstr * >> & Orders,DenseMap<SDValue,unsigned> & VRBaseMap,unsigned Order)714 ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
715 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders,
716 DenseMap<SDValue, unsigned> &VRBaseMap, unsigned Order) {
717 if (!N->getHasDebugValue())
718 return;
719
720 // Opportunistically insert immediate dbg_value uses, i.e. those with the same
721 // source order number as N.
722 MachineBasicBlock *BB = Emitter.getBlock();
723 MachineBasicBlock::iterator InsertPos = Emitter.getInsertPos();
724 for (auto DV : DAG->GetDbgValues(N)) {
725 if (DV->isEmitted())
726 continue;
727 unsigned DVOrder = DV->getOrder();
728 if (!Order || DVOrder == Order) {
729 MachineInstr *DbgMI = Emitter.EmitDbgValue(DV, VRBaseMap);
730 if (DbgMI) {
731 Orders.push_back({DVOrder, DbgMI});
732 BB->insert(InsertPos, DbgMI);
733 }
734 }
735 }
736 }
737
738 // ProcessSourceNode - Process nodes with source order numbers. These are added
739 // to a vector which EmitSchedule uses to determine how to insert dbg_value
740 // instructions in the right order.
741 static void
ProcessSourceNode(SDNode * N,SelectionDAG * DAG,InstrEmitter & Emitter,DenseMap<SDValue,unsigned> & VRBaseMap,SmallVectorImpl<std::pair<unsigned,MachineInstr * >> & Orders,SmallSet<unsigned,8> & Seen)742 ProcessSourceNode(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter,
743 DenseMap<SDValue, unsigned> &VRBaseMap,
744 SmallVectorImpl<std::pair<unsigned, MachineInstr*> > &Orders,
745 SmallSet<unsigned, 8> &Seen) {
746 unsigned Order = N->getIROrder();
747 if (!Order || !Seen.insert(Order).second) {
748 // Process any valid SDDbgValues even if node does not have any order
749 // assigned.
750 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, 0);
751 return;
752 }
753
754 MachineBasicBlock *BB = Emitter.getBlock();
755 auto IP = Emitter.getInsertPos();
756 if (IP == BB->begin() || BB->back().isPHI() ||
757 // Fast-isel may have inserted some instructions, in which case the
758 // BB->back().isPHI() test will not fire when we want it to.
759 std::prev(IP)->isPHI()) {
760 // Did not insert any instruction.
761 Orders.push_back({Order, (MachineInstr *)nullptr});
762 return;
763 }
764
765 Orders.push_back({Order, &*std::prev(IP)});
766 ProcessSDDbgValues(N, DAG, Emitter, Orders, VRBaseMap, Order);
767 }
768
769 void ScheduleDAGSDNodes::
EmitPhysRegCopy(SUnit * SU,DenseMap<SUnit *,unsigned> & VRBaseMap,MachineBasicBlock::iterator InsertPos)770 EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap,
771 MachineBasicBlock::iterator InsertPos) {
772 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
773 I != E; ++I) {
774 if (I->isCtrl()) continue; // ignore chain preds
775 if (I->getSUnit()->CopyDstRC) {
776 // Copy to physical register.
777 DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->getSUnit());
778 assert(VRI != VRBaseMap.end() && "Node emitted out of order - late");
779 // Find the destination physical register.
780 unsigned Reg = 0;
781 for (SUnit::const_succ_iterator II = SU->Succs.begin(),
782 EE = SU->Succs.end(); II != EE; ++II) {
783 if (II->isCtrl()) continue; // ignore chain preds
784 if (II->getReg()) {
785 Reg = II->getReg();
786 break;
787 }
788 }
789 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg)
790 .addReg(VRI->second);
791 } else {
792 // Copy from physical register.
793 assert(I->getReg() && "Unknown physical register!");
794 unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
795 bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
796 (void)isNew; // Silence compiler warning.
797 assert(isNew && "Node emitted out of order - early");
798 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), VRBase)
799 .addReg(I->getReg());
800 }
801 break;
802 }
803 }
804
805 /// EmitSchedule - Emit the machine code in scheduled order. Return the new
806 /// InsertPos and MachineBasicBlock that contains this insertion
807 /// point. ScheduleDAGSDNodes holds a BB pointer for convenience, but this does
808 /// not necessarily refer to returned BB. The emitter may split blocks.
809 MachineBasicBlock *ScheduleDAGSDNodes::
EmitSchedule(MachineBasicBlock::iterator & InsertPos)810 EmitSchedule(MachineBasicBlock::iterator &InsertPos) {
811 InstrEmitter Emitter(BB, InsertPos);
812 DenseMap<SDValue, unsigned> VRBaseMap;
813 DenseMap<SUnit*, unsigned> CopyVRBaseMap;
814 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;
815 SmallSet<unsigned, 8> Seen;
816 bool HasDbg = DAG->hasDebugValues();
817
818 // If this is the first BB, emit byval parameter dbg_value's.
819 if (HasDbg && BB->getParent()->begin() == MachineFunction::iterator(BB)) {
820 SDDbgInfo::DbgIterator PDI = DAG->ByvalParmDbgBegin();
821 SDDbgInfo::DbgIterator PDE = DAG->ByvalParmDbgEnd();
822 for (; PDI != PDE; ++PDI) {
823 MachineInstr *DbgMI= Emitter.EmitDbgValue(*PDI, VRBaseMap);
824 if (DbgMI) {
825 BB->insert(InsertPos, DbgMI);
826 // We re-emit the dbg_value closer to its use, too, after instructions
827 // are emitted to the BB.
828 (*PDI)->clearIsEmitted();
829 }
830 }
831 }
832
833 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
834 SUnit *SU = Sequence[i];
835 if (!SU) {
836 // Null SUnit* is a noop.
837 TII->insertNoop(*Emitter.getBlock(), InsertPos);
838 continue;
839 }
840
841 // For pre-regalloc scheduling, create instructions corresponding to the
842 // SDNode and any glued SDNodes and append them to the block.
843 if (!SU->getNode()) {
844 // Emit a copy.
845 EmitPhysRegCopy(SU, CopyVRBaseMap, InsertPos);
846 continue;
847 }
848
849 SmallVector<SDNode *, 4> GluedNodes;
850 for (SDNode *N = SU->getNode()->getGluedNode(); N; N = N->getGluedNode())
851 GluedNodes.push_back(N);
852 while (!GluedNodes.empty()) {
853 SDNode *N = GluedNodes.back();
854 Emitter.EmitNode(N, SU->OrigNode != SU, SU->isCloned, VRBaseMap);
855 // Remember the source order of the inserted instruction.
856 if (HasDbg)
857 ProcessSourceNode(N, DAG, Emitter, VRBaseMap, Orders, Seen);
858 GluedNodes.pop_back();
859 }
860 Emitter.EmitNode(SU->getNode(), SU->OrigNode != SU, SU->isCloned,
861 VRBaseMap);
862 // Remember the source order of the inserted instruction.
863 if (HasDbg)
864 ProcessSourceNode(SU->getNode(), DAG, Emitter, VRBaseMap, Orders,
865 Seen);
866 }
867
868 // Insert all the dbg_values which have not already been inserted in source
869 // order sequence.
870 if (HasDbg) {
871 MachineBasicBlock::iterator BBBegin = BB->getFirstNonPHI();
872
873 // Sort the source order instructions and use the order to insert debug
874 // values. Use stable_sort so that DBG_VALUEs are inserted in the same order
875 // regardless of the host's implementation fo std::sort.
876 std::stable_sort(Orders.begin(), Orders.end(), less_first());
877 std::stable_sort(DAG->DbgBegin(), DAG->DbgEnd(),
878 [](const SDDbgValue *LHS, const SDDbgValue *RHS) {
879 return LHS->getOrder() < RHS->getOrder();
880 });
881
882 SDDbgInfo::DbgIterator DI = DAG->DbgBegin();
883 SDDbgInfo::DbgIterator DE = DAG->DbgEnd();
884 // Now emit the rest according to source order.
885 unsigned LastOrder = 0;
886 for (unsigned i = 0, e = Orders.size(); i != e && DI != DE; ++i) {
887 unsigned Order = Orders[i].first;
888 MachineInstr *MI = Orders[i].second;
889 // Insert all SDDbgValue's whose order(s) are before "Order".
890 if (!MI)
891 continue;
892 for (; DI != DE; ++DI) {
893 if ((*DI)->getOrder() < LastOrder || (*DI)->getOrder() >= Order)
894 break;
895 if ((*DI)->isEmitted())
896 continue;
897
898 MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap);
899 if (DbgMI) {
900 if (!LastOrder)
901 // Insert to start of the BB (after PHIs).
902 BB->insert(BBBegin, DbgMI);
903 else {
904 // Insert at the instruction, which may be in a different
905 // block, if the block was split by a custom inserter.
906 MachineBasicBlock::iterator Pos = MI;
907 MI->getParent()->insert(Pos, DbgMI);
908 }
909 }
910 }
911 LastOrder = Order;
912 }
913 // Add trailing DbgValue's before the terminator. FIXME: May want to add
914 // some of them before one or more conditional branches?
915 SmallVector<MachineInstr*, 8> DbgMIs;
916 for (; DI != DE; ++DI) {
917 if ((*DI)->isEmitted())
918 continue;
919 assert((*DI)->getOrder() >= LastOrder &&
920 "emitting DBG_VALUE out of order");
921 if (MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap))
922 DbgMIs.push_back(DbgMI);
923 }
924
925 MachineBasicBlock *InsertBB = Emitter.getBlock();
926 MachineBasicBlock::iterator Pos = InsertBB->getFirstTerminator();
927 InsertBB->insert(Pos, DbgMIs.begin(), DbgMIs.end());
928
929 SDDbgInfo::DbgLabelIterator DLI = DAG->DbgLabelBegin();
930 SDDbgInfo::DbgLabelIterator DLE = DAG->DbgLabelEnd();
931 // Now emit the rest according to source order.
932 LastOrder = 0;
933 for (const auto &InstrOrder : Orders) {
934 unsigned Order = InstrOrder.first;
935 MachineInstr *MI = InstrOrder.second;
936 if (!MI)
937 continue;
938
939 // Insert all SDDbgLabel's whose order(s) are before "Order".
940 for (; DLI != DLE &&
941 (*DLI)->getOrder() >= LastOrder && (*DLI)->getOrder() < Order;
942 ++DLI) {
943 MachineInstr *DbgMI = Emitter.EmitDbgLabel(*DLI);
944 if (DbgMI) {
945 if (!LastOrder)
946 // Insert to start of the BB (after PHIs).
947 BB->insert(BBBegin, DbgMI);
948 else {
949 // Insert at the instruction, which may be in a different
950 // block, if the block was split by a custom inserter.
951 MachineBasicBlock::iterator Pos = MI;
952 MI->getParent()->insert(Pos, DbgMI);
953 }
954 }
955 }
956 if (DLI == DLE)
957 break;
958
959 LastOrder = Order;
960 }
961 }
962
963 InsertPos = Emitter.getInsertPos();
964 return Emitter.getBlock();
965 }
966
967 /// Return the basic block label.
getDAGName() const968 std::string ScheduleDAGSDNodes::getDAGName() const {
969 return "sunit-dag." + BB->getFullName();
970 }
971