1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "AArch64TargetMachine.h"
14 #include "AArch64.h"
15 #include "AArch64MacroFusion.h"
16 #include "AArch64Subtarget.h"
17 #include "AArch64TargetObjectFile.h"
18 #include "AArch64TargetTransformInfo.h"
19 #include "MCTargetDesc/AArch64MCTargetDesc.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
24 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
25 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
26 #include "llvm/CodeGen/GlobalISel/Localizer.h"
27 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
28 #include "llvm/CodeGen/MachineScheduler.h"
29 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/CodeGen/TargetPassConfig.h"
31 #include "llvm/IR/Attributes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCTargetOptions.h"
35 #include "llvm/Pass.h"
36 #include "llvm/Support/CodeGen.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/TargetRegistry.h"
39 #include "llvm/Target/TargetLoweringObjectFile.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/Transforms/Scalar.h"
42 #include <memory>
43 #include <string>
44
45 using namespace llvm;
46
47 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
48 cl::desc("Enable the CCMP formation pass"),
49 cl::init(true), cl::Hidden);
50
51 static cl::opt<bool>
52 EnableCondBrTuning("aarch64-enable-cond-br-tune",
53 cl::desc("Enable the conditional branch tuning pass"),
54 cl::init(true), cl::Hidden);
55
56 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
57 cl::desc("Enable the machine combiner pass"),
58 cl::init(true), cl::Hidden);
59
60 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
61 cl::desc("Suppress STP for AArch64"),
62 cl::init(true), cl::Hidden);
63
64 static cl::opt<bool> EnableAdvSIMDScalar(
65 "aarch64-enable-simd-scalar",
66 cl::desc("Enable use of AdvSIMD scalar integer instructions"),
67 cl::init(false), cl::Hidden);
68
69 static cl::opt<bool>
70 EnablePromoteConstant("aarch64-enable-promote-const",
71 cl::desc("Enable the promote constant pass"),
72 cl::init(true), cl::Hidden);
73
74 static cl::opt<bool> EnableCollectLOH(
75 "aarch64-enable-collect-loh",
76 cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
77 cl::init(true), cl::Hidden);
78
79 static cl::opt<bool>
80 EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
81 cl::desc("Enable the pass that removes dead"
82 " definitons and replaces stores to"
83 " them with stores to the zero"
84 " register"),
85 cl::init(true));
86
87 static cl::opt<bool> EnableRedundantCopyElimination(
88 "aarch64-enable-copyelim",
89 cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
90 cl::Hidden);
91
92 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
93 cl::desc("Enable the load/store pair"
94 " optimization pass"),
95 cl::init(true), cl::Hidden);
96
97 static cl::opt<bool> EnableAtomicTidy(
98 "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
99 cl::desc("Run SimplifyCFG after expanding atomic operations"
100 " to make use of cmpxchg flow-based information"),
101 cl::init(true));
102
103 static cl::opt<bool>
104 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
105 cl::desc("Run early if-conversion"),
106 cl::init(true));
107
108 static cl::opt<bool>
109 EnableCondOpt("aarch64-enable-condopt",
110 cl::desc("Enable the condition optimizer pass"),
111 cl::init(true), cl::Hidden);
112
113 static cl::opt<bool>
114 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
115 cl::desc("Work around Cortex-A53 erratum 835769"),
116 cl::init(false));
117
118 static cl::opt<bool>
119 EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
120 cl::desc("Enable optimizations on complex GEPs"),
121 cl::init(false));
122
123 static cl::opt<bool>
124 BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
125 cl::desc("Relax out of range conditional branches"));
126
127 static cl::opt<bool> EnableCompressJumpTables(
128 "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
129 cl::desc("Use smallest entry possible for jump tables"));
130
131 // FIXME: Unify control over GlobalMerge.
132 static cl::opt<cl::boolOrDefault>
133 EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
134 cl::desc("Enable the global merge pass"));
135
136 static cl::opt<bool>
137 EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
138 cl::desc("Enable the loop data prefetch pass"),
139 cl::init(true));
140
141 static cl::opt<int> EnableGlobalISelAtO(
142 "aarch64-enable-global-isel-at-O", cl::Hidden,
143 cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
144 cl::init(0));
145
146 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
147 cl::init(true), cl::Hidden);
148
149 static cl::opt<bool>
150 EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
151 cl::desc("Enable the AAcrh64 branch target pass"),
152 cl::init(true));
153
LLVMInitializeAArch64Target()154 extern "C" void LLVMInitializeAArch64Target() {
155 // Register the target.
156 RegisterTargetMachine<AArch64leTargetMachine> X(getTheAArch64leTarget());
157 RegisterTargetMachine<AArch64beTargetMachine> Y(getTheAArch64beTarget());
158 RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
159 auto PR = PassRegistry::getPassRegistry();
160 initializeGlobalISel(*PR);
161 initializeAArch64A53Fix835769Pass(*PR);
162 initializeAArch64A57FPLoadBalancingPass(*PR);
163 initializeAArch64AdvSIMDScalarPass(*PR);
164 initializeAArch64BranchTargetsPass(*PR);
165 initializeAArch64CollectLOHPass(*PR);
166 initializeAArch64CompressJumpTablesPass(*PR);
167 initializeAArch64ConditionalComparesPass(*PR);
168 initializeAArch64ConditionOptimizerPass(*PR);
169 initializeAArch64DeadRegisterDefinitionsPass(*PR);
170 initializeAArch64ExpandPseudoPass(*PR);
171 initializeAArch64LoadStoreOptPass(*PR);
172 initializeAArch64SIMDInstrOptPass(*PR);
173 initializeAArch64PreLegalizerCombinerPass(*PR);
174 initializeAArch64PromoteConstantPass(*PR);
175 initializeAArch64RedundantCopyEliminationPass(*PR);
176 initializeAArch64StorePairSuppressPass(*PR);
177 initializeFalkorHWPFFixPass(*PR);
178 initializeFalkorMarkStridedAccessesLegacyPass(*PR);
179 initializeLDTLSCleanupPass(*PR);
180 initializeAArch64SpeculationHardeningPass(*PR);
181 }
182
183 //===----------------------------------------------------------------------===//
184 // AArch64 Lowering public interface.
185 //===----------------------------------------------------------------------===//
createTLOF(const Triple & TT)186 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
187 if (TT.isOSBinFormatMachO())
188 return llvm::make_unique<AArch64_MachoTargetObjectFile>();
189 if (TT.isOSBinFormatCOFF())
190 return llvm::make_unique<AArch64_COFFTargetObjectFile>();
191
192 return llvm::make_unique<AArch64_ELFTargetObjectFile>();
193 }
194
195 // Helper function to build a DataLayout string
computeDataLayout(const Triple & TT,const MCTargetOptions & Options,bool LittleEndian)196 static std::string computeDataLayout(const Triple &TT,
197 const MCTargetOptions &Options,
198 bool LittleEndian) {
199 if (Options.getABIName() == "ilp32")
200 return "e-m:e-p:32:32-i8:8-i16:16-i64:64-S128";
201 if (TT.isOSBinFormatMachO())
202 return "e-m:o-i64:64-i128:128-n32:64-S128";
203 if (TT.isOSBinFormatCOFF())
204 return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
205 if (LittleEndian)
206 return "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
207 return "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
208 }
209
getEffectiveRelocModel(const Triple & TT,Optional<Reloc::Model> RM)210 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
211 Optional<Reloc::Model> RM) {
212 // AArch64 Darwin and Windows are always PIC.
213 if (TT.isOSDarwin() || TT.isOSWindows())
214 return Reloc::PIC_;
215 // On ELF platforms the default static relocation model has a smart enough
216 // linker to cope with referencing external symbols defined in a shared
217 // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
218 if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
219 return Reloc::Static;
220 return *RM;
221 }
222
223 static CodeModel::Model
getEffectiveAArch64CodeModel(const Triple & TT,Optional<CodeModel::Model> CM,bool JIT)224 getEffectiveAArch64CodeModel(const Triple &TT, Optional<CodeModel::Model> CM,
225 bool JIT) {
226 if (CM) {
227 if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
228 *CM != CodeModel::Large) {
229 if (!TT.isOSFuchsia())
230 report_fatal_error(
231 "Only small, tiny and large code models are allowed on AArch64");
232 else if (*CM != CodeModel::Kernel)
233 report_fatal_error("Only small, tiny, kernel, and large code models "
234 "are allowed on AArch64");
235 } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
236 report_fatal_error("tiny code model is only supported on ELF");
237 return *CM;
238 }
239 // The default MCJIT memory managers make no guarantees about where they can
240 // find an executable page; JITed code needs to be able to refer to globals
241 // no matter how far away they are.
242 if (JIT)
243 return CodeModel::Large;
244 return CodeModel::Small;
245 }
246
247 /// Create an AArch64 architecture model.
248 ///
AArch64TargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,Optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT,bool LittleEndian)249 AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
250 StringRef CPU, StringRef FS,
251 const TargetOptions &Options,
252 Optional<Reloc::Model> RM,
253 Optional<CodeModel::Model> CM,
254 CodeGenOpt::Level OL, bool JIT,
255 bool LittleEndian)
256 : LLVMTargetMachine(T,
257 computeDataLayout(TT, Options.MCOptions, LittleEndian),
258 TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM),
259 getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
260 TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
261 initAsmInfo();
262
263 if (TT.isOSBinFormatMachO()) {
264 this->Options.TrapUnreachable = true;
265 this->Options.NoTrapAfterNoreturn = true;
266 }
267
268 if (getMCAsmInfo()->usesWindowsCFI()) {
269 // Unwinding can get confused if the last instruction in an
270 // exception-handling region (function, funclet, try block, etc.)
271 // is a call.
272 //
273 // FIXME: We could elide the trap if the next instruction would be in
274 // the same region anyway.
275 this->Options.TrapUnreachable = true;
276 }
277
278 // Enable GlobalISel at or below EnableGlobalISelAt0.
279 if (getOptLevel() <= EnableGlobalISelAtO) {
280 setGlobalISel(true);
281 setGlobalISelAbort(GlobalISelAbortMode::Disable);
282 }
283
284 // AArch64 supports the MachineOutliner.
285 setMachineOutliner(true);
286
287 // AArch64 supports default outlining behaviour.
288 setSupportsDefaultOutlining(true);
289 }
290
291 AArch64TargetMachine::~AArch64TargetMachine() = default;
292
293 const AArch64Subtarget *
getSubtargetImpl(const Function & F) const294 AArch64TargetMachine::getSubtargetImpl(const Function &F) const {
295 Attribute CPUAttr = F.getFnAttribute("target-cpu");
296 Attribute FSAttr = F.getFnAttribute("target-features");
297
298 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
299 ? CPUAttr.getValueAsString().str()
300 : TargetCPU;
301 std::string FS = !FSAttr.hasAttribute(Attribute::None)
302 ? FSAttr.getValueAsString().str()
303 : TargetFS;
304
305 auto &I = SubtargetMap[CPU + FS];
306 if (!I) {
307 // This needs to be done before we create a new subtarget since any
308 // creation will depend on the TM and the code generation flags on the
309 // function that reside in TargetOptions.
310 resetTargetOptions(F);
311 I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
312 isLittle);
313 }
314 return I.get();
315 }
316
anchor()317 void AArch64leTargetMachine::anchor() { }
318
AArch64leTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,Optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT)319 AArch64leTargetMachine::AArch64leTargetMachine(
320 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
321 const TargetOptions &Options, Optional<Reloc::Model> RM,
322 Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
323 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
324
anchor()325 void AArch64beTargetMachine::anchor() { }
326
AArch64beTargetMachine(const Target & T,const Triple & TT,StringRef CPU,StringRef FS,const TargetOptions & Options,Optional<Reloc::Model> RM,Optional<CodeModel::Model> CM,CodeGenOpt::Level OL,bool JIT)327 AArch64beTargetMachine::AArch64beTargetMachine(
328 const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
329 const TargetOptions &Options, Optional<Reloc::Model> RM,
330 Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT)
331 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
332
333 namespace {
334
335 /// AArch64 Code Generator Pass Configuration Options.
336 class AArch64PassConfig : public TargetPassConfig {
337 public:
AArch64PassConfig(AArch64TargetMachine & TM,PassManagerBase & PM)338 AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
339 : TargetPassConfig(TM, PM) {
340 if (TM.getOptLevel() != CodeGenOpt::None)
341 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
342 }
343
getAArch64TargetMachine() const344 AArch64TargetMachine &getAArch64TargetMachine() const {
345 return getTM<AArch64TargetMachine>();
346 }
347
348 ScheduleDAGInstrs *
createMachineScheduler(MachineSchedContext * C) const349 createMachineScheduler(MachineSchedContext *C) const override {
350 const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
351 ScheduleDAGMILive *DAG = createGenericSchedLive(C);
352 DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
353 DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
354 if (ST.hasFusion())
355 DAG->addMutation(createAArch64MacroFusionDAGMutation());
356 return DAG;
357 }
358
359 ScheduleDAGInstrs *
createPostMachineScheduler(MachineSchedContext * C) const360 createPostMachineScheduler(MachineSchedContext *C) const override {
361 const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
362 if (ST.hasFusion()) {
363 // Run the Macro Fusion after RA again since literals are expanded from
364 // pseudos then (v. addPreSched2()).
365 ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
366 DAG->addMutation(createAArch64MacroFusionDAGMutation());
367 return DAG;
368 }
369
370 return nullptr;
371 }
372
373 void addIRPasses() override;
374 bool addPreISel() override;
375 bool addInstSelector() override;
376 bool addIRTranslator() override;
377 void addPreLegalizeMachineIR() override;
378 bool addLegalizeMachineIR() override;
379 bool addRegBankSelect() override;
380 void addPreGlobalInstructionSelect() override;
381 bool addGlobalInstructionSelect() override;
382 bool addILPOpts() override;
383 void addPreRegAlloc() override;
384 void addPostRegAlloc() override;
385 void addPreSched2() override;
386 void addPreEmitPass() override;
387 };
388
389 } // end anonymous namespace
390
391 TargetTransformInfo
getTargetTransformInfo(const Function & F)392 AArch64TargetMachine::getTargetTransformInfo(const Function &F) {
393 return TargetTransformInfo(AArch64TTIImpl(this, F));
394 }
395
createPassConfig(PassManagerBase & PM)396 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
397 return new AArch64PassConfig(*this, PM);
398 }
399
addIRPasses()400 void AArch64PassConfig::addIRPasses() {
401 // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
402 // ourselves.
403 addPass(createAtomicExpandPass());
404
405 // Cmpxchg instructions are often used with a subsequent comparison to
406 // determine whether it succeeded. We can exploit existing control-flow in
407 // ldrex/strex loops to simplify this, but it needs tidying up.
408 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
409 addPass(createCFGSimplificationPass(1, true, true, false, true));
410
411 // Run LoopDataPrefetch
412 //
413 // Run this before LSR to remove the multiplies involved in computing the
414 // pointer values N iterations ahead.
415 if (TM->getOptLevel() != CodeGenOpt::None) {
416 if (EnableLoopDataPrefetch)
417 addPass(createLoopDataPrefetchPass());
418 if (EnableFalkorHWPFFix)
419 addPass(createFalkorMarkStridedAccessesPass());
420 }
421
422 TargetPassConfig::addIRPasses();
423
424 // Match interleaved memory accesses to ldN/stN intrinsics.
425 if (TM->getOptLevel() != CodeGenOpt::None) {
426 addPass(createInterleavedLoadCombinePass());
427 addPass(createInterleavedAccessPass());
428 }
429
430 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
431 // Call SeparateConstOffsetFromGEP pass to extract constants within indices
432 // and lower a GEP with multiple indices to either arithmetic operations or
433 // multiple GEPs with single index.
434 addPass(createSeparateConstOffsetFromGEPPass(true));
435 // Call EarlyCSE pass to find and remove subexpressions in the lowered
436 // result.
437 addPass(createEarlyCSEPass());
438 // Do loop invariant code motion in case part of the lowered result is
439 // invariant.
440 addPass(createLICMPass());
441 }
442 }
443
444 // Pass Pipeline Configuration
addPreISel()445 bool AArch64PassConfig::addPreISel() {
446 // Run promote constant before global merge, so that the promoted constants
447 // get a chance to be merged
448 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
449 addPass(createAArch64PromoteConstantPass());
450 // FIXME: On AArch64, this depends on the type.
451 // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
452 // and the offset has to be a multiple of the related size in bytes.
453 if ((TM->getOptLevel() != CodeGenOpt::None &&
454 EnableGlobalMerge == cl::BOU_UNSET) ||
455 EnableGlobalMerge == cl::BOU_TRUE) {
456 bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
457 (EnableGlobalMerge == cl::BOU_UNSET);
458 addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize));
459 }
460
461 return false;
462 }
463
addInstSelector()464 bool AArch64PassConfig::addInstSelector() {
465 addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
466
467 // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
468 // references to _TLS_MODULE_BASE_ as possible.
469 if (TM->getTargetTriple().isOSBinFormatELF() &&
470 getOptLevel() != CodeGenOpt::None)
471 addPass(createAArch64CleanupLocalDynamicTLSPass());
472
473 return false;
474 }
475
addIRTranslator()476 bool AArch64PassConfig::addIRTranslator() {
477 addPass(new IRTranslator());
478 return false;
479 }
480
addPreLegalizeMachineIR()481 void AArch64PassConfig::addPreLegalizeMachineIR() {
482 addPass(createAArch64PreLegalizeCombiner());
483 }
484
addLegalizeMachineIR()485 bool AArch64PassConfig::addLegalizeMachineIR() {
486 addPass(new Legalizer());
487 return false;
488 }
489
addRegBankSelect()490 bool AArch64PassConfig::addRegBankSelect() {
491 addPass(new RegBankSelect());
492 return false;
493 }
494
addPreGlobalInstructionSelect()495 void AArch64PassConfig::addPreGlobalInstructionSelect() {
496 // Workaround the deficiency of the fast register allocator.
497 if (TM->getOptLevel() == CodeGenOpt::None)
498 addPass(new Localizer());
499 }
500
addGlobalInstructionSelect()501 bool AArch64PassConfig::addGlobalInstructionSelect() {
502 addPass(new InstructionSelect());
503 return false;
504 }
505
addILPOpts()506 bool AArch64PassConfig::addILPOpts() {
507 if (EnableCondOpt)
508 addPass(createAArch64ConditionOptimizerPass());
509 if (EnableCCMP)
510 addPass(createAArch64ConditionalCompares());
511 if (EnableMCR)
512 addPass(&MachineCombinerID);
513 if (EnableCondBrTuning)
514 addPass(createAArch64CondBrTuning());
515 if (EnableEarlyIfConversion)
516 addPass(&EarlyIfConverterID);
517 if (EnableStPairSuppress)
518 addPass(createAArch64StorePairSuppressPass());
519 addPass(createAArch64SIMDInstrOptPass());
520 return true;
521 }
522
addPreRegAlloc()523 void AArch64PassConfig::addPreRegAlloc() {
524 // Change dead register definitions to refer to the zero register.
525 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
526 addPass(createAArch64DeadRegisterDefinitions());
527
528 // Use AdvSIMD scalar instructions whenever profitable.
529 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
530 addPass(createAArch64AdvSIMDScalar());
531 // The AdvSIMD pass may produce copies that can be rewritten to
532 // be register coaleascer friendly.
533 addPass(&PeepholeOptimizerID);
534 }
535 }
536
addPostRegAlloc()537 void AArch64PassConfig::addPostRegAlloc() {
538 // Remove redundant copy instructions.
539 if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
540 addPass(createAArch64RedundantCopyEliminationPass());
541
542 if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
543 // Improve performance for some FP/SIMD code for A57.
544 addPass(createAArch64A57FPLoadBalancing());
545 }
546
addPreSched2()547 void AArch64PassConfig::addPreSched2() {
548 // Expand some pseudo instructions to allow proper scheduling.
549 addPass(createAArch64ExpandPseudoPass());
550 // Use load/store pair instructions when possible.
551 if (TM->getOptLevel() != CodeGenOpt::None) {
552 if (EnableLoadStoreOpt)
553 addPass(createAArch64LoadStoreOptimizationPass());
554 }
555
556 // The AArch64SpeculationHardeningPass destroys dominator tree and natural
557 // loop info, which is needed for the FalkorHWPFFixPass and also later on.
558 // Therefore, run the AArch64SpeculationHardeningPass before the
559 // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
560 // info.
561 addPass(createAArch64SpeculationHardeningPass());
562
563 if (TM->getOptLevel() != CodeGenOpt::None) {
564 if (EnableFalkorHWPFFix)
565 addPass(createFalkorHWPFFixPass());
566 }
567 }
568
addPreEmitPass()569 void AArch64PassConfig::addPreEmitPass() {
570 // Machine Block Placement might have created new opportunities when run
571 // at O3, where the Tail Duplication Threshold is set to 4 instructions.
572 // Run the load/store optimizer once more.
573 if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt)
574 addPass(createAArch64LoadStoreOptimizationPass());
575
576 if (EnableA53Fix835769)
577 addPass(createAArch64A53Fix835769());
578 // Relax conditional branch instructions if they're otherwise out of
579 // range of their destination.
580 if (BranchRelaxation)
581 addPass(&BranchRelaxationPassID);
582
583 if (EnableBranchTargets)
584 addPass(createAArch64BranchTargetsPass());
585
586 if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
587 addPass(createAArch64CompressJumpTablesPass());
588
589 if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
590 TM->getTargetTriple().isOSBinFormatMachO())
591 addPass(createAArch64CollectLOHPass());
592 }
593