1//===-- AMDGPU.td - AMDGPU Tablegen files --------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===------------------------------------------------------------===//
9
10include "llvm/TableGen/SearchableTable.td"
11include "llvm/Target/Target.td"
12include "AMDGPUFeatures.td"
13
14class BoolToList<bit Value> {
15  list<int> ret = !if(Value, [1]<int>, []<int>);
16}
17
18//===------------------------------------------------------------===//
19// Subtarget Features (device properties)
20//===------------------------------------------------------------===//
21
22def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
23  "FastFMAF32",
24  "true",
25  "Assuming f32 fma is at least as fast as mul + add"
26>;
27
28def FeatureMIMG_R128 : SubtargetFeature<"mimg-r128",
29  "MIMG_R128",
30  "true",
31  "Support 128-bit texture resources"
32>;
33
34def HalfRate64Ops : SubtargetFeature<"half-rate-64-ops",
35  "HalfRate64Ops",
36  "true",
37  "Most fp64 instructions are half rate instead of quarter"
38>;
39
40def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
41  "FlatAddressSpace",
42  "true",
43  "Support flat address space"
44>;
45
46def FeatureFlatInstOffsets : SubtargetFeature<"flat-inst-offsets",
47  "FlatInstOffsets",
48  "true",
49  "Flat instructions have immediate offset addressing mode"
50>;
51
52def FeatureFlatGlobalInsts : SubtargetFeature<"flat-global-insts",
53  "FlatGlobalInsts",
54  "true",
55  "Have global_* flat memory instructions"
56>;
57
58def FeatureFlatScratchInsts : SubtargetFeature<"flat-scratch-insts",
59  "FlatScratchInsts",
60  "true",
61  "Have scratch_* flat memory instructions"
62>;
63
64def FeatureAddNoCarryInsts : SubtargetFeature<"add-no-carry-insts",
65  "AddNoCarryInsts",
66  "true",
67  "Have VALU add/sub instructions without carry out"
68>;
69
70def FeatureUnalignedBufferAccess : SubtargetFeature<"unaligned-buffer-access",
71  "UnalignedBufferAccess",
72  "true",
73  "Support unaligned global loads and stores"
74>;
75
76def FeatureTrapHandler: SubtargetFeature<"trap-handler",
77  "TrapHandler",
78  "true",
79  "Trap handler support"
80>;
81
82def FeatureUnalignedScratchAccess : SubtargetFeature<"unaligned-scratch-access",
83  "UnalignedScratchAccess",
84  "true",
85  "Support unaligned scratch loads and stores"
86>;
87
88def FeatureApertureRegs : SubtargetFeature<"aperture-regs",
89  "HasApertureRegs",
90  "true",
91  "Has Memory Aperture Base and Size Registers"
92>;
93
94def FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts",
95  "HasMadMixInsts",
96  "true",
97  "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
98>;
99
100def FeatureFmaMixInsts : SubtargetFeature<"fma-mix-insts",
101  "HasFmaMixInsts",
102  "true",
103  "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
104>;
105
106// XNACK is disabled if SH_MEM_CONFIG.ADDRESS_MODE = GPUVM on chips that support
107// XNACK. The current default kernel driver setting is:
108// - graphics ring: XNACK disabled
109// - compute ring: XNACK enabled
110//
111// If XNACK is enabled, the VMEM latency can be worse.
112// If XNACK is disabled, the 2 SGPRs can be used for general purposes.
113def FeatureXNACK : SubtargetFeature<"xnack",
114  "EnableXNACK",
115  "true",
116  "Enable XNACK support"
117>;
118
119def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
120  "SGPRInitBug",
121  "true",
122  "VI SGPR initialization bug requiring a fixed SGPR allocation size"
123>;
124
125class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
126  "ldsbankcount"#Value,
127  "LDSBankCount",
128  !cast<string>(Value),
129  "The number of LDS banks per compute unit."
130>;
131
132def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
133def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
134
135def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
136  "GCN3Encoding",
137  "true",
138  "Encoding format for VI"
139>;
140
141def FeatureCIInsts : SubtargetFeature<"ci-insts",
142  "CIInsts",
143  "true",
144  "Additional instructions for CI+"
145>;
146
147def FeatureVIInsts : SubtargetFeature<"vi-insts",
148  "VIInsts",
149  "true",
150  "Additional instructions for VI+"
151>;
152
153def FeatureGFX9Insts : SubtargetFeature<"gfx9-insts",
154  "GFX9Insts",
155  "true",
156  "Additional instructions for GFX9+"
157>;
158
159def FeatureSMemRealTime : SubtargetFeature<"s-memrealtime",
160  "HasSMemRealTime",
161  "true",
162  "Has s_memrealtime instruction"
163>;
164
165def FeatureInv2PiInlineImm : SubtargetFeature<"inv-2pi-inline-imm",
166  "HasInv2PiInlineImm",
167  "true",
168  "Has 1 / (2 * pi) as inline immediate"
169>;
170
171def Feature16BitInsts : SubtargetFeature<"16-bit-insts",
172  "Has16BitInsts",
173  "true",
174  "Has i16/f16 instructions"
175>;
176
177def FeatureVOP3P : SubtargetFeature<"vop3p",
178  "HasVOP3PInsts",
179  "true",
180  "Has VOP3P packed instructions"
181>;
182
183def FeatureMovrel : SubtargetFeature<"movrel",
184  "HasMovrel",
185  "true",
186  "Has v_movrel*_b32 instructions"
187>;
188
189def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
190  "HasVGPRIndexMode",
191  "true",
192  "Has VGPR mode register indexing"
193>;
194
195def FeatureScalarStores : SubtargetFeature<"scalar-stores",
196  "HasScalarStores",
197  "true",
198  "Has store scalar memory instructions"
199>;
200
201def FeatureScalarAtomics : SubtargetFeature<"scalar-atomics",
202  "HasScalarAtomics",
203  "true",
204  "Has atomic scalar memory instructions"
205>;
206
207def FeatureSDWA : SubtargetFeature<"sdwa",
208  "HasSDWA",
209  "true",
210  "Support SDWA (Sub-DWORD Addressing) extension"
211>;
212
213def FeatureSDWAOmod : SubtargetFeature<"sdwa-omod",
214  "HasSDWAOmod",
215  "true",
216  "Support OMod with SDWA (Sub-DWORD Addressing) extension"
217>;
218
219def FeatureSDWAScalar : SubtargetFeature<"sdwa-scalar",
220  "HasSDWAScalar",
221  "true",
222  "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
223>;
224
225def FeatureSDWASdst : SubtargetFeature<"sdwa-sdst",
226  "HasSDWASdst",
227  "true",
228  "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
229>;
230
231def FeatureSDWAMac : SubtargetFeature<"sdwa-mav",
232  "HasSDWAMac",
233  "true",
234  "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
235>;
236
237def FeatureSDWAOutModsVOPC : SubtargetFeature<"sdwa-out-mods-vopc",
238  "HasSDWAOutModsVOPC",
239  "true",
240  "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
241>;
242
243def FeatureDPP : SubtargetFeature<"dpp",
244  "HasDPP",
245  "true",
246  "Support DPP (Data Parallel Primitives) extension"
247>;
248
249def FeatureR128A16 : SubtargetFeature<"r128-a16",
250  "HasR128A16",
251  "true",
252  "Support 16 bit coordindates/gradients/lod/clamp/mip types on gfx9"
253>;
254
255def FeatureIntClamp : SubtargetFeature<"int-clamp-insts",
256  "HasIntClamp",
257  "true",
258  "Support clamp for integer destination"
259>;
260
261def FeatureUnpackedD16VMem : SubtargetFeature<"unpacked-d16-vmem",
262  "HasUnpackedD16VMem",
263  "true",
264  "Has unpacked d16 vmem instructions"
265>;
266
267def FeatureDLInsts : SubtargetFeature<"dl-insts",
268  "HasDLInsts",
269  "true",
270  "Has v_fmac_f32 and v_xnor_b32 instructions"
271>;
272
273def FeatureDotInsts : SubtargetFeature<"dot-insts",
274  "HasDotInsts",
275  "true",
276  "Has v_dot* instructions"
277>;
278
279def FeatureSRAMECC : SubtargetFeature<"sram-ecc",
280  "EnableSRAMECC",
281  "true",
282  "Enable SRAM ECC"
283>;
284
285//===------------------------------------------------------------===//
286// Subtarget Features (options and debugging)
287//===------------------------------------------------------------===//
288
289// Denormal handling for fp64 and fp16 is controlled by the same
290// config register when fp16 supported.
291// TODO: Do we need a separate f16 setting when not legal?
292def FeatureFP64FP16Denormals : SubtargetFeature<"fp64-fp16-denormals",
293  "FP64FP16Denormals",
294  "true",
295  "Enable double and half precision denormal handling",
296  [FeatureFP64]
297>;
298
299def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
300  "FP64FP16Denormals",
301  "true",
302  "Enable double and half precision denormal handling",
303  [FeatureFP64, FeatureFP64FP16Denormals]
304>;
305
306def FeatureFP16Denormals : SubtargetFeature<"fp16-denormals",
307  "FP64FP16Denormals",
308  "true",
309  "Enable half precision denormal handling",
310  [FeatureFP64FP16Denormals]
311>;
312
313def FeatureFPExceptions : SubtargetFeature<"fp-exceptions",
314  "FPExceptions",
315  "true",
316  "Enable floating point exceptions"
317>;
318
319class FeatureMaxPrivateElementSize<int size> : SubtargetFeature<
320  "max-private-element-size-"#size,
321  "MaxPrivateElementSize",
322  !cast<string>(size),
323  "Maximum private access size may be "#size
324>;
325
326def FeatureMaxPrivateElementSize4 : FeatureMaxPrivateElementSize<4>;
327def FeatureMaxPrivateElementSize8 : FeatureMaxPrivateElementSize<8>;
328def FeatureMaxPrivateElementSize16 : FeatureMaxPrivateElementSize<16>;
329
330def FeatureEnableHugePrivateBuffer : SubtargetFeature<
331  "huge-private-buffer",
332  "EnableHugePrivateBuffer",
333  "true",
334  "Enable private/scratch buffer sizes greater than 128 GB"
335>;
336
337def FeatureDumpCode : SubtargetFeature <"DumpCode",
338  "DumpCode",
339  "true",
340  "Dump MachineInstrs in the CodeEmitter"
341>;
342
343def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
344  "DumpCode",
345  "true",
346  "Dump MachineInstrs in the CodeEmitter"
347>;
348
349// XXX - This should probably be removed once enabled by default
350def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
351  "EnableLoadStoreOpt",
352  "true",
353  "Enable SI load/store optimizer pass"
354>;
355
356// Performance debugging feature. Allow using DS instruction immediate
357// offsets even if the base pointer can't be proven to be base. On SI,
358// base pointer values that won't give the same result as a 16-bit add
359// are not safe to fold, but this will override the conservative test
360// for the base pointer.
361def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <
362  "unsafe-ds-offset-folding",
363  "EnableUnsafeDSOffsetFolding",
364  "true",
365  "Force using DS instruction immediate offsets on SI"
366>;
367
368def FeatureEnableSIScheduler : SubtargetFeature<"si-scheduler",
369  "EnableSIScheduler",
370  "true",
371  "Enable SI Machine Scheduler"
372>;
373
374def FeatureEnableDS128 : SubtargetFeature<"enable-ds128",
375  "EnableDS128",
376  "true",
377  "Use ds_{read|write}_b128"
378>;
379
380// Sparse texture support requires that all result registers are zeroed when
381// PRTStrictNull is set to true. This feature is turned on for all architectures
382// but is enabled as a feature in case there are situations where PRTStrictNull
383// is disabled by the driver.
384def FeatureEnablePRTStrictNull : SubtargetFeature<"enable-prt-strict-null",
385  "EnablePRTStrictNull",
386  "true",
387  "Enable zeroing of result registers for sparse texture fetches"
388>;
389
390// Unless +-flat-for-global is specified, turn on FlatForGlobal for
391// all OS-es on VI and newer hardware to avoid assertion failures due
392// to missing ADDR64 variants of MUBUF instructions.
393// FIXME: moveToVALU should be able to handle converting addr64 MUBUF
394// instructions.
395
396def FeatureFlatForGlobal : SubtargetFeature<"flat-for-global",
397  "FlatForGlobal",
398  "true",
399  "Force to generate flat instruction for global"
400>;
401
402def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
403  "auto-waitcnt-before-barrier",
404  "AutoWaitcntBeforeBarrier",
405  "true",
406  "Hardware automatically inserts waitcnt before barrier"
407>;
408
409def FeatureCodeObjectV3 : SubtargetFeature <
410  "code-object-v3",
411  "CodeObjectV3",
412  "true",
413  "Generate code object version 3"
414>;
415
416def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
417  "HasTrigReducedRange",
418  "true",
419  "Requires use of fract on arguments to trig instructions"
420>;
421
422// Dummy feature used to disable assembler instructions.
423def FeatureDisable : SubtargetFeature<"",
424  "FeatureDisable","true",
425  "Dummy feature to disable assembler instructions"
426>;
427
428def FeatureGCN : SubtargetFeature<"gcn",
429  "IsGCN",
430  "true",
431  "GCN or newer GPU"
432>;
433
434class GCNSubtargetFeatureGeneration <string Value,
435                                  list<SubtargetFeature> Implies> :
436        SubtargetFeatureGeneration <Value, "GCNSubtarget", Implies>;
437
438def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
439  [FeatureFP64, FeatureLocalMemorySize32768, FeatureMIMG_R128,
440  FeatureWavefrontSize64, FeatureGCN,
441  FeatureLDSBankCount32, FeatureMovrel, FeatureTrigReducedRange]
442>;
443
444def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
445  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
446  FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
447  FeatureCIInsts, FeatureMovrel, FeatureTrigReducedRange]
448>;
449
450def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
451  [FeatureFP64, FeatureLocalMemorySize65536, FeatureMIMG_R128,
452   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
453   FeatureGCN3Encoding, FeatureCIInsts, FeatureVIInsts, Feature16BitInsts,
454   FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
455   FeatureScalarStores, FeatureInv2PiInlineImm,
456   FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP,
457   FeatureIntClamp, FeatureTrigReducedRange
458  ]
459>;
460
461def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
462  [FeatureFP64, FeatureLocalMemorySize65536,
463   FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
464   FeatureGCN3Encoding, FeatureCIInsts, FeatureVIInsts, Feature16BitInsts,
465   FeatureSMemRealTime, FeatureScalarStores, FeatureInv2PiInlineImm,
466   FeatureApertureRegs, FeatureGFX9Insts, FeatureVOP3P, FeatureVGPRIndexMode,
467   FeatureFastFMAF32, FeatureDPP, FeatureIntClamp,
468   FeatureSDWA, FeatureSDWAOmod, FeatureSDWAScalar, FeatureSDWASdst,
469   FeatureFlatInstOffsets, FeatureFlatGlobalInsts, FeatureFlatScratchInsts,
470   FeatureAddNoCarryInsts, FeatureScalarAtomics, FeatureR128A16
471  ]
472>;
473
474class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping,
475                                  list<SubtargetFeature> Implies>
476                                 : SubtargetFeature <
477  "isaver"#Major#"."#Minor#"."#Stepping,
478  "IsaVersion",
479  "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
480  "Instruction set version number",
481  Implies
482>;
483
484def FeatureISAVersion6_0_0 : SubtargetFeatureISAVersion <6,0,0,
485  [FeatureSouthernIslands,
486   FeatureFastFMAF32,
487   HalfRate64Ops,
488   FeatureLDSBankCount32,
489   FeatureCodeObjectV3]>;
490
491def FeatureISAVersion6_0_1 : SubtargetFeatureISAVersion <6,0,1,
492  [FeatureSouthernIslands,
493   FeatureLDSBankCount32,
494   FeatureCodeObjectV3]>;
495
496def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0,
497  [FeatureSeaIslands,
498   FeatureLDSBankCount32,
499   FeatureCodeObjectV3]>;
500
501def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1,
502  [FeatureSeaIslands,
503   HalfRate64Ops,
504   FeatureLDSBankCount32,
505   FeatureFastFMAF32,
506   FeatureCodeObjectV3]>;
507
508def FeatureISAVersion7_0_2 : SubtargetFeatureISAVersion <7,0,2,
509  [FeatureSeaIslands,
510   FeatureLDSBankCount16,
511   FeatureFastFMAF32,
512   FeatureCodeObjectV3]>;
513
514def FeatureISAVersion7_0_3 : SubtargetFeatureISAVersion <7,0,3,
515  [FeatureSeaIslands,
516   FeatureLDSBankCount16,
517   FeatureCodeObjectV3]>;
518
519def FeatureISAVersion7_0_4 : SubtargetFeatureISAVersion <7,0,4,
520  [FeatureSeaIslands,
521   FeatureLDSBankCount32,
522   FeatureCodeObjectV3]>;
523
524def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1,
525  [FeatureVolcanicIslands,
526   FeatureFastFMAF32,
527   HalfRate64Ops,
528   FeatureLDSBankCount32,
529   FeatureXNACK,
530   FeatureUnpackedD16VMem,
531   FeatureCodeObjectV3]>;
532
533def FeatureISAVersion8_0_2 : SubtargetFeatureISAVersion <8,0,2,
534  [FeatureVolcanicIslands,
535   FeatureLDSBankCount32,
536   FeatureSGPRInitBug,
537   FeatureUnpackedD16VMem,
538   FeatureCodeObjectV3]>;
539
540def FeatureISAVersion8_0_3 : SubtargetFeatureISAVersion <8,0,3,
541  [FeatureVolcanicIslands,
542   FeatureLDSBankCount32,
543   FeatureUnpackedD16VMem,
544   FeatureCodeObjectV3]>;
545
546def FeatureISAVersion8_1_0 : SubtargetFeatureISAVersion <8,1,0,
547  [FeatureVolcanicIslands,
548   FeatureLDSBankCount16,
549   FeatureXNACK,
550   FeatureCodeObjectV3]>;
551
552def FeatureISAVersion9_0_0 : SubtargetFeatureISAVersion <9,0,0,
553  [FeatureGFX9,
554   FeatureMadMixInsts,
555   FeatureLDSBankCount32,
556   FeatureCodeObjectV3]>;
557
558def FeatureISAVersion9_0_2 : SubtargetFeatureISAVersion <9,0,2,
559  [FeatureGFX9,
560   FeatureMadMixInsts,
561   FeatureLDSBankCount32,
562   FeatureXNACK,
563   FeatureCodeObjectV3]>;
564
565def FeatureISAVersion9_0_4 : SubtargetFeatureISAVersion <9,0,4,
566  [FeatureGFX9,
567   FeatureLDSBankCount32,
568   FeatureFmaMixInsts,
569   FeatureCodeObjectV3]>;
570
571def FeatureISAVersion9_0_6 : SubtargetFeatureISAVersion <9,0,6,
572  [FeatureGFX9,
573   HalfRate64Ops,
574   FeatureFmaMixInsts,
575   FeatureLDSBankCount32,
576   FeatureDLInsts,
577   FeatureDotInsts,
578   FeatureSRAMECC,
579   FeatureCodeObjectV3]>;
580
581def FeatureISAVersion9_0_9 : SubtargetFeatureISAVersion <9,0,9,
582  [FeatureGFX9,
583   FeatureMadMixInsts,
584   FeatureLDSBankCount32,
585   FeatureXNACK,
586   FeatureCodeObjectV3]>;
587
588//===----------------------------------------------------------------------===//
589// Debugger related subtarget features.
590//===----------------------------------------------------------------------===//
591
592def FeatureDebuggerInsertNops : SubtargetFeature<
593  "amdgpu-debugger-insert-nops",
594  "DebuggerInsertNops",
595  "true",
596  "Insert one nop instruction for each high level source statement"
597>;
598
599def FeatureDebuggerEmitPrologue : SubtargetFeature<
600  "amdgpu-debugger-emit-prologue",
601  "DebuggerEmitPrologue",
602  "true",
603  "Emit debugger prologue"
604>;
605
606//===----------------------------------------------------------------------===//
607
608def AMDGPUInstrInfo : InstrInfo {
609  let guessInstructionProperties = 1;
610  let noNamedPositionallyEncodedOperands = 1;
611}
612
613def AMDGPUAsmParser : AsmParser {
614  // Some of the R600 registers have the same name, so this crashes.
615  // For example T0_XYZW and T0_XY both have the asm name T0.
616  let ShouldEmitMatchRegisterName = 0;
617}
618
619def AMDGPUAsmWriter : AsmWriter {
620  int PassSubtarget = 1;
621}
622
623def AMDGPUAsmVariants {
624  string Default = "Default";
625  int Default_ID = 0;
626  string VOP3 = "VOP3";
627  int VOP3_ID = 1;
628  string SDWA = "SDWA";
629  int SDWA_ID = 2;
630  string SDWA9 = "SDWA9";
631  int SDWA9_ID = 3;
632  string DPP = "DPP";
633  int DPP_ID = 4;
634  string Disable = "Disable";
635  int Disable_ID = 5;
636}
637
638def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
639  let Variant = AMDGPUAsmVariants.Default_ID;
640  let Name = AMDGPUAsmVariants.Default;
641}
642
643def VOP3AsmParserVariant : AsmParserVariant {
644  let Variant = AMDGPUAsmVariants.VOP3_ID;
645  let Name = AMDGPUAsmVariants.VOP3;
646}
647
648def SDWAAsmParserVariant : AsmParserVariant {
649  let Variant = AMDGPUAsmVariants.SDWA_ID;
650  let Name = AMDGPUAsmVariants.SDWA;
651}
652
653def SDWA9AsmParserVariant : AsmParserVariant {
654  let Variant = AMDGPUAsmVariants.SDWA9_ID;
655  let Name = AMDGPUAsmVariants.SDWA9;
656}
657
658
659def DPPAsmParserVariant : AsmParserVariant {
660  let Variant = AMDGPUAsmVariants.DPP_ID;
661  let Name = AMDGPUAsmVariants.DPP;
662}
663
664def AMDGPU : Target {
665  // Pull in Instruction Info:
666  let InstructionSet = AMDGPUInstrInfo;
667  let AssemblyParsers = [AMDGPUAsmParser];
668  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
669                                VOP3AsmParserVariant,
670                                SDWAAsmParserVariant,
671                                SDWA9AsmParserVariant,
672                                DPPAsmParserVariant];
673  let AssemblyWriters = [AMDGPUAsmWriter];
674  let AllowRegisterRenaming = 1;
675}
676
677// Dummy Instruction itineraries for pseudo instructions
678def ALU_NULL : FuncUnit;
679def NullALU : InstrItinClass;
680
681//===----------------------------------------------------------------------===//
682// Predicate helper class
683//===----------------------------------------------------------------------===//
684
685def isSICI : Predicate<
686  "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
687  "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
688>, AssemblerPredicate<"!FeatureGCN3Encoding">;
689
690def isVI : Predicate <
691  "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">,
692  AssemblerPredicate<"FeatureGCN3Encoding">;
693
694def isGFX9 : Predicate <
695  "Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
696  AssemblerPredicate<"FeatureGFX9Insts">;
697
698// TODO: Either the name to be changed or we simply use IsCI!
699def isCIVI : Predicate <
700  "Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
701  AssemblerPredicate<"FeatureCIInsts">;
702
703def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
704  AssemblerPredicate<"FeatureFlatAddressSpace">;
705
706def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
707  AssemblerPredicate<"FeatureFlatGlobalInsts">;
708def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
709  AssemblerPredicate<"FeatureFlatScratchInsts">;
710def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
711  AssemblerPredicate<"FeatureGFX9Insts">;
712
713def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
714  AssemblerPredicate<"FeatureUnpackedD16VMem">;
715def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
716  AssemblerPredicate<"!FeatureUnpackedD16VMem">;
717
718def D16PreservesUnusedBits :
719  Predicate<"Subtarget->hasD16LoadStore() && !Subtarget->isSRAMECCEnabled()">,
720  AssemblerPredicate<"FeatureGFX9Insts,!FeatureSRAMECC">;
721
722def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">;
723def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">;
724
725def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">,
726  AssemblerPredicate<"FeatureGFX9Insts">;
727
728def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">,
729  AssemblerPredicate<"FeatureAddNoCarryInsts">;
730
731def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">,
732  AssemblerPredicate<"!FeatureAddNoCarryInsts">;
733
734def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
735  AssemblerPredicate<"Feature16BitInsts">;
736def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
737  AssemblerPredicate<"FeatureVOP3P">;
738
739def NotHasVOP3PInsts : Predicate<"!Subtarget->hasVOP3PInsts()">,
740  AssemblerPredicate<"!FeatureVOP3P">;
741
742def HasSDWA : Predicate<"Subtarget->hasSDWA()">,
743  AssemblerPredicate<"FeatureSDWA,FeatureVolcanicIslands">;
744
745def HasSDWA9 : Predicate<"Subtarget->hasSDWA()">,
746  AssemblerPredicate<"FeatureSDWA,FeatureGFX9">;
747
748def HasDPP : Predicate<"Subtarget->hasDPP()">,
749  AssemblerPredicate<"FeatureDPP">;
750
751def HasR128A16 : Predicate<"Subtarget->hasR128A16()">,
752  AssemblerPredicate<"FeatureR128A16">;
753
754def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">,
755  AssemblerPredicate<"FeatureIntClamp">;
756
757def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
758  AssemblerPredicate<"FeatureMadMixInsts">;
759
760def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">,
761  AssemblerPredicate<"FeatureScalarAtomics">;
762
763def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
764def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
765def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
766                      AssemblerPredicate<"FeatureVGPRIndexMode">;
767def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
768                AssemblerPredicate<"FeatureMovrel">;
769
770def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">,
771  AssemblerPredicate<"FeatureFmaMixInsts">;
772
773def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">,
774  AssemblerPredicate<"FeatureDLInsts">;
775
776def HasDotInsts : Predicate<"Subtarget->hasDotInsts()">,
777  AssemblerPredicate<"FeatureDotInsts">;
778
779
780def EnableLateCFGStructurize : Predicate<
781  "EnableLateStructurizeCFG">;
782
783// Include AMDGPU TD files
784include "SISchedule.td"
785include "GCNProcessors.td"
786include "AMDGPUInstrInfo.td"
787include "SIIntrinsics.td"
788include "AMDGPURegisterInfo.td"
789include "AMDGPURegisterBanks.td"
790include "AMDGPUInstructions.td"
791include "SIInstrInfo.td"
792include "AMDGPUCallingConv.td"
793include "AMDGPUSearchableTables.td"
794