1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "ARMBaseInstrInfo.h"
15 #include "ARMBaseRegisterInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMFeatures.h"
18 #include "ARMHazardRecognizer.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
21 #include "MCTargetDesc/ARMAddressingModes.h"
22 #include "MCTargetDesc/ARMBaseInfo.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallSet.h"
26 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/CodeGen/LiveVariables.h"
29 #include "llvm/CodeGen/MachineBasicBlock.h"
30 #include "llvm/CodeGen/MachineConstantPool.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstr.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineMemOperand.h"
36 #include "llvm/CodeGen/MachineOperand.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
39 #include "llvm/CodeGen/SelectionDAGNodes.h"
40 #include "llvm/CodeGen/TargetInstrInfo.h"
41 #include "llvm/CodeGen/TargetRegisterInfo.h"
42 #include "llvm/CodeGen/TargetSchedule.h"
43 #include "llvm/IR/Attributes.h"
44 #include "llvm/IR/Constants.h"
45 #include "llvm/IR/DebugLoc.h"
46 #include "llvm/IR/Function.h"
47 #include "llvm/IR/GlobalValue.h"
48 #include "llvm/MC/MCAsmInfo.h"
49 #include "llvm/MC/MCInstrDesc.h"
50 #include "llvm/MC/MCInstrItineraries.h"
51 #include "llvm/Support/BranchProbability.h"
52 #include "llvm/Support/Casting.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Compiler.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/raw_ostream.h"
58 #include "llvm/Target/TargetMachine.h"
59 #include <algorithm>
60 #include <cassert>
61 #include <cstdint>
62 #include <iterator>
63 #include <new>
64 #include <utility>
65 #include <vector>
66
67 using namespace llvm;
68
69 #define DEBUG_TYPE "arm-instrinfo"
70
71 #define GET_INSTRINFO_CTOR_DTOR
72 #include "ARMGenInstrInfo.inc"
73
74 static cl::opt<bool>
75 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
76 cl::desc("Enable ARM 2-addr to 3-addr conv"));
77
78 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
79 struct ARM_MLxEntry {
80 uint16_t MLxOpc; // MLA / MLS opcode
81 uint16_t MulOpc; // Expanded multiplication opcode
82 uint16_t AddSubOpc; // Expanded add / sub opcode
83 bool NegAcc; // True if the acc is negated before the add / sub.
84 bool HasLane; // True if instruction has an extra "lane" operand.
85 };
86
87 static const ARM_MLxEntry ARM_MLxTable[] = {
88 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
89 // fp scalar ops
90 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
91 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
92 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
93 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
94 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
95 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
96 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
97 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
98
99 // fp SIMD ops
100 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
101 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
102 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
103 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
104 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
105 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
106 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
107 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
108 };
109
ARMBaseInstrInfo(const ARMSubtarget & STI)110 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
111 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
112 Subtarget(STI) {
113 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
114 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
115 llvm_unreachable("Duplicated entries?");
116 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
117 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
118 }
119 }
120
121 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
122 // currently defaults to no prepass hazard recognizer.
123 ScheduleHazardRecognizer *
CreateTargetHazardRecognizer(const TargetSubtargetInfo * STI,const ScheduleDAG * DAG) const124 ARMBaseInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
125 const ScheduleDAG *DAG) const {
126 if (usePreRAHazardRecognizer()) {
127 const InstrItineraryData *II =
128 static_cast<const ARMSubtarget *>(STI)->getInstrItineraryData();
129 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
130 }
131 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
132 }
133
134 ScheduleHazardRecognizer *ARMBaseInstrInfo::
CreateTargetPostRAHazardRecognizer(const InstrItineraryData * II,const ScheduleDAG * DAG) const135 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
136 const ScheduleDAG *DAG) const {
137 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
138 return (ScheduleHazardRecognizer *)new ARMHazardRecognizer(II, DAG);
139 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
140 }
141
convertToThreeAddress(MachineFunction::iterator & MFI,MachineInstr & MI,LiveVariables * LV) const142 MachineInstr *ARMBaseInstrInfo::convertToThreeAddress(
143 MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const {
144 // FIXME: Thumb2 support.
145
146 if (!EnableARM3Addr)
147 return nullptr;
148
149 MachineFunction &MF = *MI.getParent()->getParent();
150 uint64_t TSFlags = MI.getDesc().TSFlags;
151 bool isPre = false;
152 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
153 default: return nullptr;
154 case ARMII::IndexModePre:
155 isPre = true;
156 break;
157 case ARMII::IndexModePost:
158 break;
159 }
160
161 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
162 // operation.
163 unsigned MemOpc = getUnindexedOpcode(MI.getOpcode());
164 if (MemOpc == 0)
165 return nullptr;
166
167 MachineInstr *UpdateMI = nullptr;
168 MachineInstr *MemMI = nullptr;
169 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
170 const MCInstrDesc &MCID = MI.getDesc();
171 unsigned NumOps = MCID.getNumOperands();
172 bool isLoad = !MI.mayStore();
173 const MachineOperand &WB = isLoad ? MI.getOperand(1) : MI.getOperand(0);
174 const MachineOperand &Base = MI.getOperand(2);
175 const MachineOperand &Offset = MI.getOperand(NumOps - 3);
176 unsigned WBReg = WB.getReg();
177 unsigned BaseReg = Base.getReg();
178 unsigned OffReg = Offset.getReg();
179 unsigned OffImm = MI.getOperand(NumOps - 2).getImm();
180 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI.getOperand(NumOps - 1).getImm();
181 switch (AddrMode) {
182 default: llvm_unreachable("Unknown indexed op!");
183 case ARMII::AddrMode2: {
184 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
185 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
186 if (OffReg == 0) {
187 if (ARM_AM::getSOImmVal(Amt) == -1)
188 // Can't encode it in a so_imm operand. This transformation will
189 // add more than 1 instruction. Abandon!
190 return nullptr;
191 UpdateMI = BuildMI(MF, MI.getDebugLoc(),
192 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
193 .addReg(BaseReg)
194 .addImm(Amt)
195 .add(predOps(Pred))
196 .add(condCodeOp());
197 } else if (Amt != 0) {
198 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
199 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
200 UpdateMI = BuildMI(MF, MI.getDebugLoc(),
201 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
202 .addReg(BaseReg)
203 .addReg(OffReg)
204 .addReg(0)
205 .addImm(SOOpc)
206 .add(predOps(Pred))
207 .add(condCodeOp());
208 } else
209 UpdateMI = BuildMI(MF, MI.getDebugLoc(),
210 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
211 .addReg(BaseReg)
212 .addReg(OffReg)
213 .add(predOps(Pred))
214 .add(condCodeOp());
215 break;
216 }
217 case ARMII::AddrMode3 : {
218 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
219 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
220 if (OffReg == 0)
221 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
222 UpdateMI = BuildMI(MF, MI.getDebugLoc(),
223 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
224 .addReg(BaseReg)
225 .addImm(Amt)
226 .add(predOps(Pred))
227 .add(condCodeOp());
228 else
229 UpdateMI = BuildMI(MF, MI.getDebugLoc(),
230 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
231 .addReg(BaseReg)
232 .addReg(OffReg)
233 .add(predOps(Pred))
234 .add(condCodeOp());
235 break;
236 }
237 }
238
239 std::vector<MachineInstr*> NewMIs;
240 if (isPre) {
241 if (isLoad)
242 MemMI =
243 BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())
244 .addReg(WBReg)
245 .addImm(0)
246 .addImm(Pred);
247 else
248 MemMI = BuildMI(MF, MI.getDebugLoc(), get(MemOpc))
249 .addReg(MI.getOperand(1).getReg())
250 .addReg(WBReg)
251 .addReg(0)
252 .addImm(0)
253 .addImm(Pred);
254 NewMIs.push_back(MemMI);
255 NewMIs.push_back(UpdateMI);
256 } else {
257 if (isLoad)
258 MemMI =
259 BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())
260 .addReg(BaseReg)
261 .addImm(0)
262 .addImm(Pred);
263 else
264 MemMI = BuildMI(MF, MI.getDebugLoc(), get(MemOpc))
265 .addReg(MI.getOperand(1).getReg())
266 .addReg(BaseReg)
267 .addReg(0)
268 .addImm(0)
269 .addImm(Pred);
270 if (WB.isDead())
271 UpdateMI->getOperand(0).setIsDead();
272 NewMIs.push_back(UpdateMI);
273 NewMIs.push_back(MemMI);
274 }
275
276 // Transfer LiveVariables states, kill / dead info.
277 if (LV) {
278 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
279 MachineOperand &MO = MI.getOperand(i);
280 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
281 unsigned Reg = MO.getReg();
282
283 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
284 if (MO.isDef()) {
285 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
286 if (MO.isDead())
287 LV->addVirtualRegisterDead(Reg, *NewMI);
288 }
289 if (MO.isUse() && MO.isKill()) {
290 for (unsigned j = 0; j < 2; ++j) {
291 // Look at the two new MI's in reverse order.
292 MachineInstr *NewMI = NewMIs[j];
293 if (!NewMI->readsRegister(Reg))
294 continue;
295 LV->addVirtualRegisterKilled(Reg, *NewMI);
296 if (VI.removeKill(MI))
297 VI.Kills.push_back(NewMI);
298 break;
299 }
300 }
301 }
302 }
303 }
304
305 MachineBasicBlock::iterator MBBI = MI.getIterator();
306 MFI->insert(MBBI, NewMIs[1]);
307 MFI->insert(MBBI, NewMIs[0]);
308 return NewMIs[0];
309 }
310
311 // Branch analysis.
analyzeBranch(MachineBasicBlock & MBB,MachineBasicBlock * & TBB,MachineBasicBlock * & FBB,SmallVectorImpl<MachineOperand> & Cond,bool AllowModify) const312 bool ARMBaseInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
313 MachineBasicBlock *&TBB,
314 MachineBasicBlock *&FBB,
315 SmallVectorImpl<MachineOperand> &Cond,
316 bool AllowModify) const {
317 TBB = nullptr;
318 FBB = nullptr;
319
320 MachineBasicBlock::iterator I = MBB.end();
321 if (I == MBB.begin())
322 return false; // Empty blocks are easy.
323 --I;
324
325 // Walk backwards from the end of the basic block until the branch is
326 // analyzed or we give up.
327 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) {
328 // Flag to be raised on unanalyzeable instructions. This is useful in cases
329 // where we want to clean up on the end of the basic block before we bail
330 // out.
331 bool CantAnalyze = false;
332
333 // Skip over DEBUG values and predicated nonterminators.
334 while (I->isDebugInstr() || !I->isTerminator()) {
335 if (I == MBB.begin())
336 return false;
337 --I;
338 }
339
340 if (isIndirectBranchOpcode(I->getOpcode()) ||
341 isJumpTableBranchOpcode(I->getOpcode())) {
342 // Indirect branches and jump tables can't be analyzed, but we still want
343 // to clean up any instructions at the tail of the basic block.
344 CantAnalyze = true;
345 } else if (isUncondBranchOpcode(I->getOpcode())) {
346 TBB = I->getOperand(0).getMBB();
347 } else if (isCondBranchOpcode(I->getOpcode())) {
348 // Bail out if we encounter multiple conditional branches.
349 if (!Cond.empty())
350 return true;
351
352 assert(!FBB && "FBB should have been null.");
353 FBB = TBB;
354 TBB = I->getOperand(0).getMBB();
355 Cond.push_back(I->getOperand(1));
356 Cond.push_back(I->getOperand(2));
357 } else if (I->isReturn()) {
358 // Returns can't be analyzed, but we should run cleanup.
359 CantAnalyze = !isPredicated(*I);
360 } else {
361 // We encountered other unrecognized terminator. Bail out immediately.
362 return true;
363 }
364
365 // Cleanup code - to be run for unpredicated unconditional branches and
366 // returns.
367 if (!isPredicated(*I) &&
368 (isUncondBranchOpcode(I->getOpcode()) ||
369 isIndirectBranchOpcode(I->getOpcode()) ||
370 isJumpTableBranchOpcode(I->getOpcode()) ||
371 I->isReturn())) {
372 // Forget any previous condition branch information - it no longer applies.
373 Cond.clear();
374 FBB = nullptr;
375
376 // If we can modify the function, delete everything below this
377 // unconditional branch.
378 if (AllowModify) {
379 MachineBasicBlock::iterator DI = std::next(I);
380 while (DI != MBB.end()) {
381 MachineInstr &InstToDelete = *DI;
382 ++DI;
383 InstToDelete.eraseFromParent();
384 }
385 }
386 }
387
388 if (CantAnalyze)
389 return true;
390
391 if (I == MBB.begin())
392 return false;
393
394 --I;
395 }
396
397 // We made it past the terminators without bailing out - we must have
398 // analyzed this branch successfully.
399 return false;
400 }
401
removeBranch(MachineBasicBlock & MBB,int * BytesRemoved) const402 unsigned ARMBaseInstrInfo::removeBranch(MachineBasicBlock &MBB,
403 int *BytesRemoved) const {
404 assert(!BytesRemoved && "code size not handled");
405
406 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
407 if (I == MBB.end())
408 return 0;
409
410 if (!isUncondBranchOpcode(I->getOpcode()) &&
411 !isCondBranchOpcode(I->getOpcode()))
412 return 0;
413
414 // Remove the branch.
415 I->eraseFromParent();
416
417 I = MBB.end();
418
419 if (I == MBB.begin()) return 1;
420 --I;
421 if (!isCondBranchOpcode(I->getOpcode()))
422 return 1;
423
424 // Remove the branch.
425 I->eraseFromParent();
426 return 2;
427 }
428
insertBranch(MachineBasicBlock & MBB,MachineBasicBlock * TBB,MachineBasicBlock * FBB,ArrayRef<MachineOperand> Cond,const DebugLoc & DL,int * BytesAdded) const429 unsigned ARMBaseInstrInfo::insertBranch(MachineBasicBlock &MBB,
430 MachineBasicBlock *TBB,
431 MachineBasicBlock *FBB,
432 ArrayRef<MachineOperand> Cond,
433 const DebugLoc &DL,
434 int *BytesAdded) const {
435 assert(!BytesAdded && "code size not handled");
436 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
437 int BOpc = !AFI->isThumbFunction()
438 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
439 int BccOpc = !AFI->isThumbFunction()
440 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
441 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
442
443 // Shouldn't be a fall through.
444 assert(TBB && "insertBranch must not be told to insert a fallthrough");
445 assert((Cond.size() == 2 || Cond.size() == 0) &&
446 "ARM branch conditions have two components!");
447
448 // For conditional branches, we use addOperand to preserve CPSR flags.
449
450 if (!FBB) {
451 if (Cond.empty()) { // Unconditional branch?
452 if (isThumb)
453 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).add(predOps(ARMCC::AL));
454 else
455 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
456 } else
457 BuildMI(&MBB, DL, get(BccOpc))
458 .addMBB(TBB)
459 .addImm(Cond[0].getImm())
460 .add(Cond[1]);
461 return 1;
462 }
463
464 // Two-way conditional branch.
465 BuildMI(&MBB, DL, get(BccOpc))
466 .addMBB(TBB)
467 .addImm(Cond[0].getImm())
468 .add(Cond[1]);
469 if (isThumb)
470 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).add(predOps(ARMCC::AL));
471 else
472 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
473 return 2;
474 }
475
476 bool ARMBaseInstrInfo::
reverseBranchCondition(SmallVectorImpl<MachineOperand> & Cond) const477 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
478 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
479 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
480 return false;
481 }
482
isPredicated(const MachineInstr & MI) const483 bool ARMBaseInstrInfo::isPredicated(const MachineInstr &MI) const {
484 if (MI.isBundle()) {
485 MachineBasicBlock::const_instr_iterator I = MI.getIterator();
486 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
487 while (++I != E && I->isInsideBundle()) {
488 int PIdx = I->findFirstPredOperandIdx();
489 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
490 return true;
491 }
492 return false;
493 }
494
495 int PIdx = MI.findFirstPredOperandIdx();
496 return PIdx != -1 && MI.getOperand(PIdx).getImm() != ARMCC::AL;
497 }
498
PredicateInstruction(MachineInstr & MI,ArrayRef<MachineOperand> Pred) const499 bool ARMBaseInstrInfo::PredicateInstruction(
500 MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
501 unsigned Opc = MI.getOpcode();
502 if (isUncondBranchOpcode(Opc)) {
503 MI.setDesc(get(getMatchingCondBranchOpcode(Opc)));
504 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
505 .addImm(Pred[0].getImm())
506 .addReg(Pred[1].getReg());
507 return true;
508 }
509
510 int PIdx = MI.findFirstPredOperandIdx();
511 if (PIdx != -1) {
512 MachineOperand &PMO = MI.getOperand(PIdx);
513 PMO.setImm(Pred[0].getImm());
514 MI.getOperand(PIdx+1).setReg(Pred[1].getReg());
515 return true;
516 }
517 return false;
518 }
519
SubsumesPredicate(ArrayRef<MachineOperand> Pred1,ArrayRef<MachineOperand> Pred2) const520 bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
521 ArrayRef<MachineOperand> Pred2) const {
522 if (Pred1.size() > 2 || Pred2.size() > 2)
523 return false;
524
525 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
526 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
527 if (CC1 == CC2)
528 return true;
529
530 switch (CC1) {
531 default:
532 return false;
533 case ARMCC::AL:
534 return true;
535 case ARMCC::HS:
536 return CC2 == ARMCC::HI;
537 case ARMCC::LS:
538 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
539 case ARMCC::GE:
540 return CC2 == ARMCC::GT;
541 case ARMCC::LE:
542 return CC2 == ARMCC::LT;
543 }
544 }
545
DefinesPredicate(MachineInstr & MI,std::vector<MachineOperand> & Pred) const546 bool ARMBaseInstrInfo::DefinesPredicate(
547 MachineInstr &MI, std::vector<MachineOperand> &Pred) const {
548 bool Found = false;
549 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
550 const MachineOperand &MO = MI.getOperand(i);
551 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
552 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
553 Pred.push_back(MO);
554 Found = true;
555 }
556 }
557
558 return Found;
559 }
560
isCPSRDefined(const MachineInstr & MI)561 bool ARMBaseInstrInfo::isCPSRDefined(const MachineInstr &MI) {
562 for (const auto &MO : MI.operands())
563 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead())
564 return true;
565 return false;
566 }
567
isAddrMode3OpImm(const MachineInstr & MI,unsigned Op) const568 bool ARMBaseInstrInfo::isAddrMode3OpImm(const MachineInstr &MI,
569 unsigned Op) const {
570 const MachineOperand &Offset = MI.getOperand(Op + 1);
571 return Offset.getReg() != 0;
572 }
573
574 // Load with negative register offset requires additional 1cyc and +I unit
575 // for Cortex A57
isAddrMode3OpMinusReg(const MachineInstr & MI,unsigned Op) const576 bool ARMBaseInstrInfo::isAddrMode3OpMinusReg(const MachineInstr &MI,
577 unsigned Op) const {
578 const MachineOperand &Offset = MI.getOperand(Op + 1);
579 const MachineOperand &Opc = MI.getOperand(Op + 2);
580 assert(Opc.isImm());
581 assert(Offset.isReg());
582 int64_t OpcImm = Opc.getImm();
583
584 bool isSub = ARM_AM::getAM3Op(OpcImm) == ARM_AM::sub;
585 return (isSub && Offset.getReg() != 0);
586 }
587
isLdstScaledReg(const MachineInstr & MI,unsigned Op) const588 bool ARMBaseInstrInfo::isLdstScaledReg(const MachineInstr &MI,
589 unsigned Op) const {
590 const MachineOperand &Opc = MI.getOperand(Op + 2);
591 unsigned OffImm = Opc.getImm();
592 return ARM_AM::getAM2ShiftOpc(OffImm) != ARM_AM::no_shift;
593 }
594
595 // Load, scaled register offset, not plus LSL2
isLdstScaledRegNotPlusLsl2(const MachineInstr & MI,unsigned Op) const596 bool ARMBaseInstrInfo::isLdstScaledRegNotPlusLsl2(const MachineInstr &MI,
597 unsigned Op) const {
598 const MachineOperand &Opc = MI.getOperand(Op + 2);
599 unsigned OffImm = Opc.getImm();
600
601 bool isAdd = ARM_AM::getAM2Op(OffImm) == ARM_AM::add;
602 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
603 ARM_AM::ShiftOpc ShiftOpc = ARM_AM::getAM2ShiftOpc(OffImm);
604 if (ShiftOpc == ARM_AM::no_shift) return false; // not scaled
605 bool SimpleScaled = (isAdd && ShiftOpc == ARM_AM::lsl && Amt == 2);
606 return !SimpleScaled;
607 }
608
609 // Minus reg for ldstso addr mode
isLdstSoMinusReg(const MachineInstr & MI,unsigned Op) const610 bool ARMBaseInstrInfo::isLdstSoMinusReg(const MachineInstr &MI,
611 unsigned Op) const {
612 unsigned OffImm = MI.getOperand(Op + 2).getImm();
613 return ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
614 }
615
616 // Load, scaled register offset
isAm2ScaledReg(const MachineInstr & MI,unsigned Op) const617 bool ARMBaseInstrInfo::isAm2ScaledReg(const MachineInstr &MI,
618 unsigned Op) const {
619 unsigned OffImm = MI.getOperand(Op + 2).getImm();
620 return ARM_AM::getAM2ShiftOpc(OffImm) != ARM_AM::no_shift;
621 }
622
isEligibleForITBlock(const MachineInstr * MI)623 static bool isEligibleForITBlock(const MachineInstr *MI) {
624 switch (MI->getOpcode()) {
625 default: return true;
626 case ARM::tADC: // ADC (register) T1
627 case ARM::tADDi3: // ADD (immediate) T1
628 case ARM::tADDi8: // ADD (immediate) T2
629 case ARM::tADDrr: // ADD (register) T1
630 case ARM::tAND: // AND (register) T1
631 case ARM::tASRri: // ASR (immediate) T1
632 case ARM::tASRrr: // ASR (register) T1
633 case ARM::tBIC: // BIC (register) T1
634 case ARM::tEOR: // EOR (register) T1
635 case ARM::tLSLri: // LSL (immediate) T1
636 case ARM::tLSLrr: // LSL (register) T1
637 case ARM::tLSRri: // LSR (immediate) T1
638 case ARM::tLSRrr: // LSR (register) T1
639 case ARM::tMUL: // MUL T1
640 case ARM::tMVN: // MVN (register) T1
641 case ARM::tORR: // ORR (register) T1
642 case ARM::tROR: // ROR (register) T1
643 case ARM::tRSB: // RSB (immediate) T1
644 case ARM::tSBC: // SBC (register) T1
645 case ARM::tSUBi3: // SUB (immediate) T1
646 case ARM::tSUBi8: // SUB (immediate) T2
647 case ARM::tSUBrr: // SUB (register) T1
648 return !ARMBaseInstrInfo::isCPSRDefined(*MI);
649 }
650 }
651
652 /// isPredicable - Return true if the specified instruction can be predicated.
653 /// By default, this returns true for every instruction with a
654 /// PredicateOperand.
isPredicable(const MachineInstr & MI) const655 bool ARMBaseInstrInfo::isPredicable(const MachineInstr &MI) const {
656 if (!MI.isPredicable())
657 return false;
658
659 if (MI.isBundle())
660 return false;
661
662 if (!isEligibleForITBlock(&MI))
663 return false;
664
665 const ARMFunctionInfo *AFI =
666 MI.getParent()->getParent()->getInfo<ARMFunctionInfo>();
667
668 // Neon instructions in Thumb2 IT blocks are deprecated, see ARMARM.
669 // In their ARM encoding, they can't be encoded in a conditional form.
670 if ((MI.getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
671 return false;
672
673 if (AFI->isThumb2Function()) {
674 if (getSubtarget().restrictIT())
675 return isV8EligibleForIT(&MI);
676 }
677
678 return true;
679 }
680
681 namespace llvm {
682
IsCPSRDead(const MachineInstr * MI)683 template <> bool IsCPSRDead<MachineInstr>(const MachineInstr *MI) {
684 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
685 const MachineOperand &MO = MI->getOperand(i);
686 if (!MO.isReg() || MO.isUndef() || MO.isUse())
687 continue;
688 if (MO.getReg() != ARM::CPSR)
689 continue;
690 if (!MO.isDead())
691 return false;
692 }
693 // all definitions of CPSR are dead
694 return true;
695 }
696
697 } // end namespace llvm
698
699 /// GetInstSize - Return the size of the specified MachineInstr.
700 ///
getInstSizeInBytes(const MachineInstr & MI) const701 unsigned ARMBaseInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
702 const MachineBasicBlock &MBB = *MI.getParent();
703 const MachineFunction *MF = MBB.getParent();
704 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
705
706 const MCInstrDesc &MCID = MI.getDesc();
707 if (MCID.getSize())
708 return MCID.getSize();
709
710 // If this machine instr is an inline asm, measure it.
711 if (MI.getOpcode() == ARM::INLINEASM) {
712 unsigned Size = getInlineAsmLength(MI.getOperand(0).getSymbolName(), *MAI);
713 if (!MF->getInfo<ARMFunctionInfo>()->isThumbFunction())
714 Size = alignTo(Size, 4);
715 return Size;
716 }
717 unsigned Opc = MI.getOpcode();
718 switch (Opc) {
719 default:
720 // pseudo-instruction sizes are zero.
721 return 0;
722 case TargetOpcode::BUNDLE:
723 return getInstBundleLength(MI);
724 case ARM::MOVi16_ga_pcrel:
725 case ARM::MOVTi16_ga_pcrel:
726 case ARM::t2MOVi16_ga_pcrel:
727 case ARM::t2MOVTi16_ga_pcrel:
728 return 4;
729 case ARM::MOVi32imm:
730 case ARM::t2MOVi32imm:
731 return 8;
732 case ARM::CONSTPOOL_ENTRY:
733 case ARM::JUMPTABLE_INSTS:
734 case ARM::JUMPTABLE_ADDRS:
735 case ARM::JUMPTABLE_TBB:
736 case ARM::JUMPTABLE_TBH:
737 // If this machine instr is a constant pool entry, its size is recorded as
738 // operand #2.
739 return MI.getOperand(2).getImm();
740 case ARM::Int_eh_sjlj_longjmp:
741 return 16;
742 case ARM::tInt_eh_sjlj_longjmp:
743 return 10;
744 case ARM::tInt_WIN_eh_sjlj_longjmp:
745 return 12;
746 case ARM::Int_eh_sjlj_setjmp:
747 case ARM::Int_eh_sjlj_setjmp_nofp:
748 return 20;
749 case ARM::tInt_eh_sjlj_setjmp:
750 case ARM::t2Int_eh_sjlj_setjmp:
751 case ARM::t2Int_eh_sjlj_setjmp_nofp:
752 return 12;
753 case ARM::SPACE:
754 return MI.getOperand(1).getImm();
755 }
756 }
757
getInstBundleLength(const MachineInstr & MI) const758 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr &MI) const {
759 unsigned Size = 0;
760 MachineBasicBlock::const_instr_iterator I = MI.getIterator();
761 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
762 while (++I != E && I->isInsideBundle()) {
763 assert(!I->isBundle() && "No nested bundle!");
764 Size += getInstSizeInBytes(*I);
765 }
766 return Size;
767 }
768
copyFromCPSR(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,unsigned DestReg,bool KillSrc,const ARMSubtarget & Subtarget) const769 void ARMBaseInstrInfo::copyFromCPSR(MachineBasicBlock &MBB,
770 MachineBasicBlock::iterator I,
771 unsigned DestReg, bool KillSrc,
772 const ARMSubtarget &Subtarget) const {
773 unsigned Opc = Subtarget.isThumb()
774 ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR)
775 : ARM::MRS;
776
777 MachineInstrBuilder MIB =
778 BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg);
779
780 // There is only 1 A/R class MRS instruction, and it always refers to
781 // APSR. However, there are lots of other possibilities on M-class cores.
782 if (Subtarget.isMClass())
783 MIB.addImm(0x800);
784
785 MIB.add(predOps(ARMCC::AL))
786 .addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc));
787 }
788
copyToCPSR(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,unsigned SrcReg,bool KillSrc,const ARMSubtarget & Subtarget) const789 void ARMBaseInstrInfo::copyToCPSR(MachineBasicBlock &MBB,
790 MachineBasicBlock::iterator I,
791 unsigned SrcReg, bool KillSrc,
792 const ARMSubtarget &Subtarget) const {
793 unsigned Opc = Subtarget.isThumb()
794 ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR)
795 : ARM::MSR;
796
797 MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
798
799 if (Subtarget.isMClass())
800 MIB.addImm(0x800);
801 else
802 MIB.addImm(8);
803
804 MIB.addReg(SrcReg, getKillRegState(KillSrc))
805 .add(predOps(ARMCC::AL))
806 .addReg(ARM::CPSR, RegState::Implicit | RegState::Define);
807 }
808
copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,const DebugLoc & DL,unsigned DestReg,unsigned SrcReg,bool KillSrc) const809 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
810 MachineBasicBlock::iterator I,
811 const DebugLoc &DL, unsigned DestReg,
812 unsigned SrcReg, bool KillSrc) const {
813 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
814 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
815
816 if (GPRDest && GPRSrc) {
817 BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
818 .addReg(SrcReg, getKillRegState(KillSrc))
819 .add(predOps(ARMCC::AL))
820 .add(condCodeOp());
821 return;
822 }
823
824 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
825 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
826
827 unsigned Opc = 0;
828 if (SPRDest && SPRSrc)
829 Opc = ARM::VMOVS;
830 else if (GPRDest && SPRSrc)
831 Opc = ARM::VMOVRS;
832 else if (SPRDest && GPRSrc)
833 Opc = ARM::VMOVSR;
834 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && !Subtarget.isFPOnlySP())
835 Opc = ARM::VMOVD;
836 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
837 Opc = ARM::VORRq;
838
839 if (Opc) {
840 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
841 MIB.addReg(SrcReg, getKillRegState(KillSrc));
842 if (Opc == ARM::VORRq)
843 MIB.addReg(SrcReg, getKillRegState(KillSrc));
844 MIB.add(predOps(ARMCC::AL));
845 return;
846 }
847
848 // Handle register classes that require multiple instructions.
849 unsigned BeginIdx = 0;
850 unsigned SubRegs = 0;
851 int Spacing = 1;
852
853 // Use VORRq when possible.
854 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) {
855 Opc = ARM::VORRq;
856 BeginIdx = ARM::qsub_0;
857 SubRegs = 2;
858 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
859 Opc = ARM::VORRq;
860 BeginIdx = ARM::qsub_0;
861 SubRegs = 4;
862 // Fall back to VMOVD.
863 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) {
864 Opc = ARM::VMOVD;
865 BeginIdx = ARM::dsub_0;
866 SubRegs = 2;
867 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) {
868 Opc = ARM::VMOVD;
869 BeginIdx = ARM::dsub_0;
870 SubRegs = 3;
871 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) {
872 Opc = ARM::VMOVD;
873 BeginIdx = ARM::dsub_0;
874 SubRegs = 4;
875 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) {
876 Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr;
877 BeginIdx = ARM::gsub_0;
878 SubRegs = 2;
879 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) {
880 Opc = ARM::VMOVD;
881 BeginIdx = ARM::dsub_0;
882 SubRegs = 2;
883 Spacing = 2;
884 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) {
885 Opc = ARM::VMOVD;
886 BeginIdx = ARM::dsub_0;
887 SubRegs = 3;
888 Spacing = 2;
889 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) {
890 Opc = ARM::VMOVD;
891 BeginIdx = ARM::dsub_0;
892 SubRegs = 4;
893 Spacing = 2;
894 } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.isFPOnlySP()) {
895 Opc = ARM::VMOVS;
896 BeginIdx = ARM::ssub_0;
897 SubRegs = 2;
898 } else if (SrcReg == ARM::CPSR) {
899 copyFromCPSR(MBB, I, DestReg, KillSrc, Subtarget);
900 return;
901 } else if (DestReg == ARM::CPSR) {
902 copyToCPSR(MBB, I, SrcReg, KillSrc, Subtarget);
903 return;
904 }
905
906 assert(Opc && "Impossible reg-to-reg copy");
907
908 const TargetRegisterInfo *TRI = &getRegisterInfo();
909 MachineInstrBuilder Mov;
910
911 // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
912 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
913 BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing);
914 Spacing = -Spacing;
915 }
916 #ifndef NDEBUG
917 SmallSet<unsigned, 4> DstRegs;
918 #endif
919 for (unsigned i = 0; i != SubRegs; ++i) {
920 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
921 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
922 assert(Dst && Src && "Bad sub-register");
923 #ifndef NDEBUG
924 assert(!DstRegs.count(Src) && "destructive vector copy");
925 DstRegs.insert(Dst);
926 #endif
927 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
928 // VORR takes two source operands.
929 if (Opc == ARM::VORRq)
930 Mov.addReg(Src);
931 Mov = Mov.add(predOps(ARMCC::AL));
932 // MOVr can set CC.
933 if (Opc == ARM::MOVr)
934 Mov = Mov.add(condCodeOp());
935 }
936 // Add implicit super-register defs and kills to the last instruction.
937 Mov->addRegisterDefined(DestReg, TRI);
938 if (KillSrc)
939 Mov->addRegisterKilled(SrcReg, TRI);
940 }
941
isCopyInstrImpl(const MachineInstr & MI,const MachineOperand * & Src,const MachineOperand * & Dest) const942 bool ARMBaseInstrInfo::isCopyInstrImpl(const MachineInstr &MI,
943 const MachineOperand *&Src,
944 const MachineOperand *&Dest) const {
945 // VMOVRRD is also a copy instruction but it requires
946 // special way of handling. It is more complex copy version
947 // and since that we are not considering it. For recognition
948 // of such instruction isExtractSubregLike MI interface fuction
949 // could be used.
950 // VORRq is considered as a move only if two inputs are
951 // the same register.
952 if (!MI.isMoveReg() ||
953 (MI.getOpcode() == ARM::VORRq &&
954 MI.getOperand(1).getReg() != MI.getOperand(2).getReg()))
955 return false;
956 Dest = &MI.getOperand(0);
957 Src = &MI.getOperand(1);
958 return true;
959 }
960
961 const MachineInstrBuilder &
AddDReg(MachineInstrBuilder & MIB,unsigned Reg,unsigned SubIdx,unsigned State,const TargetRegisterInfo * TRI) const962 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
963 unsigned SubIdx, unsigned State,
964 const TargetRegisterInfo *TRI) const {
965 if (!SubIdx)
966 return MIB.addReg(Reg, State);
967
968 if (TargetRegisterInfo::isPhysicalRegister(Reg))
969 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
970 return MIB.addReg(Reg, State, SubIdx);
971 }
972
973 void ARMBaseInstrInfo::
storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,unsigned SrcReg,bool isKill,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const974 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
975 unsigned SrcReg, bool isKill, int FI,
976 const TargetRegisterClass *RC,
977 const TargetRegisterInfo *TRI) const {
978 MachineFunction &MF = *MBB.getParent();
979 MachineFrameInfo &MFI = MF.getFrameInfo();
980 unsigned Align = MFI.getObjectAlignment(FI);
981
982 MachineMemOperand *MMO = MF.getMachineMemOperand(
983 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
984 MFI.getObjectSize(FI), Align);
985
986 switch (TRI->getSpillSize(*RC)) {
987 case 2:
988 if (ARM::HPRRegClass.hasSubClassEq(RC)) {
989 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRH))
990 .addReg(SrcReg, getKillRegState(isKill))
991 .addFrameIndex(FI)
992 .addImm(0)
993 .addMemOperand(MMO)
994 .add(predOps(ARMCC::AL));
995 } else
996 llvm_unreachable("Unknown reg class!");
997 break;
998 case 4:
999 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
1000 BuildMI(MBB, I, DebugLoc(), get(ARM::STRi12))
1001 .addReg(SrcReg, getKillRegState(isKill))
1002 .addFrameIndex(FI)
1003 .addImm(0)
1004 .addMemOperand(MMO)
1005 .add(predOps(ARMCC::AL));
1006 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
1007 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRS))
1008 .addReg(SrcReg, getKillRegState(isKill))
1009 .addFrameIndex(FI)
1010 .addImm(0)
1011 .addMemOperand(MMO)
1012 .add(predOps(ARMCC::AL));
1013 } else
1014 llvm_unreachable("Unknown reg class!");
1015 break;
1016 case 8:
1017 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
1018 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRD))
1019 .addReg(SrcReg, getKillRegState(isKill))
1020 .addFrameIndex(FI)
1021 .addImm(0)
1022 .addMemOperand(MMO)
1023 .add(predOps(ARMCC::AL));
1024 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
1025 if (Subtarget.hasV5TEOps()) {
1026 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STRD));
1027 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
1028 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
1029 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
1030 .add(predOps(ARMCC::AL));
1031 } else {
1032 // Fallback to STM instruction, which has existed since the dawn of
1033 // time.
1034 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STMIA))
1035 .addFrameIndex(FI)
1036 .addMemOperand(MMO)
1037 .add(predOps(ARMCC::AL));
1038 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
1039 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
1040 }
1041 } else
1042 llvm_unreachable("Unknown reg class!");
1043 break;
1044 case 16:
1045 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
1046 // Use aligned spills if the stack can be realigned.
1047 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1048 BuildMI(MBB, I, DebugLoc(), get(ARM::VST1q64))
1049 .addFrameIndex(FI)
1050 .addImm(16)
1051 .addReg(SrcReg, getKillRegState(isKill))
1052 .addMemOperand(MMO)
1053 .add(predOps(ARMCC::AL));
1054 } else {
1055 BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMQIA))
1056 .addReg(SrcReg, getKillRegState(isKill))
1057 .addFrameIndex(FI)
1058 .addMemOperand(MMO)
1059 .add(predOps(ARMCC::AL));
1060 }
1061 } else
1062 llvm_unreachable("Unknown reg class!");
1063 break;
1064 case 24:
1065 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1066 // Use aligned spills if the stack can be realigned.
1067 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1068 BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64TPseudo))
1069 .addFrameIndex(FI)
1070 .addImm(16)
1071 .addReg(SrcReg, getKillRegState(isKill))
1072 .addMemOperand(MMO)
1073 .add(predOps(ARMCC::AL));
1074 } else {
1075 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(),
1076 get(ARM::VSTMDIA))
1077 .addFrameIndex(FI)
1078 .add(predOps(ARMCC::AL))
1079 .addMemOperand(MMO);
1080 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1081 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1082 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1083 }
1084 } else
1085 llvm_unreachable("Unknown reg class!");
1086 break;
1087 case 32:
1088 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1089 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1090 // FIXME: It's possible to only store part of the QQ register if the
1091 // spilled def has a sub-register index.
1092 BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64QPseudo))
1093 .addFrameIndex(FI)
1094 .addImm(16)
1095 .addReg(SrcReg, getKillRegState(isKill))
1096 .addMemOperand(MMO)
1097 .add(predOps(ARMCC::AL));
1098 } else {
1099 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(),
1100 get(ARM::VSTMDIA))
1101 .addFrameIndex(FI)
1102 .add(predOps(ARMCC::AL))
1103 .addMemOperand(MMO);
1104 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1105 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1106 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1107 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
1108 }
1109 } else
1110 llvm_unreachable("Unknown reg class!");
1111 break;
1112 case 64:
1113 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1114 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMDIA))
1115 .addFrameIndex(FI)
1116 .add(predOps(ARMCC::AL))
1117 .addMemOperand(MMO);
1118 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1119 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1120 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1121 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
1122 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
1123 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
1124 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
1125 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
1126 } else
1127 llvm_unreachable("Unknown reg class!");
1128 break;
1129 default:
1130 llvm_unreachable("Unknown reg class!");
1131 }
1132 }
1133
isStoreToStackSlot(const MachineInstr & MI,int & FrameIndex) const1134 unsigned ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
1135 int &FrameIndex) const {
1136 switch (MI.getOpcode()) {
1137 default: break;
1138 case ARM::STRrs:
1139 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
1140 if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
1141 MI.getOperand(3).isImm() && MI.getOperand(2).getReg() == 0 &&
1142 MI.getOperand(3).getImm() == 0) {
1143 FrameIndex = MI.getOperand(1).getIndex();
1144 return MI.getOperand(0).getReg();
1145 }
1146 break;
1147 case ARM::STRi12:
1148 case ARM::t2STRi12:
1149 case ARM::tSTRspi:
1150 case ARM::VSTRD:
1151 case ARM::VSTRS:
1152 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
1153 MI.getOperand(2).getImm() == 0) {
1154 FrameIndex = MI.getOperand(1).getIndex();
1155 return MI.getOperand(0).getReg();
1156 }
1157 break;
1158 case ARM::VST1q64:
1159 case ARM::VST1d64TPseudo:
1160 case ARM::VST1d64QPseudo:
1161 if (MI.getOperand(0).isFI() && MI.getOperand(2).getSubReg() == 0) {
1162 FrameIndex = MI.getOperand(0).getIndex();
1163 return MI.getOperand(2).getReg();
1164 }
1165 break;
1166 case ARM::VSTMQIA:
1167 if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1168 FrameIndex = MI.getOperand(1).getIndex();
1169 return MI.getOperand(0).getReg();
1170 }
1171 break;
1172 }
1173
1174 return 0;
1175 }
1176
isStoreToStackSlotPostFE(const MachineInstr & MI,int & FrameIndex) const1177 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
1178 int &FrameIndex) const {
1179 SmallVector<const MachineMemOperand *, 1> Accesses;
1180 if (MI.mayStore() && hasStoreToStackSlot(MI, Accesses)) {
1181 FrameIndex =
1182 cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
1183 ->getFrameIndex();
1184 return true;
1185 }
1186 return false;
1187 }
1188
1189 void ARMBaseInstrInfo::
loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,unsigned DestReg,int FI,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const1190 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
1191 unsigned DestReg, int FI,
1192 const TargetRegisterClass *RC,
1193 const TargetRegisterInfo *TRI) const {
1194 DebugLoc DL;
1195 if (I != MBB.end()) DL = I->getDebugLoc();
1196 MachineFunction &MF = *MBB.getParent();
1197 MachineFrameInfo &MFI = MF.getFrameInfo();
1198 unsigned Align = MFI.getObjectAlignment(FI);
1199 MachineMemOperand *MMO = MF.getMachineMemOperand(
1200 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
1201 MFI.getObjectSize(FI), Align);
1202
1203 switch (TRI->getSpillSize(*RC)) {
1204 case 2:
1205 if (ARM::HPRRegClass.hasSubClassEq(RC)) {
1206 BuildMI(MBB, I, DL, get(ARM::VLDRH), DestReg)
1207 .addFrameIndex(FI)
1208 .addImm(0)
1209 .addMemOperand(MMO)
1210 .add(predOps(ARMCC::AL));
1211 } else
1212 llvm_unreachable("Unknown reg class!");
1213 break;
1214 case 4:
1215 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
1216 BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
1217 .addFrameIndex(FI)
1218 .addImm(0)
1219 .addMemOperand(MMO)
1220 .add(predOps(ARMCC::AL));
1221 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
1222 BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
1223 .addFrameIndex(FI)
1224 .addImm(0)
1225 .addMemOperand(MMO)
1226 .add(predOps(ARMCC::AL));
1227 } else
1228 llvm_unreachable("Unknown reg class!");
1229 break;
1230 case 8:
1231 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
1232 BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
1233 .addFrameIndex(FI)
1234 .addImm(0)
1235 .addMemOperand(MMO)
1236 .add(predOps(ARMCC::AL));
1237 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
1238 MachineInstrBuilder MIB;
1239
1240 if (Subtarget.hasV5TEOps()) {
1241 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
1242 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1243 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1244 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
1245 .add(predOps(ARMCC::AL));
1246 } else {
1247 // Fallback to LDM instruction, which has existed since the dawn of
1248 // time.
1249 MIB = BuildMI(MBB, I, DL, get(ARM::LDMIA))
1250 .addFrameIndex(FI)
1251 .addMemOperand(MMO)
1252 .add(predOps(ARMCC::AL));
1253 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1254 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1255 }
1256
1257 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1258 MIB.addReg(DestReg, RegState::ImplicitDefine);
1259 } else
1260 llvm_unreachable("Unknown reg class!");
1261 break;
1262 case 16:
1263 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
1264 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1265 BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
1266 .addFrameIndex(FI)
1267 .addImm(16)
1268 .addMemOperand(MMO)
1269 .add(predOps(ARMCC::AL));
1270 } else {
1271 BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
1272 .addFrameIndex(FI)
1273 .addMemOperand(MMO)
1274 .add(predOps(ARMCC::AL));
1275 }
1276 } else
1277 llvm_unreachable("Unknown reg class!");
1278 break;
1279 case 24:
1280 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1281 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1282 BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
1283 .addFrameIndex(FI)
1284 .addImm(16)
1285 .addMemOperand(MMO)
1286 .add(predOps(ARMCC::AL));
1287 } else {
1288 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1289 .addFrameIndex(FI)
1290 .addMemOperand(MMO)
1291 .add(predOps(ARMCC::AL));
1292 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1293 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1294 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1295 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1296 MIB.addReg(DestReg, RegState::ImplicitDefine);
1297 }
1298 } else
1299 llvm_unreachable("Unknown reg class!");
1300 break;
1301 case 32:
1302 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1303 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1304 BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1305 .addFrameIndex(FI)
1306 .addImm(16)
1307 .addMemOperand(MMO)
1308 .add(predOps(ARMCC::AL));
1309 } else {
1310 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1311 .addFrameIndex(FI)
1312 .add(predOps(ARMCC::AL))
1313 .addMemOperand(MMO);
1314 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1315 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1316 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1317 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1318 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1319 MIB.addReg(DestReg, RegState::ImplicitDefine);
1320 }
1321 } else
1322 llvm_unreachable("Unknown reg class!");
1323 break;
1324 case 64:
1325 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1326 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1327 .addFrameIndex(FI)
1328 .add(predOps(ARMCC::AL))
1329 .addMemOperand(MMO);
1330 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1331 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1332 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1333 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1334 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1335 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1336 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1337 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1338 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1339 MIB.addReg(DestReg, RegState::ImplicitDefine);
1340 } else
1341 llvm_unreachable("Unknown reg class!");
1342 break;
1343 default:
1344 llvm_unreachable("Unknown regclass!");
1345 }
1346 }
1347
isLoadFromStackSlot(const MachineInstr & MI,int & FrameIndex) const1348 unsigned ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
1349 int &FrameIndex) const {
1350 switch (MI.getOpcode()) {
1351 default: break;
1352 case ARM::LDRrs:
1353 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
1354 if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
1355 MI.getOperand(3).isImm() && MI.getOperand(2).getReg() == 0 &&
1356 MI.getOperand(3).getImm() == 0) {
1357 FrameIndex = MI.getOperand(1).getIndex();
1358 return MI.getOperand(0).getReg();
1359 }
1360 break;
1361 case ARM::LDRi12:
1362 case ARM::t2LDRi12:
1363 case ARM::tLDRspi:
1364 case ARM::VLDRD:
1365 case ARM::VLDRS:
1366 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
1367 MI.getOperand(2).getImm() == 0) {
1368 FrameIndex = MI.getOperand(1).getIndex();
1369 return MI.getOperand(0).getReg();
1370 }
1371 break;
1372 case ARM::VLD1q64:
1373 case ARM::VLD1d8TPseudo:
1374 case ARM::VLD1d16TPseudo:
1375 case ARM::VLD1d32TPseudo:
1376 case ARM::VLD1d64TPseudo:
1377 case ARM::VLD1d8QPseudo:
1378 case ARM::VLD1d16QPseudo:
1379 case ARM::VLD1d32QPseudo:
1380 case ARM::VLD1d64QPseudo:
1381 if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1382 FrameIndex = MI.getOperand(1).getIndex();
1383 return MI.getOperand(0).getReg();
1384 }
1385 break;
1386 case ARM::VLDMQIA:
1387 if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1388 FrameIndex = MI.getOperand(1).getIndex();
1389 return MI.getOperand(0).getReg();
1390 }
1391 break;
1392 }
1393
1394 return 0;
1395 }
1396
isLoadFromStackSlotPostFE(const MachineInstr & MI,int & FrameIndex) const1397 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
1398 int &FrameIndex) const {
1399 SmallVector<const MachineMemOperand *, 1> Accesses;
1400 if (MI.mayLoad() && hasLoadFromStackSlot(MI, Accesses)) {
1401 FrameIndex =
1402 cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
1403 ->getFrameIndex();
1404 return true;
1405 }
1406 return false;
1407 }
1408
1409 /// Expands MEMCPY to either LDMIA/STMIA or LDMIA_UPD/STMID_UPD
1410 /// depending on whether the result is used.
expandMEMCPY(MachineBasicBlock::iterator MI) const1411 void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const {
1412 bool isThumb1 = Subtarget.isThumb1Only();
1413 bool isThumb2 = Subtarget.isThumb2();
1414 const ARMBaseInstrInfo *TII = Subtarget.getInstrInfo();
1415
1416 DebugLoc dl = MI->getDebugLoc();
1417 MachineBasicBlock *BB = MI->getParent();
1418
1419 MachineInstrBuilder LDM, STM;
1420 if (isThumb1 || !MI->getOperand(1).isDead()) {
1421 MachineOperand LDWb(MI->getOperand(1));
1422 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD
1423 : isThumb1 ? ARM::tLDMIA_UPD
1424 : ARM::LDMIA_UPD))
1425 .add(LDWb);
1426 } else {
1427 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA : ARM::LDMIA));
1428 }
1429
1430 if (isThumb1 || !MI->getOperand(0).isDead()) {
1431 MachineOperand STWb(MI->getOperand(0));
1432 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD
1433 : isThumb1 ? ARM::tSTMIA_UPD
1434 : ARM::STMIA_UPD))
1435 .add(STWb);
1436 } else {
1437 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA));
1438 }
1439
1440 MachineOperand LDBase(MI->getOperand(3));
1441 LDM.add(LDBase).add(predOps(ARMCC::AL));
1442
1443 MachineOperand STBase(MI->getOperand(2));
1444 STM.add(STBase).add(predOps(ARMCC::AL));
1445
1446 // Sort the scratch registers into ascending order.
1447 const TargetRegisterInfo &TRI = getRegisterInfo();
1448 SmallVector<unsigned, 6> ScratchRegs;
1449 for(unsigned I = 5; I < MI->getNumOperands(); ++I)
1450 ScratchRegs.push_back(MI->getOperand(I).getReg());
1451 llvm::sort(ScratchRegs,
1452 [&TRI](const unsigned &Reg1, const unsigned &Reg2) -> bool {
1453 return TRI.getEncodingValue(Reg1) <
1454 TRI.getEncodingValue(Reg2);
1455 });
1456
1457 for (const auto &Reg : ScratchRegs) {
1458 LDM.addReg(Reg, RegState::Define);
1459 STM.addReg(Reg, RegState::Kill);
1460 }
1461
1462 BB->erase(MI);
1463 }
1464
expandPostRAPseudo(MachineInstr & MI) const1465 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1466 if (MI.getOpcode() == TargetOpcode::LOAD_STACK_GUARD) {
1467 assert(getSubtarget().getTargetTriple().isOSBinFormatMachO() &&
1468 "LOAD_STACK_GUARD currently supported only for MachO.");
1469 expandLoadStackGuard(MI);
1470 MI.getParent()->erase(MI);
1471 return true;
1472 }
1473
1474 if (MI.getOpcode() == ARM::MEMCPY) {
1475 expandMEMCPY(MI);
1476 return true;
1477 }
1478
1479 // This hook gets to expand COPY instructions before they become
1480 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1481 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1482 // changed into a VORR that can go down the NEON pipeline.
1483 if (!MI.isCopy() || Subtarget.dontWidenVMOVS() || Subtarget.isFPOnlySP())
1484 return false;
1485
1486 // Look for a copy between even S-registers. That is where we keep floats
1487 // when using NEON v2f32 instructions for f32 arithmetic.
1488 unsigned DstRegS = MI.getOperand(0).getReg();
1489 unsigned SrcRegS = MI.getOperand(1).getReg();
1490 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1491 return false;
1492
1493 const TargetRegisterInfo *TRI = &getRegisterInfo();
1494 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1495 &ARM::DPRRegClass);
1496 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1497 &ARM::DPRRegClass);
1498 if (!DstRegD || !SrcRegD)
1499 return false;
1500
1501 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1502 // legal if the COPY already defines the full DstRegD, and it isn't a
1503 // sub-register insertion.
1504 if (!MI.definesRegister(DstRegD, TRI) || MI.readsRegister(DstRegD, TRI))
1505 return false;
1506
1507 // A dead copy shouldn't show up here, but reject it just in case.
1508 if (MI.getOperand(0).isDead())
1509 return false;
1510
1511 // All clear, widen the COPY.
1512 LLVM_DEBUG(dbgs() << "widening: " << MI);
1513 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
1514
1515 // Get rid of the old implicit-def of DstRegD. Leave it if it defines a Q-reg
1516 // or some other super-register.
1517 int ImpDefIdx = MI.findRegisterDefOperandIdx(DstRegD);
1518 if (ImpDefIdx != -1)
1519 MI.RemoveOperand(ImpDefIdx);
1520
1521 // Change the opcode and operands.
1522 MI.setDesc(get(ARM::VMOVD));
1523 MI.getOperand(0).setReg(DstRegD);
1524 MI.getOperand(1).setReg(SrcRegD);
1525 MIB.add(predOps(ARMCC::AL));
1526
1527 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1528 // register scavenger and machine verifier, so we need to indicate that we
1529 // are reading an undefined value from SrcRegD, but a proper value from
1530 // SrcRegS.
1531 MI.getOperand(1).setIsUndef();
1532 MIB.addReg(SrcRegS, RegState::Implicit);
1533
1534 // SrcRegD may actually contain an unrelated value in the ssub_1
1535 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1536 if (MI.getOperand(1).isKill()) {
1537 MI.getOperand(1).setIsKill(false);
1538 MI.addRegisterKilled(SrcRegS, TRI, true);
1539 }
1540
1541 LLVM_DEBUG(dbgs() << "replaced by: " << MI);
1542 return true;
1543 }
1544
1545 /// Create a copy of a const pool value. Update CPI to the new index and return
1546 /// the label UID.
duplicateCPV(MachineFunction & MF,unsigned & CPI)1547 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1548 MachineConstantPool *MCP = MF.getConstantPool();
1549 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1550
1551 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1552 assert(MCPE.isMachineConstantPoolEntry() &&
1553 "Expecting a machine constantpool entry!");
1554 ARMConstantPoolValue *ACPV =
1555 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1556
1557 unsigned PCLabelId = AFI->createPICLabelUId();
1558 ARMConstantPoolValue *NewCPV = nullptr;
1559
1560 // FIXME: The below assumes PIC relocation model and that the function
1561 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1562 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1563 // instructions, so that's probably OK, but is PIC always correct when
1564 // we get here?
1565 if (ACPV->isGlobalValue())
1566 NewCPV = ARMConstantPoolConstant::Create(
1567 cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId, ARMCP::CPValue,
1568 4, ACPV->getModifier(), ACPV->mustAddCurrentAddress());
1569 else if (ACPV->isExtSymbol())
1570 NewCPV = ARMConstantPoolSymbol::
1571 Create(MF.getFunction().getContext(),
1572 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1573 else if (ACPV->isBlockAddress())
1574 NewCPV = ARMConstantPoolConstant::
1575 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1576 ARMCP::CPBlockAddress, 4);
1577 else if (ACPV->isLSDA())
1578 NewCPV = ARMConstantPoolConstant::Create(&MF.getFunction(), PCLabelId,
1579 ARMCP::CPLSDA, 4);
1580 else if (ACPV->isMachineBasicBlock())
1581 NewCPV = ARMConstantPoolMBB::
1582 Create(MF.getFunction().getContext(),
1583 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1584 else
1585 llvm_unreachable("Unexpected ARM constantpool value type!!");
1586 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1587 return PCLabelId;
1588 }
1589
reMaterialize(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,unsigned DestReg,unsigned SubIdx,const MachineInstr & Orig,const TargetRegisterInfo & TRI) const1590 void ARMBaseInstrInfo::reMaterialize(MachineBasicBlock &MBB,
1591 MachineBasicBlock::iterator I,
1592 unsigned DestReg, unsigned SubIdx,
1593 const MachineInstr &Orig,
1594 const TargetRegisterInfo &TRI) const {
1595 unsigned Opcode = Orig.getOpcode();
1596 switch (Opcode) {
1597 default: {
1598 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
1599 MI->substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
1600 MBB.insert(I, MI);
1601 break;
1602 }
1603 case ARM::tLDRpci_pic:
1604 case ARM::t2LDRpci_pic: {
1605 MachineFunction &MF = *MBB.getParent();
1606 unsigned CPI = Orig.getOperand(1).getIndex();
1607 unsigned PCLabelId = duplicateCPV(MF, CPI);
1608 BuildMI(MBB, I, Orig.getDebugLoc(), get(Opcode), DestReg)
1609 .addConstantPoolIndex(CPI)
1610 .addImm(PCLabelId)
1611 .cloneMemRefs(Orig);
1612 break;
1613 }
1614 }
1615 }
1616
1617 MachineInstr &
duplicate(MachineBasicBlock & MBB,MachineBasicBlock::iterator InsertBefore,const MachineInstr & Orig) const1618 ARMBaseInstrInfo::duplicate(MachineBasicBlock &MBB,
1619 MachineBasicBlock::iterator InsertBefore,
1620 const MachineInstr &Orig) const {
1621 MachineInstr &Cloned = TargetInstrInfo::duplicate(MBB, InsertBefore, Orig);
1622 MachineBasicBlock::instr_iterator I = Cloned.getIterator();
1623 for (;;) {
1624 switch (I->getOpcode()) {
1625 case ARM::tLDRpci_pic:
1626 case ARM::t2LDRpci_pic: {
1627 MachineFunction &MF = *MBB.getParent();
1628 unsigned CPI = I->getOperand(1).getIndex();
1629 unsigned PCLabelId = duplicateCPV(MF, CPI);
1630 I->getOperand(1).setIndex(CPI);
1631 I->getOperand(2).setImm(PCLabelId);
1632 break;
1633 }
1634 }
1635 if (!I->isBundledWithSucc())
1636 break;
1637 ++I;
1638 }
1639 return Cloned;
1640 }
1641
produceSameValue(const MachineInstr & MI0,const MachineInstr & MI1,const MachineRegisterInfo * MRI) const1642 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr &MI0,
1643 const MachineInstr &MI1,
1644 const MachineRegisterInfo *MRI) const {
1645 unsigned Opcode = MI0.getOpcode();
1646 if (Opcode == ARM::t2LDRpci ||
1647 Opcode == ARM::t2LDRpci_pic ||
1648 Opcode == ARM::tLDRpci ||
1649 Opcode == ARM::tLDRpci_pic ||
1650 Opcode == ARM::LDRLIT_ga_pcrel ||
1651 Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1652 Opcode == ARM::tLDRLIT_ga_pcrel ||
1653 Opcode == ARM::MOV_ga_pcrel ||
1654 Opcode == ARM::MOV_ga_pcrel_ldr ||
1655 Opcode == ARM::t2MOV_ga_pcrel) {
1656 if (MI1.getOpcode() != Opcode)
1657 return false;
1658 if (MI0.getNumOperands() != MI1.getNumOperands())
1659 return false;
1660
1661 const MachineOperand &MO0 = MI0.getOperand(1);
1662 const MachineOperand &MO1 = MI1.getOperand(1);
1663 if (MO0.getOffset() != MO1.getOffset())
1664 return false;
1665
1666 if (Opcode == ARM::LDRLIT_ga_pcrel ||
1667 Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1668 Opcode == ARM::tLDRLIT_ga_pcrel ||
1669 Opcode == ARM::MOV_ga_pcrel ||
1670 Opcode == ARM::MOV_ga_pcrel_ldr ||
1671 Opcode == ARM::t2MOV_ga_pcrel)
1672 // Ignore the PC labels.
1673 return MO0.getGlobal() == MO1.getGlobal();
1674
1675 const MachineFunction *MF = MI0.getParent()->getParent();
1676 const MachineConstantPool *MCP = MF->getConstantPool();
1677 int CPI0 = MO0.getIndex();
1678 int CPI1 = MO1.getIndex();
1679 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1680 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1681 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1682 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1683 if (isARMCP0 && isARMCP1) {
1684 ARMConstantPoolValue *ACPV0 =
1685 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1686 ARMConstantPoolValue *ACPV1 =
1687 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1688 return ACPV0->hasSameValue(ACPV1);
1689 } else if (!isARMCP0 && !isARMCP1) {
1690 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1691 }
1692 return false;
1693 } else if (Opcode == ARM::PICLDR) {
1694 if (MI1.getOpcode() != Opcode)
1695 return false;
1696 if (MI0.getNumOperands() != MI1.getNumOperands())
1697 return false;
1698
1699 unsigned Addr0 = MI0.getOperand(1).getReg();
1700 unsigned Addr1 = MI1.getOperand(1).getReg();
1701 if (Addr0 != Addr1) {
1702 if (!MRI ||
1703 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1704 !TargetRegisterInfo::isVirtualRegister(Addr1))
1705 return false;
1706
1707 // This assumes SSA form.
1708 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1709 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1710 // Check if the loaded value, e.g. a constantpool of a global address, are
1711 // the same.
1712 if (!produceSameValue(*Def0, *Def1, MRI))
1713 return false;
1714 }
1715
1716 for (unsigned i = 3, e = MI0.getNumOperands(); i != e; ++i) {
1717 // %12 = PICLDR %11, 0, 14, %noreg
1718 const MachineOperand &MO0 = MI0.getOperand(i);
1719 const MachineOperand &MO1 = MI1.getOperand(i);
1720 if (!MO0.isIdenticalTo(MO1))
1721 return false;
1722 }
1723 return true;
1724 }
1725
1726 return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1727 }
1728
1729 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1730 /// determine if two loads are loading from the same base address. It should
1731 /// only return true if the base pointers are the same and the only differences
1732 /// between the two addresses is the offset. It also returns the offsets by
1733 /// reference.
1734 ///
1735 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1736 /// is permanently disabled.
areLoadsFromSameBasePtr(SDNode * Load1,SDNode * Load2,int64_t & Offset1,int64_t & Offset2) const1737 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1738 int64_t &Offset1,
1739 int64_t &Offset2) const {
1740 // Don't worry about Thumb: just ARM and Thumb2.
1741 if (Subtarget.isThumb1Only()) return false;
1742
1743 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1744 return false;
1745
1746 switch (Load1->getMachineOpcode()) {
1747 default:
1748 return false;
1749 case ARM::LDRi12:
1750 case ARM::LDRBi12:
1751 case ARM::LDRD:
1752 case ARM::LDRH:
1753 case ARM::LDRSB:
1754 case ARM::LDRSH:
1755 case ARM::VLDRD:
1756 case ARM::VLDRS:
1757 case ARM::t2LDRi8:
1758 case ARM::t2LDRBi8:
1759 case ARM::t2LDRDi8:
1760 case ARM::t2LDRSHi8:
1761 case ARM::t2LDRi12:
1762 case ARM::t2LDRBi12:
1763 case ARM::t2LDRSHi12:
1764 break;
1765 }
1766
1767 switch (Load2->getMachineOpcode()) {
1768 default:
1769 return false;
1770 case ARM::LDRi12:
1771 case ARM::LDRBi12:
1772 case ARM::LDRD:
1773 case ARM::LDRH:
1774 case ARM::LDRSB:
1775 case ARM::LDRSH:
1776 case ARM::VLDRD:
1777 case ARM::VLDRS:
1778 case ARM::t2LDRi8:
1779 case ARM::t2LDRBi8:
1780 case ARM::t2LDRSHi8:
1781 case ARM::t2LDRi12:
1782 case ARM::t2LDRBi12:
1783 case ARM::t2LDRSHi12:
1784 break;
1785 }
1786
1787 // Check if base addresses and chain operands match.
1788 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1789 Load1->getOperand(4) != Load2->getOperand(4))
1790 return false;
1791
1792 // Index should be Reg0.
1793 if (Load1->getOperand(3) != Load2->getOperand(3))
1794 return false;
1795
1796 // Determine the offsets.
1797 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1798 isa<ConstantSDNode>(Load2->getOperand(1))) {
1799 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1800 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1801 return true;
1802 }
1803
1804 return false;
1805 }
1806
1807 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1808 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1809 /// be scheduled togther. On some targets if two loads are loading from
1810 /// addresses in the same cache line, it's better if they are scheduled
1811 /// together. This function takes two integers that represent the load offsets
1812 /// from the common base address. It returns true if it decides it's desirable
1813 /// to schedule the two loads together. "NumLoads" is the number of loads that
1814 /// have already been scheduled after Load1.
1815 ///
1816 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1817 /// is permanently disabled.
shouldScheduleLoadsNear(SDNode * Load1,SDNode * Load2,int64_t Offset1,int64_t Offset2,unsigned NumLoads) const1818 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1819 int64_t Offset1, int64_t Offset2,
1820 unsigned NumLoads) const {
1821 // Don't worry about Thumb: just ARM and Thumb2.
1822 if (Subtarget.isThumb1Only()) return false;
1823
1824 assert(Offset2 > Offset1);
1825
1826 if ((Offset2 - Offset1) / 8 > 64)
1827 return false;
1828
1829 // Check if the machine opcodes are different. If they are different
1830 // then we consider them to not be of the same base address,
1831 // EXCEPT in the case of Thumb2 byte loads where one is LDRBi8 and the other LDRBi12.
1832 // In this case, they are considered to be the same because they are different
1833 // encoding forms of the same basic instruction.
1834 if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) &&
1835 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 &&
1836 Load2->getMachineOpcode() == ARM::t2LDRBi12) ||
1837 (Load1->getMachineOpcode() == ARM::t2LDRBi12 &&
1838 Load2->getMachineOpcode() == ARM::t2LDRBi8)))
1839 return false; // FIXME: overly conservative?
1840
1841 // Four loads in a row should be sufficient.
1842 if (NumLoads >= 3)
1843 return false;
1844
1845 return true;
1846 }
1847
isSchedulingBoundary(const MachineInstr & MI,const MachineBasicBlock * MBB,const MachineFunction & MF) const1848 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
1849 const MachineBasicBlock *MBB,
1850 const MachineFunction &MF) const {
1851 // Debug info is never a scheduling boundary. It's necessary to be explicit
1852 // due to the special treatment of IT instructions below, otherwise a
1853 // dbg_value followed by an IT will result in the IT instruction being
1854 // considered a scheduling hazard, which is wrong. It should be the actual
1855 // instruction preceding the dbg_value instruction(s), just like it is
1856 // when debug info is not present.
1857 if (MI.isDebugInstr())
1858 return false;
1859
1860 // Terminators and labels can't be scheduled around.
1861 if (MI.isTerminator() || MI.isPosition())
1862 return true;
1863
1864 // Treat the start of the IT block as a scheduling boundary, but schedule
1865 // t2IT along with all instructions following it.
1866 // FIXME: This is a big hammer. But the alternative is to add all potential
1867 // true and anti dependencies to IT block instructions as implicit operands
1868 // to the t2IT instruction. The added compile time and complexity does not
1869 // seem worth it.
1870 MachineBasicBlock::const_iterator I = MI;
1871 // Make sure to skip any debug instructions
1872 while (++I != MBB->end() && I->isDebugInstr())
1873 ;
1874 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1875 return true;
1876
1877 // Don't attempt to schedule around any instruction that defines
1878 // a stack-oriented pointer, as it's unlikely to be profitable. This
1879 // saves compile time, because it doesn't require every single
1880 // stack slot reference to depend on the instruction that does the
1881 // modification.
1882 // Calls don't actually change the stack pointer, even if they have imp-defs.
1883 // No ARM calling conventions change the stack pointer. (X86 calling
1884 // conventions sometimes do).
1885 if (!MI.isCall() && MI.definesRegister(ARM::SP))
1886 return true;
1887
1888 return false;
1889 }
1890
1891 bool ARMBaseInstrInfo::
isProfitableToIfCvt(MachineBasicBlock & MBB,unsigned NumCycles,unsigned ExtraPredCycles,BranchProbability Probability) const1892 isProfitableToIfCvt(MachineBasicBlock &MBB,
1893 unsigned NumCycles, unsigned ExtraPredCycles,
1894 BranchProbability Probability) const {
1895 if (!NumCycles)
1896 return false;
1897
1898 // If we are optimizing for size, see if the branch in the predecessor can be
1899 // lowered to cbn?z by the constant island lowering pass, and return false if
1900 // so. This results in a shorter instruction sequence.
1901 if (MBB.getParent()->getFunction().optForSize()) {
1902 MachineBasicBlock *Pred = *MBB.pred_begin();
1903 if (!Pred->empty()) {
1904 MachineInstr *LastMI = &*Pred->rbegin();
1905 if (LastMI->getOpcode() == ARM::t2Bcc) {
1906 MachineBasicBlock::iterator CmpMI = LastMI;
1907 if (CmpMI != Pred->begin()) {
1908 --CmpMI;
1909 if (CmpMI->getOpcode() == ARM::tCMPi8 ||
1910 CmpMI->getOpcode() == ARM::t2CMPri) {
1911 unsigned Reg = CmpMI->getOperand(0).getReg();
1912 unsigned PredReg = 0;
1913 ARMCC::CondCodes P = getInstrPredicate(*CmpMI, PredReg);
1914 if (P == ARMCC::AL && CmpMI->getOperand(1).getImm() == 0 &&
1915 isARMLowRegister(Reg))
1916 return false;
1917 }
1918 }
1919 }
1920 }
1921 }
1922 return isProfitableToIfCvt(MBB, NumCycles, ExtraPredCycles,
1923 MBB, 0, 0, Probability);
1924 }
1925
1926 bool ARMBaseInstrInfo::
isProfitableToIfCvt(MachineBasicBlock & TBB,unsigned TCycles,unsigned TExtra,MachineBasicBlock & FBB,unsigned FCycles,unsigned FExtra,BranchProbability Probability) const1927 isProfitableToIfCvt(MachineBasicBlock &TBB,
1928 unsigned TCycles, unsigned TExtra,
1929 MachineBasicBlock &FBB,
1930 unsigned FCycles, unsigned FExtra,
1931 BranchProbability Probability) const {
1932 if (!TCycles)
1933 return false;
1934
1935 // Attempt to estimate the relative costs of predication versus branching.
1936 // Here we scale up each component of UnpredCost to avoid precision issue when
1937 // scaling TCycles/FCycles by Probability.
1938 const unsigned ScalingUpFactor = 1024;
1939
1940 unsigned PredCost = (TCycles + FCycles + TExtra + FExtra) * ScalingUpFactor;
1941 unsigned UnpredCost;
1942 if (!Subtarget.hasBranchPredictor()) {
1943 // When we don't have a branch predictor it's always cheaper to not take a
1944 // branch than take it, so we have to take that into account.
1945 unsigned NotTakenBranchCost = 1;
1946 unsigned TakenBranchCost = Subtarget.getMispredictionPenalty();
1947 unsigned TUnpredCycles, FUnpredCycles;
1948 if (!FCycles) {
1949 // Triangle: TBB is the fallthrough
1950 TUnpredCycles = TCycles + NotTakenBranchCost;
1951 FUnpredCycles = TakenBranchCost;
1952 } else {
1953 // Diamond: TBB is the block that is branched to, FBB is the fallthrough
1954 TUnpredCycles = TCycles + TakenBranchCost;
1955 FUnpredCycles = FCycles + NotTakenBranchCost;
1956 // The branch at the end of FBB will disappear when it's predicated, so
1957 // discount it from PredCost.
1958 PredCost -= 1 * ScalingUpFactor;
1959 }
1960 // The total cost is the cost of each path scaled by their probabilites
1961 unsigned TUnpredCost = Probability.scale(TUnpredCycles * ScalingUpFactor);
1962 unsigned FUnpredCost = Probability.getCompl().scale(FUnpredCycles * ScalingUpFactor);
1963 UnpredCost = TUnpredCost + FUnpredCost;
1964 // When predicating assume that the first IT can be folded away but later
1965 // ones cost one cycle each
1966 if (Subtarget.isThumb2() && TCycles + FCycles > 4) {
1967 PredCost += ((TCycles + FCycles - 4) / 4) * ScalingUpFactor;
1968 }
1969 } else {
1970 unsigned TUnpredCost = Probability.scale(TCycles * ScalingUpFactor);
1971 unsigned FUnpredCost =
1972 Probability.getCompl().scale(FCycles * ScalingUpFactor);
1973 UnpredCost = TUnpredCost + FUnpredCost;
1974 UnpredCost += 1 * ScalingUpFactor; // The branch itself
1975 UnpredCost += Subtarget.getMispredictionPenalty() * ScalingUpFactor / 10;
1976 }
1977
1978 return PredCost <= UnpredCost;
1979 }
1980
1981 bool
isProfitableToUnpredicate(MachineBasicBlock & TMBB,MachineBasicBlock & FMBB) const1982 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
1983 MachineBasicBlock &FMBB) const {
1984 // Reduce false anti-dependencies to let the target's out-of-order execution
1985 // engine do its thing.
1986 return Subtarget.isProfitableToUnpredicate();
1987 }
1988
1989 /// getInstrPredicate - If instruction is predicated, returns its predicate
1990 /// condition, otherwise returns AL. It also returns the condition code
1991 /// register by reference.
getInstrPredicate(const MachineInstr & MI,unsigned & PredReg)1992 ARMCC::CondCodes llvm::getInstrPredicate(const MachineInstr &MI,
1993 unsigned &PredReg) {
1994 int PIdx = MI.findFirstPredOperandIdx();
1995 if (PIdx == -1) {
1996 PredReg = 0;
1997 return ARMCC::AL;
1998 }
1999
2000 PredReg = MI.getOperand(PIdx+1).getReg();
2001 return (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
2002 }
2003
getMatchingCondBranchOpcode(unsigned Opc)2004 unsigned llvm::getMatchingCondBranchOpcode(unsigned Opc) {
2005 if (Opc == ARM::B)
2006 return ARM::Bcc;
2007 if (Opc == ARM::tB)
2008 return ARM::tBcc;
2009 if (Opc == ARM::t2B)
2010 return ARM::t2Bcc;
2011
2012 llvm_unreachable("Unknown unconditional branch opcode!");
2013 }
2014
commuteInstructionImpl(MachineInstr & MI,bool NewMI,unsigned OpIdx1,unsigned OpIdx2) const2015 MachineInstr *ARMBaseInstrInfo::commuteInstructionImpl(MachineInstr &MI,
2016 bool NewMI,
2017 unsigned OpIdx1,
2018 unsigned OpIdx2) const {
2019 switch (MI.getOpcode()) {
2020 case ARM::MOVCCr:
2021 case ARM::t2MOVCCr: {
2022 // MOVCC can be commuted by inverting the condition.
2023 unsigned PredReg = 0;
2024 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
2025 // MOVCC AL can't be inverted. Shouldn't happen.
2026 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
2027 return nullptr;
2028 MachineInstr *CommutedMI =
2029 TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
2030 if (!CommutedMI)
2031 return nullptr;
2032 // After swapping the MOVCC operands, also invert the condition.
2033 CommutedMI->getOperand(CommutedMI->findFirstPredOperandIdx())
2034 .setImm(ARMCC::getOppositeCondition(CC));
2035 return CommutedMI;
2036 }
2037 }
2038 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
2039 }
2040
2041 /// Identify instructions that can be folded into a MOVCC instruction, and
2042 /// return the defining instruction.
canFoldIntoMOVCC(unsigned Reg,const MachineRegisterInfo & MRI,const TargetInstrInfo * TII)2043 static MachineInstr *canFoldIntoMOVCC(unsigned Reg,
2044 const MachineRegisterInfo &MRI,
2045 const TargetInstrInfo *TII) {
2046 if (!TargetRegisterInfo::isVirtualRegister(Reg))
2047 return nullptr;
2048 if (!MRI.hasOneNonDBGUse(Reg))
2049 return nullptr;
2050 MachineInstr *MI = MRI.getVRegDef(Reg);
2051 if (!MI)
2052 return nullptr;
2053 // MI is folded into the MOVCC by predicating it.
2054 if (!MI->isPredicable())
2055 return nullptr;
2056 // Check if MI has any non-dead defs or physreg uses. This also detects
2057 // predicated instructions which will be reading CPSR.
2058 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
2059 const MachineOperand &MO = MI->getOperand(i);
2060 // Reject frame index operands, PEI can't handle the predicated pseudos.
2061 if (MO.isFI() || MO.isCPI() || MO.isJTI())
2062 return nullptr;
2063 if (!MO.isReg())
2064 continue;
2065 // MI can't have any tied operands, that would conflict with predication.
2066 if (MO.isTied())
2067 return nullptr;
2068 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
2069 return nullptr;
2070 if (MO.isDef() && !MO.isDead())
2071 return nullptr;
2072 }
2073 bool DontMoveAcrossStores = true;
2074 if (!MI->isSafeToMove(/* AliasAnalysis = */ nullptr, DontMoveAcrossStores))
2075 return nullptr;
2076 return MI;
2077 }
2078
analyzeSelect(const MachineInstr & MI,SmallVectorImpl<MachineOperand> & Cond,unsigned & TrueOp,unsigned & FalseOp,bool & Optimizable) const2079 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr &MI,
2080 SmallVectorImpl<MachineOperand> &Cond,
2081 unsigned &TrueOp, unsigned &FalseOp,
2082 bool &Optimizable) const {
2083 assert((MI.getOpcode() == ARM::MOVCCr || MI.getOpcode() == ARM::t2MOVCCr) &&
2084 "Unknown select instruction");
2085 // MOVCC operands:
2086 // 0: Def.
2087 // 1: True use.
2088 // 2: False use.
2089 // 3: Condition code.
2090 // 4: CPSR use.
2091 TrueOp = 1;
2092 FalseOp = 2;
2093 Cond.push_back(MI.getOperand(3));
2094 Cond.push_back(MI.getOperand(4));
2095 // We can always fold a def.
2096 Optimizable = true;
2097 return false;
2098 }
2099
2100 MachineInstr *
optimizeSelect(MachineInstr & MI,SmallPtrSetImpl<MachineInstr * > & SeenMIs,bool PreferFalse) const2101 ARMBaseInstrInfo::optimizeSelect(MachineInstr &MI,
2102 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
2103 bool PreferFalse) const {
2104 assert((MI.getOpcode() == ARM::MOVCCr || MI.getOpcode() == ARM::t2MOVCCr) &&
2105 "Unknown select instruction");
2106 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
2107 MachineInstr *DefMI = canFoldIntoMOVCC(MI.getOperand(2).getReg(), MRI, this);
2108 bool Invert = !DefMI;
2109 if (!DefMI)
2110 DefMI = canFoldIntoMOVCC(MI.getOperand(1).getReg(), MRI, this);
2111 if (!DefMI)
2112 return nullptr;
2113
2114 // Find new register class to use.
2115 MachineOperand FalseReg = MI.getOperand(Invert ? 2 : 1);
2116 unsigned DestReg = MI.getOperand(0).getReg();
2117 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
2118 if (!MRI.constrainRegClass(DestReg, PreviousClass))
2119 return nullptr;
2120
2121 // Create a new predicated version of DefMI.
2122 // Rfalse is the first use.
2123 MachineInstrBuilder NewMI =
2124 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg);
2125
2126 // Copy all the DefMI operands, excluding its (null) predicate.
2127 const MCInstrDesc &DefDesc = DefMI->getDesc();
2128 for (unsigned i = 1, e = DefDesc.getNumOperands();
2129 i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
2130 NewMI.add(DefMI->getOperand(i));
2131
2132 unsigned CondCode = MI.getOperand(3).getImm();
2133 if (Invert)
2134 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
2135 else
2136 NewMI.addImm(CondCode);
2137 NewMI.add(MI.getOperand(4));
2138
2139 // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
2140 if (NewMI->hasOptionalDef())
2141 NewMI.add(condCodeOp());
2142
2143 // The output register value when the predicate is false is an implicit
2144 // register operand tied to the first def.
2145 // The tie makes the register allocator ensure the FalseReg is allocated the
2146 // same register as operand 0.
2147 FalseReg.setImplicit();
2148 NewMI.add(FalseReg);
2149 NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
2150
2151 // Update SeenMIs set: register newly created MI and erase removed DefMI.
2152 SeenMIs.insert(NewMI);
2153 SeenMIs.erase(DefMI);
2154
2155 // If MI is inside a loop, and DefMI is outside the loop, then kill flags on
2156 // DefMI would be invalid when tranferred inside the loop. Checking for a
2157 // loop is expensive, but at least remove kill flags if they are in different
2158 // BBs.
2159 if (DefMI->getParent() != MI.getParent())
2160 NewMI->clearKillInfo();
2161
2162 // The caller will erase MI, but not DefMI.
2163 DefMI->eraseFromParent();
2164 return NewMI;
2165 }
2166
2167 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
2168 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
2169 /// def operand.
2170 ///
2171 /// This will go away once we can teach tblgen how to set the optional CPSR def
2172 /// operand itself.
2173 struct AddSubFlagsOpcodePair {
2174 uint16_t PseudoOpc;
2175 uint16_t MachineOpc;
2176 };
2177
2178 static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
2179 {ARM::ADDSri, ARM::ADDri},
2180 {ARM::ADDSrr, ARM::ADDrr},
2181 {ARM::ADDSrsi, ARM::ADDrsi},
2182 {ARM::ADDSrsr, ARM::ADDrsr},
2183
2184 {ARM::SUBSri, ARM::SUBri},
2185 {ARM::SUBSrr, ARM::SUBrr},
2186 {ARM::SUBSrsi, ARM::SUBrsi},
2187 {ARM::SUBSrsr, ARM::SUBrsr},
2188
2189 {ARM::RSBSri, ARM::RSBri},
2190 {ARM::RSBSrsi, ARM::RSBrsi},
2191 {ARM::RSBSrsr, ARM::RSBrsr},
2192
2193 {ARM::tADDSi3, ARM::tADDi3},
2194 {ARM::tADDSi8, ARM::tADDi8},
2195 {ARM::tADDSrr, ARM::tADDrr},
2196 {ARM::tADCS, ARM::tADC},
2197
2198 {ARM::tSUBSi3, ARM::tSUBi3},
2199 {ARM::tSUBSi8, ARM::tSUBi8},
2200 {ARM::tSUBSrr, ARM::tSUBrr},
2201 {ARM::tSBCS, ARM::tSBC},
2202 {ARM::tRSBS, ARM::tRSB},
2203
2204 {ARM::t2ADDSri, ARM::t2ADDri},
2205 {ARM::t2ADDSrr, ARM::t2ADDrr},
2206 {ARM::t2ADDSrs, ARM::t2ADDrs},
2207
2208 {ARM::t2SUBSri, ARM::t2SUBri},
2209 {ARM::t2SUBSrr, ARM::t2SUBrr},
2210 {ARM::t2SUBSrs, ARM::t2SUBrs},
2211
2212 {ARM::t2RSBSri, ARM::t2RSBri},
2213 {ARM::t2RSBSrs, ARM::t2RSBrs},
2214 };
2215
convertAddSubFlagsOpcode(unsigned OldOpc)2216 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
2217 for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i)
2218 if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc)
2219 return AddSubFlagsOpcodeMap[i].MachineOpc;
2220 return 0;
2221 }
2222
emitARMRegPlusImmediate(MachineBasicBlock & MBB,MachineBasicBlock::iterator & MBBI,const DebugLoc & dl,unsigned DestReg,unsigned BaseReg,int NumBytes,ARMCC::CondCodes Pred,unsigned PredReg,const ARMBaseInstrInfo & TII,unsigned MIFlags)2223 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
2224 MachineBasicBlock::iterator &MBBI,
2225 const DebugLoc &dl, unsigned DestReg,
2226 unsigned BaseReg, int NumBytes,
2227 ARMCC::CondCodes Pred, unsigned PredReg,
2228 const ARMBaseInstrInfo &TII,
2229 unsigned MIFlags) {
2230 if (NumBytes == 0 && DestReg != BaseReg) {
2231 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg)
2232 .addReg(BaseReg, RegState::Kill)
2233 .add(predOps(Pred, PredReg))
2234 .add(condCodeOp())
2235 .setMIFlags(MIFlags);
2236 return;
2237 }
2238
2239 bool isSub = NumBytes < 0;
2240 if (isSub) NumBytes = -NumBytes;
2241
2242 while (NumBytes) {
2243 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
2244 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
2245 assert(ThisVal && "Didn't extract field correctly");
2246
2247 // We will handle these bits from offset, clear them.
2248 NumBytes &= ~ThisVal;
2249
2250 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
2251
2252 // Build the new ADD / SUB.
2253 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
2254 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
2255 .addReg(BaseReg, RegState::Kill)
2256 .addImm(ThisVal)
2257 .add(predOps(Pred, PredReg))
2258 .add(condCodeOp())
2259 .setMIFlags(MIFlags);
2260 BaseReg = DestReg;
2261 }
2262 }
2263
tryFoldSPUpdateIntoPushPop(const ARMSubtarget & Subtarget,MachineFunction & MF,MachineInstr * MI,unsigned NumBytes)2264 bool llvm::tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
2265 MachineFunction &MF, MachineInstr *MI,
2266 unsigned NumBytes) {
2267 // This optimisation potentially adds lots of load and store
2268 // micro-operations, it's only really a great benefit to code-size.
2269 if (!MF.getFunction().optForMinSize())
2270 return false;
2271
2272 // If only one register is pushed/popped, LLVM can use an LDR/STR
2273 // instead. We can't modify those so make sure we're dealing with an
2274 // instruction we understand.
2275 bool IsPop = isPopOpcode(MI->getOpcode());
2276 bool IsPush = isPushOpcode(MI->getOpcode());
2277 if (!IsPush && !IsPop)
2278 return false;
2279
2280 bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD ||
2281 MI->getOpcode() == ARM::VLDMDIA_UPD;
2282 bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH ||
2283 MI->getOpcode() == ARM::tPOP ||
2284 MI->getOpcode() == ARM::tPOP_RET;
2285
2286 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP &&
2287 MI->getOperand(1).getReg() == ARM::SP)) &&
2288 "trying to fold sp update into non-sp-updating push/pop");
2289
2290 // The VFP push & pop act on D-registers, so we can only fold an adjustment
2291 // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try
2292 // if this is violated.
2293 if (NumBytes % (IsVFPPushPop ? 8 : 4) != 0)
2294 return false;
2295
2296 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
2297 // pred) so the list starts at 4. Thumb1 starts after the predicate.
2298 int RegListIdx = IsT1PushPop ? 2 : 4;
2299
2300 // Calculate the space we'll need in terms of registers.
2301 unsigned RegsNeeded;
2302 const TargetRegisterClass *RegClass;
2303 if (IsVFPPushPop) {
2304 RegsNeeded = NumBytes / 8;
2305 RegClass = &ARM::DPRRegClass;
2306 } else {
2307 RegsNeeded = NumBytes / 4;
2308 RegClass = &ARM::GPRRegClass;
2309 }
2310
2311 // We're going to have to strip all list operands off before
2312 // re-adding them since the order matters, so save the existing ones
2313 // for later.
2314 SmallVector<MachineOperand, 4> RegList;
2315
2316 // We're also going to need the first register transferred by this
2317 // instruction, which won't necessarily be the first register in the list.
2318 unsigned FirstRegEnc = -1;
2319
2320 const TargetRegisterInfo *TRI = MF.getRegInfo().getTargetRegisterInfo();
2321 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i) {
2322 MachineOperand &MO = MI->getOperand(i);
2323 RegList.push_back(MO);
2324
2325 if (MO.isReg() && TRI->getEncodingValue(MO.getReg()) < FirstRegEnc)
2326 FirstRegEnc = TRI->getEncodingValue(MO.getReg());
2327 }
2328
2329 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
2330
2331 // Now try to find enough space in the reglist to allocate NumBytes.
2332 for (int CurRegEnc = FirstRegEnc - 1; CurRegEnc >= 0 && RegsNeeded;
2333 --CurRegEnc) {
2334 unsigned CurReg = RegClass->getRegister(CurRegEnc);
2335 if (!IsPop) {
2336 // Pushing any register is completely harmless, mark the register involved
2337 // as undef since we don't care about its value and must not restore it
2338 // during stack unwinding.
2339 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false,
2340 false, false, true));
2341 --RegsNeeded;
2342 continue;
2343 }
2344
2345 // However, we can only pop an extra register if it's not live. For
2346 // registers live within the function we might clobber a return value
2347 // register; the other way a register can be live here is if it's
2348 // callee-saved.
2349 if (isCalleeSavedRegister(CurReg, CSRegs) ||
2350 MI->getParent()->computeRegisterLiveness(TRI, CurReg, MI) !=
2351 MachineBasicBlock::LQR_Dead) {
2352 // VFP pops don't allow holes in the register list, so any skip is fatal
2353 // for our transformation. GPR pops do, so we should just keep looking.
2354 if (IsVFPPushPop)
2355 return false;
2356 else
2357 continue;
2358 }
2359
2360 // Mark the unimportant registers as <def,dead> in the POP.
2361 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false,
2362 true));
2363 --RegsNeeded;
2364 }
2365
2366 if (RegsNeeded > 0)
2367 return false;
2368
2369 // Finally we know we can profitably perform the optimisation so go
2370 // ahead: strip all existing registers off and add them back again
2371 // in the right order.
2372 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
2373 MI->RemoveOperand(i);
2374
2375 // Add the complete list back in.
2376 MachineInstrBuilder MIB(MF, &*MI);
2377 for (int i = RegList.size() - 1; i >= 0; --i)
2378 MIB.add(RegList[i]);
2379
2380 return true;
2381 }
2382
rewriteARMFrameIndex(MachineInstr & MI,unsigned FrameRegIdx,unsigned FrameReg,int & Offset,const ARMBaseInstrInfo & TII)2383 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
2384 unsigned FrameReg, int &Offset,
2385 const ARMBaseInstrInfo &TII) {
2386 unsigned Opcode = MI.getOpcode();
2387 const MCInstrDesc &Desc = MI.getDesc();
2388 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
2389 bool isSub = false;
2390
2391 // Memory operands in inline assembly always use AddrMode2.
2392 if (Opcode == ARM::INLINEASM)
2393 AddrMode = ARMII::AddrMode2;
2394
2395 if (Opcode == ARM::ADDri) {
2396 Offset += MI.getOperand(FrameRegIdx+1).getImm();
2397 if (Offset == 0) {
2398 // Turn it into a move.
2399 MI.setDesc(TII.get(ARM::MOVr));
2400 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2401 MI.RemoveOperand(FrameRegIdx+1);
2402 Offset = 0;
2403 return true;
2404 } else if (Offset < 0) {
2405 Offset = -Offset;
2406 isSub = true;
2407 MI.setDesc(TII.get(ARM::SUBri));
2408 }
2409
2410 // Common case: small offset, fits into instruction.
2411 if (ARM_AM::getSOImmVal(Offset) != -1) {
2412 // Replace the FrameIndex with sp / fp
2413 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2414 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
2415 Offset = 0;
2416 return true;
2417 }
2418
2419 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
2420 // as possible.
2421 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
2422 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
2423
2424 // We will handle these bits from offset, clear them.
2425 Offset &= ~ThisImmVal;
2426
2427 // Get the properly encoded SOImmVal field.
2428 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
2429 "Bit extraction didn't work?");
2430 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
2431 } else {
2432 unsigned ImmIdx = 0;
2433 int InstrOffs = 0;
2434 unsigned NumBits = 0;
2435 unsigned Scale = 1;
2436 switch (AddrMode) {
2437 case ARMII::AddrMode_i12:
2438 ImmIdx = FrameRegIdx + 1;
2439 InstrOffs = MI.getOperand(ImmIdx).getImm();
2440 NumBits = 12;
2441 break;
2442 case ARMII::AddrMode2:
2443 ImmIdx = FrameRegIdx+2;
2444 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
2445 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2446 InstrOffs *= -1;
2447 NumBits = 12;
2448 break;
2449 case ARMII::AddrMode3:
2450 ImmIdx = FrameRegIdx+2;
2451 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
2452 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2453 InstrOffs *= -1;
2454 NumBits = 8;
2455 break;
2456 case ARMII::AddrMode4:
2457 case ARMII::AddrMode6:
2458 // Can't fold any offset even if it's zero.
2459 return false;
2460 case ARMII::AddrMode5:
2461 ImmIdx = FrameRegIdx+1;
2462 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2463 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2464 InstrOffs *= -1;
2465 NumBits = 8;
2466 Scale = 4;
2467 break;
2468 case ARMII::AddrMode5FP16:
2469 ImmIdx = FrameRegIdx+1;
2470 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2471 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2472 InstrOffs *= -1;
2473 NumBits = 8;
2474 Scale = 2;
2475 break;
2476 default:
2477 llvm_unreachable("Unsupported addressing mode!");
2478 }
2479
2480 Offset += InstrOffs * Scale;
2481 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
2482 if (Offset < 0) {
2483 Offset = -Offset;
2484 isSub = true;
2485 }
2486
2487 // Attempt to fold address comp. if opcode has offset bits
2488 if (NumBits > 0) {
2489 // Common case: small offset, fits into instruction.
2490 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
2491 int ImmedOffset = Offset / Scale;
2492 unsigned Mask = (1 << NumBits) - 1;
2493 if ((unsigned)Offset <= Mask * Scale) {
2494 // Replace the FrameIndex with sp
2495 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2496 // FIXME: When addrmode2 goes away, this will simplify (like the
2497 // T2 version), as the LDR.i12 versions don't need the encoding
2498 // tricks for the offset value.
2499 if (isSub) {
2500 if (AddrMode == ARMII::AddrMode_i12)
2501 ImmedOffset = -ImmedOffset;
2502 else
2503 ImmedOffset |= 1 << NumBits;
2504 }
2505 ImmOp.ChangeToImmediate(ImmedOffset);
2506 Offset = 0;
2507 return true;
2508 }
2509
2510 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
2511 ImmedOffset = ImmedOffset & Mask;
2512 if (isSub) {
2513 if (AddrMode == ARMII::AddrMode_i12)
2514 ImmedOffset = -ImmedOffset;
2515 else
2516 ImmedOffset |= 1 << NumBits;
2517 }
2518 ImmOp.ChangeToImmediate(ImmedOffset);
2519 Offset &= ~(Mask*Scale);
2520 }
2521 }
2522
2523 Offset = (isSub) ? -Offset : Offset;
2524 return Offset == 0;
2525 }
2526
2527 /// analyzeCompare - For a comparison instruction, return the source registers
2528 /// in SrcReg and SrcReg2 if having two register operands, and the value it
2529 /// compares against in CmpValue. Return true if the comparison instruction
2530 /// can be analyzed.
analyzeCompare(const MachineInstr & MI,unsigned & SrcReg,unsigned & SrcReg2,int & CmpMask,int & CmpValue) const2531 bool ARMBaseInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
2532 unsigned &SrcReg2, int &CmpMask,
2533 int &CmpValue) const {
2534 switch (MI.getOpcode()) {
2535 default: break;
2536 case ARM::CMPri:
2537 case ARM::t2CMPri:
2538 case ARM::tCMPi8:
2539 SrcReg = MI.getOperand(0).getReg();
2540 SrcReg2 = 0;
2541 CmpMask = ~0;
2542 CmpValue = MI.getOperand(1).getImm();
2543 return true;
2544 case ARM::CMPrr:
2545 case ARM::t2CMPrr:
2546 SrcReg = MI.getOperand(0).getReg();
2547 SrcReg2 = MI.getOperand(1).getReg();
2548 CmpMask = ~0;
2549 CmpValue = 0;
2550 return true;
2551 case ARM::TSTri:
2552 case ARM::t2TSTri:
2553 SrcReg = MI.getOperand(0).getReg();
2554 SrcReg2 = 0;
2555 CmpMask = MI.getOperand(1).getImm();
2556 CmpValue = 0;
2557 return true;
2558 }
2559
2560 return false;
2561 }
2562
2563 /// isSuitableForMask - Identify a suitable 'and' instruction that
2564 /// operates on the given source register and applies the same mask
2565 /// as a 'tst' instruction. Provide a limited look-through for copies.
2566 /// When successful, MI will hold the found instruction.
isSuitableForMask(MachineInstr * & MI,unsigned SrcReg,int CmpMask,bool CommonUse)2567 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
2568 int CmpMask, bool CommonUse) {
2569 switch (MI->getOpcode()) {
2570 case ARM::ANDri:
2571 case ARM::t2ANDri:
2572 if (CmpMask != MI->getOperand(2).getImm())
2573 return false;
2574 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
2575 return true;
2576 break;
2577 }
2578
2579 return false;
2580 }
2581
2582 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2583 /// the condition code if we modify the instructions such that flags are
2584 /// set by MI(b,a).
getSwappedCondition(ARMCC::CondCodes CC)2585 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) {
2586 switch (CC) {
2587 default: return ARMCC::AL;
2588 case ARMCC::EQ: return ARMCC::EQ;
2589 case ARMCC::NE: return ARMCC::NE;
2590 case ARMCC::HS: return ARMCC::LS;
2591 case ARMCC::LO: return ARMCC::HI;
2592 case ARMCC::HI: return ARMCC::LO;
2593 case ARMCC::LS: return ARMCC::HS;
2594 case ARMCC::GE: return ARMCC::LE;
2595 case ARMCC::LT: return ARMCC::GT;
2596 case ARMCC::GT: return ARMCC::LT;
2597 case ARMCC::LE: return ARMCC::GE;
2598 }
2599 }
2600
2601 /// getCmpToAddCondition - assume the flags are set by CMP(a,b), return
2602 /// the condition code if we modify the instructions such that flags are
2603 /// set by ADD(a,b,X).
getCmpToAddCondition(ARMCC::CondCodes CC)2604 inline static ARMCC::CondCodes getCmpToAddCondition(ARMCC::CondCodes CC) {
2605 switch (CC) {
2606 default: return ARMCC::AL;
2607 case ARMCC::HS: return ARMCC::LO;
2608 case ARMCC::LO: return ARMCC::HS;
2609 case ARMCC::VS: return ARMCC::VS;
2610 case ARMCC::VC: return ARMCC::VC;
2611 }
2612 }
2613
2614 /// isRedundantFlagInstr - check whether the first instruction, whose only
2615 /// purpose is to update flags, can be made redundant.
2616 /// CMPrr can be made redundant by SUBrr if the operands are the same.
2617 /// CMPri can be made redundant by SUBri if the operands are the same.
2618 /// CMPrr(r0, r1) can be made redundant by ADDr[ri](r0, r1, X).
2619 /// This function can be extended later on.
isRedundantFlagInstr(const MachineInstr * CmpI,unsigned SrcReg,unsigned SrcReg2,int ImmValue,const MachineInstr * OI)2620 inline static bool isRedundantFlagInstr(const MachineInstr *CmpI,
2621 unsigned SrcReg, unsigned SrcReg2,
2622 int ImmValue, const MachineInstr *OI) {
2623 if ((CmpI->getOpcode() == ARM::CMPrr ||
2624 CmpI->getOpcode() == ARM::t2CMPrr) &&
2625 (OI->getOpcode() == ARM::SUBrr ||
2626 OI->getOpcode() == ARM::t2SUBrr) &&
2627 ((OI->getOperand(1).getReg() == SrcReg &&
2628 OI->getOperand(2).getReg() == SrcReg2) ||
2629 (OI->getOperand(1).getReg() == SrcReg2 &&
2630 OI->getOperand(2).getReg() == SrcReg)))
2631 return true;
2632
2633 if ((CmpI->getOpcode() == ARM::CMPri ||
2634 CmpI->getOpcode() == ARM::t2CMPri) &&
2635 (OI->getOpcode() == ARM::SUBri ||
2636 OI->getOpcode() == ARM::t2SUBri) &&
2637 OI->getOperand(1).getReg() == SrcReg &&
2638 OI->getOperand(2).getImm() == ImmValue)
2639 return true;
2640
2641 if ((CmpI->getOpcode() == ARM::CMPrr || CmpI->getOpcode() == ARM::t2CMPrr) &&
2642 (OI->getOpcode() == ARM::ADDrr || OI->getOpcode() == ARM::t2ADDrr ||
2643 OI->getOpcode() == ARM::ADDri || OI->getOpcode() == ARM::t2ADDri) &&
2644 OI->getOperand(0).isReg() && OI->getOperand(1).isReg() &&
2645 OI->getOperand(0).getReg() == SrcReg &&
2646 OI->getOperand(1).getReg() == SrcReg2)
2647 return true;
2648 return false;
2649 }
2650
isOptimizeCompareCandidate(MachineInstr * MI,bool & IsThumb1)2651 static bool isOptimizeCompareCandidate(MachineInstr *MI, bool &IsThumb1) {
2652 switch (MI->getOpcode()) {
2653 default: return false;
2654 case ARM::tLSLri:
2655 case ARM::tLSRri:
2656 case ARM::tLSLrr:
2657 case ARM::tLSRrr:
2658 case ARM::tSUBrr:
2659 case ARM::tADDrr:
2660 case ARM::tADDi3:
2661 case ARM::tADDi8:
2662 case ARM::tSUBi3:
2663 case ARM::tSUBi8:
2664 case ARM::tMUL:
2665 IsThumb1 = true;
2666 LLVM_FALLTHROUGH;
2667 case ARM::RSBrr:
2668 case ARM::RSBri:
2669 case ARM::RSCrr:
2670 case ARM::RSCri:
2671 case ARM::ADDrr:
2672 case ARM::ADDri:
2673 case ARM::ADCrr:
2674 case ARM::ADCri:
2675 case ARM::SUBrr:
2676 case ARM::SUBri:
2677 case ARM::SBCrr:
2678 case ARM::SBCri:
2679 case ARM::t2RSBri:
2680 case ARM::t2ADDrr:
2681 case ARM::t2ADDri:
2682 case ARM::t2ADCrr:
2683 case ARM::t2ADCri:
2684 case ARM::t2SUBrr:
2685 case ARM::t2SUBri:
2686 case ARM::t2SBCrr:
2687 case ARM::t2SBCri:
2688 case ARM::ANDrr:
2689 case ARM::ANDri:
2690 case ARM::t2ANDrr:
2691 case ARM::t2ANDri:
2692 case ARM::ORRrr:
2693 case ARM::ORRri:
2694 case ARM::t2ORRrr:
2695 case ARM::t2ORRri:
2696 case ARM::EORrr:
2697 case ARM::EORri:
2698 case ARM::t2EORrr:
2699 case ARM::t2EORri:
2700 case ARM::t2LSRri:
2701 case ARM::t2LSRrr:
2702 case ARM::t2LSLri:
2703 case ARM::t2LSLrr:
2704 return true;
2705 }
2706 }
2707
2708 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
2709 /// comparison into one that sets the zero bit in the flags register;
2710 /// Remove a redundant Compare instruction if an earlier instruction can set the
2711 /// flags in the same way as Compare.
2712 /// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
2713 /// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
2714 /// condition code of instructions which use the flags.
optimizeCompareInstr(MachineInstr & CmpInstr,unsigned SrcReg,unsigned SrcReg2,int CmpMask,int CmpValue,const MachineRegisterInfo * MRI) const2715 bool ARMBaseInstrInfo::optimizeCompareInstr(
2716 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask,
2717 int CmpValue, const MachineRegisterInfo *MRI) const {
2718 // Get the unique definition of SrcReg.
2719 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2720 if (!MI) return false;
2721
2722 // Masked compares sometimes use the same register as the corresponding 'and'.
2723 if (CmpMask != ~0) {
2724 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(*MI)) {
2725 MI = nullptr;
2726 for (MachineRegisterInfo::use_instr_iterator
2727 UI = MRI->use_instr_begin(SrcReg), UE = MRI->use_instr_end();
2728 UI != UE; ++UI) {
2729 if (UI->getParent() != CmpInstr.getParent())
2730 continue;
2731 MachineInstr *PotentialAND = &*UI;
2732 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) ||
2733 isPredicated(*PotentialAND))
2734 continue;
2735 MI = PotentialAND;
2736 break;
2737 }
2738 if (!MI) return false;
2739 }
2740 }
2741
2742 // Get ready to iterate backward from CmpInstr.
2743 MachineBasicBlock::iterator I = CmpInstr, E = MI,
2744 B = CmpInstr.getParent()->begin();
2745
2746 // Early exit if CmpInstr is at the beginning of the BB.
2747 if (I == B) return false;
2748
2749 // There are two possible candidates which can be changed to set CPSR:
2750 // One is MI, the other is a SUB or ADD instruction.
2751 // For CMPrr(r1,r2), we are looking for SUB(r1,r2), SUB(r2,r1), or
2752 // ADDr[ri](r1, r2, X).
2753 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
2754 MachineInstr *SubAdd = nullptr;
2755 if (SrcReg2 != 0)
2756 // MI is not a candidate for CMPrr.
2757 MI = nullptr;
2758 else if (MI->getParent() != CmpInstr.getParent() || CmpValue != 0) {
2759 // Conservatively refuse to convert an instruction which isn't in the same
2760 // BB as the comparison.
2761 // For CMPri w/ CmpValue != 0, a SubAdd may still be a candidate.
2762 // Thus we cannot return here.
2763 if (CmpInstr.getOpcode() == ARM::CMPri ||
2764 CmpInstr.getOpcode() == ARM::t2CMPri)
2765 MI = nullptr;
2766 else
2767 return false;
2768 }
2769
2770 bool IsThumb1 = false;
2771 if (MI && !isOptimizeCompareCandidate(MI, IsThumb1))
2772 return false;
2773
2774 // We also want to do this peephole for cases like this: if (a*b == 0),
2775 // and optimise away the CMP instruction from the generated code sequence:
2776 // MULS, MOVS, MOVS, CMP. Here the MOVS instructions load the boolean values
2777 // resulting from the select instruction, but these MOVS instructions for
2778 // Thumb1 (V6M) are flag setting and are thus preventing this optimisation.
2779 // However, if we only have MOVS instructions in between the CMP and the
2780 // other instruction (the MULS in this example), then the CPSR is dead so we
2781 // can safely reorder the sequence into: MOVS, MOVS, MULS, CMP. We do this
2782 // reordering and then continue the analysis hoping we can eliminate the
2783 // CMP. This peephole works on the vregs, so is still in SSA form. As a
2784 // consequence, the movs won't redefine/kill the MUL operands which would
2785 // make this reordering illegal.
2786 if (MI && IsThumb1) {
2787 --I;
2788 bool CanReorder = true;
2789 const bool HasStmts = I != E;
2790 for (; I != E; --I) {
2791 if (I->getOpcode() != ARM::tMOVi8) {
2792 CanReorder = false;
2793 break;
2794 }
2795 }
2796 if (HasStmts && CanReorder) {
2797 MI = MI->removeFromParent();
2798 E = CmpInstr;
2799 CmpInstr.getParent()->insert(E, MI);
2800 }
2801 I = CmpInstr;
2802 E = MI;
2803 }
2804
2805 // Check that CPSR isn't set between the comparison instruction and the one we
2806 // want to change. At the same time, search for SubAdd.
2807 const TargetRegisterInfo *TRI = &getRegisterInfo();
2808 do {
2809 const MachineInstr &Instr = *--I;
2810
2811 // Check whether CmpInstr can be made redundant by the current instruction.
2812 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &Instr)) {
2813 SubAdd = &*I;
2814 break;
2815 }
2816
2817 // Allow E (which was initially MI) to be SubAdd but do not search before E.
2818 if (I == E)
2819 break;
2820
2821 if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
2822 Instr.readsRegister(ARM::CPSR, TRI))
2823 // This instruction modifies or uses CPSR after the one we want to
2824 // change. We can't do this transformation.
2825 return false;
2826
2827 } while (I != B);
2828
2829 // Return false if no candidates exist.
2830 if (!MI && !SubAdd)
2831 return false;
2832
2833 // The single candidate is called MI.
2834 if (!MI) MI = SubAdd;
2835
2836 // We can't use a predicated instruction - it doesn't always write the flags.
2837 if (isPredicated(*MI))
2838 return false;
2839
2840 // Scan forward for the use of CPSR
2841 // When checking against MI: if it's a conditional code that requires
2842 // checking of the V bit or C bit, then this is not safe to do.
2843 // It is safe to remove CmpInstr if CPSR is redefined or killed.
2844 // If we are done with the basic block, we need to check whether CPSR is
2845 // live-out.
2846 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4>
2847 OperandsToUpdate;
2848 bool isSafe = false;
2849 I = CmpInstr;
2850 E = CmpInstr.getParent()->end();
2851 while (!isSafe && ++I != E) {
2852 const MachineInstr &Instr = *I;
2853 for (unsigned IO = 0, EO = Instr.getNumOperands();
2854 !isSafe && IO != EO; ++IO) {
2855 const MachineOperand &MO = Instr.getOperand(IO);
2856 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
2857 isSafe = true;
2858 break;
2859 }
2860 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
2861 continue;
2862 if (MO.isDef()) {
2863 isSafe = true;
2864 break;
2865 }
2866 // Condition code is after the operand before CPSR except for VSELs.
2867 ARMCC::CondCodes CC;
2868 bool IsInstrVSel = true;
2869 switch (Instr.getOpcode()) {
2870 default:
2871 IsInstrVSel = false;
2872 CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm();
2873 break;
2874 case ARM::VSELEQD:
2875 case ARM::VSELEQS:
2876 CC = ARMCC::EQ;
2877 break;
2878 case ARM::VSELGTD:
2879 case ARM::VSELGTS:
2880 CC = ARMCC::GT;
2881 break;
2882 case ARM::VSELGED:
2883 case ARM::VSELGES:
2884 CC = ARMCC::GE;
2885 break;
2886 case ARM::VSELVSS:
2887 case ARM::VSELVSD:
2888 CC = ARMCC::VS;
2889 break;
2890 }
2891
2892 if (SubAdd) {
2893 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
2894 // on CMP needs to be updated to be based on SUB.
2895 // If we have ADD(r1, r2, X) and CMP(r1, r2), the condition code also
2896 // needs to be modified.
2897 // Push the condition code operands to OperandsToUpdate.
2898 // If it is safe to remove CmpInstr, the condition code of these
2899 // operands will be modified.
2900 unsigned Opc = SubAdd->getOpcode();
2901 bool IsSub = Opc == ARM::SUBrr || Opc == ARM::t2SUBrr ||
2902 Opc == ARM::SUBri || Opc == ARM::t2SUBri;
2903 if (!IsSub || (SrcReg2 != 0 && SubAdd->getOperand(1).getReg() == SrcReg2 &&
2904 SubAdd->getOperand(2).getReg() == SrcReg)) {
2905 // VSel doesn't support condition code update.
2906 if (IsInstrVSel)
2907 return false;
2908 // Ensure we can swap the condition.
2909 ARMCC::CondCodes NewCC = (IsSub ? getSwappedCondition(CC) : getCmpToAddCondition(CC));
2910 if (NewCC == ARMCC::AL)
2911 return false;
2912 OperandsToUpdate.push_back(
2913 std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
2914 }
2915 } else {
2916 // No SubAdd, so this is x = <op> y, z; cmp x, 0.
2917 switch (CC) {
2918 case ARMCC::EQ: // Z
2919 case ARMCC::NE: // Z
2920 case ARMCC::MI: // N
2921 case ARMCC::PL: // N
2922 case ARMCC::AL: // none
2923 // CPSR can be used multiple times, we should continue.
2924 break;
2925 case ARMCC::HS: // C
2926 case ARMCC::LO: // C
2927 case ARMCC::VS: // V
2928 case ARMCC::VC: // V
2929 case ARMCC::HI: // C Z
2930 case ARMCC::LS: // C Z
2931 case ARMCC::GE: // N V
2932 case ARMCC::LT: // N V
2933 case ARMCC::GT: // Z N V
2934 case ARMCC::LE: // Z N V
2935 // The instruction uses the V bit or C bit which is not safe.
2936 return false;
2937 }
2938 }
2939 }
2940 }
2941
2942 // If CPSR is not killed nor re-defined, we should check whether it is
2943 // live-out. If it is live-out, do not optimize.
2944 if (!isSafe) {
2945 MachineBasicBlock *MBB = CmpInstr.getParent();
2946 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
2947 SE = MBB->succ_end(); SI != SE; ++SI)
2948 if ((*SI)->isLiveIn(ARM::CPSR))
2949 return false;
2950 }
2951
2952 // Toggle the optional operand to CPSR (if it exists - in Thumb1 we always
2953 // set CPSR so this is represented as an explicit output)
2954 if (!IsThumb1) {
2955 MI->getOperand(5).setReg(ARM::CPSR);
2956 MI->getOperand(5).setIsDef(true);
2957 }
2958 assert(!isPredicated(*MI) && "Can't use flags from predicated instruction");
2959 CmpInstr.eraseFromParent();
2960
2961 // Modify the condition code of operands in OperandsToUpdate.
2962 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2963 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2964 for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
2965 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
2966
2967 MI->clearRegisterDeads(ARM::CPSR);
2968
2969 return true;
2970 }
2971
shouldSink(const MachineInstr & MI) const2972 bool ARMBaseInstrInfo::shouldSink(const MachineInstr &MI) const {
2973 // Do not sink MI if it might be used to optimize a redundant compare.
2974 // We heuristically only look at the instruction immediately following MI to
2975 // avoid potentially searching the entire basic block.
2976 if (isPredicated(MI))
2977 return true;
2978 MachineBasicBlock::const_iterator Next = &MI;
2979 ++Next;
2980 unsigned SrcReg, SrcReg2;
2981 int CmpMask, CmpValue;
2982 if (Next != MI.getParent()->end() &&
2983 analyzeCompare(*Next, SrcReg, SrcReg2, CmpMask, CmpValue) &&
2984 isRedundantFlagInstr(&*Next, SrcReg, SrcReg2, CmpValue, &MI))
2985 return false;
2986 return true;
2987 }
2988
FoldImmediate(MachineInstr & UseMI,MachineInstr & DefMI,unsigned Reg,MachineRegisterInfo * MRI) const2989 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
2990 unsigned Reg,
2991 MachineRegisterInfo *MRI) const {
2992 // Fold large immediates into add, sub, or, xor.
2993 unsigned DefOpc = DefMI.getOpcode();
2994 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
2995 return false;
2996 if (!DefMI.getOperand(1).isImm())
2997 // Could be t2MOVi32imm @xx
2998 return false;
2999
3000 if (!MRI->hasOneNonDBGUse(Reg))
3001 return false;
3002
3003 const MCInstrDesc &DefMCID = DefMI.getDesc();
3004 if (DefMCID.hasOptionalDef()) {
3005 unsigned NumOps = DefMCID.getNumOperands();
3006 const MachineOperand &MO = DefMI.getOperand(NumOps - 1);
3007 if (MO.getReg() == ARM::CPSR && !MO.isDead())
3008 // If DefMI defines CPSR and it is not dead, it's obviously not safe
3009 // to delete DefMI.
3010 return false;
3011 }
3012
3013 const MCInstrDesc &UseMCID = UseMI.getDesc();
3014 if (UseMCID.hasOptionalDef()) {
3015 unsigned NumOps = UseMCID.getNumOperands();
3016 if (UseMI.getOperand(NumOps - 1).getReg() == ARM::CPSR)
3017 // If the instruction sets the flag, do not attempt this optimization
3018 // since it may change the semantics of the code.
3019 return false;
3020 }
3021
3022 unsigned UseOpc = UseMI.getOpcode();
3023 unsigned NewUseOpc = 0;
3024 uint32_t ImmVal = (uint32_t)DefMI.getOperand(1).getImm();
3025 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
3026 bool Commute = false;
3027 switch (UseOpc) {
3028 default: return false;
3029 case ARM::SUBrr:
3030 case ARM::ADDrr:
3031 case ARM::ORRrr:
3032 case ARM::EORrr:
3033 case ARM::t2SUBrr:
3034 case ARM::t2ADDrr:
3035 case ARM::t2ORRrr:
3036 case ARM::t2EORrr: {
3037 Commute = UseMI.getOperand(2).getReg() != Reg;
3038 switch (UseOpc) {
3039 default: break;
3040 case ARM::ADDrr:
3041 case ARM::SUBrr:
3042 if (UseOpc == ARM::SUBrr && Commute)
3043 return false;
3044
3045 // ADD/SUB are special because they're essentially the same operation, so
3046 // we can handle a larger range of immediates.
3047 if (ARM_AM::isSOImmTwoPartVal(ImmVal))
3048 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::ADDri : ARM::SUBri;
3049 else if (ARM_AM::isSOImmTwoPartVal(-ImmVal)) {
3050 ImmVal = -ImmVal;
3051 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::SUBri : ARM::ADDri;
3052 } else
3053 return false;
3054 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
3055 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
3056 break;
3057 case ARM::ORRrr:
3058 case ARM::EORrr:
3059 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
3060 return false;
3061 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
3062 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
3063 switch (UseOpc) {
3064 default: break;
3065 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
3066 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
3067 }
3068 break;
3069 case ARM::t2ADDrr:
3070 case ARM::t2SUBrr:
3071 if (UseOpc == ARM::t2SUBrr && Commute)
3072 return false;
3073
3074 // ADD/SUB are special because they're essentially the same operation, so
3075 // we can handle a larger range of immediates.
3076 if (ARM_AM::isT2SOImmTwoPartVal(ImmVal))
3077 NewUseOpc = UseOpc == ARM::t2ADDrr ? ARM::t2ADDri : ARM::t2SUBri;
3078 else if (ARM_AM::isT2SOImmTwoPartVal(-ImmVal)) {
3079 ImmVal = -ImmVal;
3080 NewUseOpc = UseOpc == ARM::t2ADDrr ? ARM::t2SUBri : ARM::t2ADDri;
3081 } else
3082 return false;
3083 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
3084 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
3085 break;
3086 case ARM::t2ORRrr:
3087 case ARM::t2EORrr:
3088 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
3089 return false;
3090 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
3091 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
3092 switch (UseOpc) {
3093 default: break;
3094 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
3095 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
3096 }
3097 break;
3098 }
3099 }
3100 }
3101
3102 unsigned OpIdx = Commute ? 2 : 1;
3103 unsigned Reg1 = UseMI.getOperand(OpIdx).getReg();
3104 bool isKill = UseMI.getOperand(OpIdx).isKill();
3105 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
3106 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(), get(NewUseOpc),
3107 NewReg)
3108 .addReg(Reg1, getKillRegState(isKill))
3109 .addImm(SOImmValV1)
3110 .add(predOps(ARMCC::AL))
3111 .add(condCodeOp());
3112 UseMI.setDesc(get(NewUseOpc));
3113 UseMI.getOperand(1).setReg(NewReg);
3114 UseMI.getOperand(1).setIsKill();
3115 UseMI.getOperand(2).ChangeToImmediate(SOImmValV2);
3116 DefMI.eraseFromParent();
3117 return true;
3118 }
3119
getNumMicroOpsSwiftLdSt(const InstrItineraryData * ItinData,const MachineInstr & MI)3120 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
3121 const MachineInstr &MI) {
3122 switch (MI.getOpcode()) {
3123 default: {
3124 const MCInstrDesc &Desc = MI.getDesc();
3125 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
3126 assert(UOps >= 0 && "bad # UOps");
3127 return UOps;
3128 }
3129
3130 case ARM::LDRrs:
3131 case ARM::LDRBrs:
3132 case ARM::STRrs:
3133 case ARM::STRBrs: {
3134 unsigned ShOpVal = MI.getOperand(3).getImm();
3135 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3136 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3137 if (!isSub &&
3138 (ShImm == 0 ||
3139 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3140 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3141 return 1;
3142 return 2;
3143 }
3144
3145 case ARM::LDRH:
3146 case ARM::STRH: {
3147 if (!MI.getOperand(2).getReg())
3148 return 1;
3149
3150 unsigned ShOpVal = MI.getOperand(3).getImm();
3151 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3152 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3153 if (!isSub &&
3154 (ShImm == 0 ||
3155 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3156 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3157 return 1;
3158 return 2;
3159 }
3160
3161 case ARM::LDRSB:
3162 case ARM::LDRSH:
3163 return (ARM_AM::getAM3Op(MI.getOperand(3).getImm()) == ARM_AM::sub) ? 3 : 2;
3164
3165 case ARM::LDRSB_POST:
3166 case ARM::LDRSH_POST: {
3167 unsigned Rt = MI.getOperand(0).getReg();
3168 unsigned Rm = MI.getOperand(3).getReg();
3169 return (Rt == Rm) ? 4 : 3;
3170 }
3171
3172 case ARM::LDR_PRE_REG:
3173 case ARM::LDRB_PRE_REG: {
3174 unsigned Rt = MI.getOperand(0).getReg();
3175 unsigned Rm = MI.getOperand(3).getReg();
3176 if (Rt == Rm)
3177 return 3;
3178 unsigned ShOpVal = MI.getOperand(4).getImm();
3179 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3180 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3181 if (!isSub &&
3182 (ShImm == 0 ||
3183 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3184 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3185 return 2;
3186 return 3;
3187 }
3188
3189 case ARM::STR_PRE_REG:
3190 case ARM::STRB_PRE_REG: {
3191 unsigned ShOpVal = MI.getOperand(4).getImm();
3192 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3193 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3194 if (!isSub &&
3195 (ShImm == 0 ||
3196 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3197 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3198 return 2;
3199 return 3;
3200 }
3201
3202 case ARM::LDRH_PRE:
3203 case ARM::STRH_PRE: {
3204 unsigned Rt = MI.getOperand(0).getReg();
3205 unsigned Rm = MI.getOperand(3).getReg();
3206 if (!Rm)
3207 return 2;
3208 if (Rt == Rm)
3209 return 3;
3210 return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 3 : 2;
3211 }
3212
3213 case ARM::LDR_POST_REG:
3214 case ARM::LDRB_POST_REG:
3215 case ARM::LDRH_POST: {
3216 unsigned Rt = MI.getOperand(0).getReg();
3217 unsigned Rm = MI.getOperand(3).getReg();
3218 return (Rt == Rm) ? 3 : 2;
3219 }
3220
3221 case ARM::LDR_PRE_IMM:
3222 case ARM::LDRB_PRE_IMM:
3223 case ARM::LDR_POST_IMM:
3224 case ARM::LDRB_POST_IMM:
3225 case ARM::STRB_POST_IMM:
3226 case ARM::STRB_POST_REG:
3227 case ARM::STRB_PRE_IMM:
3228 case ARM::STRH_POST:
3229 case ARM::STR_POST_IMM:
3230 case ARM::STR_POST_REG:
3231 case ARM::STR_PRE_IMM:
3232 return 2;
3233
3234 case ARM::LDRSB_PRE:
3235 case ARM::LDRSH_PRE: {
3236 unsigned Rm = MI.getOperand(3).getReg();
3237 if (Rm == 0)
3238 return 3;
3239 unsigned Rt = MI.getOperand(0).getReg();
3240 if (Rt == Rm)
3241 return 4;
3242 unsigned ShOpVal = MI.getOperand(4).getImm();
3243 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3244 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3245 if (!isSub &&
3246 (ShImm == 0 ||
3247 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3248 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3249 return 3;
3250 return 4;
3251 }
3252
3253 case ARM::LDRD: {
3254 unsigned Rt = MI.getOperand(0).getReg();
3255 unsigned Rn = MI.getOperand(2).getReg();
3256 unsigned Rm = MI.getOperand(3).getReg();
3257 if (Rm)
3258 return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 4
3259 : 3;
3260 return (Rt == Rn) ? 3 : 2;
3261 }
3262
3263 case ARM::STRD: {
3264 unsigned Rm = MI.getOperand(3).getReg();
3265 if (Rm)
3266 return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 4
3267 : 3;
3268 return 2;
3269 }
3270
3271 case ARM::LDRD_POST:
3272 case ARM::t2LDRD_POST:
3273 return 3;
3274
3275 case ARM::STRD_POST:
3276 case ARM::t2STRD_POST:
3277 return 4;
3278
3279 case ARM::LDRD_PRE: {
3280 unsigned Rt = MI.getOperand(0).getReg();
3281 unsigned Rn = MI.getOperand(3).getReg();
3282 unsigned Rm = MI.getOperand(4).getReg();
3283 if (Rm)
3284 return (ARM_AM::getAM3Op(MI.getOperand(5).getImm()) == ARM_AM::sub) ? 5
3285 : 4;
3286 return (Rt == Rn) ? 4 : 3;
3287 }
3288
3289 case ARM::t2LDRD_PRE: {
3290 unsigned Rt = MI.getOperand(0).getReg();
3291 unsigned Rn = MI.getOperand(3).getReg();
3292 return (Rt == Rn) ? 4 : 3;
3293 }
3294
3295 case ARM::STRD_PRE: {
3296 unsigned Rm = MI.getOperand(4).getReg();
3297 if (Rm)
3298 return (ARM_AM::getAM3Op(MI.getOperand(5).getImm()) == ARM_AM::sub) ? 5
3299 : 4;
3300 return 3;
3301 }
3302
3303 case ARM::t2STRD_PRE:
3304 return 3;
3305
3306 case ARM::t2LDR_POST:
3307 case ARM::t2LDRB_POST:
3308 case ARM::t2LDRB_PRE:
3309 case ARM::t2LDRSBi12:
3310 case ARM::t2LDRSBi8:
3311 case ARM::t2LDRSBpci:
3312 case ARM::t2LDRSBs:
3313 case ARM::t2LDRH_POST:
3314 case ARM::t2LDRH_PRE:
3315 case ARM::t2LDRSBT:
3316 case ARM::t2LDRSB_POST:
3317 case ARM::t2LDRSB_PRE:
3318 case ARM::t2LDRSH_POST:
3319 case ARM::t2LDRSH_PRE:
3320 case ARM::t2LDRSHi12:
3321 case ARM::t2LDRSHi8:
3322 case ARM::t2LDRSHpci:
3323 case ARM::t2LDRSHs:
3324 return 2;
3325
3326 case ARM::t2LDRDi8: {
3327 unsigned Rt = MI.getOperand(0).getReg();
3328 unsigned Rn = MI.getOperand(2).getReg();
3329 return (Rt == Rn) ? 3 : 2;
3330 }
3331
3332 case ARM::t2STRB_POST:
3333 case ARM::t2STRB_PRE:
3334 case ARM::t2STRBs:
3335 case ARM::t2STRDi8:
3336 case ARM::t2STRH_POST:
3337 case ARM::t2STRH_PRE:
3338 case ARM::t2STRHs:
3339 case ARM::t2STR_POST:
3340 case ARM::t2STR_PRE:
3341 case ARM::t2STRs:
3342 return 2;
3343 }
3344 }
3345
3346 // Return the number of 32-bit words loaded by LDM or stored by STM. If this
3347 // can't be easily determined return 0 (missing MachineMemOperand).
3348 //
3349 // FIXME: The current MachineInstr design does not support relying on machine
3350 // mem operands to determine the width of a memory access. Instead, we expect
3351 // the target to provide this information based on the instruction opcode and
3352 // operands. However, using MachineMemOperand is the best solution now for
3353 // two reasons:
3354 //
3355 // 1) getNumMicroOps tries to infer LDM memory width from the total number of MI
3356 // operands. This is much more dangerous than using the MachineMemOperand
3357 // sizes because CodeGen passes can insert/remove optional machine operands. In
3358 // fact, it's totally incorrect for preRA passes and appears to be wrong for
3359 // postRA passes as well.
3360 //
3361 // 2) getNumLDMAddresses is only used by the scheduling machine model and any
3362 // machine model that calls this should handle the unknown (zero size) case.
3363 //
3364 // Long term, we should require a target hook that verifies MachineMemOperand
3365 // sizes during MC lowering. That target hook should be local to MC lowering
3366 // because we can't ensure that it is aware of other MI forms. Doing this will
3367 // ensure that MachineMemOperands are correctly propagated through all passes.
getNumLDMAddresses(const MachineInstr & MI) const3368 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr &MI) const {
3369 unsigned Size = 0;
3370 for (MachineInstr::mmo_iterator I = MI.memoperands_begin(),
3371 E = MI.memoperands_end();
3372 I != E; ++I) {
3373 Size += (*I)->getSize();
3374 }
3375 return Size / 4;
3376 }
3377
getNumMicroOpsSingleIssuePlusExtras(unsigned Opc,unsigned NumRegs)3378 static unsigned getNumMicroOpsSingleIssuePlusExtras(unsigned Opc,
3379 unsigned NumRegs) {
3380 unsigned UOps = 1 + NumRegs; // 1 for address computation.
3381 switch (Opc) {
3382 default:
3383 break;
3384 case ARM::VLDMDIA_UPD:
3385 case ARM::VLDMDDB_UPD:
3386 case ARM::VLDMSIA_UPD:
3387 case ARM::VLDMSDB_UPD:
3388 case ARM::VSTMDIA_UPD:
3389 case ARM::VSTMDDB_UPD:
3390 case ARM::VSTMSIA_UPD:
3391 case ARM::VSTMSDB_UPD:
3392 case ARM::LDMIA_UPD:
3393 case ARM::LDMDA_UPD:
3394 case ARM::LDMDB_UPD:
3395 case ARM::LDMIB_UPD:
3396 case ARM::STMIA_UPD:
3397 case ARM::STMDA_UPD:
3398 case ARM::STMDB_UPD:
3399 case ARM::STMIB_UPD:
3400 case ARM::tLDMIA_UPD:
3401 case ARM::tSTMIA_UPD:
3402 case ARM::t2LDMIA_UPD:
3403 case ARM::t2LDMDB_UPD:
3404 case ARM::t2STMIA_UPD:
3405 case ARM::t2STMDB_UPD:
3406 ++UOps; // One for base register writeback.
3407 break;
3408 case ARM::LDMIA_RET:
3409 case ARM::tPOP_RET:
3410 case ARM::t2LDMIA_RET:
3411 UOps += 2; // One for base reg wb, one for write to pc.
3412 break;
3413 }
3414 return UOps;
3415 }
3416
getNumMicroOps(const InstrItineraryData * ItinData,const MachineInstr & MI) const3417 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
3418 const MachineInstr &MI) const {
3419 if (!ItinData || ItinData->isEmpty())
3420 return 1;
3421
3422 const MCInstrDesc &Desc = MI.getDesc();
3423 unsigned Class = Desc.getSchedClass();
3424 int ItinUOps = ItinData->getNumMicroOps(Class);
3425 if (ItinUOps >= 0) {
3426 if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore()))
3427 return getNumMicroOpsSwiftLdSt(ItinData, MI);
3428
3429 return ItinUOps;
3430 }
3431
3432 unsigned Opc = MI.getOpcode();
3433 switch (Opc) {
3434 default:
3435 llvm_unreachable("Unexpected multi-uops instruction!");
3436 case ARM::VLDMQIA:
3437 case ARM::VSTMQIA:
3438 return 2;
3439
3440 // The number of uOps for load / store multiple are determined by the number
3441 // registers.
3442 //
3443 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
3444 // same cycle. The scheduling for the first load / store must be done
3445 // separately by assuming the address is not 64-bit aligned.
3446 //
3447 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
3448 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
3449 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
3450 case ARM::VLDMDIA:
3451 case ARM::VLDMDIA_UPD:
3452 case ARM::VLDMDDB_UPD:
3453 case ARM::VLDMSIA:
3454 case ARM::VLDMSIA_UPD:
3455 case ARM::VLDMSDB_UPD:
3456 case ARM::VSTMDIA:
3457 case ARM::VSTMDIA_UPD:
3458 case ARM::VSTMDDB_UPD:
3459 case ARM::VSTMSIA:
3460 case ARM::VSTMSIA_UPD:
3461 case ARM::VSTMSDB_UPD: {
3462 unsigned NumRegs = MI.getNumOperands() - Desc.getNumOperands();
3463 return (NumRegs / 2) + (NumRegs % 2) + 1;
3464 }
3465
3466 case ARM::LDMIA_RET:
3467 case ARM::LDMIA:
3468 case ARM::LDMDA:
3469 case ARM::LDMDB:
3470 case ARM::LDMIB:
3471 case ARM::LDMIA_UPD:
3472 case ARM::LDMDA_UPD:
3473 case ARM::LDMDB_UPD:
3474 case ARM::LDMIB_UPD:
3475 case ARM::STMIA:
3476 case ARM::STMDA:
3477 case ARM::STMDB:
3478 case ARM::STMIB:
3479 case ARM::STMIA_UPD:
3480 case ARM::STMDA_UPD:
3481 case ARM::STMDB_UPD:
3482 case ARM::STMIB_UPD:
3483 case ARM::tLDMIA:
3484 case ARM::tLDMIA_UPD:
3485 case ARM::tSTMIA_UPD:
3486 case ARM::tPOP_RET:
3487 case ARM::tPOP:
3488 case ARM::tPUSH:
3489 case ARM::t2LDMIA_RET:
3490 case ARM::t2LDMIA:
3491 case ARM::t2LDMDB:
3492 case ARM::t2LDMIA_UPD:
3493 case ARM::t2LDMDB_UPD:
3494 case ARM::t2STMIA:
3495 case ARM::t2STMDB:
3496 case ARM::t2STMIA_UPD:
3497 case ARM::t2STMDB_UPD: {
3498 unsigned NumRegs = MI.getNumOperands() - Desc.getNumOperands() + 1;
3499 switch (Subtarget.getLdStMultipleTiming()) {
3500 case ARMSubtarget::SingleIssuePlusExtras:
3501 return getNumMicroOpsSingleIssuePlusExtras(Opc, NumRegs);
3502 case ARMSubtarget::SingleIssue:
3503 // Assume the worst.
3504 return NumRegs;
3505 case ARMSubtarget::DoubleIssue: {
3506 if (NumRegs < 4)
3507 return 2;
3508 // 4 registers would be issued: 2, 2.
3509 // 5 registers would be issued: 2, 2, 1.
3510 unsigned UOps = (NumRegs / 2);
3511 if (NumRegs % 2)
3512 ++UOps;
3513 return UOps;
3514 }
3515 case ARMSubtarget::DoubleIssueCheckUnalignedAccess: {
3516 unsigned UOps = (NumRegs / 2);
3517 // If there are odd number of registers or if it's not 64-bit aligned,
3518 // then it takes an extra AGU (Address Generation Unit) cycle.
3519 if ((NumRegs % 2) || !MI.hasOneMemOperand() ||
3520 (*MI.memoperands_begin())->getAlignment() < 8)
3521 ++UOps;
3522 return UOps;
3523 }
3524 }
3525 }
3526 }
3527 llvm_unreachable("Didn't find the number of microops");
3528 }
3529
3530 int
getVLDMDefCycle(const InstrItineraryData * ItinData,const MCInstrDesc & DefMCID,unsigned DefClass,unsigned DefIdx,unsigned DefAlign) const3531 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
3532 const MCInstrDesc &DefMCID,
3533 unsigned DefClass,
3534 unsigned DefIdx, unsigned DefAlign) const {
3535 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3536 if (RegNo <= 0)
3537 // Def is the address writeback.
3538 return ItinData->getOperandCycle(DefClass, DefIdx);
3539
3540 int DefCycle;
3541 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3542 // (regno / 2) + (regno % 2) + 1
3543 DefCycle = RegNo / 2 + 1;
3544 if (RegNo % 2)
3545 ++DefCycle;
3546 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3547 DefCycle = RegNo;
3548 bool isSLoad = false;
3549
3550 switch (DefMCID.getOpcode()) {
3551 default: break;
3552 case ARM::VLDMSIA:
3553 case ARM::VLDMSIA_UPD:
3554 case ARM::VLDMSDB_UPD:
3555 isSLoad = true;
3556 break;
3557 }
3558
3559 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3560 // then it takes an extra cycle.
3561 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
3562 ++DefCycle;
3563 } else {
3564 // Assume the worst.
3565 DefCycle = RegNo + 2;
3566 }
3567
3568 return DefCycle;
3569 }
3570
isLDMBaseRegInList(const MachineInstr & MI) const3571 bool ARMBaseInstrInfo::isLDMBaseRegInList(const MachineInstr &MI) const {
3572 unsigned BaseReg = MI.getOperand(0).getReg();
3573 for (unsigned i = 1, sz = MI.getNumOperands(); i < sz; ++i) {
3574 const auto &Op = MI.getOperand(i);
3575 if (Op.isReg() && Op.getReg() == BaseReg)
3576 return true;
3577 }
3578 return false;
3579 }
3580 unsigned
getLDMVariableDefsSize(const MachineInstr & MI) const3581 ARMBaseInstrInfo::getLDMVariableDefsSize(const MachineInstr &MI) const {
3582 // ins GPR:$Rn, $p (2xOp), reglist:$regs, variable_ops
3583 // (outs GPR:$wb), (ins GPR:$Rn, $p (2xOp), reglist:$regs, variable_ops)
3584 return MI.getNumOperands() + 1 - MI.getDesc().getNumOperands();
3585 }
3586
3587 int
getLDMDefCycle(const InstrItineraryData * ItinData,const MCInstrDesc & DefMCID,unsigned DefClass,unsigned DefIdx,unsigned DefAlign) const3588 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3589 const MCInstrDesc &DefMCID,
3590 unsigned DefClass,
3591 unsigned DefIdx, unsigned DefAlign) const {
3592 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3593 if (RegNo <= 0)
3594 // Def is the address writeback.
3595 return ItinData->getOperandCycle(DefClass, DefIdx);
3596
3597 int DefCycle;
3598 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3599 // 4 registers would be issued: 1, 2, 1.
3600 // 5 registers would be issued: 1, 2, 2.
3601 DefCycle = RegNo / 2;
3602 if (DefCycle < 1)
3603 DefCycle = 1;
3604 // Result latency is issue cycle + 2: E2.
3605 DefCycle += 2;
3606 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3607 DefCycle = (RegNo / 2);
3608 // If there are odd number of registers or if it's not 64-bit aligned,
3609 // then it takes an extra AGU (Address Generation Unit) cycle.
3610 if ((RegNo % 2) || DefAlign < 8)
3611 ++DefCycle;
3612 // Result latency is AGU cycles + 2.
3613 DefCycle += 2;
3614 } else {
3615 // Assume the worst.
3616 DefCycle = RegNo + 2;
3617 }
3618
3619 return DefCycle;
3620 }
3621
3622 int
getVSTMUseCycle(const InstrItineraryData * ItinData,const MCInstrDesc & UseMCID,unsigned UseClass,unsigned UseIdx,unsigned UseAlign) const3623 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3624 const MCInstrDesc &UseMCID,
3625 unsigned UseClass,
3626 unsigned UseIdx, unsigned UseAlign) const {
3627 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3628 if (RegNo <= 0)
3629 return ItinData->getOperandCycle(UseClass, UseIdx);
3630
3631 int UseCycle;
3632 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3633 // (regno / 2) + (regno % 2) + 1
3634 UseCycle = RegNo / 2 + 1;
3635 if (RegNo % 2)
3636 ++UseCycle;
3637 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3638 UseCycle = RegNo;
3639 bool isSStore = false;
3640
3641 switch (UseMCID.getOpcode()) {
3642 default: break;
3643 case ARM::VSTMSIA:
3644 case ARM::VSTMSIA_UPD:
3645 case ARM::VSTMSDB_UPD:
3646 isSStore = true;
3647 break;
3648 }
3649
3650 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3651 // then it takes an extra cycle.
3652 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
3653 ++UseCycle;
3654 } else {
3655 // Assume the worst.
3656 UseCycle = RegNo + 2;
3657 }
3658
3659 return UseCycle;
3660 }
3661
3662 int
getSTMUseCycle(const InstrItineraryData * ItinData,const MCInstrDesc & UseMCID,unsigned UseClass,unsigned UseIdx,unsigned UseAlign) const3663 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
3664 const MCInstrDesc &UseMCID,
3665 unsigned UseClass,
3666 unsigned UseIdx, unsigned UseAlign) const {
3667 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3668 if (RegNo <= 0)
3669 return ItinData->getOperandCycle(UseClass, UseIdx);
3670
3671 int UseCycle;
3672 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3673 UseCycle = RegNo / 2;
3674 if (UseCycle < 2)
3675 UseCycle = 2;
3676 // Read in E3.
3677 UseCycle += 2;
3678 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3679 UseCycle = (RegNo / 2);
3680 // If there are odd number of registers or if it's not 64-bit aligned,
3681 // then it takes an extra AGU (Address Generation Unit) cycle.
3682 if ((RegNo % 2) || UseAlign < 8)
3683 ++UseCycle;
3684 } else {
3685 // Assume the worst.
3686 UseCycle = 1;
3687 }
3688 return UseCycle;
3689 }
3690
3691 int
getOperandLatency(const InstrItineraryData * ItinData,const MCInstrDesc & DefMCID,unsigned DefIdx,unsigned DefAlign,const MCInstrDesc & UseMCID,unsigned UseIdx,unsigned UseAlign) const3692 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3693 const MCInstrDesc &DefMCID,
3694 unsigned DefIdx, unsigned DefAlign,
3695 const MCInstrDesc &UseMCID,
3696 unsigned UseIdx, unsigned UseAlign) const {
3697 unsigned DefClass = DefMCID.getSchedClass();
3698 unsigned UseClass = UseMCID.getSchedClass();
3699
3700 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
3701 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
3702
3703 // This may be a def / use of a variable_ops instruction, the operand
3704 // latency might be determinable dynamically. Let the target try to
3705 // figure it out.
3706 int DefCycle = -1;
3707 bool LdmBypass = false;
3708 switch (DefMCID.getOpcode()) {
3709 default:
3710 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3711 break;
3712
3713 case ARM::VLDMDIA:
3714 case ARM::VLDMDIA_UPD:
3715 case ARM::VLDMDDB_UPD:
3716 case ARM::VLDMSIA:
3717 case ARM::VLDMSIA_UPD:
3718 case ARM::VLDMSDB_UPD:
3719 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3720 break;
3721
3722 case ARM::LDMIA_RET:
3723 case ARM::LDMIA:
3724 case ARM::LDMDA:
3725 case ARM::LDMDB:
3726 case ARM::LDMIB:
3727 case ARM::LDMIA_UPD:
3728 case ARM::LDMDA_UPD:
3729 case ARM::LDMDB_UPD:
3730 case ARM::LDMIB_UPD:
3731 case ARM::tLDMIA:
3732 case ARM::tLDMIA_UPD:
3733 case ARM::tPUSH:
3734 case ARM::t2LDMIA_RET:
3735 case ARM::t2LDMIA:
3736 case ARM::t2LDMDB:
3737 case ARM::t2LDMIA_UPD:
3738 case ARM::t2LDMDB_UPD:
3739 LdmBypass = true;
3740 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3741 break;
3742 }
3743
3744 if (DefCycle == -1)
3745 // We can't seem to determine the result latency of the def, assume it's 2.
3746 DefCycle = 2;
3747
3748 int UseCycle = -1;
3749 switch (UseMCID.getOpcode()) {
3750 default:
3751 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
3752 break;
3753
3754 case ARM::VSTMDIA:
3755 case ARM::VSTMDIA_UPD:
3756 case ARM::VSTMDDB_UPD:
3757 case ARM::VSTMSIA:
3758 case ARM::VSTMSIA_UPD:
3759 case ARM::VSTMSDB_UPD:
3760 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3761 break;
3762
3763 case ARM::STMIA:
3764 case ARM::STMDA:
3765 case ARM::STMDB:
3766 case ARM::STMIB:
3767 case ARM::STMIA_UPD:
3768 case ARM::STMDA_UPD:
3769 case ARM::STMDB_UPD:
3770 case ARM::STMIB_UPD:
3771 case ARM::tSTMIA_UPD:
3772 case ARM::tPOP_RET:
3773 case ARM::tPOP:
3774 case ARM::t2STMIA:
3775 case ARM::t2STMDB:
3776 case ARM::t2STMIA_UPD:
3777 case ARM::t2STMDB_UPD:
3778 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3779 break;
3780 }
3781
3782 if (UseCycle == -1)
3783 // Assume it's read in the first stage.
3784 UseCycle = 1;
3785
3786 UseCycle = DefCycle - UseCycle + 1;
3787 if (UseCycle > 0) {
3788 if (LdmBypass) {
3789 // It's a variable_ops instruction so we can't use DefIdx here. Just use
3790 // first def operand.
3791 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
3792 UseClass, UseIdx))
3793 --UseCycle;
3794 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
3795 UseClass, UseIdx)) {
3796 --UseCycle;
3797 }
3798 }
3799
3800 return UseCycle;
3801 }
3802
getBundledDefMI(const TargetRegisterInfo * TRI,const MachineInstr * MI,unsigned Reg,unsigned & DefIdx,unsigned & Dist)3803 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
3804 const MachineInstr *MI, unsigned Reg,
3805 unsigned &DefIdx, unsigned &Dist) {
3806 Dist = 0;
3807
3808 MachineBasicBlock::const_iterator I = MI; ++I;
3809 MachineBasicBlock::const_instr_iterator II = std::prev(I.getInstrIterator());
3810 assert(II->isInsideBundle() && "Empty bundle?");
3811
3812 int Idx = -1;
3813 while (II->isInsideBundle()) {
3814 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
3815 if (Idx != -1)
3816 break;
3817 --II;
3818 ++Dist;
3819 }
3820
3821 assert(Idx != -1 && "Cannot find bundled definition!");
3822 DefIdx = Idx;
3823 return &*II;
3824 }
3825
getBundledUseMI(const TargetRegisterInfo * TRI,const MachineInstr & MI,unsigned Reg,unsigned & UseIdx,unsigned & Dist)3826 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
3827 const MachineInstr &MI, unsigned Reg,
3828 unsigned &UseIdx, unsigned &Dist) {
3829 Dist = 0;
3830
3831 MachineBasicBlock::const_instr_iterator II = ++MI.getIterator();
3832 assert(II->isInsideBundle() && "Empty bundle?");
3833 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
3834
3835 // FIXME: This doesn't properly handle multiple uses.
3836 int Idx = -1;
3837 while (II != E && II->isInsideBundle()) {
3838 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
3839 if (Idx != -1)
3840 break;
3841 if (II->getOpcode() != ARM::t2IT)
3842 ++Dist;
3843 ++II;
3844 }
3845
3846 if (Idx == -1) {
3847 Dist = 0;
3848 return nullptr;
3849 }
3850
3851 UseIdx = Idx;
3852 return &*II;
3853 }
3854
3855 /// Return the number of cycles to add to (or subtract from) the static
3856 /// itinerary based on the def opcode and alignment. The caller will ensure that
3857 /// adjusted latency is at least one cycle.
adjustDefLatency(const ARMSubtarget & Subtarget,const MachineInstr & DefMI,const MCInstrDesc & DefMCID,unsigned DefAlign)3858 static int adjustDefLatency(const ARMSubtarget &Subtarget,
3859 const MachineInstr &DefMI,
3860 const MCInstrDesc &DefMCID, unsigned DefAlign) {
3861 int Adjust = 0;
3862 if (Subtarget.isCortexA8() || Subtarget.isLikeA9() || Subtarget.isCortexA7()) {
3863 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3864 // variants are one cycle cheaper.
3865 switch (DefMCID.getOpcode()) {
3866 default: break;
3867 case ARM::LDRrs:
3868 case ARM::LDRBrs: {
3869 unsigned ShOpVal = DefMI.getOperand(3).getImm();
3870 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3871 if (ShImm == 0 ||
3872 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3873 --Adjust;
3874 break;
3875 }
3876 case ARM::t2LDRs:
3877 case ARM::t2LDRBs:
3878 case ARM::t2LDRHs:
3879 case ARM::t2LDRSHs: {
3880 // Thumb2 mode: lsl only.
3881 unsigned ShAmt = DefMI.getOperand(3).getImm();
3882 if (ShAmt == 0 || ShAmt == 2)
3883 --Adjust;
3884 break;
3885 }
3886 }
3887 } else if (Subtarget.isSwift()) {
3888 // FIXME: Properly handle all of the latency adjustments for address
3889 // writeback.
3890 switch (DefMCID.getOpcode()) {
3891 default: break;
3892 case ARM::LDRrs:
3893 case ARM::LDRBrs: {
3894 unsigned ShOpVal = DefMI.getOperand(3).getImm();
3895 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3896 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3897 if (!isSub &&
3898 (ShImm == 0 ||
3899 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3900 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3901 Adjust -= 2;
3902 else if (!isSub &&
3903 ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3904 --Adjust;
3905 break;
3906 }
3907 case ARM::t2LDRs:
3908 case ARM::t2LDRBs:
3909 case ARM::t2LDRHs:
3910 case ARM::t2LDRSHs: {
3911 // Thumb2 mode: lsl only.
3912 unsigned ShAmt = DefMI.getOperand(3).getImm();
3913 if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3)
3914 Adjust -= 2;
3915 break;
3916 }
3917 }
3918 }
3919
3920 if (DefAlign < 8 && Subtarget.checkVLDnAccessAlignment()) {
3921 switch (DefMCID.getOpcode()) {
3922 default: break;
3923 case ARM::VLD1q8:
3924 case ARM::VLD1q16:
3925 case ARM::VLD1q32:
3926 case ARM::VLD1q64:
3927 case ARM::VLD1q8wb_fixed:
3928 case ARM::VLD1q16wb_fixed:
3929 case ARM::VLD1q32wb_fixed:
3930 case ARM::VLD1q64wb_fixed:
3931 case ARM::VLD1q8wb_register:
3932 case ARM::VLD1q16wb_register:
3933 case ARM::VLD1q32wb_register:
3934 case ARM::VLD1q64wb_register:
3935 case ARM::VLD2d8:
3936 case ARM::VLD2d16:
3937 case ARM::VLD2d32:
3938 case ARM::VLD2q8:
3939 case ARM::VLD2q16:
3940 case ARM::VLD2q32:
3941 case ARM::VLD2d8wb_fixed:
3942 case ARM::VLD2d16wb_fixed:
3943 case ARM::VLD2d32wb_fixed:
3944 case ARM::VLD2q8wb_fixed:
3945 case ARM::VLD2q16wb_fixed:
3946 case ARM::VLD2q32wb_fixed:
3947 case ARM::VLD2d8wb_register:
3948 case ARM::VLD2d16wb_register:
3949 case ARM::VLD2d32wb_register:
3950 case ARM::VLD2q8wb_register:
3951 case ARM::VLD2q16wb_register:
3952 case ARM::VLD2q32wb_register:
3953 case ARM::VLD3d8:
3954 case ARM::VLD3d16:
3955 case ARM::VLD3d32:
3956 case ARM::VLD1d64T:
3957 case ARM::VLD3d8_UPD:
3958 case ARM::VLD3d16_UPD:
3959 case ARM::VLD3d32_UPD:
3960 case ARM::VLD1d64Twb_fixed:
3961 case ARM::VLD1d64Twb_register:
3962 case ARM::VLD3q8_UPD:
3963 case ARM::VLD3q16_UPD:
3964 case ARM::VLD3q32_UPD:
3965 case ARM::VLD4d8:
3966 case ARM::VLD4d16:
3967 case ARM::VLD4d32:
3968 case ARM::VLD1d64Q:
3969 case ARM::VLD4d8_UPD:
3970 case ARM::VLD4d16_UPD:
3971 case ARM::VLD4d32_UPD:
3972 case ARM::VLD1d64Qwb_fixed:
3973 case ARM::VLD1d64Qwb_register:
3974 case ARM::VLD4q8_UPD:
3975 case ARM::VLD4q16_UPD:
3976 case ARM::VLD4q32_UPD:
3977 case ARM::VLD1DUPq8:
3978 case ARM::VLD1DUPq16:
3979 case ARM::VLD1DUPq32:
3980 case ARM::VLD1DUPq8wb_fixed:
3981 case ARM::VLD1DUPq16wb_fixed:
3982 case ARM::VLD1DUPq32wb_fixed:
3983 case ARM::VLD1DUPq8wb_register:
3984 case ARM::VLD1DUPq16wb_register:
3985 case ARM::VLD1DUPq32wb_register:
3986 case ARM::VLD2DUPd8:
3987 case ARM::VLD2DUPd16:
3988 case ARM::VLD2DUPd32:
3989 case ARM::VLD2DUPd8wb_fixed:
3990 case ARM::VLD2DUPd16wb_fixed:
3991 case ARM::VLD2DUPd32wb_fixed:
3992 case ARM::VLD2DUPd8wb_register:
3993 case ARM::VLD2DUPd16wb_register:
3994 case ARM::VLD2DUPd32wb_register:
3995 case ARM::VLD4DUPd8:
3996 case ARM::VLD4DUPd16:
3997 case ARM::VLD4DUPd32:
3998 case ARM::VLD4DUPd8_UPD:
3999 case ARM::VLD4DUPd16_UPD:
4000 case ARM::VLD4DUPd32_UPD:
4001 case ARM::VLD1LNd8:
4002 case ARM::VLD1LNd16:
4003 case ARM::VLD1LNd32:
4004 case ARM::VLD1LNd8_UPD:
4005 case ARM::VLD1LNd16_UPD:
4006 case ARM::VLD1LNd32_UPD:
4007 case ARM::VLD2LNd8:
4008 case ARM::VLD2LNd16:
4009 case ARM::VLD2LNd32:
4010 case ARM::VLD2LNq16:
4011 case ARM::VLD2LNq32:
4012 case ARM::VLD2LNd8_UPD:
4013 case ARM::VLD2LNd16_UPD:
4014 case ARM::VLD2LNd32_UPD:
4015 case ARM::VLD2LNq16_UPD:
4016 case ARM::VLD2LNq32_UPD:
4017 case ARM::VLD4LNd8:
4018 case ARM::VLD4LNd16:
4019 case ARM::VLD4LNd32:
4020 case ARM::VLD4LNq16:
4021 case ARM::VLD4LNq32:
4022 case ARM::VLD4LNd8_UPD:
4023 case ARM::VLD4LNd16_UPD:
4024 case ARM::VLD4LNd32_UPD:
4025 case ARM::VLD4LNq16_UPD:
4026 case ARM::VLD4LNq32_UPD:
4027 // If the address is not 64-bit aligned, the latencies of these
4028 // instructions increases by one.
4029 ++Adjust;
4030 break;
4031 }
4032 }
4033 return Adjust;
4034 }
4035
getOperandLatency(const InstrItineraryData * ItinData,const MachineInstr & DefMI,unsigned DefIdx,const MachineInstr & UseMI,unsigned UseIdx) const4036 int ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
4037 const MachineInstr &DefMI,
4038 unsigned DefIdx,
4039 const MachineInstr &UseMI,
4040 unsigned UseIdx) const {
4041 // No operand latency. The caller may fall back to getInstrLatency.
4042 if (!ItinData || ItinData->isEmpty())
4043 return -1;
4044
4045 const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
4046 unsigned Reg = DefMO.getReg();
4047
4048 const MachineInstr *ResolvedDefMI = &DefMI;
4049 unsigned DefAdj = 0;
4050 if (DefMI.isBundle())
4051 ResolvedDefMI =
4052 getBundledDefMI(&getRegisterInfo(), &DefMI, Reg, DefIdx, DefAdj);
4053 if (ResolvedDefMI->isCopyLike() || ResolvedDefMI->isInsertSubreg() ||
4054 ResolvedDefMI->isRegSequence() || ResolvedDefMI->isImplicitDef()) {
4055 return 1;
4056 }
4057
4058 const MachineInstr *ResolvedUseMI = &UseMI;
4059 unsigned UseAdj = 0;
4060 if (UseMI.isBundle()) {
4061 ResolvedUseMI =
4062 getBundledUseMI(&getRegisterInfo(), UseMI, Reg, UseIdx, UseAdj);
4063 if (!ResolvedUseMI)
4064 return -1;
4065 }
4066
4067 return getOperandLatencyImpl(
4068 ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO,
4069 Reg, *ResolvedUseMI, UseIdx, ResolvedUseMI->getDesc(), UseAdj);
4070 }
4071
getOperandLatencyImpl(const InstrItineraryData * ItinData,const MachineInstr & DefMI,unsigned DefIdx,const MCInstrDesc & DefMCID,unsigned DefAdj,const MachineOperand & DefMO,unsigned Reg,const MachineInstr & UseMI,unsigned UseIdx,const MCInstrDesc & UseMCID,unsigned UseAdj) const4072 int ARMBaseInstrInfo::getOperandLatencyImpl(
4073 const InstrItineraryData *ItinData, const MachineInstr &DefMI,
4074 unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj,
4075 const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI,
4076 unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const {
4077 if (Reg == ARM::CPSR) {
4078 if (DefMI.getOpcode() == ARM::FMSTAT) {
4079 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
4080 return Subtarget.isLikeA9() ? 1 : 20;
4081 }
4082
4083 // CPSR set and branch can be paired in the same cycle.
4084 if (UseMI.isBranch())
4085 return 0;
4086
4087 // Otherwise it takes the instruction latency (generally one).
4088 unsigned Latency = getInstrLatency(ItinData, DefMI);
4089
4090 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
4091 // its uses. Instructions which are otherwise scheduled between them may
4092 // incur a code size penalty (not able to use the CPSR setting 16-bit
4093 // instructions).
4094 if (Latency > 0 && Subtarget.isThumb2()) {
4095 const MachineFunction *MF = DefMI.getParent()->getParent();
4096 // FIXME: Use Function::optForSize().
4097 if (MF->getFunction().hasFnAttribute(Attribute::OptimizeForSize))
4098 --Latency;
4099 }
4100 return Latency;
4101 }
4102
4103 if (DefMO.isImplicit() || UseMI.getOperand(UseIdx).isImplicit())
4104 return -1;
4105
4106 unsigned DefAlign = DefMI.hasOneMemOperand()
4107 ? (*DefMI.memoperands_begin())->getAlignment()
4108 : 0;
4109 unsigned UseAlign = UseMI.hasOneMemOperand()
4110 ? (*UseMI.memoperands_begin())->getAlignment()
4111 : 0;
4112
4113 // Get the itinerary's latency if possible, and handle variable_ops.
4114 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, UseMCID,
4115 UseIdx, UseAlign);
4116 // Unable to find operand latency. The caller may resort to getInstrLatency.
4117 if (Latency < 0)
4118 return Latency;
4119
4120 // Adjust for IT block position.
4121 int Adj = DefAdj + UseAdj;
4122
4123 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
4124 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
4125 if (Adj >= 0 || (int)Latency > -Adj) {
4126 return Latency + Adj;
4127 }
4128 // Return the itinerary latency, which may be zero but not less than zero.
4129 return Latency;
4130 }
4131
4132 int
getOperandLatency(const InstrItineraryData * ItinData,SDNode * DefNode,unsigned DefIdx,SDNode * UseNode,unsigned UseIdx) const4133 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
4134 SDNode *DefNode, unsigned DefIdx,
4135 SDNode *UseNode, unsigned UseIdx) const {
4136 if (!DefNode->isMachineOpcode())
4137 return 1;
4138
4139 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
4140
4141 if (isZeroCost(DefMCID.Opcode))
4142 return 0;
4143
4144 if (!ItinData || ItinData->isEmpty())
4145 return DefMCID.mayLoad() ? 3 : 1;
4146
4147 if (!UseNode->isMachineOpcode()) {
4148 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
4149 int Adj = Subtarget.getPreISelOperandLatencyAdjustment();
4150 int Threshold = 1 + Adj;
4151 return Latency <= Threshold ? 1 : Latency - Adj;
4152 }
4153
4154 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
4155 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
4156 unsigned DefAlign = !DefMN->memoperands_empty()
4157 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
4158 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
4159 unsigned UseAlign = !UseMN->memoperands_empty()
4160 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
4161 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
4162 UseMCID, UseIdx, UseAlign);
4163
4164 if (Latency > 1 &&
4165 (Subtarget.isCortexA8() || Subtarget.isLikeA9() ||
4166 Subtarget.isCortexA7())) {
4167 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
4168 // variants are one cycle cheaper.
4169 switch (DefMCID.getOpcode()) {
4170 default: break;
4171 case ARM::LDRrs:
4172 case ARM::LDRBrs: {
4173 unsigned ShOpVal =
4174 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
4175 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
4176 if (ShImm == 0 ||
4177 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
4178 --Latency;
4179 break;
4180 }
4181 case ARM::t2LDRs:
4182 case ARM::t2LDRBs:
4183 case ARM::t2LDRHs:
4184 case ARM::t2LDRSHs: {
4185 // Thumb2 mode: lsl only.
4186 unsigned ShAmt =
4187 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
4188 if (ShAmt == 0 || ShAmt == 2)
4189 --Latency;
4190 break;
4191 }
4192 }
4193 } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) {
4194 // FIXME: Properly handle all of the latency adjustments for address
4195 // writeback.
4196 switch (DefMCID.getOpcode()) {
4197 default: break;
4198 case ARM::LDRrs:
4199 case ARM::LDRBrs: {
4200 unsigned ShOpVal =
4201 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
4202 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
4203 if (ShImm == 0 ||
4204 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
4205 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
4206 Latency -= 2;
4207 else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
4208 --Latency;
4209 break;
4210 }
4211 case ARM::t2LDRs:
4212 case ARM::t2LDRBs:
4213 case ARM::t2LDRHs:
4214 case ARM::t2LDRSHs:
4215 // Thumb2 mode: lsl 0-3 only.
4216 Latency -= 2;
4217 break;
4218 }
4219 }
4220
4221 if (DefAlign < 8 && Subtarget.checkVLDnAccessAlignment())
4222 switch (DefMCID.getOpcode()) {
4223 default: break;
4224 case ARM::VLD1q8:
4225 case ARM::VLD1q16:
4226 case ARM::VLD1q32:
4227 case ARM::VLD1q64:
4228 case ARM::VLD1q8wb_register:
4229 case ARM::VLD1q16wb_register:
4230 case ARM::VLD1q32wb_register:
4231 case ARM::VLD1q64wb_register:
4232 case ARM::VLD1q8wb_fixed:
4233 case ARM::VLD1q16wb_fixed:
4234 case ARM::VLD1q32wb_fixed:
4235 case ARM::VLD1q64wb_fixed:
4236 case ARM::VLD2d8:
4237 case ARM::VLD2d16:
4238 case ARM::VLD2d32:
4239 case ARM::VLD2q8Pseudo:
4240 case ARM::VLD2q16Pseudo:
4241 case ARM::VLD2q32Pseudo:
4242 case ARM::VLD2d8wb_fixed:
4243 case ARM::VLD2d16wb_fixed:
4244 case ARM::VLD2d32wb_fixed:
4245 case ARM::VLD2q8PseudoWB_fixed:
4246 case ARM::VLD2q16PseudoWB_fixed:
4247 case ARM::VLD2q32PseudoWB_fixed:
4248 case ARM::VLD2d8wb_register:
4249 case ARM::VLD2d16wb_register:
4250 case ARM::VLD2d32wb_register:
4251 case ARM::VLD2q8PseudoWB_register:
4252 case ARM::VLD2q16PseudoWB_register:
4253 case ARM::VLD2q32PseudoWB_register:
4254 case ARM::VLD3d8Pseudo:
4255 case ARM::VLD3d16Pseudo:
4256 case ARM::VLD3d32Pseudo:
4257 case ARM::VLD1d8TPseudo:
4258 case ARM::VLD1d16TPseudo:
4259 case ARM::VLD1d32TPseudo:
4260 case ARM::VLD1d64TPseudo:
4261 case ARM::VLD1d64TPseudoWB_fixed:
4262 case ARM::VLD1d64TPseudoWB_register:
4263 case ARM::VLD3d8Pseudo_UPD:
4264 case ARM::VLD3d16Pseudo_UPD:
4265 case ARM::VLD3d32Pseudo_UPD:
4266 case ARM::VLD3q8Pseudo_UPD:
4267 case ARM::VLD3q16Pseudo_UPD:
4268 case ARM::VLD3q32Pseudo_UPD:
4269 case ARM::VLD3q8oddPseudo:
4270 case ARM::VLD3q16oddPseudo:
4271 case ARM::VLD3q32oddPseudo:
4272 case ARM::VLD3q8oddPseudo_UPD:
4273 case ARM::VLD3q16oddPseudo_UPD:
4274 case ARM::VLD3q32oddPseudo_UPD:
4275 case ARM::VLD4d8Pseudo:
4276 case ARM::VLD4d16Pseudo:
4277 case ARM::VLD4d32Pseudo:
4278 case ARM::VLD1d8QPseudo:
4279 case ARM::VLD1d16QPseudo:
4280 case ARM::VLD1d32QPseudo:
4281 case ARM::VLD1d64QPseudo:
4282 case ARM::VLD1d64QPseudoWB_fixed:
4283 case ARM::VLD1d64QPseudoWB_register:
4284 case ARM::VLD1q8HighQPseudo:
4285 case ARM::VLD1q8LowQPseudo_UPD:
4286 case ARM::VLD1q8HighTPseudo:
4287 case ARM::VLD1q8LowTPseudo_UPD:
4288 case ARM::VLD1q16HighQPseudo:
4289 case ARM::VLD1q16LowQPseudo_UPD:
4290 case ARM::VLD1q16HighTPseudo:
4291 case ARM::VLD1q16LowTPseudo_UPD:
4292 case ARM::VLD1q32HighQPseudo:
4293 case ARM::VLD1q32LowQPseudo_UPD:
4294 case ARM::VLD1q32HighTPseudo:
4295 case ARM::VLD1q32LowTPseudo_UPD:
4296 case ARM::VLD1q64HighQPseudo:
4297 case ARM::VLD1q64LowQPseudo_UPD:
4298 case ARM::VLD1q64HighTPseudo:
4299 case ARM::VLD1q64LowTPseudo_UPD:
4300 case ARM::VLD4d8Pseudo_UPD:
4301 case ARM::VLD4d16Pseudo_UPD:
4302 case ARM::VLD4d32Pseudo_UPD:
4303 case ARM::VLD4q8Pseudo_UPD:
4304 case ARM::VLD4q16Pseudo_UPD:
4305 case ARM::VLD4q32Pseudo_UPD:
4306 case ARM::VLD4q8oddPseudo:
4307 case ARM::VLD4q16oddPseudo:
4308 case ARM::VLD4q32oddPseudo:
4309 case ARM::VLD4q8oddPseudo_UPD:
4310 case ARM::VLD4q16oddPseudo_UPD:
4311 case ARM::VLD4q32oddPseudo_UPD:
4312 case ARM::VLD1DUPq8:
4313 case ARM::VLD1DUPq16:
4314 case ARM::VLD1DUPq32:
4315 case ARM::VLD1DUPq8wb_fixed:
4316 case ARM::VLD1DUPq16wb_fixed:
4317 case ARM::VLD1DUPq32wb_fixed:
4318 case ARM::VLD1DUPq8wb_register:
4319 case ARM::VLD1DUPq16wb_register:
4320 case ARM::VLD1DUPq32wb_register:
4321 case ARM::VLD2DUPd8:
4322 case ARM::VLD2DUPd16:
4323 case ARM::VLD2DUPd32:
4324 case ARM::VLD2DUPd8wb_fixed:
4325 case ARM::VLD2DUPd16wb_fixed:
4326 case ARM::VLD2DUPd32wb_fixed:
4327 case ARM::VLD2DUPd8wb_register:
4328 case ARM::VLD2DUPd16wb_register:
4329 case ARM::VLD2DUPd32wb_register:
4330 case ARM::VLD2DUPq8EvenPseudo:
4331 case ARM::VLD2DUPq8OddPseudo:
4332 case ARM::VLD2DUPq16EvenPseudo:
4333 case ARM::VLD2DUPq16OddPseudo:
4334 case ARM::VLD2DUPq32EvenPseudo:
4335 case ARM::VLD2DUPq32OddPseudo:
4336 case ARM::VLD3DUPq8EvenPseudo:
4337 case ARM::VLD3DUPq8OddPseudo:
4338 case ARM::VLD3DUPq16EvenPseudo:
4339 case ARM::VLD3DUPq16OddPseudo:
4340 case ARM::VLD3DUPq32EvenPseudo:
4341 case ARM::VLD3DUPq32OddPseudo:
4342 case ARM::VLD4DUPd8Pseudo:
4343 case ARM::VLD4DUPd16Pseudo:
4344 case ARM::VLD4DUPd32Pseudo:
4345 case ARM::VLD4DUPd8Pseudo_UPD:
4346 case ARM::VLD4DUPd16Pseudo_UPD:
4347 case ARM::VLD4DUPd32Pseudo_UPD:
4348 case ARM::VLD4DUPq8EvenPseudo:
4349 case ARM::VLD4DUPq8OddPseudo:
4350 case ARM::VLD4DUPq16EvenPseudo:
4351 case ARM::VLD4DUPq16OddPseudo:
4352 case ARM::VLD4DUPq32EvenPseudo:
4353 case ARM::VLD4DUPq32OddPseudo:
4354 case ARM::VLD1LNq8Pseudo:
4355 case ARM::VLD1LNq16Pseudo:
4356 case ARM::VLD1LNq32Pseudo:
4357 case ARM::VLD1LNq8Pseudo_UPD:
4358 case ARM::VLD1LNq16Pseudo_UPD:
4359 case ARM::VLD1LNq32Pseudo_UPD:
4360 case ARM::VLD2LNd8Pseudo:
4361 case ARM::VLD2LNd16Pseudo:
4362 case ARM::VLD2LNd32Pseudo:
4363 case ARM::VLD2LNq16Pseudo:
4364 case ARM::VLD2LNq32Pseudo:
4365 case ARM::VLD2LNd8Pseudo_UPD:
4366 case ARM::VLD2LNd16Pseudo_UPD:
4367 case ARM::VLD2LNd32Pseudo_UPD:
4368 case ARM::VLD2LNq16Pseudo_UPD:
4369 case ARM::VLD2LNq32Pseudo_UPD:
4370 case ARM::VLD4LNd8Pseudo:
4371 case ARM::VLD4LNd16Pseudo:
4372 case ARM::VLD4LNd32Pseudo:
4373 case ARM::VLD4LNq16Pseudo:
4374 case ARM::VLD4LNq32Pseudo:
4375 case ARM::VLD4LNd8Pseudo_UPD:
4376 case ARM::VLD4LNd16Pseudo_UPD:
4377 case ARM::VLD4LNd32Pseudo_UPD:
4378 case ARM::VLD4LNq16Pseudo_UPD:
4379 case ARM::VLD4LNq32Pseudo_UPD:
4380 // If the address is not 64-bit aligned, the latencies of these
4381 // instructions increases by one.
4382 ++Latency;
4383 break;
4384 }
4385
4386 return Latency;
4387 }
4388
getPredicationCost(const MachineInstr & MI) const4389 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr &MI) const {
4390 if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() ||
4391 MI.isImplicitDef())
4392 return 0;
4393
4394 if (MI.isBundle())
4395 return 0;
4396
4397 const MCInstrDesc &MCID = MI.getDesc();
4398
4399 if (MCID.isCall() || (MCID.hasImplicitDefOfPhysReg(ARM::CPSR) &&
4400 !Subtarget.cheapPredicableCPSRDef())) {
4401 // When predicated, CPSR is an additional source operand for CPSR updating
4402 // instructions, this apparently increases their latencies.
4403 return 1;
4404 }
4405 return 0;
4406 }
4407
getInstrLatency(const InstrItineraryData * ItinData,const MachineInstr & MI,unsigned * PredCost) const4408 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4409 const MachineInstr &MI,
4410 unsigned *PredCost) const {
4411 if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() ||
4412 MI.isImplicitDef())
4413 return 1;
4414
4415 // An instruction scheduler typically runs on unbundled instructions, however
4416 // other passes may query the latency of a bundled instruction.
4417 if (MI.isBundle()) {
4418 unsigned Latency = 0;
4419 MachineBasicBlock::const_instr_iterator I = MI.getIterator();
4420 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
4421 while (++I != E && I->isInsideBundle()) {
4422 if (I->getOpcode() != ARM::t2IT)
4423 Latency += getInstrLatency(ItinData, *I, PredCost);
4424 }
4425 return Latency;
4426 }
4427
4428 const MCInstrDesc &MCID = MI.getDesc();
4429 if (PredCost && (MCID.isCall() || (MCID.hasImplicitDefOfPhysReg(ARM::CPSR) &&
4430 !Subtarget.cheapPredicableCPSRDef()))) {
4431 // When predicated, CPSR is an additional source operand for CPSR updating
4432 // instructions, this apparently increases their latencies.
4433 *PredCost = 1;
4434 }
4435 // Be sure to call getStageLatency for an empty itinerary in case it has a
4436 // valid MinLatency property.
4437 if (!ItinData)
4438 return MI.mayLoad() ? 3 : 1;
4439
4440 unsigned Class = MCID.getSchedClass();
4441
4442 // For instructions with variable uops, use uops as latency.
4443 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
4444 return getNumMicroOps(ItinData, MI);
4445
4446 // For the common case, fall back on the itinerary's latency.
4447 unsigned Latency = ItinData->getStageLatency(Class);
4448
4449 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
4450 unsigned DefAlign =
4451 MI.hasOneMemOperand() ? (*MI.memoperands_begin())->getAlignment() : 0;
4452 int Adj = adjustDefLatency(Subtarget, MI, MCID, DefAlign);
4453 if (Adj >= 0 || (int)Latency > -Adj) {
4454 return Latency + Adj;
4455 }
4456 return Latency;
4457 }
4458
getInstrLatency(const InstrItineraryData * ItinData,SDNode * Node) const4459 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4460 SDNode *Node) const {
4461 if (!Node->isMachineOpcode())
4462 return 1;
4463
4464 if (!ItinData || ItinData->isEmpty())
4465 return 1;
4466
4467 unsigned Opcode = Node->getMachineOpcode();
4468 switch (Opcode) {
4469 default:
4470 return ItinData->getStageLatency(get(Opcode).getSchedClass());
4471 case ARM::VLDMQIA:
4472 case ARM::VSTMQIA:
4473 return 2;
4474 }
4475 }
4476
hasHighOperandLatency(const TargetSchedModel & SchedModel,const MachineRegisterInfo * MRI,const MachineInstr & DefMI,unsigned DefIdx,const MachineInstr & UseMI,unsigned UseIdx) const4477 bool ARMBaseInstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
4478 const MachineRegisterInfo *MRI,
4479 const MachineInstr &DefMI,
4480 unsigned DefIdx,
4481 const MachineInstr &UseMI,
4482 unsigned UseIdx) const {
4483 unsigned DDomain = DefMI.getDesc().TSFlags & ARMII::DomainMask;
4484 unsigned UDomain = UseMI.getDesc().TSFlags & ARMII::DomainMask;
4485 if (Subtarget.nonpipelinedVFP() &&
4486 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
4487 return true;
4488
4489 // Hoist VFP / NEON instructions with 4 or higher latency.
4490 unsigned Latency =
4491 SchedModel.computeOperandLatency(&DefMI, DefIdx, &UseMI, UseIdx);
4492 if (Latency <= 3)
4493 return false;
4494 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
4495 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
4496 }
4497
hasLowDefLatency(const TargetSchedModel & SchedModel,const MachineInstr & DefMI,unsigned DefIdx) const4498 bool ARMBaseInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
4499 const MachineInstr &DefMI,
4500 unsigned DefIdx) const {
4501 const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
4502 if (!ItinData || ItinData->isEmpty())
4503 return false;
4504
4505 unsigned DDomain = DefMI.getDesc().TSFlags & ARMII::DomainMask;
4506 if (DDomain == ARMII::DomainGeneral) {
4507 unsigned DefClass = DefMI.getDesc().getSchedClass();
4508 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
4509 return (DefCycle != -1 && DefCycle <= 2);
4510 }
4511 return false;
4512 }
4513
verifyInstruction(const MachineInstr & MI,StringRef & ErrInfo) const4514 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr &MI,
4515 StringRef &ErrInfo) const {
4516 if (convertAddSubFlagsOpcode(MI.getOpcode())) {
4517 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
4518 return false;
4519 }
4520 return true;
4521 }
4522
4523 // LoadStackGuard has so far only been implemented for MachO. Different code
4524 // sequence is needed for other targets.
expandLoadStackGuardBase(MachineBasicBlock::iterator MI,unsigned LoadImmOpc,unsigned LoadOpc) const4525 void ARMBaseInstrInfo::expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
4526 unsigned LoadImmOpc,
4527 unsigned LoadOpc) const {
4528 assert(!Subtarget.isROPI() && !Subtarget.isRWPI() &&
4529 "ROPI/RWPI not currently supported with stack guard");
4530
4531 MachineBasicBlock &MBB = *MI->getParent();
4532 DebugLoc DL = MI->getDebugLoc();
4533 unsigned Reg = MI->getOperand(0).getReg();
4534 const GlobalValue *GV =
4535 cast<GlobalValue>((*MI->memoperands_begin())->getValue());
4536 MachineInstrBuilder MIB;
4537
4538 BuildMI(MBB, MI, DL, get(LoadImmOpc), Reg)
4539 .addGlobalAddress(GV, 0, ARMII::MO_NONLAZY);
4540
4541 if (Subtarget.isGVIndirectSymbol(GV)) {
4542 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4543 MIB.addReg(Reg, RegState::Kill).addImm(0);
4544 auto Flags = MachineMemOperand::MOLoad |
4545 MachineMemOperand::MODereferenceable |
4546 MachineMemOperand::MOInvariant;
4547 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
4548 MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 4, 4);
4549 MIB.addMemOperand(MMO).add(predOps(ARMCC::AL));
4550 }
4551
4552 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4553 MIB.addReg(Reg, RegState::Kill)
4554 .addImm(0)
4555 .cloneMemRefs(*MI)
4556 .add(predOps(ARMCC::AL));
4557 }
4558
4559 bool
isFpMLxInstruction(unsigned Opcode,unsigned & MulOpc,unsigned & AddSubOpc,bool & NegAcc,bool & HasLane) const4560 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
4561 unsigned &AddSubOpc,
4562 bool &NegAcc, bool &HasLane) const {
4563 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
4564 if (I == MLxEntryMap.end())
4565 return false;
4566
4567 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
4568 MulOpc = Entry.MulOpc;
4569 AddSubOpc = Entry.AddSubOpc;
4570 NegAcc = Entry.NegAcc;
4571 HasLane = Entry.HasLane;
4572 return true;
4573 }
4574
4575 //===----------------------------------------------------------------------===//
4576 // Execution domains.
4577 //===----------------------------------------------------------------------===//
4578 //
4579 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
4580 // and some can go down both. The vmov instructions go down the VFP pipeline,
4581 // but they can be changed to vorr equivalents that are executed by the NEON
4582 // pipeline.
4583 //
4584 // We use the following execution domain numbering:
4585 //
4586 enum ARMExeDomain {
4587 ExeGeneric = 0,
4588 ExeVFP = 1,
4589 ExeNEON = 2
4590 };
4591
4592 //
4593 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
4594 //
4595 std::pair<uint16_t, uint16_t>
getExecutionDomain(const MachineInstr & MI) const4596 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr &MI) const {
4597 // If we don't have access to NEON instructions then we won't be able
4598 // to swizzle anything to the NEON domain. Check to make sure.
4599 if (Subtarget.hasNEON()) {
4600 // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
4601 // if they are not predicated.
4602 if (MI.getOpcode() == ARM::VMOVD && !isPredicated(MI))
4603 return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
4604
4605 // CortexA9 is particularly picky about mixing the two and wants these
4606 // converted.
4607 if (Subtarget.useNEONForFPMovs() && !isPredicated(MI) &&
4608 (MI.getOpcode() == ARM::VMOVRS || MI.getOpcode() == ARM::VMOVSR ||
4609 MI.getOpcode() == ARM::VMOVS))
4610 return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
4611 }
4612 // No other instructions can be swizzled, so just determine their domain.
4613 unsigned Domain = MI.getDesc().TSFlags & ARMII::DomainMask;
4614
4615 if (Domain & ARMII::DomainNEON)
4616 return std::make_pair(ExeNEON, 0);
4617
4618 // Certain instructions can go either way on Cortex-A8.
4619 // Treat them as NEON instructions.
4620 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
4621 return std::make_pair(ExeNEON, 0);
4622
4623 if (Domain & ARMII::DomainVFP)
4624 return std::make_pair(ExeVFP, 0);
4625
4626 return std::make_pair(ExeGeneric, 0);
4627 }
4628
getCorrespondingDRegAndLane(const TargetRegisterInfo * TRI,unsigned SReg,unsigned & Lane)4629 static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
4630 unsigned SReg, unsigned &Lane) {
4631 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
4632 Lane = 0;
4633
4634 if (DReg != ARM::NoRegister)
4635 return DReg;
4636
4637 Lane = 1;
4638 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
4639
4640 assert(DReg && "S-register with no D super-register?");
4641 return DReg;
4642 }
4643
4644 /// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane,
4645 /// set ImplicitSReg to a register number that must be marked as implicit-use or
4646 /// zero if no register needs to be defined as implicit-use.
4647 ///
4648 /// If the function cannot determine if an SPR should be marked implicit use or
4649 /// not, it returns false.
4650 ///
4651 /// This function handles cases where an instruction is being modified from taking
4652 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
4653 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
4654 /// lane of the DPR).
4655 ///
4656 /// If the other SPR is defined, an implicit-use of it should be added. Else,
4657 /// (including the case where the DPR itself is defined), it should not.
4658 ///
getImplicitSPRUseForDPRUse(const TargetRegisterInfo * TRI,MachineInstr & MI,unsigned DReg,unsigned Lane,unsigned & ImplicitSReg)4659 static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI,
4660 MachineInstr &MI, unsigned DReg,
4661 unsigned Lane, unsigned &ImplicitSReg) {
4662 // If the DPR is defined or used already, the other SPR lane will be chained
4663 // correctly, so there is nothing to be done.
4664 if (MI.definesRegister(DReg, TRI) || MI.readsRegister(DReg, TRI)) {
4665 ImplicitSReg = 0;
4666 return true;
4667 }
4668
4669 // Otherwise we need to go searching to see if the SPR is set explicitly.
4670 ImplicitSReg = TRI->getSubReg(DReg,
4671 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
4672 MachineBasicBlock::LivenessQueryResult LQR =
4673 MI.getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI);
4674
4675 if (LQR == MachineBasicBlock::LQR_Live)
4676 return true;
4677 else if (LQR == MachineBasicBlock::LQR_Unknown)
4678 return false;
4679
4680 // If the register is known not to be live, there is no need to add an
4681 // implicit-use.
4682 ImplicitSReg = 0;
4683 return true;
4684 }
4685
setExecutionDomain(MachineInstr & MI,unsigned Domain) const4686 void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,
4687 unsigned Domain) const {
4688 unsigned DstReg, SrcReg, DReg;
4689 unsigned Lane;
4690 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4691 const TargetRegisterInfo *TRI = &getRegisterInfo();
4692 switch (MI.getOpcode()) {
4693 default:
4694 llvm_unreachable("cannot handle opcode!");
4695 break;
4696 case ARM::VMOVD:
4697 if (Domain != ExeNEON)
4698 break;
4699
4700 // Zap the predicate operands.
4701 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
4702
4703 // Make sure we've got NEON instructions.
4704 assert(Subtarget.hasNEON() && "VORRd requires NEON");
4705
4706 // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits)
4707 DstReg = MI.getOperand(0).getReg();
4708 SrcReg = MI.getOperand(1).getReg();
4709
4710 for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
4711 MI.RemoveOperand(i - 1);
4712
4713 // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits)
4714 MI.setDesc(get(ARM::VORRd));
4715 MIB.addReg(DstReg, RegState::Define)
4716 .addReg(SrcReg)
4717 .addReg(SrcReg)
4718 .add(predOps(ARMCC::AL));
4719 break;
4720 case ARM::VMOVRS:
4721 if (Domain != ExeNEON)
4722 break;
4723 assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
4724
4725 // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits)
4726 DstReg = MI.getOperand(0).getReg();
4727 SrcReg = MI.getOperand(1).getReg();
4728
4729 for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
4730 MI.RemoveOperand(i - 1);
4731
4732 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
4733
4734 // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps)
4735 // Note that DSrc has been widened and the other lane may be undef, which
4736 // contaminates the entire register.
4737 MI.setDesc(get(ARM::VGETLNi32));
4738 MIB.addReg(DstReg, RegState::Define)
4739 .addReg(DReg, RegState::Undef)
4740 .addImm(Lane)
4741 .add(predOps(ARMCC::AL));
4742
4743 // The old source should be an implicit use, otherwise we might think it
4744 // was dead before here.
4745 MIB.addReg(SrcReg, RegState::Implicit);
4746 break;
4747 case ARM::VMOVSR: {
4748 if (Domain != ExeNEON)
4749 break;
4750 assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
4751
4752 // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits)
4753 DstReg = MI.getOperand(0).getReg();
4754 SrcReg = MI.getOperand(1).getReg();
4755
4756 DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
4757
4758 unsigned ImplicitSReg;
4759 if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
4760 break;
4761
4762 for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
4763 MI.RemoveOperand(i - 1);
4764
4765 // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps)
4766 // Again DDst may be undefined at the beginning of this instruction.
4767 MI.setDesc(get(ARM::VSETLNi32));
4768 MIB.addReg(DReg, RegState::Define)
4769 .addReg(DReg, getUndefRegState(!MI.readsRegister(DReg, TRI)))
4770 .addReg(SrcReg)
4771 .addImm(Lane)
4772 .add(predOps(ARMCC::AL));
4773
4774 // The narrower destination must be marked as set to keep previous chains
4775 // in place.
4776 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4777 if (ImplicitSReg != 0)
4778 MIB.addReg(ImplicitSReg, RegState::Implicit);
4779 break;
4780 }
4781 case ARM::VMOVS: {
4782 if (Domain != ExeNEON)
4783 break;
4784
4785 // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits)
4786 DstReg = MI.getOperand(0).getReg();
4787 SrcReg = MI.getOperand(1).getReg();
4788
4789 unsigned DstLane = 0, SrcLane = 0, DDst, DSrc;
4790 DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane);
4791 DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane);
4792
4793 unsigned ImplicitSReg;
4794 if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
4795 break;
4796
4797 for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
4798 MI.RemoveOperand(i - 1);
4799
4800 if (DSrc == DDst) {
4801 // Destination can be:
4802 // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits)
4803 MI.setDesc(get(ARM::VDUPLN32d));
4804 MIB.addReg(DDst, RegState::Define)
4805 .addReg(DDst, getUndefRegState(!MI.readsRegister(DDst, TRI)))
4806 .addImm(SrcLane)
4807 .add(predOps(ARMCC::AL));
4808
4809 // Neither the source or the destination are naturally represented any
4810 // more, so add them in manually.
4811 MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
4812 MIB.addReg(SrcReg, RegState::Implicit);
4813 if (ImplicitSReg != 0)
4814 MIB.addReg(ImplicitSReg, RegState::Implicit);
4815 break;
4816 }
4817
4818 // In general there's no single instruction that can perform an S <-> S
4819 // move in NEON space, but a pair of VEXT instructions *can* do the
4820 // job. It turns out that the VEXTs needed will only use DSrc once, with
4821 // the position based purely on the combination of lane-0 and lane-1
4822 // involved. For example
4823 // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1
4824 // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1
4825 // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1
4826 // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1
4827 //
4828 // Pattern of the MachineInstrs is:
4829 // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits)
4830 MachineInstrBuilder NewMIB;
4831 NewMIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::VEXTd32),
4832 DDst);
4833
4834 // On the first instruction, both DSrc and DDst may be undef if present.
4835 // Specifically when the original instruction didn't have them as an
4836 // <imp-use>.
4837 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
4838 bool CurUndef = !MI.readsRegister(CurReg, TRI);
4839 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4840
4841 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst;
4842 CurUndef = !MI.readsRegister(CurReg, TRI);
4843 NewMIB.addReg(CurReg, getUndefRegState(CurUndef))
4844 .addImm(1)
4845 .add(predOps(ARMCC::AL));
4846
4847 if (SrcLane == DstLane)
4848 NewMIB.addReg(SrcReg, RegState::Implicit);
4849
4850 MI.setDesc(get(ARM::VEXTd32));
4851 MIB.addReg(DDst, RegState::Define);
4852
4853 // On the second instruction, DDst has definitely been defined above, so
4854 // it is not undef. DSrc, if present, can be undef as above.
4855 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst;
4856 CurUndef = CurReg == DSrc && !MI.readsRegister(CurReg, TRI);
4857 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4858
4859 CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst;
4860 CurUndef = CurReg == DSrc && !MI.readsRegister(CurReg, TRI);
4861 MIB.addReg(CurReg, getUndefRegState(CurUndef))
4862 .addImm(1)
4863 .add(predOps(ARMCC::AL));
4864
4865 if (SrcLane != DstLane)
4866 MIB.addReg(SrcReg, RegState::Implicit);
4867
4868 // As before, the original destination is no longer represented, add it
4869 // implicitly.
4870 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4871 if (ImplicitSReg != 0)
4872 MIB.addReg(ImplicitSReg, RegState::Implicit);
4873 break;
4874 }
4875 }
4876 }
4877
4878 //===----------------------------------------------------------------------===//
4879 // Partial register updates
4880 //===----------------------------------------------------------------------===//
4881 //
4882 // Swift renames NEON registers with 64-bit granularity. That means any
4883 // instruction writing an S-reg implicitly reads the containing D-reg. The
4884 // problem is mostly avoided by translating f32 operations to v2f32 operations
4885 // on D-registers, but f32 loads are still a problem.
4886 //
4887 // These instructions can load an f32 into a NEON register:
4888 //
4889 // VLDRS - Only writes S, partial D update.
4890 // VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops.
4891 // VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops.
4892 //
4893 // FCONSTD can be used as a dependency-breaking instruction.
getPartialRegUpdateClearance(const MachineInstr & MI,unsigned OpNum,const TargetRegisterInfo * TRI) const4894 unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance(
4895 const MachineInstr &MI, unsigned OpNum,
4896 const TargetRegisterInfo *TRI) const {
4897 auto PartialUpdateClearance = Subtarget.getPartialUpdateClearance();
4898 if (!PartialUpdateClearance)
4899 return 0;
4900
4901 assert(TRI && "Need TRI instance");
4902
4903 const MachineOperand &MO = MI.getOperand(OpNum);
4904 if (MO.readsReg())
4905 return 0;
4906 unsigned Reg = MO.getReg();
4907 int UseOp = -1;
4908
4909 switch (MI.getOpcode()) {
4910 // Normal instructions writing only an S-register.
4911 case ARM::VLDRS:
4912 case ARM::FCONSTS:
4913 case ARM::VMOVSR:
4914 case ARM::VMOVv8i8:
4915 case ARM::VMOVv4i16:
4916 case ARM::VMOVv2i32:
4917 case ARM::VMOVv2f32:
4918 case ARM::VMOVv1i64:
4919 UseOp = MI.findRegisterUseOperandIdx(Reg, false, TRI);
4920 break;
4921
4922 // Explicitly reads the dependency.
4923 case ARM::VLD1LNd32:
4924 UseOp = 3;
4925 break;
4926 default:
4927 return 0;
4928 }
4929
4930 // If this instruction actually reads a value from Reg, there is no unwanted
4931 // dependency.
4932 if (UseOp != -1 && MI.getOperand(UseOp).readsReg())
4933 return 0;
4934
4935 // We must be able to clobber the whole D-reg.
4936 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4937 // Virtual register must be a def undef foo:ssub_0 operand.
4938 if (!MO.getSubReg() || MI.readsVirtualRegister(Reg))
4939 return 0;
4940 } else if (ARM::SPRRegClass.contains(Reg)) {
4941 // Physical register: MI must define the full D-reg.
4942 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
4943 &ARM::DPRRegClass);
4944 if (!DReg || !MI.definesRegister(DReg, TRI))
4945 return 0;
4946 }
4947
4948 // MI has an unwanted D-register dependency.
4949 // Avoid defs in the previous N instructrions.
4950 return PartialUpdateClearance;
4951 }
4952
4953 // Break a partial register dependency after getPartialRegUpdateClearance
4954 // returned non-zero.
breakPartialRegDependency(MachineInstr & MI,unsigned OpNum,const TargetRegisterInfo * TRI) const4955 void ARMBaseInstrInfo::breakPartialRegDependency(
4956 MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
4957 assert(OpNum < MI.getDesc().getNumDefs() && "OpNum is not a def");
4958 assert(TRI && "Need TRI instance");
4959
4960 const MachineOperand &MO = MI.getOperand(OpNum);
4961 unsigned Reg = MO.getReg();
4962 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
4963 "Can't break virtual register dependencies.");
4964 unsigned DReg = Reg;
4965
4966 // If MI defines an S-reg, find the corresponding D super-register.
4967 if (ARM::SPRRegClass.contains(Reg)) {
4968 DReg = ARM::D0 + (Reg - ARM::S0) / 2;
4969 assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken");
4970 }
4971
4972 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps");
4973 assert(MI.definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");
4974
4975 // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines
4976 // the full D-register by loading the same value to both lanes. The
4977 // instruction is micro-coded with 2 uops, so don't do this until we can
4978 // properly schedule micro-coded instructions. The dispatcher stalls cause
4979 // too big regressions.
4980
4981 // Insert the dependency-breaking FCONSTD before MI.
4982 // 96 is the encoding of 0.5, but the actual value doesn't matter here.
4983 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::FCONSTD), DReg)
4984 .addImm(96)
4985 .add(predOps(ARMCC::AL));
4986 MI.addRegisterKilled(DReg, TRI, true);
4987 }
4988
hasNOP() const4989 bool ARMBaseInstrInfo::hasNOP() const {
4990 return Subtarget.getFeatureBits()[ARM::HasV6KOps];
4991 }
4992
isSwiftFastImmShift(const MachineInstr * MI) const4993 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
4994 if (MI->getNumOperands() < 4)
4995 return true;
4996 unsigned ShOpVal = MI->getOperand(3).getImm();
4997 unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal);
4998 // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1.
4999 if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) ||
5000 ((ShImm == 1 || ShImm == 2) &&
5001 ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl))
5002 return true;
5003
5004 return false;
5005 }
5006
getRegSequenceLikeInputs(const MachineInstr & MI,unsigned DefIdx,SmallVectorImpl<RegSubRegPairAndIdx> & InputRegs) const5007 bool ARMBaseInstrInfo::getRegSequenceLikeInputs(
5008 const MachineInstr &MI, unsigned DefIdx,
5009 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
5010 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
5011 assert(MI.isRegSequenceLike() && "Invalid kind of instruction");
5012
5013 switch (MI.getOpcode()) {
5014 case ARM::VMOVDRR:
5015 // dX = VMOVDRR rY, rZ
5016 // is the same as:
5017 // dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1
5018 // Populate the InputRegs accordingly.
5019 // rY
5020 const MachineOperand *MOReg = &MI.getOperand(1);
5021 if (!MOReg->isUndef())
5022 InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(),
5023 MOReg->getSubReg(), ARM::ssub_0));
5024 // rZ
5025 MOReg = &MI.getOperand(2);
5026 if (!MOReg->isUndef())
5027 InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(),
5028 MOReg->getSubReg(), ARM::ssub_1));
5029 return true;
5030 }
5031 llvm_unreachable("Target dependent opcode missing");
5032 }
5033
getExtractSubregLikeInputs(const MachineInstr & MI,unsigned DefIdx,RegSubRegPairAndIdx & InputReg) const5034 bool ARMBaseInstrInfo::getExtractSubregLikeInputs(
5035 const MachineInstr &MI, unsigned DefIdx,
5036 RegSubRegPairAndIdx &InputReg) const {
5037 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
5038 assert(MI.isExtractSubregLike() && "Invalid kind of instruction");
5039
5040 switch (MI.getOpcode()) {
5041 case ARM::VMOVRRD:
5042 // rX, rY = VMOVRRD dZ
5043 // is the same as:
5044 // rX = EXTRACT_SUBREG dZ, ssub_0
5045 // rY = EXTRACT_SUBREG dZ, ssub_1
5046 const MachineOperand &MOReg = MI.getOperand(2);
5047 if (MOReg.isUndef())
5048 return false;
5049 InputReg.Reg = MOReg.getReg();
5050 InputReg.SubReg = MOReg.getSubReg();
5051 InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1;
5052 return true;
5053 }
5054 llvm_unreachable("Target dependent opcode missing");
5055 }
5056
getInsertSubregLikeInputs(const MachineInstr & MI,unsigned DefIdx,RegSubRegPair & BaseReg,RegSubRegPairAndIdx & InsertedReg) const5057 bool ARMBaseInstrInfo::getInsertSubregLikeInputs(
5058 const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg,
5059 RegSubRegPairAndIdx &InsertedReg) const {
5060 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
5061 assert(MI.isInsertSubregLike() && "Invalid kind of instruction");
5062
5063 switch (MI.getOpcode()) {
5064 case ARM::VSETLNi32:
5065 // dX = VSETLNi32 dY, rZ, imm
5066 const MachineOperand &MOBaseReg = MI.getOperand(1);
5067 const MachineOperand &MOInsertedReg = MI.getOperand(2);
5068 if (MOInsertedReg.isUndef())
5069 return false;
5070 const MachineOperand &MOIndex = MI.getOperand(3);
5071 BaseReg.Reg = MOBaseReg.getReg();
5072 BaseReg.SubReg = MOBaseReg.getSubReg();
5073
5074 InsertedReg.Reg = MOInsertedReg.getReg();
5075 InsertedReg.SubReg = MOInsertedReg.getSubReg();
5076 InsertedReg.SubIdx = MOIndex.getImm() == 0 ? ARM::ssub_0 : ARM::ssub_1;
5077 return true;
5078 }
5079 llvm_unreachable("Target dependent opcode missing");
5080 }
5081
5082 std::pair<unsigned, unsigned>
decomposeMachineOperandsTargetFlags(unsigned TF) const5083 ARMBaseInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
5084 const unsigned Mask = ARMII::MO_OPTION_MASK;
5085 return std::make_pair(TF & Mask, TF & ~Mask);
5086 }
5087
5088 ArrayRef<std::pair<unsigned, const char *>>
getSerializableDirectMachineOperandTargetFlags() const5089 ARMBaseInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
5090 using namespace ARMII;
5091
5092 static const std::pair<unsigned, const char *> TargetFlags[] = {
5093 {MO_LO16, "arm-lo16"}, {MO_HI16, "arm-hi16"}};
5094 return makeArrayRef(TargetFlags);
5095 }
5096
5097 ArrayRef<std::pair<unsigned, const char *>>
getSerializableBitmaskMachineOperandTargetFlags() const5098 ARMBaseInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
5099 using namespace ARMII;
5100
5101 static const std::pair<unsigned, const char *> TargetFlags[] = {
5102 {MO_COFFSTUB, "arm-coffstub"},
5103 {MO_GOT, "arm-got"},
5104 {MO_SBREL, "arm-sbrel"},
5105 {MO_DLLIMPORT, "arm-dllimport"},
5106 {MO_SECREL, "arm-secrel"},
5107 {MO_NONLAZY, "arm-nonlazy"}};
5108 return makeArrayRef(TargetFlags);
5109 }
5110