1//===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the ARM instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// ARM specific DAG Nodes. 16// 17 18// Type profiles. 19def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 20 SDTCisVT<1, i32> ]>; 21def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>; 22def SDT_ARMStructByVal : SDTypeProfile<0, 4, 23 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 24 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 25 26def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>; 27 28def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 29 30def SDT_ARMCMov : SDTypeProfile<1, 3, 31 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 32 SDTCisVT<3, i32>]>; 33 34def SDT_ARMBrcond : SDTypeProfile<0, 2, 35 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 36 37def SDT_ARMBrJT : SDTypeProfile<0, 2, 38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 39 40def SDT_ARMBr2JT : SDTypeProfile<0, 3, 41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>, 42 SDTCisVT<2, i32>]>; 43 44def SDT_ARMBCC_i64 : SDTypeProfile<0, 6, 45 [SDTCisVT<0, i32>, 46 SDTCisVT<1, i32>, SDTCisVT<2, i32>, 47 SDTCisVT<3, i32>, SDTCisVT<4, i32>, 48 SDTCisVT<5, OtherVT>]>; 49 50def SDT_ARMAnd : SDTypeProfile<1, 2, 51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 52 SDTCisVT<2, i32>]>; 53 54def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; 55def SDT_ARMFCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, 56 SDTCisVT<2, i32>]>; 57 58def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 59 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>; 60 61def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 62def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>, 63 SDTCisInt<2>]>; 64def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; 65def SDT_ARMEH_SJLJ_SetupDispatch: SDTypeProfile<0, 0, []>; 66 67def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 68 69def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, 70 SDTCisInt<1>]>; 71 72def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 73 74def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 75 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 76 77def SDT_WIN__DBZCHK : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 78 79def SDT_ARMMEMCPY : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 80 SDTCisVT<2, i32>, SDTCisVT<3, i32>, 81 SDTCisVT<4, i32>]>; 82 83def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 84 [SDTCisSameAs<0, 2>, 85 SDTCisSameAs<0, 3>, 86 SDTCisInt<0>, SDTCisVT<1, i32>]>; 87 88// SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR 89def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 90 [SDTCisSameAs<0, 2>, 91 SDTCisSameAs<0, 3>, 92 SDTCisInt<0>, 93 SDTCisVT<1, i32>, 94 SDTCisVT<4, i32>]>; 95 96def SDT_LongMac : SDTypeProfile<2, 4, [SDTCisVT<0, i32>, 97 SDTCisSameAs<0, 1>, 98 SDTCisSameAs<0, 2>, 99 SDTCisSameAs<0, 3>, 100 SDTCisSameAs<0, 4>, 101 SDTCisSameAs<0, 5>]>; 102 103def ARMSmlald : SDNode<"ARMISD::SMLALD", SDT_LongMac>; 104def ARMSmlaldx : SDNode<"ARMISD::SMLALDX", SDT_LongMac>; 105def ARMSmlsld : SDNode<"ARMISD::SMLSLD", SDT_LongMac>; 106def ARMSmlsldx : SDNode<"ARMISD::SMLSLDX", SDT_LongMac>; 107 108def SDT_MulHSR : SDTypeProfile<1, 3, [SDTCisVT<0,i32>, 109 SDTCisSameAs<0, 1>, 110 SDTCisSameAs<0, 2>, 111 SDTCisSameAs<0, 3>]>; 112 113def ARMsmmlar : SDNode<"ARMISD::SMMLAR", SDT_MulHSR>; 114def ARMsmmlsr : SDNode<"ARMISD::SMMLSR", SDT_MulHSR>; 115 116// Node definitions. 117def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>; 118def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>; 119def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntUnaryOp>; 120 121def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart, 122 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 123def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd, 124 [SDNPHasChain, SDNPSideEffect, 125 SDNPOptInGlue, SDNPOutGlue]>; 126def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" , 127 SDT_ARMStructByVal, 128 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 129 SDNPMayStore, SDNPMayLoad]>; 130 131def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall, 132 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 133 SDNPVariadic]>; 134def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall, 135 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 136 SDNPVariadic]>; 137def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall, 138 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 139 SDNPVariadic]>; 140 141def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone, 142 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 143def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall, 144 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 145def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov, 146 [SDNPInGlue]>; 147def ARMsubs : SDNode<"ARMISD::SUBS", SDTIntBinOp, [SDNPOutGlue]>; 148 149def ARMssatnoshift : SDNode<"ARMISD::SSAT", SDTIntSatNoShOp, []>; 150 151def ARMusatnoshift : SDNode<"ARMISD::USAT", SDTIntSatNoShOp, []>; 152 153def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond, 154 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 155 156def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT, 157 [SDNPHasChain]>; 158def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT, 159 [SDNPHasChain]>; 160 161def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64, 162 [SDNPHasChain]>; 163 164def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp, 165 [SDNPOutGlue]>; 166 167def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp, 168 [SDNPOutGlue]>; 169 170def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp, 171 [SDNPOutGlue, SDNPCommutative]>; 172 173def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>; 174 175def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 176def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>; 177def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>; 178 179def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags, 180 [SDNPCommutative]>; 181def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>; 182def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>; 183def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>; 184 185def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>; 186def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", 187 SDT_ARMEH_SJLJ_Setjmp, 188 [SDNPHasChain, SDNPSideEffect]>; 189def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP", 190 SDT_ARMEH_SJLJ_Longjmp, 191 [SDNPHasChain, SDNPSideEffect]>; 192def ARMeh_sjlj_setup_dispatch: SDNode<"ARMISD::EH_SJLJ_SETUP_DISPATCH", 193 SDT_ARMEH_SJLJ_SetupDispatch, 194 [SDNPHasChain, SDNPSideEffect]>; 195 196def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER, 197 [SDNPHasChain, SDNPSideEffect]>; 198def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH, 199 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; 200 201def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET, 202 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 203 204def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; 205 206def ARMmemcopy : SDNode<"ARMISD::MEMCPY", SDT_ARMMEMCPY, 207 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 208 SDNPMayStore, SDNPMayLoad]>; 209 210def ARMsmulwb : SDNode<"ARMISD::SMULWB", SDTIntBinOp, []>; 211def ARMsmulwt : SDNode<"ARMISD::SMULWT", SDTIntBinOp, []>; 212def ARMsmlalbb : SDNode<"ARMISD::SMLALBB", SDT_LongMac, []>; 213def ARMsmlalbt : SDNode<"ARMISD::SMLALBT", SDT_LongMac, []>; 214def ARMsmlaltb : SDNode<"ARMISD::SMLALTB", SDT_LongMac, []>; 215def ARMsmlaltt : SDNode<"ARMISD::SMLALTT", SDT_LongMac, []>; 216 217//===----------------------------------------------------------------------===// 218// ARM Instruction Predicate Definitions. 219// 220def HasV4T : Predicate<"Subtarget->hasV4TOps()">, 221 AssemblerPredicate<"HasV4TOps", "armv4t">; 222def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; 223def HasV5T : Predicate<"Subtarget->hasV5TOps()">, 224 AssemblerPredicate<"HasV5TOps", "armv5t">; 225def NoV5T : Predicate<"!Subtarget->hasV5TOps()">; 226def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, 227 AssemblerPredicate<"HasV5TEOps", "armv5te">; 228def HasV6 : Predicate<"Subtarget->hasV6Ops()">, 229 AssemblerPredicate<"HasV6Ops", "armv6">; 230def NoV6 : Predicate<"!Subtarget->hasV6Ops()">; 231def HasV6M : Predicate<"Subtarget->hasV6MOps()">, 232 AssemblerPredicate<"HasV6MOps", 233 "armv6m or armv6t2">; 234def HasV8MBaseline : Predicate<"Subtarget->hasV8MBaselineOps()">, 235 AssemblerPredicate<"HasV8MBaselineOps", 236 "armv8m.base">; 237def HasV8MMainline : Predicate<"Subtarget->hasV8MMainlineOps()">, 238 AssemblerPredicate<"HasV8MMainlineOps", 239 "armv8m.main">; 240def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, 241 AssemblerPredicate<"HasV6T2Ops", "armv6t2">; 242def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; 243def HasV6K : Predicate<"Subtarget->hasV6KOps()">, 244 AssemblerPredicate<"HasV6KOps", "armv6k">; 245def NoV6K : Predicate<"!Subtarget->hasV6KOps()">; 246def HasV7 : Predicate<"Subtarget->hasV7Ops()">, 247 AssemblerPredicate<"HasV7Ops", "armv7">; 248def HasV8 : Predicate<"Subtarget->hasV8Ops()">, 249 AssemblerPredicate<"HasV8Ops", "armv8">; 250def PreV8 : Predicate<"!Subtarget->hasV8Ops()">, 251 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">; 252def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">, 253 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">; 254def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">, 255 AssemblerPredicate<"HasV8_2aOps", "armv8.2a">; 256def HasV8_3a : Predicate<"Subtarget->hasV8_3aOps()">, 257 AssemblerPredicate<"HasV8_3aOps", "armv8.3a">; 258def HasV8_4a : Predicate<"Subtarget->hasV8_4aOps()">, 259 AssemblerPredicate<"HasV8_4aOps", "armv8.4a">; 260def HasV8_5a : Predicate<"Subtarget->hasV8_5aOps()">, 261 AssemblerPredicate<"HasV8_5aOps", "armv8.5a">; 262def NoVFP : Predicate<"!Subtarget->hasVFP2()">; 263def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, 264 AssemblerPredicate<"FeatureVFP2", "VFP2">; 265def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, 266 AssemblerPredicate<"FeatureVFP3", "VFP3">; 267def HasVFP4 : Predicate<"Subtarget->hasVFP4()">, 268 AssemblerPredicate<"FeatureVFP4", "VFP4">; 269def HasDPVFP : Predicate<"!Subtarget->isFPOnlySP()">, 270 AssemblerPredicate<"!FeatureVFPOnlySP", 271 "double precision VFP">; 272def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, 273 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">; 274def HasNEON : Predicate<"Subtarget->hasNEON()">, 275 AssemblerPredicate<"FeatureNEON", "NEON">; 276def HasSHA2 : Predicate<"Subtarget->hasSHA2()">, 277 AssemblerPredicate<"FeatureSHA2", "sha2">; 278def HasAES : Predicate<"Subtarget->hasAES()">, 279 AssemblerPredicate<"FeatureAES", "aes">; 280def HasCrypto : Predicate<"Subtarget->hasCrypto()">, 281 AssemblerPredicate<"FeatureCrypto", "crypto">; 282def HasDotProd : Predicate<"Subtarget->hasDotProd()">, 283 AssemblerPredicate<"FeatureDotProd", "dotprod">; 284def HasCRC : Predicate<"Subtarget->hasCRC()">, 285 AssemblerPredicate<"FeatureCRC", "crc">; 286def HasRAS : Predicate<"Subtarget->hasRAS()">, 287 AssemblerPredicate<"FeatureRAS", "ras">; 288def HasFP16 : Predicate<"Subtarget->hasFP16()">, 289 AssemblerPredicate<"FeatureFP16","half-float conversions">; 290def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">, 291 AssemblerPredicate<"FeatureFullFP16","full half-float">; 292def HasFP16FML : Predicate<"Subtarget->hasFP16FML()">, 293 AssemblerPredicate<"FeatureFP16FML","full half-float fml">; 294def HasDivideInThumb : Predicate<"Subtarget->hasDivideInThumbMode()">, 295 AssemblerPredicate<"FeatureHWDivThumb", "divide in THUMB">; 296def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">, 297 AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">; 298def HasDSP : Predicate<"Subtarget->hasDSP()">, 299 AssemblerPredicate<"FeatureDSP", "dsp">; 300def HasDB : Predicate<"Subtarget->hasDataBarrier()">, 301 AssemblerPredicate<"FeatureDB", 302 "data-barriers">; 303def HasDFB : Predicate<"Subtarget->hasFullDataBarrier()">, 304 AssemblerPredicate<"FeatureDFB", 305 "full-data-barrier">; 306def HasV7Clrex : Predicate<"Subtarget->hasV7Clrex()">, 307 AssemblerPredicate<"FeatureV7Clrex", 308 "v7 clrex">; 309def HasAcquireRelease : Predicate<"Subtarget->hasAcquireRelease()">, 310 AssemblerPredicate<"FeatureAcquireRelease", 311 "acquire/release">; 312def HasMP : Predicate<"Subtarget->hasMPExtension()">, 313 AssemblerPredicate<"FeatureMP", 314 "mp-extensions">; 315def HasVirtualization: Predicate<"false">, 316 AssemblerPredicate<"FeatureVirtualization", 317 "virtualization-extensions">; 318def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">, 319 AssemblerPredicate<"FeatureTrustZone", 320 "TrustZone">; 321def Has8MSecExt : Predicate<"Subtarget->has8MSecExt()">, 322 AssemblerPredicate<"Feature8MSecExt", 323 "ARMv8-M Security Extensions">; 324def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">; 325def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; 326def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; 327def IsThumb : Predicate<"Subtarget->isThumb()">, 328 AssemblerPredicate<"ModeThumb", "thumb">; 329def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; 330def IsThumb2 : Predicate<"Subtarget->isThumb2()">, 331 AssemblerPredicate<"ModeThumb,FeatureThumb2", 332 "thumb2">; 333def IsMClass : Predicate<"Subtarget->isMClass()">, 334 AssemblerPredicate<"FeatureMClass", "armv*m">; 335def IsNotMClass : Predicate<"!Subtarget->isMClass()">, 336 AssemblerPredicate<"!FeatureMClass", 337 "!armv*m">; 338def IsARM : Predicate<"!Subtarget->isThumb()">, 339 AssemblerPredicate<"!ModeThumb", "arm-mode">; 340def IsMachO : Predicate<"Subtarget->isTargetMachO()">; 341def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">; 342def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 343def IsWindows : Predicate<"Subtarget->isTargetWindows()">; 344def IsNotWindows : Predicate<"!Subtarget->isTargetWindows()">; 345def IsReadTPHard : Predicate<"Subtarget->isReadTPHard()">; 346def IsReadTPSoft : Predicate<"!Subtarget->isReadTPHard()">; 347def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">, 348 AssemblerPredicate<"FeatureNaClTrap", "NaCl">; 349def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">; 350 351def UseNegativeImmediates : 352 Predicate<"false">, 353 AssemblerPredicate<"!FeatureNoNegativeImmediates", 354 "NegativeImmediates">; 355 356// FIXME: Eventually this will be just "hasV6T2Ops". 357let RecomputePerFunction = 1 in { 358 def UseMovt : Predicate<"Subtarget->useMovt(*MF)">; 359 def DontUseMovt : Predicate<"!Subtarget->useMovt(*MF)">; 360 def UseMovtInPic : Predicate<"Subtarget->useMovt(*MF) && Subtarget->allowPositionIndependentMovt()">; 361 def DontUseMovtInPic : Predicate<"!Subtarget->useMovt(*MF) || !Subtarget->allowPositionIndependentMovt()">; 362 363 def UseFPVMLx: Predicate<"((Subtarget->useFPVMLx() &&" 364 " TM.Options.AllowFPOpFusion != FPOpFusion::Fast) ||" 365 "MF->getFunction().optForMinSize())">; 366} 367def UseMulOps : Predicate<"Subtarget->useMulOps()">; 368 369// Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available. 370// But only select them if more precision in FP computation is allowed, and when 371// they are not slower than a mul + add sequence. 372// Do not use them for Darwin platforms. 373def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion ==" 374 " FPOpFusion::Fast && " 375 " Subtarget->hasVFP4()) && " 376 "!Subtarget->isTargetDarwin() &&" 377 "Subtarget->useFPVMLx()">; 378 379def HasFastVGETLNi32 : Predicate<"!Subtarget->hasSlowVGETLNi32()">; 380def HasSlowVGETLNi32 : Predicate<"Subtarget->hasSlowVGETLNi32()">; 381 382def HasFastVDUP32 : Predicate<"!Subtarget->hasSlowVDUP32()">; 383def HasSlowVDUP32 : Predicate<"Subtarget->hasSlowVDUP32()">; 384 385def UseVMOVSR : Predicate<"Subtarget->preferVMOVSR() ||" 386 "!Subtarget->useNEONForSinglePrecisionFP()">; 387def DontUseVMOVSR : Predicate<"!Subtarget->preferVMOVSR() &&" 388 "Subtarget->useNEONForSinglePrecisionFP()">; 389 390let RecomputePerFunction = 1 in { 391 def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">; 392 def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">; 393} 394 395def GenExecuteOnly : Predicate<"Subtarget->genExecuteOnly()">; 396 397// Armv8.5-A extensions 398def HasSB : Predicate<"Subtarget->hasSB()">, 399 AssemblerPredicate<"FeatureSB", "sb">; 400 401//===----------------------------------------------------------------------===// 402// ARM Flag Definitions. 403 404class RegConstraint<string C> { 405 string Constraints = C; 406} 407 408//===----------------------------------------------------------------------===// 409// ARM specific transformation functions and pattern fragments. 410// 411 412// imm_neg_XFORM - Return the negation of an i32 immediate value. 413def imm_neg_XFORM : SDNodeXForm<imm, [{ 414 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32); 415}]>; 416 417// imm_not_XFORM - Return the complement of a i32 immediate value. 418def imm_not_XFORM : SDNodeXForm<imm, [{ 419 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32); 420}]>; 421 422/// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31]. 423def imm16_31 : ImmLeaf<i32, [{ 424 return (int32_t)Imm >= 16 && (int32_t)Imm < 32; 425}]>; 426 427// sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits. 428def sext_16_node : PatLeaf<(i32 GPR:$a), [{ 429 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17; 430}]>; 431 432def sext_bottom_16 : PatFrag<(ops node:$a), 433 (sext_inreg node:$a, i16)>; 434def sext_top_16 : PatFrag<(ops node:$a), 435 (i32 (sra node:$a, (i32 16)))>; 436 437def bb_mul : PatFrag<(ops node:$a, node:$b), 438 (mul (sext_bottom_16 node:$a), (sext_bottom_16 node:$b))>; 439def bt_mul : PatFrag<(ops node:$a, node:$b), 440 (mul (sext_bottom_16 node:$a), (sra node:$b, (i32 16)))>; 441def tb_mul : PatFrag<(ops node:$a, node:$b), 442 (mul (sra node:$a, (i32 16)), (sext_bottom_16 node:$b))>; 443def tt_mul : PatFrag<(ops node:$a, node:$b), 444 (mul (sra node:$a, (i32 16)), (sra node:$b, (i32 16)))>; 445 446/// Split a 32-bit immediate into two 16 bit parts. 447def hi16 : SDNodeXForm<imm, [{ 448 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N), 449 MVT::i32); 450}]>; 451 452def lo16AllZero : PatLeaf<(i32 imm), [{ 453 // Returns true if all low 16-bits are 0. 454 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0; 455}], hi16>; 456 457class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>; 458class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>; 459 460// An 'and' node with a single use. 461def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 462 return N->hasOneUse(); 463}]>; 464 465// An 'xor' node with a single use. 466def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{ 467 return N->hasOneUse(); 468}]>; 469 470// An 'fmul' node with a single use. 471def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{ 472 return N->hasOneUse(); 473}]>; 474 475// An 'fadd' node which checks for single non-hazardous use. 476def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{ 477 return hasNoVMLxHazardUse(N); 478}]>; 479 480// An 'fsub' node which checks for single non-hazardous use. 481def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{ 482 return hasNoVMLxHazardUse(N); 483}]>; 484 485//===----------------------------------------------------------------------===// 486// Operand Definitions. 487// 488 489// Immediate operands with a shared generic asm render method. 490class ImmAsmOperand<int Low, int High> : AsmOperandClass { 491 let RenderMethod = "addImmOperands"; 492 let PredicateMethod = "isImmediate<" # Low # "," # High # ">"; 493 let DiagnosticString = "operand must be an immediate in the range [" # Low # "," # High # "]"; 494} 495 496class ImmAsmOperandMinusOne<int Low, int High> : AsmOperandClass { 497 let PredicateMethod = "isImmediate<" # Low # "," # High # ">"; 498 let DiagnosticType = "ImmRange" # Low # "_" # High; 499 let DiagnosticString = "operand must be an immediate in the range [" # Low # "," # High # "]"; 500} 501 502// Operands that are part of a memory addressing mode. 503class MemOperand : Operand<i32> { let OperandType = "OPERAND_MEMORY"; } 504 505// Branch target. 506// FIXME: rename brtarget to t2_brtarget 507def brtarget : Operand<OtherVT> { 508 let EncoderMethod = "getBranchTargetOpValue"; 509 let OperandType = "OPERAND_PCREL"; 510 let DecoderMethod = "DecodeT2BROperand"; 511} 512 513// Branches targeting ARM-mode must be divisible by 4 if they're a raw 514// immediate. 515def ARMBranchTarget : AsmOperandClass { 516 let Name = "ARMBranchTarget"; 517} 518 519// Branches targeting Thumb-mode must be divisible by 2 if they're a raw 520// immediate. 521def ThumbBranchTarget : AsmOperandClass { 522 let Name = "ThumbBranchTarget"; 523} 524 525def arm_br_target : Operand<OtherVT> { 526 let ParserMatchClass = ARMBranchTarget; 527 let EncoderMethod = "getARMBranchTargetOpValue"; 528 let OperandType = "OPERAND_PCREL"; 529} 530 531// Call target for ARM. Handles conditional/unconditional 532// FIXME: rename bl_target to t2_bltarget? 533def arm_bl_target : Operand<i32> { 534 let ParserMatchClass = ARMBranchTarget; 535 let EncoderMethod = "getARMBLTargetOpValue"; 536 let OperandType = "OPERAND_PCREL"; 537} 538 539// Target for BLX *from* ARM mode. 540def arm_blx_target : Operand<i32> { 541 let ParserMatchClass = ThumbBranchTarget; 542 let EncoderMethod = "getARMBLXTargetOpValue"; 543 let OperandType = "OPERAND_PCREL"; 544} 545 546// A list of registers separated by comma. Used by load/store multiple. 547def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; } 548def reglist : Operand<i32> { 549 let EncoderMethod = "getRegisterListOpValue"; 550 let ParserMatchClass = RegListAsmOperand; 551 let PrintMethod = "printRegisterList"; 552 let DecoderMethod = "DecodeRegListOperand"; 553} 554 555def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">; 556 557def DPRRegListAsmOperand : AsmOperandClass { 558 let Name = "DPRRegList"; 559 let DiagnosticType = "DPR_RegList"; 560} 561def dpr_reglist : Operand<i32> { 562 let EncoderMethod = "getRegisterListOpValue"; 563 let ParserMatchClass = DPRRegListAsmOperand; 564 let PrintMethod = "printRegisterList"; 565 let DecoderMethod = "DecodeDPRRegListOperand"; 566} 567 568def SPRRegListAsmOperand : AsmOperandClass { 569 let Name = "SPRRegList"; 570 let DiagnosticString = "operand must be a list of registers in range [s0, s31]"; 571} 572def spr_reglist : Operand<i32> { 573 let EncoderMethod = "getRegisterListOpValue"; 574 let ParserMatchClass = SPRRegListAsmOperand; 575 let PrintMethod = "printRegisterList"; 576 let DecoderMethod = "DecodeSPRRegListOperand"; 577} 578 579// An operand for the CONSTPOOL_ENTRY pseudo-instruction. 580def cpinst_operand : Operand<i32> { 581 let PrintMethod = "printCPInstOperand"; 582} 583 584// Local PC labels. 585def pclabel : Operand<i32> { 586 let PrintMethod = "printPCLabel"; 587} 588 589// ADR instruction labels. 590def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; } 591def adrlabel : Operand<i32> { 592 let EncoderMethod = "getAdrLabelOpValue"; 593 let ParserMatchClass = AdrLabelAsmOperand; 594 let PrintMethod = "printAdrLabelOperand<0>"; 595} 596 597def neon_vcvt_imm32 : Operand<i32> { 598 let EncoderMethod = "getNEONVcvtImm32OpValue"; 599 let DecoderMethod = "DecodeVCVTImmOperand"; 600} 601 602// rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24. 603def rot_imm_XFORM: SDNodeXForm<imm, [{ 604 switch (N->getZExtValue()){ 605 default: llvm_unreachable(nullptr); 606 case 0: return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32); 607 case 8: return CurDAG->getTargetConstant(1, SDLoc(N), MVT::i32); 608 case 16: return CurDAG->getTargetConstant(2, SDLoc(N), MVT::i32); 609 case 24: return CurDAG->getTargetConstant(3, SDLoc(N), MVT::i32); 610 } 611}]>; 612def RotImmAsmOperand : AsmOperandClass { 613 let Name = "RotImm"; 614 let ParserMethod = "parseRotImm"; 615} 616def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{ 617 int32_t v = N->getZExtValue(); 618 return v == 8 || v == 16 || v == 24; }], 619 rot_imm_XFORM> { 620 let PrintMethod = "printRotImmOperand"; 621 let ParserMatchClass = RotImmAsmOperand; 622} 623 624// shift_imm: An integer that encodes a shift amount and the type of shift 625// (asr or lsl). The 6-bit immediate encodes as: 626// {5} 0 ==> lsl 627// 1 asr 628// {4-0} imm5 shift amount. 629// asr #32 encoded as imm5 == 0. 630def ShifterImmAsmOperand : AsmOperandClass { 631 let Name = "ShifterImm"; 632 let ParserMethod = "parseShifterImm"; 633} 634def shift_imm : Operand<i32> { 635 let PrintMethod = "printShiftImmOperand"; 636 let ParserMatchClass = ShifterImmAsmOperand; 637} 638 639// shifter_operand operands: so_reg_reg, so_reg_imm, and mod_imm. 640def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; } 641def so_reg_reg : Operand<i32>, // reg reg imm 642 ComplexPattern<i32, 3, "SelectRegShifterOperand", 643 [shl, srl, sra, rotr]> { 644 let EncoderMethod = "getSORegRegOpValue"; 645 let PrintMethod = "printSORegRegOperand"; 646 let DecoderMethod = "DecodeSORegRegOperand"; 647 let ParserMatchClass = ShiftedRegAsmOperand; 648 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm); 649} 650 651def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; } 652def so_reg_imm : Operand<i32>, // reg imm 653 ComplexPattern<i32, 2, "SelectImmShifterOperand", 654 [shl, srl, sra, rotr]> { 655 let EncoderMethod = "getSORegImmOpValue"; 656 let PrintMethod = "printSORegImmOperand"; 657 let DecoderMethod = "DecodeSORegImmOperand"; 658 let ParserMatchClass = ShiftedImmAsmOperand; 659 let MIOperandInfo = (ops GPR, i32imm); 660} 661 662// FIXME: Does this need to be distinct from so_reg? 663def shift_so_reg_reg : Operand<i32>, // reg reg imm 664 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand", 665 [shl,srl,sra,rotr]> { 666 let EncoderMethod = "getSORegRegOpValue"; 667 let PrintMethod = "printSORegRegOperand"; 668 let DecoderMethod = "DecodeSORegRegOperand"; 669 let ParserMatchClass = ShiftedRegAsmOperand; 670 let MIOperandInfo = (ops GPR, GPR, i32imm); 671} 672 673// FIXME: Does this need to be distinct from so_reg? 674def shift_so_reg_imm : Operand<i32>, // reg reg imm 675 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand", 676 [shl,srl,sra,rotr]> { 677 let EncoderMethod = "getSORegImmOpValue"; 678 let PrintMethod = "printSORegImmOperand"; 679 let DecoderMethod = "DecodeSORegImmOperand"; 680 let ParserMatchClass = ShiftedImmAsmOperand; 681 let MIOperandInfo = (ops GPR, i32imm); 682} 683 684// mod_imm: match a 32-bit immediate operand, which can be encoded into 685// a 12-bit immediate; an 8-bit integer and a 4-bit rotator (See ARMARM 686// - "Modified Immediate Constants"). Within the MC layer we keep this 687// immediate in its encoded form. 688def ModImmAsmOperand: AsmOperandClass { 689 let Name = "ModImm"; 690 let ParserMethod = "parseModImm"; 691} 692def mod_imm : Operand<i32>, ImmLeaf<i32, [{ 693 return ARM_AM::getSOImmVal(Imm) != -1; 694 }]> { 695 let EncoderMethod = "getModImmOpValue"; 696 let PrintMethod = "printModImmOperand"; 697 let ParserMatchClass = ModImmAsmOperand; 698} 699 700// Note: the patterns mod_imm_not and mod_imm_neg do not require an encoder 701// method and such, as they are only used on aliases (Pat<> and InstAlias<>). 702// The actual parsing, encoding, decoding are handled by the destination 703// instructions, which use mod_imm. 704 705def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; } 706def mod_imm_not : Operand<i32>, PatLeaf<(imm), [{ 707 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1; 708 }], imm_not_XFORM> { 709 let ParserMatchClass = ModImmNotAsmOperand; 710} 711 712def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; } 713def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{ 714 unsigned Value = -(unsigned)N->getZExtValue(); 715 return Value && ARM_AM::getSOImmVal(Value) != -1; 716 }], imm_neg_XFORM> { 717 let ParserMatchClass = ModImmNegAsmOperand; 718} 719 720/// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal() 721def arm_i32imm : PatLeaf<(imm), [{ 722 if (Subtarget->useMovt(*MF)) 723 return true; 724 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue()); 725}]> { 726 // Ideally this would be an IntImmLeaf, but then we wouldn't have access to 727 // the MachineFunction. 728 let GISelPredicateCode = [{ 729 const auto &MF = *MI.getParent()->getParent(); 730 if (STI.useMovt(MF)) 731 return true; 732 733 const auto &MO = MI.getOperand(1); 734 if (!MO.isCImm()) 735 return false; 736 return ARM_AM::isSOImmTwoPartVal(MO.getCImm()->getZExtValue()); 737 }]; 738} 739 740/// imm0_1 predicate - Immediate in the range [0,1]. 741def Imm0_1AsmOperand: ImmAsmOperand<0,1> { let Name = "Imm0_1"; } 742def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; } 743 744/// imm0_3 predicate - Immediate in the range [0,3]. 745def Imm0_3AsmOperand: ImmAsmOperand<0,3> { let Name = "Imm0_3"; } 746def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; } 747 748/// imm0_7 predicate - Immediate in the range [0,7]. 749def Imm0_7AsmOperand: ImmAsmOperand<0,7> { 750 let Name = "Imm0_7"; 751} 752def imm0_7 : Operand<i32>, ImmLeaf<i32, [{ 753 return Imm >= 0 && Imm < 8; 754}]> { 755 let ParserMatchClass = Imm0_7AsmOperand; 756} 757 758/// imm8_255 predicate - Immediate in the range [8,255]. 759def Imm8_255AsmOperand: ImmAsmOperand<8,255> { let Name = "Imm8_255"; } 760def imm8_255 : Operand<i32>, ImmLeaf<i32, [{ 761 return Imm >= 8 && Imm < 256; 762}]> { 763 let ParserMatchClass = Imm8_255AsmOperand; 764} 765 766/// imm8 predicate - Immediate is exactly 8. 767def Imm8AsmOperand: ImmAsmOperand<8,8> { let Name = "Imm8"; } 768def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> { 769 let ParserMatchClass = Imm8AsmOperand; 770} 771 772/// imm16 predicate - Immediate is exactly 16. 773def Imm16AsmOperand: ImmAsmOperand<16,16> { let Name = "Imm16"; } 774def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> { 775 let ParserMatchClass = Imm16AsmOperand; 776} 777 778/// imm32 predicate - Immediate is exactly 32. 779def Imm32AsmOperand: ImmAsmOperand<32,32> { let Name = "Imm32"; } 780def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> { 781 let ParserMatchClass = Imm32AsmOperand; 782} 783 784def imm8_or_16 : ImmLeaf<i32, [{ return Imm == 8 || Imm == 16;}]>; 785 786/// imm1_7 predicate - Immediate in the range [1,7]. 787def Imm1_7AsmOperand: ImmAsmOperand<1,7> { let Name = "Imm1_7"; } 788def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> { 789 let ParserMatchClass = Imm1_7AsmOperand; 790} 791 792/// imm1_15 predicate - Immediate in the range [1,15]. 793def Imm1_15AsmOperand: ImmAsmOperand<1,15> { let Name = "Imm1_15"; } 794def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> { 795 let ParserMatchClass = Imm1_15AsmOperand; 796} 797 798/// imm1_31 predicate - Immediate in the range [1,31]. 799def Imm1_31AsmOperand: ImmAsmOperand<1,31> { let Name = "Imm1_31"; } 800def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> { 801 let ParserMatchClass = Imm1_31AsmOperand; 802} 803 804/// imm0_15 predicate - Immediate in the range [0,15]. 805def Imm0_15AsmOperand: ImmAsmOperand<0,15> { 806 let Name = "Imm0_15"; 807} 808def imm0_15 : Operand<i32>, ImmLeaf<i32, [{ 809 return Imm >= 0 && Imm < 16; 810}]> { 811 let ParserMatchClass = Imm0_15AsmOperand; 812} 813 814/// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31]. 815def Imm0_31AsmOperand: ImmAsmOperand<0,31> { let Name = "Imm0_31"; } 816def imm0_31 : Operand<i32>, ImmLeaf<i32, [{ 817 return Imm >= 0 && Imm < 32; 818}]> { 819 let ParserMatchClass = Imm0_31AsmOperand; 820} 821 822/// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32]. 823def Imm0_32AsmOperand: ImmAsmOperand<0,32> { let Name = "Imm0_32"; } 824def imm0_32 : Operand<i32>, ImmLeaf<i32, [{ 825 return Imm >= 0 && Imm < 33; 826}]> { 827 let ParserMatchClass = Imm0_32AsmOperand; 828} 829 830/// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63]. 831def Imm0_63AsmOperand: ImmAsmOperand<0,63> { let Name = "Imm0_63"; } 832def imm0_63 : Operand<i32>, ImmLeaf<i32, [{ 833 return Imm >= 0 && Imm < 64; 834}]> { 835 let ParserMatchClass = Imm0_63AsmOperand; 836} 837 838/// imm0_239 predicate - Immediate in the range [0,239]. 839def Imm0_239AsmOperand : ImmAsmOperand<0,239> { 840 let Name = "Imm0_239"; 841} 842def imm0_239 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 240; }]> { 843 let ParserMatchClass = Imm0_239AsmOperand; 844} 845 846/// imm0_255 predicate - Immediate in the range [0,255]. 847def Imm0_255AsmOperand : ImmAsmOperand<0,255> { let Name = "Imm0_255"; } 848def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> { 849 let ParserMatchClass = Imm0_255AsmOperand; 850} 851 852/// imm0_65535 - An immediate is in the range [0,65535]. 853def Imm0_65535AsmOperand: ImmAsmOperand<0,65535> { let Name = "Imm0_65535"; } 854def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{ 855 return Imm >= 0 && Imm < 65536; 856}]> { 857 let ParserMatchClass = Imm0_65535AsmOperand; 858} 859 860// imm0_65535_neg - An immediate whose negative value is in the range [0.65535]. 861def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{ 862 return -Imm >= 0 && -Imm < 65536; 863}]>; 864 865// imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference 866// a relocatable expression. 867// 868// FIXME: This really needs a Thumb version separate from the ARM version. 869// While the range is the same, and can thus use the same match class, 870// the encoding is different so it should have a different encoder method. 871def Imm0_65535ExprAsmOperand: AsmOperandClass { 872 let Name = "Imm0_65535Expr"; 873 let RenderMethod = "addImmOperands"; 874 let DiagnosticString = "operand must be an immediate in the range [0,0xffff] or a relocatable expression"; 875} 876 877def imm0_65535_expr : Operand<i32> { 878 let EncoderMethod = "getHiLo16ImmOpValue"; 879 let ParserMatchClass = Imm0_65535ExprAsmOperand; 880} 881 882def Imm256_65535ExprAsmOperand: ImmAsmOperand<256,65535> { let Name = "Imm256_65535Expr"; } 883def imm256_65535_expr : Operand<i32> { 884 let ParserMatchClass = Imm256_65535ExprAsmOperand; 885} 886 887/// imm24b - True if the 32-bit immediate is encodable in 24 bits. 888def Imm24bitAsmOperand: ImmAsmOperand<0,0xffffff> { 889 let Name = "Imm24bit"; 890 let DiagnosticString = "operand must be an immediate in the range [0,0xffffff]"; 891} 892def imm24b : Operand<i32>, ImmLeaf<i32, [{ 893 return Imm >= 0 && Imm <= 0xffffff; 894}]> { 895 let ParserMatchClass = Imm24bitAsmOperand; 896} 897 898 899/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield 900/// e.g., 0xf000ffff 901def BitfieldAsmOperand : AsmOperandClass { 902 let Name = "Bitfield"; 903 let ParserMethod = "parseBitfield"; 904} 905 906def bf_inv_mask_imm : Operand<i32>, 907 PatLeaf<(imm), [{ 908 return ARM::isBitFieldInvertedMask(N->getZExtValue()); 909}] > { 910 let EncoderMethod = "getBitfieldInvertedMaskOpValue"; 911 let PrintMethod = "printBitfieldInvMaskImmOperand"; 912 let DecoderMethod = "DecodeBitfieldMaskOperand"; 913 let ParserMatchClass = BitfieldAsmOperand; 914 let GISelPredicateCode = [{ 915 // There's better methods of implementing this check. IntImmLeaf<> would be 916 // equivalent and have less boilerplate but we need a test for C++ 917 // predicates and this one causes new rules to be imported into GlobalISel 918 // without requiring additional features first. 919 const auto &MO = MI.getOperand(1); 920 if (!MO.isCImm()) 921 return false; 922 return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue()); 923 }]; 924} 925 926def imm1_32_XFORM: SDNodeXForm<imm, [{ 927 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 928 MVT::i32); 929}]>; 930def Imm1_32AsmOperand: ImmAsmOperandMinusOne<1,32> { 931 let Name = "Imm1_32"; 932} 933def imm1_32 : Operand<i32>, PatLeaf<(imm), [{ 934 uint64_t Imm = N->getZExtValue(); 935 return Imm > 0 && Imm <= 32; 936 }], 937 imm1_32_XFORM> { 938 let PrintMethod = "printImmPlusOneOperand"; 939 let ParserMatchClass = Imm1_32AsmOperand; 940} 941 942def imm1_16_XFORM: SDNodeXForm<imm, [{ 943 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N), 944 MVT::i32); 945}]>; 946def Imm1_16AsmOperand: ImmAsmOperandMinusOne<1,16> { let Name = "Imm1_16"; } 947def imm1_16 : Operand<i32>, ImmLeaf<i32, [{ 948 return Imm > 0 && Imm <= 16; 949 }], 950 imm1_16_XFORM> { 951 let PrintMethod = "printImmPlusOneOperand"; 952 let ParserMatchClass = Imm1_16AsmOperand; 953} 954 955// Define ARM specific addressing modes. 956// addrmode_imm12 := reg +/- imm12 957// 958def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; } 959class AddrMode_Imm12 : MemOperand, 960 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> { 961 // 12-bit immediate operand. Note that instructions using this encode 962 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other 963 // immediate values are as normal. 964 965 let EncoderMethod = "getAddrModeImm12OpValue"; 966 let DecoderMethod = "DecodeAddrModeImm12Operand"; 967 let ParserMatchClass = MemImm12OffsetAsmOperand; 968 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 969} 970 971def addrmode_imm12 : AddrMode_Imm12 { 972 let PrintMethod = "printAddrModeImm12Operand<false>"; 973} 974 975def addrmode_imm12_pre : AddrMode_Imm12 { 976 let PrintMethod = "printAddrModeImm12Operand<true>"; 977} 978 979// ldst_so_reg := reg +/- reg shop imm 980// 981def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; } 982def ldst_so_reg : MemOperand, 983 ComplexPattern<i32, 3, "SelectLdStSOReg", []> { 984 let EncoderMethod = "getLdStSORegOpValue"; 985 // FIXME: Simplify the printer 986 let PrintMethod = "printAddrMode2Operand"; 987 let DecoderMethod = "DecodeSORegMemOperand"; 988 let ParserMatchClass = MemRegOffsetAsmOperand; 989 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift); 990} 991 992// postidx_imm8 := +/- [0,255] 993// 994// 9 bit value: 995// {8} 1 is imm8 is non-negative. 0 otherwise. 996// {7-0} [0,255] imm8 value. 997def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; } 998def postidx_imm8 : MemOperand { 999 let PrintMethod = "printPostIdxImm8Operand"; 1000 let ParserMatchClass = PostIdxImm8AsmOperand; 1001 let MIOperandInfo = (ops i32imm); 1002} 1003 1004// postidx_imm8s4 := +/- [0,1020] 1005// 1006// 9 bit value: 1007// {8} 1 is imm8 is non-negative. 0 otherwise. 1008// {7-0} [0,255] imm8 value, scaled by 4. 1009def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; } 1010def postidx_imm8s4 : MemOperand { 1011 let PrintMethod = "printPostIdxImm8s4Operand"; 1012 let ParserMatchClass = PostIdxImm8s4AsmOperand; 1013 let MIOperandInfo = (ops i32imm); 1014} 1015 1016 1017// postidx_reg := +/- reg 1018// 1019def PostIdxRegAsmOperand : AsmOperandClass { 1020 let Name = "PostIdxReg"; 1021 let ParserMethod = "parsePostIdxReg"; 1022} 1023def postidx_reg : MemOperand { 1024 let EncoderMethod = "getPostIdxRegOpValue"; 1025 let DecoderMethod = "DecodePostIdxReg"; 1026 let PrintMethod = "printPostIdxRegOperand"; 1027 let ParserMatchClass = PostIdxRegAsmOperand; 1028 let MIOperandInfo = (ops GPRnopc, i32imm); 1029} 1030 1031def PostIdxRegShiftedAsmOperand : AsmOperandClass { 1032 let Name = "PostIdxRegShifted"; 1033 let ParserMethod = "parsePostIdxReg"; 1034} 1035def am2offset_reg : MemOperand, 1036 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg", 1037 [], [SDNPWantRoot]> { 1038 let EncoderMethod = "getAddrMode2OffsetOpValue"; 1039 let PrintMethod = "printAddrMode2OffsetOperand"; 1040 // When using this for assembly, it's always as a post-index offset. 1041 let ParserMatchClass = PostIdxRegShiftedAsmOperand; 1042 let MIOperandInfo = (ops GPRnopc, i32imm); 1043} 1044 1045// FIXME: am2offset_imm should only need the immediate, not the GPR. Having 1046// the GPR is purely vestigal at this point. 1047def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; } 1048def am2offset_imm : MemOperand, 1049 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm", 1050 [], [SDNPWantRoot]> { 1051 let EncoderMethod = "getAddrMode2OffsetOpValue"; 1052 let PrintMethod = "printAddrMode2OffsetOperand"; 1053 let ParserMatchClass = AM2OffsetImmAsmOperand; 1054 let MIOperandInfo = (ops GPRnopc, i32imm); 1055} 1056 1057 1058// addrmode3 := reg +/- reg 1059// addrmode3 := reg +/- imm8 1060// 1061// FIXME: split into imm vs. reg versions. 1062def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; } 1063class AddrMode3 : MemOperand, 1064 ComplexPattern<i32, 3, "SelectAddrMode3", []> { 1065 let EncoderMethod = "getAddrMode3OpValue"; 1066 let ParserMatchClass = AddrMode3AsmOperand; 1067 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); 1068} 1069 1070def addrmode3 : AddrMode3 1071{ 1072 let PrintMethod = "printAddrMode3Operand<false>"; 1073} 1074 1075def addrmode3_pre : AddrMode3 1076{ 1077 let PrintMethod = "printAddrMode3Operand<true>"; 1078} 1079 1080// FIXME: split into imm vs. reg versions. 1081// FIXME: parser method to handle +/- register. 1082def AM3OffsetAsmOperand : AsmOperandClass { 1083 let Name = "AM3Offset"; 1084 let ParserMethod = "parseAM3Offset"; 1085} 1086def am3offset : MemOperand, 1087 ComplexPattern<i32, 2, "SelectAddrMode3Offset", 1088 [], [SDNPWantRoot]> { 1089 let EncoderMethod = "getAddrMode3OffsetOpValue"; 1090 let PrintMethod = "printAddrMode3OffsetOperand"; 1091 let ParserMatchClass = AM3OffsetAsmOperand; 1092 let MIOperandInfo = (ops GPR, i32imm); 1093} 1094 1095// ldstm_mode := {ia, ib, da, db} 1096// 1097def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> { 1098 let EncoderMethod = "getLdStmModeOpValue"; 1099 let PrintMethod = "printLdStmModeOperand"; 1100} 1101 1102// addrmode5 := reg +/- imm8*4 1103// 1104def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; } 1105class AddrMode5 : MemOperand, 1106 ComplexPattern<i32, 2, "SelectAddrMode5", []> { 1107 let EncoderMethod = "getAddrMode5OpValue"; 1108 let DecoderMethod = "DecodeAddrMode5Operand"; 1109 let ParserMatchClass = AddrMode5AsmOperand; 1110 let MIOperandInfo = (ops GPR:$base, i32imm); 1111} 1112 1113def addrmode5 : AddrMode5 { 1114 let PrintMethod = "printAddrMode5Operand<false>"; 1115} 1116 1117def addrmode5_pre : AddrMode5 { 1118 let PrintMethod = "printAddrMode5Operand<true>"; 1119} 1120 1121// addrmode5fp16 := reg +/- imm8*2 1122// 1123def AddrMode5FP16AsmOperand : AsmOperandClass { let Name = "AddrMode5FP16"; } 1124class AddrMode5FP16 : Operand<i32>, 1125 ComplexPattern<i32, 2, "SelectAddrMode5FP16", []> { 1126 let EncoderMethod = "getAddrMode5FP16OpValue"; 1127 let DecoderMethod = "DecodeAddrMode5FP16Operand"; 1128 let ParserMatchClass = AddrMode5FP16AsmOperand; 1129 let MIOperandInfo = (ops GPR:$base, i32imm); 1130} 1131 1132def addrmode5fp16 : AddrMode5FP16 { 1133 let PrintMethod = "printAddrMode5FP16Operand<false>"; 1134} 1135 1136// addrmode6 := reg with optional alignment 1137// 1138def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; } 1139def addrmode6 : MemOperand, 1140 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1141 let PrintMethod = "printAddrMode6Operand"; 1142 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1143 let EncoderMethod = "getAddrMode6AddressOpValue"; 1144 let DecoderMethod = "DecodeAddrMode6Operand"; 1145 let ParserMatchClass = AddrMode6AsmOperand; 1146} 1147 1148def am6offset : MemOperand, 1149 ComplexPattern<i32, 1, "SelectAddrMode6Offset", 1150 [], [SDNPWantRoot]> { 1151 let PrintMethod = "printAddrMode6OffsetOperand"; 1152 let MIOperandInfo = (ops GPR); 1153 let EncoderMethod = "getAddrMode6OffsetOpValue"; 1154 let DecoderMethod = "DecodeGPRRegisterClass"; 1155} 1156 1157// Special version of addrmode6 to handle alignment encoding for VST1/VLD1 1158// (single element from one lane) for size 32. 1159def addrmode6oneL32 : MemOperand, 1160 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1161 let PrintMethod = "printAddrMode6Operand"; 1162 let MIOperandInfo = (ops GPR:$addr, i32imm); 1163 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue"; 1164} 1165 1166// Base class for addrmode6 with specific alignment restrictions. 1167class AddrMode6Align : MemOperand, 1168 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1169 let PrintMethod = "printAddrMode6Operand"; 1170 let MIOperandInfo = (ops GPR:$addr, i32imm:$align); 1171 let EncoderMethod = "getAddrMode6AddressOpValue"; 1172 let DecoderMethod = "DecodeAddrMode6Operand"; 1173} 1174 1175// Special version of addrmode6 to handle no allowed alignment encoding for 1176// VLD/VST instructions and checking the alignment is not specified. 1177def AddrMode6AlignNoneAsmOperand : AsmOperandClass { 1178 let Name = "AlignedMemoryNone"; 1179 let DiagnosticString = "alignment must be omitted"; 1180} 1181def addrmode6alignNone : AddrMode6Align { 1182 // The alignment specifier can only be omitted. 1183 let ParserMatchClass = AddrMode6AlignNoneAsmOperand; 1184} 1185 1186// Special version of addrmode6 to handle 16-bit alignment encoding for 1187// VLD/VST instructions and checking the alignment value. 1188def AddrMode6Align16AsmOperand : AsmOperandClass { 1189 let Name = "AlignedMemory16"; 1190 let DiagnosticString = "alignment must be 16 or omitted"; 1191} 1192def addrmode6align16 : AddrMode6Align { 1193 // The alignment specifier can only be 16 or omitted. 1194 let ParserMatchClass = AddrMode6Align16AsmOperand; 1195} 1196 1197// Special version of addrmode6 to handle 32-bit alignment encoding for 1198// VLD/VST instructions and checking the alignment value. 1199def AddrMode6Align32AsmOperand : AsmOperandClass { 1200 let Name = "AlignedMemory32"; 1201 let DiagnosticString = "alignment must be 32 or omitted"; 1202} 1203def addrmode6align32 : AddrMode6Align { 1204 // The alignment specifier can only be 32 or omitted. 1205 let ParserMatchClass = AddrMode6Align32AsmOperand; 1206} 1207 1208// Special version of addrmode6 to handle 64-bit alignment encoding for 1209// VLD/VST instructions and checking the alignment value. 1210def AddrMode6Align64AsmOperand : AsmOperandClass { 1211 let Name = "AlignedMemory64"; 1212 let DiagnosticString = "alignment must be 64 or omitted"; 1213} 1214def addrmode6align64 : AddrMode6Align { 1215 // The alignment specifier can only be 64 or omitted. 1216 let ParserMatchClass = AddrMode6Align64AsmOperand; 1217} 1218 1219// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1220// for VLD/VST instructions and checking the alignment value. 1221def AddrMode6Align64or128AsmOperand : AsmOperandClass { 1222 let Name = "AlignedMemory64or128"; 1223 let DiagnosticString = "alignment must be 64, 128 or omitted"; 1224} 1225def addrmode6align64or128 : AddrMode6Align { 1226 // The alignment specifier can only be 64, 128 or omitted. 1227 let ParserMatchClass = AddrMode6Align64or128AsmOperand; 1228} 1229 1230// Special version of addrmode6 to handle 64-bit, 128-bit or 256-bit alignment 1231// encoding for VLD/VST instructions and checking the alignment value. 1232def AddrMode6Align64or128or256AsmOperand : AsmOperandClass { 1233 let Name = "AlignedMemory64or128or256"; 1234 let DiagnosticString = "alignment must be 64, 128, 256 or omitted"; 1235} 1236def addrmode6align64or128or256 : AddrMode6Align { 1237 // The alignment specifier can only be 64, 128, 256 or omitted. 1238 let ParserMatchClass = AddrMode6Align64or128or256AsmOperand; 1239} 1240 1241// Special version of addrmode6 to handle alignment encoding for VLD-dup 1242// instructions, specifically VLD4-dup. 1243def addrmode6dup : MemOperand, 1244 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1245 let PrintMethod = "printAddrMode6Operand"; 1246 let MIOperandInfo = (ops GPR:$addr, i32imm); 1247 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1248 // FIXME: This is close, but not quite right. The alignment specifier is 1249 // different. 1250 let ParserMatchClass = AddrMode6AsmOperand; 1251} 1252 1253// Base class for addrmode6dup with specific alignment restrictions. 1254class AddrMode6DupAlign : MemOperand, 1255 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ 1256 let PrintMethod = "printAddrMode6Operand"; 1257 let MIOperandInfo = (ops GPR:$addr, i32imm); 1258 let EncoderMethod = "getAddrMode6DupAddressOpValue"; 1259} 1260 1261// Special version of addrmode6 to handle no allowed alignment encoding for 1262// VLD-dup instruction and checking the alignment is not specified. 1263def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass { 1264 let Name = "DupAlignedMemoryNone"; 1265 let DiagnosticString = "alignment must be omitted"; 1266} 1267def addrmode6dupalignNone : AddrMode6DupAlign { 1268 // The alignment specifier can only be omitted. 1269 let ParserMatchClass = AddrMode6dupAlignNoneAsmOperand; 1270} 1271 1272// Special version of addrmode6 to handle 16-bit alignment encoding for VLD-dup 1273// instruction and checking the alignment value. 1274def AddrMode6dupAlign16AsmOperand : AsmOperandClass { 1275 let Name = "DupAlignedMemory16"; 1276 let DiagnosticString = "alignment must be 16 or omitted"; 1277} 1278def addrmode6dupalign16 : AddrMode6DupAlign { 1279 // The alignment specifier can only be 16 or omitted. 1280 let ParserMatchClass = AddrMode6dupAlign16AsmOperand; 1281} 1282 1283// Special version of addrmode6 to handle 32-bit alignment encoding for VLD-dup 1284// instruction and checking the alignment value. 1285def AddrMode6dupAlign32AsmOperand : AsmOperandClass { 1286 let Name = "DupAlignedMemory32"; 1287 let DiagnosticString = "alignment must be 32 or omitted"; 1288} 1289def addrmode6dupalign32 : AddrMode6DupAlign { 1290 // The alignment specifier can only be 32 or omitted. 1291 let ParserMatchClass = AddrMode6dupAlign32AsmOperand; 1292} 1293 1294// Special version of addrmode6 to handle 64-bit alignment encoding for VLD 1295// instructions and checking the alignment value. 1296def AddrMode6dupAlign64AsmOperand : AsmOperandClass { 1297 let Name = "DupAlignedMemory64"; 1298 let DiagnosticString = "alignment must be 64 or omitted"; 1299} 1300def addrmode6dupalign64 : AddrMode6DupAlign { 1301 // The alignment specifier can only be 64 or omitted. 1302 let ParserMatchClass = AddrMode6dupAlign64AsmOperand; 1303} 1304 1305// Special version of addrmode6 to handle 64-bit or 128-bit alignment encoding 1306// for VLD instructions and checking the alignment value. 1307def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass { 1308 let Name = "DupAlignedMemory64or128"; 1309 let DiagnosticString = "alignment must be 64, 128 or omitted"; 1310} 1311def addrmode6dupalign64or128 : AddrMode6DupAlign { 1312 // The alignment specifier can only be 64, 128 or omitted. 1313 let ParserMatchClass = AddrMode6dupAlign64or128AsmOperand; 1314} 1315 1316// addrmodepc := pc + reg 1317// 1318def addrmodepc : MemOperand, 1319 ComplexPattern<i32, 2, "SelectAddrModePC", []> { 1320 let PrintMethod = "printAddrModePCOperand"; 1321 let MIOperandInfo = (ops GPR, i32imm); 1322} 1323 1324// addr_offset_none := reg 1325// 1326def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; } 1327def addr_offset_none : MemOperand, 1328 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> { 1329 let PrintMethod = "printAddrMode7Operand"; 1330 let DecoderMethod = "DecodeAddrMode7Operand"; 1331 let ParserMatchClass = MemNoOffsetAsmOperand; 1332 let MIOperandInfo = (ops GPR:$base); 1333} 1334 1335def nohash_imm : Operand<i32> { 1336 let PrintMethod = "printNoHashImmediate"; 1337} 1338 1339def CoprocNumAsmOperand : AsmOperandClass { 1340 let Name = "CoprocNum"; 1341 let ParserMethod = "parseCoprocNumOperand"; 1342} 1343def p_imm : Operand<i32> { 1344 let PrintMethod = "printPImmediate"; 1345 let ParserMatchClass = CoprocNumAsmOperand; 1346 let DecoderMethod = "DecodeCoprocessor"; 1347} 1348 1349def CoprocRegAsmOperand : AsmOperandClass { 1350 let Name = "CoprocReg"; 1351 let ParserMethod = "parseCoprocRegOperand"; 1352} 1353def c_imm : Operand<i32> { 1354 let PrintMethod = "printCImmediate"; 1355 let ParserMatchClass = CoprocRegAsmOperand; 1356} 1357def CoprocOptionAsmOperand : AsmOperandClass { 1358 let Name = "CoprocOption"; 1359 let ParserMethod = "parseCoprocOptionOperand"; 1360} 1361def coproc_option_imm : Operand<i32> { 1362 let PrintMethod = "printCoprocOptionImm"; 1363 let ParserMatchClass = CoprocOptionAsmOperand; 1364} 1365 1366//===----------------------------------------------------------------------===// 1367 1368include "ARMInstrFormats.td" 1369 1370//===----------------------------------------------------------------------===// 1371// Multiclass helpers... 1372// 1373 1374/// AsI1_bin_irs - Defines a set of (op r, {mod_imm|r|so_reg}) patterns for a 1375/// binop that produces a value. 1376let TwoOperandAliasConstraint = "$Rn = $Rd" in 1377multiclass AsI1_bin_irs<bits<4> opcod, string opc, 1378 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1379 SDPatternOperator opnode, bit Commutable = 0> { 1380 // The register-immediate version is re-materializable. This is useful 1381 // in particular for taking the address of a local. 1382 let isReMaterializable = 1 in { 1383 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1384 iii, opc, "\t$Rd, $Rn, $imm", 1385 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>, 1386 Sched<[WriteALU, ReadALU]> { 1387 bits<4> Rd; 1388 bits<4> Rn; 1389 bits<12> imm; 1390 let Inst{25} = 1; 1391 let Inst{19-16} = Rn; 1392 let Inst{15-12} = Rd; 1393 let Inst{11-0} = imm; 1394 } 1395 } 1396 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1397 iir, opc, "\t$Rd, $Rn, $Rm", 1398 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>, 1399 Sched<[WriteALU, ReadALU, ReadALU]> { 1400 bits<4> Rd; 1401 bits<4> Rn; 1402 bits<4> Rm; 1403 let Inst{25} = 0; 1404 let isCommutable = Commutable; 1405 let Inst{19-16} = Rn; 1406 let Inst{15-12} = Rd; 1407 let Inst{11-4} = 0b00000000; 1408 let Inst{3-0} = Rm; 1409 } 1410 1411 def rsi : AsI1<opcod, (outs GPR:$Rd), 1412 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1413 iis, opc, "\t$Rd, $Rn, $shift", 1414 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>, 1415 Sched<[WriteALUsi, ReadALU]> { 1416 bits<4> Rd; 1417 bits<4> Rn; 1418 bits<12> shift; 1419 let Inst{25} = 0; 1420 let Inst{19-16} = Rn; 1421 let Inst{15-12} = Rd; 1422 let Inst{11-5} = shift{11-5}; 1423 let Inst{4} = 0; 1424 let Inst{3-0} = shift{3-0}; 1425 } 1426 1427 def rsr : AsI1<opcod, (outs GPR:$Rd), 1428 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1429 iis, opc, "\t$Rd, $Rn, $shift", 1430 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>, 1431 Sched<[WriteALUsr, ReadALUsr]> { 1432 bits<4> Rd; 1433 bits<4> Rn; 1434 bits<12> shift; 1435 let Inst{25} = 0; 1436 let Inst{19-16} = Rn; 1437 let Inst{15-12} = Rd; 1438 let Inst{11-8} = shift{11-8}; 1439 let Inst{7} = 0; 1440 let Inst{6-5} = shift{6-5}; 1441 let Inst{4} = 1; 1442 let Inst{3-0} = shift{3-0}; 1443 } 1444} 1445 1446/// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are 1447/// reversed. The 'rr' form is only defined for the disassembler; for codegen 1448/// it is equivalent to the AsI1_bin_irs counterpart. 1449let TwoOperandAliasConstraint = "$Rn = $Rd" in 1450multiclass AsI1_rbin_irs<bits<4> opcod, string opc, 1451 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1452 SDNode opnode, bit Commutable = 0> { 1453 // The register-immediate version is re-materializable. This is useful 1454 // in particular for taking the address of a local. 1455 let isReMaterializable = 1 in { 1456 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm, 1457 iii, opc, "\t$Rd, $Rn, $imm", 1458 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>, 1459 Sched<[WriteALU, ReadALU]> { 1460 bits<4> Rd; 1461 bits<4> Rn; 1462 bits<12> imm; 1463 let Inst{25} = 1; 1464 let Inst{19-16} = Rn; 1465 let Inst{15-12} = Rd; 1466 let Inst{11-0} = imm; 1467 } 1468 } 1469 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, 1470 iir, opc, "\t$Rd, $Rn, $Rm", 1471 [/* pattern left blank */]>, 1472 Sched<[WriteALU, ReadALU, ReadALU]> { 1473 bits<4> Rd; 1474 bits<4> Rn; 1475 bits<4> Rm; 1476 let Inst{11-4} = 0b00000000; 1477 let Inst{25} = 0; 1478 let Inst{3-0} = Rm; 1479 let Inst{15-12} = Rd; 1480 let Inst{19-16} = Rn; 1481 } 1482 1483 def rsi : AsI1<opcod, (outs GPR:$Rd), 1484 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, 1485 iis, opc, "\t$Rd, $Rn, $shift", 1486 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>, 1487 Sched<[WriteALUsi, ReadALU]> { 1488 bits<4> Rd; 1489 bits<4> Rn; 1490 bits<12> shift; 1491 let Inst{25} = 0; 1492 let Inst{19-16} = Rn; 1493 let Inst{15-12} = Rd; 1494 let Inst{11-5} = shift{11-5}; 1495 let Inst{4} = 0; 1496 let Inst{3-0} = shift{3-0}; 1497 } 1498 1499 def rsr : AsI1<opcod, (outs GPR:$Rd), 1500 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, 1501 iis, opc, "\t$Rd, $Rn, $shift", 1502 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>, 1503 Sched<[WriteALUsr, ReadALUsr]> { 1504 bits<4> Rd; 1505 bits<4> Rn; 1506 bits<12> shift; 1507 let Inst{25} = 0; 1508 let Inst{19-16} = Rn; 1509 let Inst{15-12} = Rd; 1510 let Inst{11-8} = shift{11-8}; 1511 let Inst{7} = 0; 1512 let Inst{6-5} = shift{6-5}; 1513 let Inst{4} = 1; 1514 let Inst{3-0} = shift{3-0}; 1515 } 1516} 1517 1518/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default. 1519/// 1520/// These opcodes will be converted to the real non-S opcodes by 1521/// AdjustInstrPostInstrSelection after giving them an optional CPSR operand. 1522let hasPostISelHook = 1, Defs = [CPSR] in { 1523multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir, 1524 InstrItinClass iis, SDNode opnode, 1525 bit Commutable = 0> { 1526 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1527 4, iii, 1528 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>, 1529 Sched<[WriteALU, ReadALU]>; 1530 1531 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p), 1532 4, iir, 1533 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>, 1534 Sched<[WriteALU, ReadALU, ReadALU]> { 1535 let isCommutable = Commutable; 1536 } 1537 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1538 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1539 4, iis, 1540 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1541 so_reg_imm:$shift))]>, 1542 Sched<[WriteALUsi, ReadALU]>; 1543 1544 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1545 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1546 4, iis, 1547 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, 1548 so_reg_reg:$shift))]>, 1549 Sched<[WriteALUSsr, ReadALUsr]>; 1550} 1551} 1552 1553/// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG 1554/// operands are reversed. 1555let hasPostISelHook = 1, Defs = [CPSR] in { 1556multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir, 1557 InstrItinClass iis, SDNode opnode, 1558 bit Commutable = 0> { 1559 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p), 1560 4, iii, 1561 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>, 1562 Sched<[WriteALU, ReadALU]>; 1563 1564 def rsi : ARMPseudoInst<(outs GPR:$Rd), 1565 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p), 1566 4, iis, 1567 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, 1568 GPR:$Rn))]>, 1569 Sched<[WriteALUsi, ReadALU]>; 1570 1571 def rsr : ARMPseudoInst<(outs GPR:$Rd), 1572 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p), 1573 4, iis, 1574 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, 1575 GPR:$Rn))]>, 1576 Sched<[WriteALUSsr, ReadALUsr]>; 1577} 1578} 1579 1580/// AI1_cmp_irs - Defines a set of (op r, {mod_imm|r|so_reg}) cmp / test 1581/// patterns. Similar to AsI1_bin_irs except the instruction does not produce 1582/// a explicit result, only implicitly set CPSR. 1583let isCompare = 1, Defs = [CPSR] in { 1584multiclass AI1_cmp_irs<bits<4> opcod, string opc, 1585 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 1586 SDPatternOperator opnode, bit Commutable = 0, 1587 string rrDecoderMethod = ""> { 1588 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii, 1589 opc, "\t$Rn, $imm", 1590 [(opnode GPR:$Rn, mod_imm:$imm)]>, 1591 Sched<[WriteCMP, ReadALU]> { 1592 bits<4> Rn; 1593 bits<12> imm; 1594 let Inst{25} = 1; 1595 let Inst{20} = 1; 1596 let Inst{19-16} = Rn; 1597 let Inst{15-12} = 0b0000; 1598 let Inst{11-0} = imm; 1599 1600 let Unpredictable{15-12} = 0b1111; 1601 } 1602 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir, 1603 opc, "\t$Rn, $Rm", 1604 [(opnode GPR:$Rn, GPR:$Rm)]>, 1605 Sched<[WriteCMP, ReadALU, ReadALU]> { 1606 bits<4> Rn; 1607 bits<4> Rm; 1608 let isCommutable = Commutable; 1609 let Inst{25} = 0; 1610 let Inst{20} = 1; 1611 let Inst{19-16} = Rn; 1612 let Inst{15-12} = 0b0000; 1613 let Inst{11-4} = 0b00000000; 1614 let Inst{3-0} = Rm; 1615 let DecoderMethod = rrDecoderMethod; 1616 1617 let Unpredictable{15-12} = 0b1111; 1618 } 1619 def rsi : AI1<opcod, (outs), 1620 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis, 1621 opc, "\t$Rn, $shift", 1622 [(opnode GPR:$Rn, so_reg_imm:$shift)]>, 1623 Sched<[WriteCMPsi, ReadALU]> { 1624 bits<4> Rn; 1625 bits<12> shift; 1626 let Inst{25} = 0; 1627 let Inst{20} = 1; 1628 let Inst{19-16} = Rn; 1629 let Inst{15-12} = 0b0000; 1630 let Inst{11-5} = shift{11-5}; 1631 let Inst{4} = 0; 1632 let Inst{3-0} = shift{3-0}; 1633 1634 let Unpredictable{15-12} = 0b1111; 1635 } 1636 def rsr : AI1<opcod, (outs), 1637 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis, 1638 opc, "\t$Rn, $shift", 1639 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>, 1640 Sched<[WriteCMPsr, ReadALU]> { 1641 bits<4> Rn; 1642 bits<12> shift; 1643 let Inst{25} = 0; 1644 let Inst{20} = 1; 1645 let Inst{19-16} = Rn; 1646 let Inst{15-12} = 0b0000; 1647 let Inst{11-8} = shift{11-8}; 1648 let Inst{7} = 0; 1649 let Inst{6-5} = shift{6-5}; 1650 let Inst{4} = 1; 1651 let Inst{3-0} = shift{3-0}; 1652 1653 let Unpredictable{15-12} = 0b1111; 1654 } 1655 1656} 1657} 1658 1659/// AI_ext_rrot - A unary operation with two forms: one whose operand is a 1660/// register and one whose operand is a register rotated by 8/16/24. 1661/// FIXME: Remove the 'r' variant. Its rot_imm is zero. 1662class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> 1663 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1664 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", 1665 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1666 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1667 bits<4> Rd; 1668 bits<4> Rm; 1669 bits<2> rot; 1670 let Inst{19-16} = 0b1111; 1671 let Inst{15-12} = Rd; 1672 let Inst{11-10} = rot; 1673 let Inst{3-0} = Rm; 1674} 1675 1676class AI_ext_rrot_np<bits<8> opcod, string opc> 1677 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot), 1678 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>, 1679 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> { 1680 bits<2> rot; 1681 let Inst{19-16} = 0b1111; 1682 let Inst{11-10} = rot; 1683 } 1684 1685/// AI_exta_rrot - A binary operation with two forms: one whose operand is a 1686/// register and one whose operand is a register rotated by 8/16/24. 1687class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> 1688 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1689 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", 1690 [(set GPRnopc:$Rd, (opnode GPR:$Rn, 1691 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>, 1692 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1693 bits<4> Rd; 1694 bits<4> Rm; 1695 bits<4> Rn; 1696 bits<2> rot; 1697 let Inst{19-16} = Rn; 1698 let Inst{15-12} = Rd; 1699 let Inst{11-10} = rot; 1700 let Inst{9-4} = 0b000111; 1701 let Inst{3-0} = Rm; 1702} 1703 1704class AI_exta_rrot_np<bits<8> opcod, string opc> 1705 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot), 1706 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>, 1707 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> { 1708 bits<4> Rn; 1709 bits<2> rot; 1710 let Inst{19-16} = Rn; 1711 let Inst{11-10} = rot; 1712} 1713 1714/// AI1_adde_sube_irs - Define instructions and patterns for adde and sube. 1715let TwoOperandAliasConstraint = "$Rn = $Rd" in 1716multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode, 1717 bit Commutable = 0> { 1718 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1719 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1720 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1721 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>, 1722 Requires<[IsARM]>, 1723 Sched<[WriteALU, ReadALU]> { 1724 bits<4> Rd; 1725 bits<4> Rn; 1726 bits<12> imm; 1727 let Inst{25} = 1; 1728 let Inst{15-12} = Rd; 1729 let Inst{19-16} = Rn; 1730 let Inst{11-0} = imm; 1731 } 1732 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1733 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1734 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>, 1735 Requires<[IsARM]>, 1736 Sched<[WriteALU, ReadALU, ReadALU]> { 1737 bits<4> Rd; 1738 bits<4> Rn; 1739 bits<4> Rm; 1740 let Inst{11-4} = 0b00000000; 1741 let Inst{25} = 0; 1742 let isCommutable = Commutable; 1743 let Inst{3-0} = Rm; 1744 let Inst{15-12} = Rd; 1745 let Inst{19-16} = Rn; 1746 } 1747 def rsi : AsI1<opcod, (outs GPR:$Rd), 1748 (ins GPR:$Rn, so_reg_imm:$shift), 1749 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1750 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>, 1751 Requires<[IsARM]>, 1752 Sched<[WriteALUsi, ReadALU]> { 1753 bits<4> Rd; 1754 bits<4> Rn; 1755 bits<12> shift; 1756 let Inst{25} = 0; 1757 let Inst{19-16} = Rn; 1758 let Inst{15-12} = Rd; 1759 let Inst{11-5} = shift{11-5}; 1760 let Inst{4} = 0; 1761 let Inst{3-0} = shift{3-0}; 1762 } 1763 def rsr : AsI1<opcod, (outs GPRnopc:$Rd), 1764 (ins GPRnopc:$Rn, so_reg_reg:$shift), 1765 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1766 [(set GPRnopc:$Rd, CPSR, 1767 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>, 1768 Requires<[IsARM]>, 1769 Sched<[WriteALUsr, ReadALUsr]> { 1770 bits<4> Rd; 1771 bits<4> Rn; 1772 bits<12> shift; 1773 let Inst{25} = 0; 1774 let Inst{19-16} = Rn; 1775 let Inst{15-12} = Rd; 1776 let Inst{11-8} = shift{11-8}; 1777 let Inst{7} = 0; 1778 let Inst{6-5} = shift{6-5}; 1779 let Inst{4} = 1; 1780 let Inst{3-0} = shift{3-0}; 1781 } 1782 } 1783} 1784 1785/// AI1_rsc_irs - Define instructions and patterns for rsc 1786let TwoOperandAliasConstraint = "$Rn = $Rd" in 1787multiclass AI1_rsc_irs<bits<4> opcod, string opc, SDNode opnode> { 1788 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in { 1789 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), 1790 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 1791 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>, 1792 Requires<[IsARM]>, 1793 Sched<[WriteALU, ReadALU]> { 1794 bits<4> Rd; 1795 bits<4> Rn; 1796 bits<12> imm; 1797 let Inst{25} = 1; 1798 let Inst{15-12} = Rd; 1799 let Inst{19-16} = Rn; 1800 let Inst{11-0} = imm; 1801 } 1802 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1803 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm", 1804 [/* pattern left blank */]>, 1805 Sched<[WriteALU, ReadALU, ReadALU]> { 1806 bits<4> Rd; 1807 bits<4> Rn; 1808 bits<4> Rm; 1809 let Inst{11-4} = 0b00000000; 1810 let Inst{25} = 0; 1811 let Inst{3-0} = Rm; 1812 let Inst{15-12} = Rd; 1813 let Inst{19-16} = Rn; 1814 } 1815 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift), 1816 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1817 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>, 1818 Requires<[IsARM]>, 1819 Sched<[WriteALUsi, ReadALU]> { 1820 bits<4> Rd; 1821 bits<4> Rn; 1822 bits<12> shift; 1823 let Inst{25} = 0; 1824 let Inst{19-16} = Rn; 1825 let Inst{15-12} = Rd; 1826 let Inst{11-5} = shift{11-5}; 1827 let Inst{4} = 0; 1828 let Inst{3-0} = shift{3-0}; 1829 } 1830 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift), 1831 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift", 1832 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>, 1833 Requires<[IsARM]>, 1834 Sched<[WriteALUsr, ReadALUsr]> { 1835 bits<4> Rd; 1836 bits<4> Rn; 1837 bits<12> shift; 1838 let Inst{25} = 0; 1839 let Inst{19-16} = Rn; 1840 let Inst{15-12} = Rd; 1841 let Inst{11-8} = shift{11-8}; 1842 let Inst{7} = 0; 1843 let Inst{6-5} = shift{6-5}; 1844 let Inst{4} = 1; 1845 let Inst{3-0} = shift{3-0}; 1846 } 1847 } 1848} 1849 1850let canFoldAsLoad = 1, isReMaterializable = 1 in { 1851multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii, 1852 InstrItinClass iir, PatFrag opnode> { 1853 // Note: We use the complex addrmode_imm12 rather than just an input 1854 // GPR and a constrained immediate so that we can use this to match 1855 // frame index references and avoid matching constant pool references. 1856 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 1857 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1858 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> { 1859 bits<4> Rt; 1860 bits<17> addr; 1861 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1862 let Inst{19-16} = addr{16-13}; // Rn 1863 let Inst{15-12} = Rt; 1864 let Inst{11-0} = addr{11-0}; // imm12 1865 } 1866 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift), 1867 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1868 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> { 1869 bits<4> Rt; 1870 bits<17> shift; 1871 let shift{4} = 0; // Inst{4} = 0 1872 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1873 let Inst{19-16} = shift{16-13}; // Rn 1874 let Inst{15-12} = Rt; 1875 let Inst{11-0} = shift{11-0}; 1876 } 1877} 1878} 1879 1880let canFoldAsLoad = 1, isReMaterializable = 1 in { 1881multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii, 1882 InstrItinClass iir, PatFrag opnode> { 1883 // Note: We use the complex addrmode_imm12 rather than just an input 1884 // GPR and a constrained immediate so that we can use this to match 1885 // frame index references and avoid matching constant pool references. 1886 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), 1887 (ins addrmode_imm12:$addr), 1888 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr", 1889 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> { 1890 bits<4> Rt; 1891 bits<17> addr; 1892 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1893 let Inst{19-16} = addr{16-13}; // Rn 1894 let Inst{15-12} = Rt; 1895 let Inst{11-0} = addr{11-0}; // imm12 1896 } 1897 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), 1898 (ins ldst_so_reg:$shift), 1899 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift", 1900 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> { 1901 bits<4> Rt; 1902 bits<17> shift; 1903 let shift{4} = 0; // Inst{4} = 0 1904 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1905 let Inst{19-16} = shift{16-13}; // Rn 1906 let Inst{15-12} = Rt; 1907 let Inst{11-0} = shift{11-0}; 1908 } 1909} 1910} 1911 1912 1913multiclass AI_str1<bit isByte, string opc, InstrItinClass iii, 1914 InstrItinClass iir, PatFrag opnode> { 1915 // Note: We use the complex addrmode_imm12 rather than just an input 1916 // GPR and a constrained immediate so that we can use this to match 1917 // frame index references and avoid matching constant pool references. 1918 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1919 (ins GPR:$Rt, addrmode_imm12:$addr), 1920 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1921 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> { 1922 bits<4> Rt; 1923 bits<17> addr; 1924 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1925 let Inst{19-16} = addr{16-13}; // Rn 1926 let Inst{15-12} = Rt; 1927 let Inst{11-0} = addr{11-0}; // imm12 1928 } 1929 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift), 1930 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1931 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> { 1932 bits<4> Rt; 1933 bits<17> shift; 1934 let shift{4} = 0; // Inst{4} = 0 1935 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1936 let Inst{19-16} = shift{16-13}; // Rn 1937 let Inst{15-12} = Rt; 1938 let Inst{11-0} = shift{11-0}; 1939 } 1940} 1941 1942multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii, 1943 InstrItinClass iir, PatFrag opnode> { 1944 // Note: We use the complex addrmode_imm12 rather than just an input 1945 // GPR and a constrained immediate so that we can use this to match 1946 // frame index references and avoid matching constant pool references. 1947 def i12 : AI2ldst<0b010, 0, isByte, (outs), 1948 (ins GPRnopc:$Rt, addrmode_imm12:$addr), 1949 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr", 1950 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> { 1951 bits<4> Rt; 1952 bits<17> addr; 1953 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 1954 let Inst{19-16} = addr{16-13}; // Rn 1955 let Inst{15-12} = Rt; 1956 let Inst{11-0} = addr{11-0}; // imm12 1957 } 1958 def rs : AI2ldst<0b011, 0, isByte, (outs), 1959 (ins GPRnopc:$Rt, ldst_so_reg:$shift), 1960 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift", 1961 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> { 1962 bits<4> Rt; 1963 bits<17> shift; 1964 let shift{4} = 0; // Inst{4} = 0 1965 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 1966 let Inst{19-16} = shift{16-13}; // Rn 1967 let Inst{15-12} = Rt; 1968 let Inst{11-0} = shift{11-0}; 1969 } 1970} 1971 1972 1973//===----------------------------------------------------------------------===// 1974// Instructions 1975//===----------------------------------------------------------------------===// 1976 1977//===----------------------------------------------------------------------===// 1978// Miscellaneous Instructions. 1979// 1980 1981/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in 1982/// the function. The first operand is the ID# for this instruction, the second 1983/// is the index into the MachineConstantPool that this is, the third is the 1984/// size in bytes of this constant pool entry. 1985let hasSideEffects = 0, isNotDuplicable = 1 in 1986def CONSTPOOL_ENTRY : 1987PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1988 i32imm:$size), NoItinerary, []>; 1989 1990/// A jumptable consisting of direct 32-bit addresses of the destination basic 1991/// blocks (either absolute, or relative to the start of the jump-table in PIC 1992/// mode). Used mostly in ARM and Thumb-1 modes. 1993def JUMPTABLE_ADDRS : 1994PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 1995 i32imm:$size), NoItinerary, []>; 1996 1997/// A jumptable consisting of 32-bit jump instructions. Used for Thumb-2 tables 1998/// that cannot be optimised to use TBB or TBH. 1999def JUMPTABLE_INSTS : 2000PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 2001 i32imm:$size), NoItinerary, []>; 2002 2003/// A jumptable consisting of 8-bit unsigned integers representing offsets from 2004/// a TBB instruction. 2005def JUMPTABLE_TBB : 2006PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 2007 i32imm:$size), NoItinerary, []>; 2008 2009/// A jumptable consisting of 16-bit unsigned integers representing offsets from 2010/// a TBH instruction. 2011def JUMPTABLE_TBH : 2012PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx, 2013 i32imm:$size), NoItinerary, []>; 2014 2015 2016// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 2017// from removing one half of the matched pairs. That breaks PEI, which assumes 2018// these will always be in pairs, and asserts if it finds otherwise. Better way? 2019let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 2020def ADJCALLSTACKUP : 2021PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary, 2022 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>; 2023 2024def ADJCALLSTACKDOWN : 2025PseudoInst<(outs), (ins i32imm:$amt, i32imm:$amt2, pred:$p), NoItinerary, 2026 [(ARMcallseq_start timm:$amt, timm:$amt2)]>; 2027} 2028 2029def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary, 2030 "hint", "\t$imm", [(int_arm_hint imm0_239:$imm)]>, 2031 Requires<[IsARM, HasV6]> { 2032 bits<8> imm; 2033 let Inst{27-8} = 0b00110010000011110000; 2034 let Inst{7-0} = imm; 2035 let DecoderMethod = "DecodeHINTInstruction"; 2036} 2037 2038def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6K]>; 2039def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6K]>; 2040def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6K]>; 2041def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6K]>; 2042def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6K]>; 2043def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>; 2044def : InstAlias<"esb$p", (HINT 16, pred:$p)>, Requires<[IsARM, HasRAS]>; 2045def : InstAlias<"csdb$p", (HINT 20, pred:$p)>, Requires<[IsARM, HasV6K]>; 2046 2047def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel", 2048 "\t$Rd, $Rn, $Rm", 2049 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>, 2050 Requires<[IsARM, HasV6]> { 2051 bits<4> Rd; 2052 bits<4> Rn; 2053 bits<4> Rm; 2054 let Inst{3-0} = Rm; 2055 let Inst{15-12} = Rd; 2056 let Inst{19-16} = Rn; 2057 let Inst{27-20} = 0b01101000; 2058 let Inst{7-4} = 0b1011; 2059 let Inst{11-8} = 0b1111; 2060 let Unpredictable{11-8} = 0b1111; 2061} 2062 2063// The 16-bit operand $val can be used by a debugger to store more information 2064// about the breakpoint. 2065def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 2066 "bkpt", "\t$val", []>, Requires<[IsARM]> { 2067 bits<16> val; 2068 let Inst{3-0} = val{3-0}; 2069 let Inst{19-8} = val{15-4}; 2070 let Inst{27-20} = 0b00010010; 2071 let Inst{31-28} = 0xe; // AL 2072 let Inst{7-4} = 0b0111; 2073} 2074// default immediate for breakpoint mnemonic 2075def : InstAlias<"bkpt", (BKPT 0), 0>, Requires<[IsARM]>; 2076 2077def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary, 2078 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> { 2079 bits<16> val; 2080 let Inst{3-0} = val{3-0}; 2081 let Inst{19-8} = val{15-4}; 2082 let Inst{27-20} = 0b00010000; 2083 let Inst{31-28} = 0xe; // AL 2084 let Inst{7-4} = 0b0111; 2085} 2086 2087// Change Processor State 2088// FIXME: We should use InstAlias to handle the optional operands. 2089class CPS<dag iops, string asm_ops> 2090 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops), 2091 []>, Requires<[IsARM]> { 2092 bits<2> imod; 2093 bits<3> iflags; 2094 bits<5> mode; 2095 bit M; 2096 2097 let Inst{31-28} = 0b1111; 2098 let Inst{27-20} = 0b00010000; 2099 let Inst{19-18} = imod; 2100 let Inst{17} = M; // Enabled if mode is set; 2101 let Inst{16-9} = 0b00000000; 2102 let Inst{8-6} = iflags; 2103 let Inst{5} = 0; 2104 let Inst{4-0} = mode; 2105} 2106 2107let DecoderMethod = "DecodeCPSInstruction" in { 2108let M = 1 in 2109 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode), 2110 "$imod\t$iflags, $mode">; 2111let mode = 0, M = 0 in 2112 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">; 2113 2114let imod = 0, iflags = 0, M = 1 in 2115 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">; 2116} 2117 2118// Preload signals the memory system of possible future data/instruction access. 2119multiclass APreLoad<bits<1> read, bits<1> data, string opc> { 2120 2121 def i12 : AXIM<(outs), (ins addrmode_imm12:$addr), AddrMode_i12, MiscFrm, 2122 IIC_Preload, !strconcat(opc, "\t$addr"), 2123 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>, 2124 Sched<[WritePreLd]> { 2125 bits<4> Rt; 2126 bits<17> addr; 2127 let Inst{31-26} = 0b111101; 2128 let Inst{25} = 0; // 0 for immediate form 2129 let Inst{24} = data; 2130 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2131 let Inst{22} = read; 2132 let Inst{21-20} = 0b01; 2133 let Inst{19-16} = addr{16-13}; // Rn 2134 let Inst{15-12} = 0b1111; 2135 let Inst{11-0} = addr{11-0}; // imm12 2136 } 2137 2138 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload, 2139 !strconcat(opc, "\t$shift"), 2140 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>, 2141 Sched<[WritePreLd]> { 2142 bits<17> shift; 2143 let Inst{31-26} = 0b111101; 2144 let Inst{25} = 1; // 1 for register form 2145 let Inst{24} = data; 2146 let Inst{23} = shift{12}; // U (add = ('U' == 1)) 2147 let Inst{22} = read; 2148 let Inst{21-20} = 0b01; 2149 let Inst{19-16} = shift{16-13}; // Rn 2150 let Inst{15-12} = 0b1111; 2151 let Inst{11-0} = shift{11-0}; 2152 let Inst{4} = 0; 2153 } 2154} 2155 2156defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>; 2157defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>; 2158defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>; 2159 2160def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary, 2161 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> { 2162 bits<1> end; 2163 let Inst{31-10} = 0b1111000100000001000000; 2164 let Inst{9} = end; 2165 let Inst{8-0} = 0; 2166} 2167 2168def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", 2169 [(int_arm_dbg imm0_15:$opt)]>, Requires<[IsARM, HasV7]> { 2170 bits<4> opt; 2171 let Inst{27-4} = 0b001100100000111100001111; 2172 let Inst{3-0} = opt; 2173} 2174 2175// A8.8.247 UDF - Undefined (Encoding A1) 2176def UDF : AInoP<(outs), (ins imm0_65535:$imm16), MiscFrm, NoItinerary, 2177 "udf", "\t$imm16", [(int_arm_undefined imm0_65535:$imm16)]> { 2178 bits<16> imm16; 2179 let Inst{31-28} = 0b1110; // AL 2180 let Inst{27-25} = 0b011; 2181 let Inst{24-20} = 0b11111; 2182 let Inst{19-8} = imm16{15-4}; 2183 let Inst{7-4} = 0b1111; 2184 let Inst{3-0} = imm16{3-0}; 2185} 2186 2187/* 2188 * A5.4 Permanently UNDEFINED instructions. 2189 * 2190 * For most targets use UDF #65006, for which the OS will generate SIGTRAP. 2191 * Other UDF encodings generate SIGILL. 2192 * 2193 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb. 2194 * Encoding A1: 2195 * 1110 0111 1111 iiii iiii iiii 1111 iiii 2196 * Encoding T1: 2197 * 1101 1110 iiii iiii 2198 * It uses the following encoding: 2199 * 1110 0111 1111 1110 1101 1110 1111 0000 2200 * - In ARM: UDF #60896; 2201 * - In Thumb: UDF #254 followed by a branch-to-self. 2202 */ 2203let isBarrier = 1, isTerminator = 1 in 2204def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary, 2205 "trap", [(trap)]>, 2206 Requires<[IsARM,UseNaClTrap]> { 2207 let Inst = 0xe7fedef0; 2208} 2209let isBarrier = 1, isTerminator = 1 in 2210def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, 2211 "trap", [(trap)]>, 2212 Requires<[IsARM,DontUseNaClTrap]> { 2213 let Inst = 0xe7ffdefe; 2214} 2215 2216def : Pat<(debugtrap), (BKPT 0)>, Requires<[IsARM, HasV5T]>; 2217def : Pat<(debugtrap), (UDF 254)>, Requires<[IsARM, NoV5T]>; 2218 2219// Address computation and loads and stores in PIC mode. 2220let isNotDuplicable = 1 in { 2221def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), 2222 4, IIC_iALUr, 2223 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>, 2224 Sched<[WriteALU, ReadALU]>; 2225 2226let AddedComplexity = 10 in { 2227def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), 2228 4, IIC_iLoad_r, 2229 [(set GPR:$dst, (load addrmodepc:$addr))]>; 2230 2231def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2232 4, IIC_iLoad_bh_r, 2233 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>; 2234 2235def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2236 4, IIC_iLoad_bh_r, 2237 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>; 2238 2239def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2240 4, IIC_iLoad_bh_r, 2241 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>; 2242 2243def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p), 2244 4, IIC_iLoad_bh_r, 2245 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>; 2246} 2247let AddedComplexity = 10 in { 2248def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2249 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>; 2250 2251def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2252 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, 2253 addrmodepc:$addr)]>; 2254 2255def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), 2256 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>; 2257} 2258} // isNotDuplicable = 1 2259 2260 2261// LEApcrel - Load a pc-relative address into a register without offending the 2262// assembler. 2263let hasSideEffects = 0, isReMaterializable = 1 in 2264// The 'adr' mnemonic encodes differently if the label is before or after 2265// the instruction. The {24-21} opcode bits are set by the fixup, as we don't 2266// know until then which form of the instruction will be used. 2267def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label), 2268 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>, 2269 Sched<[WriteALU, ReadALU]> { 2270 bits<4> Rd; 2271 bits<14> label; 2272 let Inst{27-25} = 0b001; 2273 let Inst{24} = 0; 2274 let Inst{23-22} = label{13-12}; 2275 let Inst{21} = 0; 2276 let Inst{20} = 0; 2277 let Inst{19-16} = 0b1111; 2278 let Inst{15-12} = Rd; 2279 let Inst{11-0} = label{11-0}; 2280} 2281 2282let hasSideEffects = 1 in { 2283def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p), 2284 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2285 2286def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd), 2287 (ins i32imm:$label, pred:$p), 2288 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 2289} 2290 2291//===----------------------------------------------------------------------===// 2292// Control Flow Instructions. 2293// 2294 2295let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 2296 // ARMV4T and above 2297 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2298 "bx", "\tlr", [(ARMretflag)]>, 2299 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2300 let Inst{27-0} = 0b0001001011111111111100011110; 2301 } 2302 2303 // ARMV4 only 2304 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br, 2305 "mov", "\tpc, lr", [(ARMretflag)]>, 2306 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> { 2307 let Inst{27-0} = 0b0001101000001111000000001110; 2308 } 2309 2310 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets 2311 // the user-space one). 2312 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p), 2313 4, IIC_Br, 2314 [(ARMintretflag imm:$offset)]>; 2315} 2316 2317// Indirect branches 2318let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 2319 // ARMV4T and above 2320 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst", 2321 [(brind GPR:$dst)]>, 2322 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2323 bits<4> dst; 2324 let Inst{31-4} = 0b1110000100101111111111110001; 2325 let Inst{3-0} = dst; 2326 } 2327 2328 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, 2329 "bx", "\t$dst", [/* pattern left blank */]>, 2330 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> { 2331 bits<4> dst; 2332 let Inst{27-4} = 0b000100101111111111110001; 2333 let Inst{3-0} = dst; 2334 } 2335} 2336 2337// SP is marked as a use to prevent stack-pointer assignments that appear 2338// immediately before calls from potentially appearing dead. 2339let isCall = 1, 2340 // FIXME: Do we really need a non-predicated version? If so, it should 2341 // at least be a pseudo instruction expanding to the predicated version 2342 // at MC lowering time. 2343 Defs = [LR], Uses = [SP] in { 2344 def BL : ABXI<0b1011, (outs), (ins arm_bl_target:$func), 2345 IIC_Br, "bl\t$func", 2346 [(ARMcall tglobaladdr:$func)]>, 2347 Requires<[IsARM]>, Sched<[WriteBrL]> { 2348 let Inst{31-28} = 0b1110; 2349 bits<24> func; 2350 let Inst{23-0} = func; 2351 let DecoderMethod = "DecodeBranchImmInstruction"; 2352 } 2353 2354 def BL_pred : ABI<0b1011, (outs), (ins arm_bl_target:$func), 2355 IIC_Br, "bl", "\t$func", 2356 [(ARMcall_pred tglobaladdr:$func)]>, 2357 Requires<[IsARM]>, Sched<[WriteBrL]> { 2358 bits<24> func; 2359 let Inst{23-0} = func; 2360 let DecoderMethod = "DecodeBranchImmInstruction"; 2361 } 2362 2363 // ARMv5T and above 2364 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm, 2365 IIC_Br, "blx\t$func", 2366 [(ARMcall GPR:$func)]>, 2367 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2368 bits<4> func; 2369 let Inst{31-4} = 0b1110000100101111111111110011; 2370 let Inst{3-0} = func; 2371 } 2372 2373 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm, 2374 IIC_Br, "blx", "\t$func", 2375 [(ARMcall_pred GPR:$func)]>, 2376 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2377 bits<4> func; 2378 let Inst{27-4} = 0b000100101111111111110011; 2379 let Inst{3-0} = func; 2380 } 2381 2382 // ARMv4T 2383 // Note: Restrict $func to the tGPR regclass to prevent it being in LR. 2384 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2385 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2386 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>; 2387 2388 // ARMv4 2389 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func), 2390 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>, 2391 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 2392 2393 // mov lr, pc; b if callee is marked noreturn to avoid confusing the 2394 // return stack predictor. 2395 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins arm_bl_target:$func), 2396 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>, 2397 Requires<[IsARM]>, Sched<[WriteBr]>; 2398} 2399 2400let isBranch = 1, isTerminator = 1 in { 2401 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 2402 // a two-value operand where a dag node expects two operands. :( 2403 def Bcc : ABI<0b1010, (outs), (ins arm_br_target:$target), 2404 IIC_Br, "b", "\t$target", 2405 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>, 2406 Sched<[WriteBr]> { 2407 bits<24> target; 2408 let Inst{23-0} = target; 2409 let DecoderMethod = "DecodeBranchImmInstruction"; 2410 } 2411 2412 let isBarrier = 1 in { 2413 // B is "predicable" since it's just a Bcc with an 'always' condition. 2414 let isPredicable = 1 in 2415 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly 2416 // should be sufficient. 2417 // FIXME: Is B really a Barrier? That doesn't seem right. 2418 def B : ARMPseudoExpand<(outs), (ins arm_br_target:$target), 4, IIC_Br, 2419 [(br bb:$target)], (Bcc arm_br_target:$target, 2420 (ops 14, zero_reg))>, 2421 Sched<[WriteBr]>; 2422 2423 let Size = 4, isNotDuplicable = 1, isIndirectBranch = 1 in { 2424 def BR_JTr : ARMPseudoInst<(outs), 2425 (ins GPR:$target, i32imm:$jt), 2426 0, IIC_Br, 2427 [(ARMbrjt GPR:$target, tjumptable:$jt)]>, 2428 Sched<[WriteBr]>; 2429 def BR_JTm_i12 : ARMPseudoInst<(outs), 2430 (ins addrmode_imm12:$target, i32imm:$jt), 2431 0, IIC_Br, 2432 [(ARMbrjt (i32 (load addrmode_imm12:$target)), 2433 tjumptable:$jt)]>, Sched<[WriteBrTbl]>; 2434 def BR_JTm_rs : ARMPseudoInst<(outs), 2435 (ins ldst_so_reg:$target, i32imm:$jt), 2436 0, IIC_Br, 2437 [(ARMbrjt (i32 (load ldst_so_reg:$target)), 2438 tjumptable:$jt)]>, Sched<[WriteBrTbl]>; 2439 def BR_JTadd : ARMPseudoInst<(outs), 2440 (ins GPR:$target, GPR:$idx, i32imm:$jt), 2441 0, IIC_Br, 2442 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt)]>, 2443 Sched<[WriteBrTbl]>; 2444 } // isNotDuplicable = 1, isIndirectBranch = 1 2445 } // isBarrier = 1 2446 2447} 2448 2449// BLX (immediate) 2450def BLXi : AXI<(outs), (ins arm_blx_target:$target), BrMiscFrm, NoItinerary, 2451 "blx\t$target", []>, 2452 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> { 2453 let Inst{31-25} = 0b1111101; 2454 bits<25> target; 2455 let Inst{23-0} = target{24-1}; 2456 let Inst{24} = target{0}; 2457 let isCall = 1; 2458} 2459 2460// Branch and Exchange Jazelle 2461def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func", 2462 [/* pattern left blank */]>, Sched<[WriteBr]> { 2463 bits<4> func; 2464 let Inst{23-20} = 0b0010; 2465 let Inst{19-8} = 0xfff; 2466 let Inst{7-4} = 0b0010; 2467 let Inst{3-0} = func; 2468 let isBranch = 1; 2469} 2470 2471// Tail calls. 2472 2473let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in { 2474 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>, 2475 Sched<[WriteBr]>; 2476 2477 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>, 2478 Sched<[WriteBr]>; 2479 2480 def TAILJMPd : ARMPseudoExpand<(outs), (ins arm_br_target:$dst), 2481 4, IIC_Br, [], 2482 (Bcc arm_br_target:$dst, (ops 14, zero_reg))>, 2483 Requires<[IsARM]>, Sched<[WriteBr]>; 2484 2485 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst), 2486 4, IIC_Br, [], 2487 (BX GPR:$dst)>, Sched<[WriteBr]>, 2488 Requires<[IsARM, HasV4T]>; 2489} 2490 2491// Secure Monitor Call is a system instruction. 2492def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", 2493 []>, Requires<[IsARM, HasTrustZone]> { 2494 bits<4> opt; 2495 let Inst{23-4} = 0b01100000000000000111; 2496 let Inst{3-0} = opt; 2497} 2498def : MnemonicAlias<"smi", "smc">; 2499 2500// Supervisor Call (Software Interrupt) 2501let isCall = 1, Uses = [SP] in { 2502def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>, 2503 Sched<[WriteBr]> { 2504 bits<24> svc; 2505 let Inst{23-0} = svc; 2506} 2507} 2508 2509// Store Return State 2510class SRSI<bit wb, string asm> 2511 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm, 2512 NoItinerary, asm, "", []> { 2513 bits<5> mode; 2514 let Inst{31-28} = 0b1111; 2515 let Inst{27-25} = 0b100; 2516 let Inst{22} = 1; 2517 let Inst{21} = wb; 2518 let Inst{20} = 0; 2519 let Inst{19-16} = 0b1101; // SP 2520 let Inst{15-5} = 0b00000101000; 2521 let Inst{4-0} = mode; 2522} 2523 2524def SRSDA : SRSI<0, "srsda\tsp, $mode"> { 2525 let Inst{24-23} = 0; 2526} 2527def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> { 2528 let Inst{24-23} = 0; 2529} 2530def SRSDB : SRSI<0, "srsdb\tsp, $mode"> { 2531 let Inst{24-23} = 0b10; 2532} 2533def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> { 2534 let Inst{24-23} = 0b10; 2535} 2536def SRSIA : SRSI<0, "srsia\tsp, $mode"> { 2537 let Inst{24-23} = 0b01; 2538} 2539def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> { 2540 let Inst{24-23} = 0b01; 2541} 2542def SRSIB : SRSI<0, "srsib\tsp, $mode"> { 2543 let Inst{24-23} = 0b11; 2544} 2545def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> { 2546 let Inst{24-23} = 0b11; 2547} 2548 2549def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>; 2550def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>; 2551 2552def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>; 2553def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>; 2554 2555def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>; 2556def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>; 2557 2558def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>; 2559def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>; 2560 2561// Return From Exception 2562class RFEI<bit wb, string asm> 2563 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm, 2564 NoItinerary, asm, "", []> { 2565 bits<4> Rn; 2566 let Inst{31-28} = 0b1111; 2567 let Inst{27-25} = 0b100; 2568 let Inst{22} = 0; 2569 let Inst{21} = wb; 2570 let Inst{20} = 1; 2571 let Inst{19-16} = Rn; 2572 let Inst{15-0} = 0xa00; 2573} 2574 2575def RFEDA : RFEI<0, "rfeda\t$Rn"> { 2576 let Inst{24-23} = 0; 2577} 2578def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> { 2579 let Inst{24-23} = 0; 2580} 2581def RFEDB : RFEI<0, "rfedb\t$Rn"> { 2582 let Inst{24-23} = 0b10; 2583} 2584def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> { 2585 let Inst{24-23} = 0b10; 2586} 2587def RFEIA : RFEI<0, "rfeia\t$Rn"> { 2588 let Inst{24-23} = 0b01; 2589} 2590def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> { 2591 let Inst{24-23} = 0b01; 2592} 2593def RFEIB : RFEI<0, "rfeib\t$Rn"> { 2594 let Inst{24-23} = 0b11; 2595} 2596def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> { 2597 let Inst{24-23} = 0b11; 2598} 2599 2600// Hypervisor Call is a system instruction 2601let isCall = 1 in { 2602def HVC : AInoP< (outs), (ins imm0_65535:$imm), BrFrm, NoItinerary, 2603 "hvc", "\t$imm", []>, 2604 Requires<[IsARM, HasVirtualization]> { 2605 bits<16> imm; 2606 2607 // Even though HVC isn't predicable, it's encoding includes a condition field. 2608 // The instruction is undefined if the condition field is 0xf otherwise it is 2609 // unpredictable if it isn't condition AL (0xe). 2610 let Inst{31-28} = 0b1110; 2611 let Unpredictable{31-28} = 0b1111; 2612 let Inst{27-24} = 0b0001; 2613 let Inst{23-20} = 0b0100; 2614 let Inst{19-8} = imm{15-4}; 2615 let Inst{7-4} = 0b0111; 2616 let Inst{3-0} = imm{3-0}; 2617} 2618} 2619 2620// Return from exception in Hypervisor mode. 2621let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in 2622def ERET : ABI<0b0001, (outs), (ins), NoItinerary, "eret", "", []>, 2623 Requires<[IsARM, HasVirtualization]> { 2624 let Inst{23-0} = 0b011000000000000001101110; 2625} 2626 2627//===----------------------------------------------------------------------===// 2628// Load / Store Instructions. 2629// 2630 2631// Load 2632 2633 2634defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si, load>; 2635defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si, 2636 zextloadi8>; 2637defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si, store>; 2638defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si, 2639 truncstorei8>; 2640 2641// Special LDR for loads from non-pc-relative constpools. 2642let canFoldAsLoad = 1, mayLoad = 1, hasSideEffects = 0, 2643 isReMaterializable = 1, isCodeGenOnly = 1 in 2644def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr), 2645 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", 2646 []> { 2647 bits<4> Rt; 2648 bits<17> addr; 2649 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2650 let Inst{19-16} = 0b1111; 2651 let Inst{15-12} = Rt; 2652 let Inst{11-0} = addr{11-0}; // imm12 2653} 2654 2655// Loads with zero extension 2656def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2657 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr", 2658 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>; 2659 2660// Loads with sign extension 2661def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2662 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr", 2663 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>; 2664 2665def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm, 2666 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr", 2667 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>; 2668 2669let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in { 2670 // Load doubleword 2671 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr), 2672 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>, 2673 Requires<[IsARM, HasV5TE]>; 2674} 2675 2676def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2677 NoItinerary, "lda", "\t$Rt, $addr", []>; 2678def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2679 NoItinerary, "ldab", "\t$Rt, $addr", []>; 2680def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 2681 NoItinerary, "ldah", "\t$Rt, $addr", []>; 2682 2683// Indexed loads 2684multiclass AI2_ldridx<bit isByte, string opc, 2685 InstrItinClass iii, InstrItinClass iir> { 2686 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2687 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii, 2688 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2689 bits<17> addr; 2690 let Inst{25} = 0; 2691 let Inst{23} = addr{12}; 2692 let Inst{19-16} = addr{16-13}; 2693 let Inst{11-0} = addr{11-0}; 2694 let DecoderMethod = "DecodeLDRPreImm"; 2695 } 2696 2697 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2698 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir, 2699 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2700 bits<17> addr; 2701 let Inst{25} = 1; 2702 let Inst{23} = addr{12}; 2703 let Inst{19-16} = addr{16-13}; 2704 let Inst{11-0} = addr{11-0}; 2705 let Inst{4} = 0; 2706 let DecoderMethod = "DecodeLDRPreReg"; 2707 } 2708 2709 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2710 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2711 IndexModePost, LdFrm, iir, 2712 opc, "\t$Rt, $addr, $offset", 2713 "$addr.base = $Rn_wb", []> { 2714 // {12} isAdd 2715 // {11-0} imm12/Rm 2716 bits<14> offset; 2717 bits<4> addr; 2718 let Inst{25} = 1; 2719 let Inst{23} = offset{12}; 2720 let Inst{19-16} = addr; 2721 let Inst{11-0} = offset{11-0}; 2722 let Inst{4} = 0; 2723 2724 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2725 } 2726 2727 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2728 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2729 IndexModePost, LdFrm, iii, 2730 opc, "\t$Rt, $addr, $offset", 2731 "$addr.base = $Rn_wb", []> { 2732 // {12} isAdd 2733 // {11-0} imm12/Rm 2734 bits<14> offset; 2735 bits<4> addr; 2736 let Inst{25} = 0; 2737 let Inst{23} = offset{12}; 2738 let Inst{19-16} = addr; 2739 let Inst{11-0} = offset{11-0}; 2740 2741 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2742 } 2743 2744} 2745 2746let mayLoad = 1, hasSideEffects = 0 in { 2747// FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or 2748// IIC_iLoad_siu depending on whether it the offset register is shifted. 2749defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>; 2750defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>; 2751} 2752 2753multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> { 2754 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 2755 (ins addrmode3_pre:$addr), IndexModePre, 2756 LdMiscFrm, itin, 2757 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { 2758 bits<14> addr; 2759 let Inst{23} = addr{8}; // U bit 2760 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2761 let Inst{19-16} = addr{12-9}; // Rn 2762 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2763 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2764 let DecoderMethod = "DecodeAddrMode3Instruction"; 2765 } 2766 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2767 (ins addr_offset_none:$addr, am3offset:$offset), 2768 IndexModePost, LdMiscFrm, itin, 2769 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", 2770 []> { 2771 bits<10> offset; 2772 bits<4> addr; 2773 let Inst{23} = offset{8}; // U bit 2774 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2775 let Inst{19-16} = addr; 2776 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2777 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2778 let DecoderMethod = "DecodeAddrMode3Instruction"; 2779 } 2780} 2781 2782let mayLoad = 1, hasSideEffects = 0 in { 2783defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>; 2784defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>; 2785defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>; 2786let hasExtraDefRegAllocReq = 1 in { 2787def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2788 (ins addrmode3_pre:$addr), IndexModePre, 2789 LdMiscFrm, IIC_iLoad_d_ru, 2790 "ldrd", "\t$Rt, $Rt2, $addr!", 2791 "$addr.base = $Rn_wb", []> { 2792 bits<14> addr; 2793 let Inst{23} = addr{8}; // U bit 2794 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 2795 let Inst{19-16} = addr{12-9}; // Rn 2796 let Inst{11-8} = addr{7-4}; // imm7_4/zero 2797 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 2798 let DecoderMethod = "DecodeAddrMode3Instruction"; 2799} 2800def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), 2801 (ins addr_offset_none:$addr, am3offset:$offset), 2802 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru, 2803 "ldrd", "\t$Rt, $Rt2, $addr, $offset", 2804 "$addr.base = $Rn_wb", []> { 2805 bits<10> offset; 2806 bits<4> addr; 2807 let Inst{23} = offset{8}; // U bit 2808 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 2809 let Inst{19-16} = addr; 2810 let Inst{11-8} = offset{7-4}; // imm7_4/zero 2811 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 2812 let DecoderMethod = "DecodeAddrMode3Instruction"; 2813} 2814} // hasExtraDefRegAllocReq = 1 2815} // mayLoad = 1, hasSideEffects = 0 2816 2817// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT. 2818let mayLoad = 1, hasSideEffects = 0 in { 2819def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2820 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2821 IndexModePost, LdFrm, IIC_iLoad_ru, 2822 "ldrt", "\t$Rt, $addr, $offset", 2823 "$addr.base = $Rn_wb", []> { 2824 // {12} isAdd 2825 // {11-0} imm12/Rm 2826 bits<14> offset; 2827 bits<4> addr; 2828 let Inst{25} = 1; 2829 let Inst{23} = offset{12}; 2830 let Inst{21} = 1; // overwrite 2831 let Inst{19-16} = addr; 2832 let Inst{11-5} = offset{11-5}; 2833 let Inst{4} = 0; 2834 let Inst{3-0} = offset{3-0}; 2835 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2836} 2837 2838def LDRT_POST_IMM 2839 : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2840 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2841 IndexModePost, LdFrm, IIC_iLoad_ru, 2842 "ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2843 // {12} isAdd 2844 // {11-0} imm12/Rm 2845 bits<14> offset; 2846 bits<4> addr; 2847 let Inst{25} = 0; 2848 let Inst{23} = offset{12}; 2849 let Inst{21} = 1; // overwrite 2850 let Inst{19-16} = addr; 2851 let Inst{11-0} = offset{11-0}; 2852 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2853} 2854 2855def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2856 (ins addr_offset_none:$addr, am2offset_reg:$offset), 2857 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2858 "ldrbt", "\t$Rt, $addr, $offset", 2859 "$addr.base = $Rn_wb", []> { 2860 // {12} isAdd 2861 // {11-0} imm12/Rm 2862 bits<14> offset; 2863 bits<4> addr; 2864 let Inst{25} = 1; 2865 let Inst{23} = offset{12}; 2866 let Inst{21} = 1; // overwrite 2867 let Inst{19-16} = addr; 2868 let Inst{11-5} = offset{11-5}; 2869 let Inst{4} = 0; 2870 let Inst{3-0} = offset{3-0}; 2871 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2872} 2873 2874def LDRBT_POST_IMM 2875 : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 2876 (ins addr_offset_none:$addr, am2offset_imm:$offset), 2877 IndexModePost, LdFrm, IIC_iLoad_bh_ru, 2878 "ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 2879 // {12} isAdd 2880 // {11-0} imm12/Rm 2881 bits<14> offset; 2882 bits<4> addr; 2883 let Inst{25} = 0; 2884 let Inst{23} = offset{12}; 2885 let Inst{21} = 1; // overwrite 2886 let Inst{19-16} = addr; 2887 let Inst{11-0} = offset{11-0}; 2888 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2889} 2890 2891multiclass AI3ldrT<bits<4> op, string opc> { 2892 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb), 2893 (ins addr_offset_none:$addr, postidx_imm8:$offset), 2894 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2895 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 2896 bits<9> offset; 2897 let Inst{23} = offset{8}; 2898 let Inst{22} = 1; 2899 let Inst{11-8} = offset{7-4}; 2900 let Inst{3-0} = offset{3-0}; 2901 } 2902 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb), 2903 (ins addr_offset_none:$addr, postidx_reg:$Rm), 2904 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc, 2905 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 2906 bits<5> Rm; 2907 let Inst{23} = Rm{4}; 2908 let Inst{22} = 0; 2909 let Inst{11-8} = 0; 2910 let Unpredictable{11-8} = 0b1111; 2911 let Inst{3-0} = Rm{3-0}; 2912 let DecoderMethod = "DecodeLDR"; 2913 } 2914} 2915 2916defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">; 2917defm LDRHT : AI3ldrT<0b1011, "ldrht">; 2918defm LDRSHT : AI3ldrT<0b1111, "ldrsht">; 2919} 2920 2921def LDRT_POST 2922 : ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2923 (outs GPR:$Rt)>; 2924 2925def LDRBT_POST 2926 : ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q), 2927 (outs GPR:$Rt)>; 2928 2929// Pseudo instruction ldr Rt, =immediate 2930def LDRConstPool 2931 : ARMAsmPseudo<"ldr${q} $Rt, $immediate", 2932 (ins const_pool_asm_imm:$immediate, pred:$q), 2933 (outs GPR:$Rt)>; 2934 2935// Store 2936 2937// Stores with truncate 2938def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm, 2939 IIC_iStore_bh_r, "strh", "\t$Rt, $addr", 2940 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>; 2941 2942// Store doubleword 2943let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 2944 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr), 2945 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>, 2946 Requires<[IsARM, HasV5TE]> { 2947 let Inst{21} = 0; 2948 } 2949} 2950 2951// Indexed stores 2952multiclass AI2_stridx<bit isByte, string opc, 2953 InstrItinClass iii, InstrItinClass iir> { 2954 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2955 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre, 2956 StFrm, iii, 2957 opc, "\t$Rt, $addr!", 2958 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2959 bits<17> addr; 2960 let Inst{25} = 0; 2961 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2962 let Inst{19-16} = addr{16-13}; // Rn 2963 let Inst{11-0} = addr{11-0}; // imm12 2964 let DecoderMethod = "DecodeSTRPreImm"; 2965 } 2966 2967 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb), 2968 (ins GPR:$Rt, ldst_so_reg:$addr), 2969 IndexModePre, StFrm, iir, 2970 opc, "\t$Rt, $addr!", 2971 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2972 bits<17> addr; 2973 let Inst{25} = 1; 2974 let Inst{23} = addr{12}; // U (add = ('U' == 1)) 2975 let Inst{19-16} = addr{16-13}; // Rn 2976 let Inst{11-0} = addr{11-0}; 2977 let Inst{4} = 0; // Inst{4} = 0 2978 let DecoderMethod = "DecodeSTRPreReg"; 2979 } 2980 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2981 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 2982 IndexModePost, StFrm, iir, 2983 opc, "\t$Rt, $addr, $offset", 2984 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 2985 // {12} isAdd 2986 // {11-0} imm12/Rm 2987 bits<14> offset; 2988 bits<4> addr; 2989 let Inst{25} = 1; 2990 let Inst{23} = offset{12}; 2991 let Inst{19-16} = addr; 2992 let Inst{11-0} = offset{11-0}; 2993 let Inst{4} = 0; 2994 2995 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 2996 } 2997 2998 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb), 2999 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3000 IndexModePost, StFrm, iii, 3001 opc, "\t$Rt, $addr, $offset", 3002 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3003 // {12} isAdd 3004 // {11-0} imm12/Rm 3005 bits<14> offset; 3006 bits<4> addr; 3007 let Inst{25} = 0; 3008 let Inst{23} = offset{12}; 3009 let Inst{19-16} = addr; 3010 let Inst{11-0} = offset{11-0}; 3011 3012 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3013 } 3014} 3015 3016let mayStore = 1, hasSideEffects = 0 in { 3017// FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or 3018// IIC_iStore_siu depending on whether it the offset register is shifted. 3019defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>; 3020defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>; 3021} 3022 3023def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 3024 am2offset_reg:$offset), 3025 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr, 3026 am2offset_reg:$offset)>; 3027def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr, 3028 am2offset_imm:$offset), 3029 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr, 3030 am2offset_imm:$offset)>; 3031def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 3032 am2offset_reg:$offset), 3033 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr, 3034 am2offset_reg:$offset)>; 3035def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr, 3036 am2offset_imm:$offset), 3037 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr, 3038 am2offset_imm:$offset)>; 3039 3040// Pseudo-instructions for pattern matching the pre-indexed stores. We can't 3041// put the patterns on the instruction definitions directly as ISel wants 3042// the address base and offset to be separate operands, not a single 3043// complex operand like we represent the instructions themselves. The 3044// pseudos map between the two. 3045let usesCustomInserter = 1, 3046 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in { 3047def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3048 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 3049 4, IIC_iStore_ru, 3050 [(set GPR:$Rn_wb, 3051 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 3052def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3053 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 3054 4, IIC_iStore_ru, 3055 [(set GPR:$Rn_wb, 3056 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 3057def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3058 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p), 3059 4, IIC_iStore_ru, 3060 [(set GPR:$Rn_wb, 3061 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>; 3062def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3063 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p), 3064 4, IIC_iStore_ru, 3065 [(set GPR:$Rn_wb, 3066 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>; 3067def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb), 3068 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p), 3069 4, IIC_iStore_ru, 3070 [(set GPR:$Rn_wb, 3071 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>; 3072} 3073 3074 3075 3076def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb), 3077 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre, 3078 StMiscFrm, IIC_iStore_bh_ru, 3079 "strh", "\t$Rt, $addr!", 3080 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 3081 bits<14> addr; 3082 let Inst{23} = addr{8}; // U bit 3083 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 3084 let Inst{19-16} = addr{12-9}; // Rn 3085 let Inst{11-8} = addr{7-4}; // imm7_4/zero 3086 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 3087 let DecoderMethod = "DecodeAddrMode3Instruction"; 3088} 3089 3090def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb), 3091 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset), 3092 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, 3093 "strh", "\t$Rt, $addr, $offset", 3094 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", 3095 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt, 3096 addr_offset_none:$addr, 3097 am3offset:$offset))]> { 3098 bits<10> offset; 3099 bits<4> addr; 3100 let Inst{23} = offset{8}; // U bit 3101 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 3102 let Inst{19-16} = addr; 3103 let Inst{11-8} = offset{7-4}; // imm7_4/zero 3104 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 3105 let DecoderMethod = "DecodeAddrMode3Instruction"; 3106} 3107 3108let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in { 3109def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb), 3110 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr), 3111 IndexModePre, StMiscFrm, IIC_iStore_d_ru, 3112 "strd", "\t$Rt, $Rt2, $addr!", 3113 "$addr.base = $Rn_wb", []> { 3114 bits<14> addr; 3115 let Inst{23} = addr{8}; // U bit 3116 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm 3117 let Inst{19-16} = addr{12-9}; // Rn 3118 let Inst{11-8} = addr{7-4}; // imm7_4/zero 3119 let Inst{3-0} = addr{3-0}; // imm3_0/Rm 3120 let DecoderMethod = "DecodeAddrMode3Instruction"; 3121} 3122 3123def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb), 3124 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr, 3125 am3offset:$offset), 3126 IndexModePost, StMiscFrm, IIC_iStore_d_ru, 3127 "strd", "\t$Rt, $Rt2, $addr, $offset", 3128 "$addr.base = $Rn_wb", []> { 3129 bits<10> offset; 3130 bits<4> addr; 3131 let Inst{23} = offset{8}; // U bit 3132 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm 3133 let Inst{19-16} = addr; 3134 let Inst{11-8} = offset{7-4}; // imm7_4/zero 3135 let Inst{3-0} = offset{3-0}; // imm3_0/Rm 3136 let DecoderMethod = "DecodeAddrMode3Instruction"; 3137} 3138} // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 3139 3140// STRT, STRBT, and STRHT 3141 3142def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3143 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3144 IndexModePost, StFrm, IIC_iStore_bh_ru, 3145 "strbt", "\t$Rt, $addr, $offset", 3146 "$addr.base = $Rn_wb", []> { 3147 // {12} isAdd 3148 // {11-0} imm12/Rm 3149 bits<14> offset; 3150 bits<4> addr; 3151 let Inst{25} = 1; 3152 let Inst{23} = offset{12}; 3153 let Inst{21} = 1; // overwrite 3154 let Inst{19-16} = addr; 3155 let Inst{11-5} = offset{11-5}; 3156 let Inst{4} = 0; 3157 let Inst{3-0} = offset{3-0}; 3158 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3159} 3160 3161def STRBT_POST_IMM 3162 : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), 3163 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3164 IndexModePost, StFrm, IIC_iStore_bh_ru, 3165 "strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3166 // {12} isAdd 3167 // {11-0} imm12/Rm 3168 bits<14> offset; 3169 bits<4> addr; 3170 let Inst{25} = 0; 3171 let Inst{23} = offset{12}; 3172 let Inst{21} = 1; // overwrite 3173 let Inst{19-16} = addr; 3174 let Inst{11-0} = offset{11-0}; 3175 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3176} 3177 3178def STRBT_POST 3179 : ARMAsmPseudo<"strbt${q} $Rt, $addr", 3180 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3181 3182let mayStore = 1, hasSideEffects = 0 in { 3183def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3184 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset), 3185 IndexModePost, StFrm, IIC_iStore_ru, 3186 "strt", "\t$Rt, $addr, $offset", 3187 "$addr.base = $Rn_wb", []> { 3188 // {12} isAdd 3189 // {11-0} imm12/Rm 3190 bits<14> offset; 3191 bits<4> addr; 3192 let Inst{25} = 1; 3193 let Inst{23} = offset{12}; 3194 let Inst{21} = 1; // overwrite 3195 let Inst{19-16} = addr; 3196 let Inst{11-5} = offset{11-5}; 3197 let Inst{4} = 0; 3198 let Inst{3-0} = offset{3-0}; 3199 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3200} 3201 3202def STRT_POST_IMM 3203 : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), 3204 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset), 3205 IndexModePost, StFrm, IIC_iStore_ru, 3206 "strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> { 3207 // {12} isAdd 3208 // {11-0} imm12/Rm 3209 bits<14> offset; 3210 bits<4> addr; 3211 let Inst{25} = 0; 3212 let Inst{23} = offset{12}; 3213 let Inst{21} = 1; // overwrite 3214 let Inst{19-16} = addr; 3215 let Inst{11-0} = offset{11-0}; 3216 let DecoderMethod = "DecodeAddrMode2IdxInstruction"; 3217} 3218} 3219 3220def STRT_POST 3221 : ARMAsmPseudo<"strt${q} $Rt, $addr", 3222 (ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>; 3223 3224multiclass AI3strT<bits<4> op, string opc> { 3225 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3226 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset), 3227 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3228 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> { 3229 bits<9> offset; 3230 let Inst{23} = offset{8}; 3231 let Inst{22} = 1; 3232 let Inst{11-8} = offset{7-4}; 3233 let Inst{3-0} = offset{3-0}; 3234 } 3235 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb), 3236 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm), 3237 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc, 3238 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> { 3239 bits<5> Rm; 3240 let Inst{23} = Rm{4}; 3241 let Inst{22} = 0; 3242 let Inst{11-8} = 0; 3243 let Inst{3-0} = Rm{3-0}; 3244 } 3245} 3246 3247 3248defm STRHT : AI3strT<0b1011, "strht">; 3249 3250def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3251 NoItinerary, "stl", "\t$Rt, $addr", []>; 3252def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3253 NoItinerary, "stlb", "\t$Rt, $addr", []>; 3254def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr), 3255 NoItinerary, "stlh", "\t$Rt, $addr", []>; 3256 3257//===----------------------------------------------------------------------===// 3258// Load / store multiple Instructions. 3259// 3260 3261multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f, 3262 InstrItinClass itin, InstrItinClass itin_upd> { 3263 // IA is the default, so no need for an explicit suffix on the 3264 // mnemonic here. Without it is the canonical spelling. 3265 def IA : 3266 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3267 IndexModeNone, f, itin, 3268 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> { 3269 let Inst{24-23} = 0b01; // Increment After 3270 let Inst{22} = P_bit; 3271 let Inst{21} = 0; // No writeback 3272 let Inst{20} = L_bit; 3273 } 3274 def IA_UPD : 3275 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3276 IndexModeUpd, f, itin_upd, 3277 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3278 let Inst{24-23} = 0b01; // Increment After 3279 let Inst{22} = P_bit; 3280 let Inst{21} = 1; // Writeback 3281 let Inst{20} = L_bit; 3282 3283 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3284 } 3285 def DA : 3286 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3287 IndexModeNone, f, itin, 3288 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> { 3289 let Inst{24-23} = 0b00; // Decrement After 3290 let Inst{22} = P_bit; 3291 let Inst{21} = 0; // No writeback 3292 let Inst{20} = L_bit; 3293 } 3294 def DA_UPD : 3295 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3296 IndexModeUpd, f, itin_upd, 3297 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3298 let Inst{24-23} = 0b00; // Decrement After 3299 let Inst{22} = P_bit; 3300 let Inst{21} = 1; // Writeback 3301 let Inst{20} = L_bit; 3302 3303 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3304 } 3305 def DB : 3306 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3307 IndexModeNone, f, itin, 3308 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> { 3309 let Inst{24-23} = 0b10; // Decrement Before 3310 let Inst{22} = P_bit; 3311 let Inst{21} = 0; // No writeback 3312 let Inst{20} = L_bit; 3313 } 3314 def DB_UPD : 3315 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3316 IndexModeUpd, f, itin_upd, 3317 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3318 let Inst{24-23} = 0b10; // Decrement Before 3319 let Inst{22} = P_bit; 3320 let Inst{21} = 1; // Writeback 3321 let Inst{20} = L_bit; 3322 3323 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3324 } 3325 def IB : 3326 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3327 IndexModeNone, f, itin, 3328 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> { 3329 let Inst{24-23} = 0b11; // Increment Before 3330 let Inst{22} = P_bit; 3331 let Inst{21} = 0; // No writeback 3332 let Inst{20} = L_bit; 3333 } 3334 def IB_UPD : 3335 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 3336 IndexModeUpd, f, itin_upd, 3337 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> { 3338 let Inst{24-23} = 0b11; // Increment Before 3339 let Inst{22} = P_bit; 3340 let Inst{21} = 1; // Writeback 3341 let Inst{20} = L_bit; 3342 3343 let DecoderMethod = "DecodeMemMultipleWritebackInstruction"; 3344 } 3345} 3346 3347let hasSideEffects = 0 in { 3348 3349let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in 3350defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m, 3351 IIC_iLoad_mu>, ComplexDeprecationPredicate<"ARMLoad">; 3352 3353let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3354defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m, 3355 IIC_iStore_mu>, 3356 ComplexDeprecationPredicate<"ARMStore">; 3357 3358} // hasSideEffects 3359 3360// FIXME: remove when we have a way to marking a MI with these properties. 3361// FIXME: Should pc be an implicit operand like PICADD, etc? 3362let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 3363 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in 3364def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, 3365 reglist:$regs, variable_ops), 3366 4, IIC_iLoad_mBr, [], 3367 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, 3368 RegConstraint<"$Rn = $wb">; 3369 3370let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 3371defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m, 3372 IIC_iLoad_mu>; 3373 3374let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 3375defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m, 3376 IIC_iStore_mu>; 3377 3378 3379 3380//===----------------------------------------------------------------------===// 3381// Move Instructions. 3382// 3383 3384let hasSideEffects = 0, isMoveReg = 1 in 3385def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr, 3386 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3387 bits<4> Rd; 3388 bits<4> Rm; 3389 3390 let Inst{19-16} = 0b0000; 3391 let Inst{11-4} = 0b00000000; 3392 let Inst{25} = 0; 3393 let Inst{3-0} = Rm; 3394 let Inst{15-12} = Rd; 3395} 3396 3397// A version for the smaller set of tail call registers. 3398let hasSideEffects = 0 in 3399def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm, 3400 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> { 3401 bits<4> Rd; 3402 bits<4> Rm; 3403 3404 let Inst{11-4} = 0b00000000; 3405 let Inst{25} = 0; 3406 let Inst{3-0} = Rm; 3407 let Inst{15-12} = Rd; 3408} 3409 3410def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src), 3411 DPSoRegRegFrm, IIC_iMOVsr, 3412 "mov", "\t$Rd, $src", 3413 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP, 3414 Sched<[WriteALU]> { 3415 bits<4> Rd; 3416 bits<12> src; 3417 let Inst{15-12} = Rd; 3418 let Inst{19-16} = 0b0000; 3419 let Inst{11-8} = src{11-8}; 3420 let Inst{7} = 0; 3421 let Inst{6-5} = src{6-5}; 3422 let Inst{4} = 1; 3423 let Inst{3-0} = src{3-0}; 3424 let Inst{25} = 0; 3425} 3426 3427def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src), 3428 DPSoRegImmFrm, IIC_iMOVsr, 3429 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>, 3430 UnaryDP, Sched<[WriteALU]> { 3431 bits<4> Rd; 3432 bits<12> src; 3433 let Inst{15-12} = Rd; 3434 let Inst{19-16} = 0b0000; 3435 let Inst{11-5} = src{11-5}; 3436 let Inst{4} = 0; 3437 let Inst{3-0} = src{3-0}; 3438 let Inst{25} = 0; 3439} 3440 3441let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3442def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi, 3443 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP, 3444 Sched<[WriteALU]> { 3445 bits<4> Rd; 3446 bits<12> imm; 3447 let Inst{25} = 1; 3448 let Inst{15-12} = Rd; 3449 let Inst{19-16} = 0b0000; 3450 let Inst{11-0} = imm; 3451} 3452 3453let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 3454def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm), 3455 DPFrm, IIC_iMOVi, 3456 "movw", "\t$Rd, $imm", 3457 [(set GPR:$Rd, imm0_65535:$imm)]>, 3458 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> { 3459 bits<4> Rd; 3460 bits<16> imm; 3461 let Inst{15-12} = Rd; 3462 let Inst{11-0} = imm{11-0}; 3463 let Inst{19-16} = imm{15-12}; 3464 let Inst{20} = 0; 3465 let Inst{25} = 1; 3466 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3467} 3468 3469def : InstAlias<"mov${p} $Rd, $imm", 3470 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p), 0>, 3471 Requires<[IsARM, HasV6T2]>; 3472 3473def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3474 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3475 Sched<[WriteALU]>; 3476 3477let Constraints = "$src = $Rd" in { 3478def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd), 3479 (ins GPR:$src, imm0_65535_expr:$imm), 3480 DPFrm, IIC_iMOVi, 3481 "movt", "\t$Rd, $imm", 3482 [(set GPRnopc:$Rd, 3483 (or (and GPR:$src, 0xffff), 3484 lo16AllZero:$imm))]>, UnaryDP, 3485 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> { 3486 bits<4> Rd; 3487 bits<16> imm; 3488 let Inst{15-12} = Rd; 3489 let Inst{11-0} = imm{11-0}; 3490 let Inst{19-16} = imm{15-12}; 3491 let Inst{20} = 0; 3492 let Inst{25} = 1; 3493 let DecoderMethod = "DecodeArmMOVTWInstruction"; 3494} 3495 3496def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd), 3497 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 3498 Sched<[WriteALU]>; 3499 3500} // Constraints 3501 3502def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>, 3503 Requires<[IsARM, HasV6T2]>; 3504 3505let Uses = [CPSR] in 3506def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi, 3507 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP, 3508 Requires<[IsARM]>, Sched<[WriteALU]>; 3509 3510// These aren't really mov instructions, but we have to define them this way 3511// due to flag operands. 3512 3513let Defs = [CPSR] in { 3514def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3515 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP, 3516 Sched<[WriteALU]>, Requires<[IsARM]>; 3517def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi, 3518 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP, 3519 Sched<[WriteALU]>, Requires<[IsARM]>; 3520} 3521 3522//===----------------------------------------------------------------------===// 3523// Extend Instructions. 3524// 3525 3526// Sign extenders 3527 3528def SXTB : AI_ext_rrot<0b01101010, 3529 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; 3530def SXTH : AI_ext_rrot<0b01101011, 3531 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; 3532 3533def SXTAB : AI_exta_rrot<0b01101010, 3534 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 3535def SXTAH : AI_exta_rrot<0b01101011, 3536 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 3537 3538def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, rot_imm:$rot), i8)), 3539 (SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3540def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, imm8_or_16:$rot), 3541 i16)), 3542 (SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3543 3544def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">; 3545def : ARMV6Pat<(int_arm_sxtb16 GPR:$Src), 3546 (SXTB16 GPR:$Src, 0)>; 3547def : ARMV6Pat<(int_arm_sxtb16 (rotr GPR:$Src, rot_imm:$rot)), 3548 (SXTB16 GPR:$Src, rot_imm:$rot)>; 3549 3550def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">; 3551def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, GPR:$RHS), 3552 (SXTAB16 GPR:$LHS, GPR:$RHS, 0)>; 3553def : ARMV6Pat<(int_arm_sxtab16 GPR:$LHS, (rotr GPR:$RHS, rot_imm:$rot)), 3554 (SXTAB16 GPR:$LHS, GPR:$RHS, rot_imm:$rot)>; 3555 3556// Zero extenders 3557 3558let AddedComplexity = 16 in { 3559def UXTB : AI_ext_rrot<0b01101110, 3560 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; 3561def UXTH : AI_ext_rrot<0b01101111, 3562 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 3563def UXTB16 : AI_ext_rrot<0b01101100, 3564 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 3565 3566// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 3567// The transformation should probably be done as a combiner action 3568// instead so we can include a check for masking back in the upper 3569// eight bits of the source into the lower eight bits of the result. 3570//def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF), 3571// (UXTB16r_rot GPR:$Src, 3)>; 3572def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF), 3573 (UXTB16 GPR:$Src, 1)>; 3574def : ARMV6Pat<(int_arm_uxtb16 GPR:$Src), 3575 (UXTB16 GPR:$Src, 0)>; 3576def : ARMV6Pat<(int_arm_uxtb16 (rotr GPR:$Src, rot_imm:$rot)), 3577 (UXTB16 GPR:$Src, rot_imm:$rot)>; 3578 3579def UXTAB : AI_exta_rrot<0b01101110, "uxtab", 3580 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 3581def UXTAH : AI_exta_rrot<0b01101111, "uxtah", 3582 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 3583 3584def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 0xFF)), 3585 (UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3586def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 0xFFFF)), 3587 (UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 3588} 3589 3590// This isn't safe in general, the add is two 16-bit units, not a 32-bit add. 3591def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">; 3592def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, GPR:$RHS), 3593 (UXTAB16 GPR:$LHS, GPR:$RHS, 0)>; 3594def : ARMV6Pat<(int_arm_uxtab16 GPR:$LHS, (rotr GPR:$RHS, rot_imm:$rot)), 3595 (UXTAB16 GPR:$LHS, GPR:$RHS, rot_imm:$rot)>; 3596 3597 3598def SBFX : I<(outs GPRnopc:$Rd), 3599 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3600 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3601 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3602 Requires<[IsARM, HasV6T2]> { 3603 bits<4> Rd; 3604 bits<4> Rn; 3605 bits<5> lsb; 3606 bits<5> width; 3607 let Inst{27-21} = 0b0111101; 3608 let Inst{6-4} = 0b101; 3609 let Inst{20-16} = width; 3610 let Inst{15-12} = Rd; 3611 let Inst{11-7} = lsb; 3612 let Inst{3-0} = Rn; 3613} 3614 3615def UBFX : I<(outs GPRnopc:$Rd), 3616 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width), 3617 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3618 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>, 3619 Requires<[IsARM, HasV6T2]> { 3620 bits<4> Rd; 3621 bits<4> Rn; 3622 bits<5> lsb; 3623 bits<5> width; 3624 let Inst{27-21} = 0b0111111; 3625 let Inst{6-4} = 0b101; 3626 let Inst{20-16} = width; 3627 let Inst{15-12} = Rd; 3628 let Inst{11-7} = lsb; 3629 let Inst{3-0} = Rn; 3630} 3631 3632//===----------------------------------------------------------------------===// 3633// Arithmetic Instructions. 3634// 3635 3636let isAdd = 1 in 3637defm ADD : AsI1_bin_irs<0b0100, "add", 3638 IIC_iALUi, IIC_iALUr, IIC_iALUsr, add, 1>; 3639defm SUB : AsI1_bin_irs<0b0010, "sub", 3640 IIC_iALUi, IIC_iALUr, IIC_iALUsr, sub>; 3641 3642// ADD and SUB with 's' bit set. 3643// 3644// Currently, ADDS/SUBS are pseudo opcodes that exist only in the 3645// selection DAG. They are "lowered" to real ADD/SUB opcodes by 3646// AdjustInstrPostInstrSelection where we determine whether or not to 3647// set the "s" bit based on CPSR liveness. 3648// 3649// FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen 3650// support for an optional CPSR definition that corresponds to the DAG 3651// node's second value. We can then eliminate the implicit def of CPSR. 3652let isAdd = 1 in 3653defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMaddc, 1>; 3654defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>; 3655 3656def : ARMPat<(ARMsubs GPR:$Rn, mod_imm:$imm), (SUBSri $Rn, mod_imm:$imm)>; 3657def : ARMPat<(ARMsubs GPR:$Rn, GPR:$Rm), (SUBSrr $Rn, $Rm)>; 3658def : ARMPat<(ARMsubs GPR:$Rn, so_reg_imm:$shift), 3659 (SUBSrsi $Rn, so_reg_imm:$shift)>; 3660def : ARMPat<(ARMsubs GPR:$Rn, so_reg_reg:$shift), 3661 (SUBSrsr $Rn, so_reg_reg:$shift)>; 3662 3663 3664let isAdd = 1 in 3665defm ADC : AI1_adde_sube_irs<0b0101, "adc", ARMadde, 1>; 3666defm SBC : AI1_adde_sube_irs<0b0110, "sbc", ARMsube>; 3667 3668defm RSB : AsI1_rbin_irs<0b0011, "rsb", 3669 IIC_iALUi, IIC_iALUr, IIC_iALUsr, 3670 sub>; 3671 3672// FIXME: Eliminate them if we can write def : Pat patterns which defines 3673// CPSR and the implicit def of CPSR is not needed. 3674defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>; 3675 3676defm RSC : AI1_rsc_irs<0b0111, "rsc", ARMsube>; 3677 3678// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 3679// The assume-no-carry-in form uses the negation of the input since add/sub 3680// assume opposite meanings of the carry flag (i.e., carry == !borrow). 3681// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 3682// details. 3683def : ARMPat<(add GPR:$src, mod_imm_neg:$imm), 3684 (SUBri GPR:$src, mod_imm_neg:$imm)>; 3685def : ARMPat<(ARMaddc GPR:$src, mod_imm_neg:$imm), 3686 (SUBSri GPR:$src, mod_imm_neg:$imm)>; 3687 3688def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm), 3689 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3690 Requires<[IsARM, HasV6T2]>; 3691def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm), 3692 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>, 3693 Requires<[IsARM, HasV6T2]>; 3694 3695// The with-carry-in form matches bitwise not instead of the negation. 3696// Effectively, the inverse interpretation of the carry flag already accounts 3697// for part of the negation. 3698def : ARMPat<(ARMadde GPR:$src, mod_imm_not:$imm, CPSR), 3699 (SBCri GPR:$src, mod_imm_not:$imm)>; 3700def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR), 3701 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>, 3702 Requires<[IsARM, HasV6T2]>; 3703 3704// Note: These are implemented in C++ code, because they have to generate 3705// ADD/SUBrs instructions, which use a complex pattern that a xform function 3706// cannot produce. 3707// (mul X, 2^n+1) -> (add (X << n), X) 3708// (mul X, 2^n-1) -> (rsb X, (X << n)) 3709 3710// ARM Arithmetic Instruction 3711// GPR:$dst = GPR:$a op GPR:$b 3712class AAI<bits<8> op27_20, bits<8> op11_4, string opc, 3713 list<dag> pattern = [], 3714 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm), 3715 string asm = "\t$Rd, $Rn, $Rm"> 3716 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>, 3717 Sched<[WriteALU, ReadALU, ReadALU]> { 3718 bits<4> Rn; 3719 bits<4> Rd; 3720 bits<4> Rm; 3721 let Inst{27-20} = op27_20; 3722 let Inst{11-4} = op11_4; 3723 let Inst{19-16} = Rn; 3724 let Inst{15-12} = Rd; 3725 let Inst{3-0} = Rm; 3726 3727 let Unpredictable{11-8} = 0b1111; 3728} 3729 3730// Wrappers around the AAI class 3731class AAIRevOpr<bits<8> op27_20, bits<8> op11_4, string opc, 3732 list<dag> pattern = []> 3733 : AAI<op27_20, op11_4, opc, 3734 pattern, 3735 (ins GPRnopc:$Rm, GPRnopc:$Rn), 3736 "\t$Rd, $Rm, $Rn">; 3737 3738class AAIIntrinsic<bits<8> op27_20, bits<8> op11_4, string opc, 3739 Intrinsic intrinsic> 3740 : AAI<op27_20, op11_4, opc, 3741 [(set GPRnopc:$Rd, (intrinsic GPRnopc:$Rn, GPRnopc:$Rm))]>; 3742 3743// Saturating add/subtract 3744let hasSideEffects = 1 in { 3745def QADD8 : AAIIntrinsic<0b01100010, 0b11111001, "qadd8", int_arm_qadd8>; 3746def QADD16 : AAIIntrinsic<0b01100010, 0b11110001, "qadd16", int_arm_qadd16>; 3747def QSUB16 : AAIIntrinsic<0b01100010, 0b11110111, "qsub16", int_arm_qsub16>; 3748def QSUB8 : AAIIntrinsic<0b01100010, 0b11111111, "qsub8", int_arm_qsub8>; 3749 3750def QDADD : AAIRevOpr<0b00010100, 0b00000101, "qdadd", 3751 [(set GPRnopc:$Rd, (int_arm_qadd (int_arm_qadd GPRnopc:$Rm, 3752 GPRnopc:$Rm), 3753 GPRnopc:$Rn))]>; 3754def QDSUB : AAIRevOpr<0b00010110, 0b00000101, "qdsub", 3755 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, 3756 (int_arm_qadd GPRnopc:$Rn, GPRnopc:$Rn)))]>; 3757def QSUB : AAIRevOpr<0b00010010, 0b00000101, "qsub", 3758 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))]>; 3759let DecoderMethod = "DecodeQADDInstruction" in 3760 def QADD : AAIRevOpr<0b00010000, 0b00000101, "qadd", 3761 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))]>; 3762} 3763 3764def UQADD16 : AAIIntrinsic<0b01100110, 0b11110001, "uqadd16", int_arm_uqadd16>; 3765def UQADD8 : AAIIntrinsic<0b01100110, 0b11111001, "uqadd8", int_arm_uqadd8>; 3766def UQSUB16 : AAIIntrinsic<0b01100110, 0b11110111, "uqsub16", int_arm_uqsub16>; 3767def UQSUB8 : AAIIntrinsic<0b01100110, 0b11111111, "uqsub8", int_arm_uqsub8>; 3768def QASX : AAIIntrinsic<0b01100010, 0b11110011, "qasx", int_arm_qasx>; 3769def QSAX : AAIIntrinsic<0b01100010, 0b11110101, "qsax", int_arm_qsax>; 3770def UQASX : AAIIntrinsic<0b01100110, 0b11110011, "uqasx", int_arm_uqasx>; 3771def UQSAX : AAIIntrinsic<0b01100110, 0b11110101, "uqsax", int_arm_uqsax>; 3772 3773// Signed/Unsigned add/subtract 3774 3775def SASX : AAIIntrinsic<0b01100001, 0b11110011, "sasx", int_arm_sasx>; 3776def SADD16 : AAIIntrinsic<0b01100001, 0b11110001, "sadd16", int_arm_sadd16>; 3777def SADD8 : AAIIntrinsic<0b01100001, 0b11111001, "sadd8", int_arm_sadd8>; 3778def SSAX : AAIIntrinsic<0b01100001, 0b11110101, "ssax", int_arm_ssax>; 3779def SSUB16 : AAIIntrinsic<0b01100001, 0b11110111, "ssub16", int_arm_ssub16>; 3780def SSUB8 : AAIIntrinsic<0b01100001, 0b11111111, "ssub8", int_arm_ssub8>; 3781def UASX : AAIIntrinsic<0b01100101, 0b11110011, "uasx", int_arm_uasx>; 3782def UADD16 : AAIIntrinsic<0b01100101, 0b11110001, "uadd16", int_arm_uadd16>; 3783def UADD8 : AAIIntrinsic<0b01100101, 0b11111001, "uadd8", int_arm_uadd8>; 3784def USAX : AAIIntrinsic<0b01100101, 0b11110101, "usax", int_arm_usax>; 3785def USUB16 : AAIIntrinsic<0b01100101, 0b11110111, "usub16", int_arm_usub16>; 3786def USUB8 : AAIIntrinsic<0b01100101, 0b11111111, "usub8", int_arm_usub8>; 3787 3788// Signed/Unsigned halving add/subtract 3789 3790def SHASX : AAIIntrinsic<0b01100011, 0b11110011, "shasx", int_arm_shasx>; 3791def SHADD16 : AAIIntrinsic<0b01100011, 0b11110001, "shadd16", int_arm_shadd16>; 3792def SHADD8 : AAIIntrinsic<0b01100011, 0b11111001, "shadd8", int_arm_shadd8>; 3793def SHSAX : AAIIntrinsic<0b01100011, 0b11110101, "shsax", int_arm_shsax>; 3794def SHSUB16 : AAIIntrinsic<0b01100011, 0b11110111, "shsub16", int_arm_shsub16>; 3795def SHSUB8 : AAIIntrinsic<0b01100011, 0b11111111, "shsub8", int_arm_shsub8>; 3796def UHASX : AAIIntrinsic<0b01100111, 0b11110011, "uhasx", int_arm_uhasx>; 3797def UHADD16 : AAIIntrinsic<0b01100111, 0b11110001, "uhadd16", int_arm_uhadd16>; 3798def UHADD8 : AAIIntrinsic<0b01100111, 0b11111001, "uhadd8", int_arm_uhadd8>; 3799def UHSAX : AAIIntrinsic<0b01100111, 0b11110101, "uhsax", int_arm_uhsax>; 3800def UHSUB16 : AAIIntrinsic<0b01100111, 0b11110111, "uhsub16", int_arm_uhsub16>; 3801def UHSUB8 : AAIIntrinsic<0b01100111, 0b11111111, "uhsub8", int_arm_uhsub8>; 3802 3803// Unsigned Sum of Absolute Differences [and Accumulate]. 3804 3805def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 3806 MulFrm /* for convenience */, NoItinerary, "usad8", 3807 "\t$Rd, $Rn, $Rm", 3808 [(set GPR:$Rd, (int_arm_usad8 GPR:$Rn, GPR:$Rm))]>, 3809 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> { 3810 bits<4> Rd; 3811 bits<4> Rn; 3812 bits<4> Rm; 3813 let Inst{27-20} = 0b01111000; 3814 let Inst{15-12} = 0b1111; 3815 let Inst{7-4} = 0b0001; 3816 let Inst{19-16} = Rd; 3817 let Inst{11-8} = Rm; 3818 let Inst{3-0} = Rn; 3819} 3820def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 3821 MulFrm /* for convenience */, NoItinerary, "usada8", 3822 "\t$Rd, $Rn, $Rm, $Ra", 3823 [(set GPR:$Rd, (int_arm_usada8 GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 3824 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{ 3825 bits<4> Rd; 3826 bits<4> Rn; 3827 bits<4> Rm; 3828 bits<4> Ra; 3829 let Inst{27-20} = 0b01111000; 3830 let Inst{7-4} = 0b0001; 3831 let Inst{19-16} = Rd; 3832 let Inst{15-12} = Ra; 3833 let Inst{11-8} = Rm; 3834 let Inst{3-0} = Rn; 3835} 3836 3837// Signed/Unsigned saturate 3838def SSAT : AI<(outs GPRnopc:$Rd), 3839 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3840 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>, 3841 Requires<[IsARM,HasV6]>{ 3842 bits<4> Rd; 3843 bits<5> sat_imm; 3844 bits<4> Rn; 3845 bits<8> sh; 3846 let Inst{27-21} = 0b0110101; 3847 let Inst{5-4} = 0b01; 3848 let Inst{20-16} = sat_imm; 3849 let Inst{15-12} = Rd; 3850 let Inst{11-7} = sh{4-0}; 3851 let Inst{6} = sh{5}; 3852 let Inst{3-0} = Rn; 3853} 3854 3855def SSAT16 : AI<(outs GPRnopc:$Rd), 3856 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm, 3857 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []>, 3858 Requires<[IsARM,HasV6]>{ 3859 bits<4> Rd; 3860 bits<4> sat_imm; 3861 bits<4> Rn; 3862 let Inst{27-20} = 0b01101010; 3863 let Inst{11-4} = 0b11110011; 3864 let Inst{15-12} = Rd; 3865 let Inst{19-16} = sat_imm; 3866 let Inst{3-0} = Rn; 3867} 3868 3869def USAT : AI<(outs GPRnopc:$Rd), 3870 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh), 3871 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>, 3872 Requires<[IsARM,HasV6]> { 3873 bits<4> Rd; 3874 bits<5> sat_imm; 3875 bits<4> Rn; 3876 bits<8> sh; 3877 let Inst{27-21} = 0b0110111; 3878 let Inst{5-4} = 0b01; 3879 let Inst{15-12} = Rd; 3880 let Inst{11-7} = sh{4-0}; 3881 let Inst{6} = sh{5}; 3882 let Inst{20-16} = sat_imm; 3883 let Inst{3-0} = Rn; 3884} 3885 3886def USAT16 : AI<(outs GPRnopc:$Rd), 3887 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm, 3888 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []>, 3889 Requires<[IsARM,HasV6]>{ 3890 bits<4> Rd; 3891 bits<4> sat_imm; 3892 bits<4> Rn; 3893 let Inst{27-20} = 0b01101110; 3894 let Inst{11-4} = 0b11110011; 3895 let Inst{15-12} = Rd; 3896 let Inst{19-16} = sat_imm; 3897 let Inst{3-0} = Rn; 3898} 3899 3900def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm1_32:$pos), 3901 (SSAT imm1_32:$pos, GPRnopc:$a, 0)>; 3902def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm0_31:$pos), 3903 (USAT imm0_31:$pos, GPRnopc:$a, 0)>; 3904def : ARMPat<(ARMssatnoshift GPRnopc:$Rn, imm0_31:$imm), 3905 (SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>; 3906def : ARMPat<(ARMusatnoshift GPRnopc:$Rn, imm0_31:$imm), 3907 (USAT imm0_31:$imm, GPRnopc:$Rn, 0)>; 3908def : ARMV6Pat<(int_arm_ssat16 GPRnopc:$a, imm1_16:$pos), 3909 (SSAT16 imm1_16:$pos, GPRnopc:$a)>; 3910def : ARMV6Pat<(int_arm_usat16 GPRnopc:$a, imm0_15:$pos), 3911 (USAT16 imm0_15:$pos, GPRnopc:$a)>; 3912 3913//===----------------------------------------------------------------------===// 3914// Bitwise Instructions. 3915// 3916 3917defm AND : AsI1_bin_irs<0b0000, "and", 3918 IIC_iBITi, IIC_iBITr, IIC_iBITsr, and, 1>; 3919defm ORR : AsI1_bin_irs<0b1100, "orr", 3920 IIC_iBITi, IIC_iBITr, IIC_iBITsr, or, 1>; 3921defm EOR : AsI1_bin_irs<0b0001, "eor", 3922 IIC_iBITi, IIC_iBITr, IIC_iBITsr, xor, 1>; 3923defm BIC : AsI1_bin_irs<0b1110, "bic", 3924 IIC_iBITi, IIC_iBITr, IIC_iBITsr, 3925 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 3926 3927// FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just 3928// like in the actual instruction encoding. The complexity of mapping the mask 3929// to the lsb/msb pair should be handled by ISel, not encapsulated in the 3930// instruction description. 3931def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm), 3932 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3933 "bfc", "\t$Rd, $imm", "$src = $Rd", 3934 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>, 3935 Requires<[IsARM, HasV6T2]> { 3936 bits<4> Rd; 3937 bits<10> imm; 3938 let Inst{27-21} = 0b0111110; 3939 let Inst{6-0} = 0b0011111; 3940 let Inst{15-12} = Rd; 3941 let Inst{11-7} = imm{4-0}; // lsb 3942 let Inst{20-16} = imm{9-5}; // msb 3943} 3944 3945// A8.6.18 BFI - Bitfield insert (Encoding A1) 3946def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm), 3947 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi, 3948 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd", 3949 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn, 3950 bf_inv_mask_imm:$imm))]>, 3951 Requires<[IsARM, HasV6T2]> { 3952 bits<4> Rd; 3953 bits<4> Rn; 3954 bits<10> imm; 3955 let Inst{27-21} = 0b0111110; 3956 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15 3957 let Inst{15-12} = Rd; 3958 let Inst{11-7} = imm{4-0}; // lsb 3959 let Inst{20-16} = imm{9-5}; // width 3960 let Inst{3-0} = Rn; 3961} 3962 3963def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr, 3964 "mvn", "\t$Rd, $Rm", 3965 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> { 3966 bits<4> Rd; 3967 bits<4> Rm; 3968 let Inst{25} = 0; 3969 let Inst{19-16} = 0b0000; 3970 let Inst{11-4} = 0b00000000; 3971 let Inst{15-12} = Rd; 3972 let Inst{3-0} = Rm; 3973 3974 let Unpredictable{19-16} = 0b1111; 3975} 3976def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift), 3977 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3978 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP, 3979 Sched<[WriteALU]> { 3980 bits<4> Rd; 3981 bits<12> shift; 3982 let Inst{25} = 0; 3983 let Inst{19-16} = 0b0000; 3984 let Inst{15-12} = Rd; 3985 let Inst{11-5} = shift{11-5}; 3986 let Inst{4} = 0; 3987 let Inst{3-0} = shift{3-0}; 3988 3989 let Unpredictable{19-16} = 0b1111; 3990} 3991def MVNsr : AsI1<0b1111, (outs GPRnopc:$Rd), (ins so_reg_reg:$shift), 3992 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift", 3993 [(set GPRnopc:$Rd, (not so_reg_reg:$shift))]>, UnaryDP, 3994 Sched<[WriteALU]> { 3995 bits<4> Rd; 3996 bits<12> shift; 3997 let Inst{25} = 0; 3998 let Inst{19-16} = 0b0000; 3999 let Inst{15-12} = Rd; 4000 let Inst{11-8} = shift{11-8}; 4001 let Inst{7} = 0; 4002 let Inst{6-5} = shift{6-5}; 4003 let Inst{4} = 1; 4004 let Inst{3-0} = shift{3-0}; 4005 4006 let Unpredictable{19-16} = 0b1111; 4007} 4008let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 4009def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, 4010 IIC_iMVNi, "mvn", "\t$Rd, $imm", 4011 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> { 4012 bits<4> Rd; 4013 bits<12> imm; 4014 let Inst{25} = 1; 4015 let Inst{19-16} = 0b0000; 4016 let Inst{15-12} = Rd; 4017 let Inst{11-0} = imm; 4018} 4019 4020let AddedComplexity = 1 in 4021def : ARMPat<(and GPR:$src, mod_imm_not:$imm), 4022 (BICri GPR:$src, mod_imm_not:$imm)>; 4023 4024//===----------------------------------------------------------------------===// 4025// Multiply Instructions. 4026// 4027class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 4028 string opc, string asm, list<dag> pattern> 4029 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 4030 bits<4> Rd; 4031 bits<4> Rm; 4032 bits<4> Rn; 4033 let Inst{19-16} = Rd; 4034 let Inst{11-8} = Rm; 4035 let Inst{3-0} = Rn; 4036} 4037class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 4038 string opc, string asm, list<dag> pattern> 4039 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 4040 bits<4> RdLo; 4041 bits<4> RdHi; 4042 bits<4> Rm; 4043 bits<4> Rn; 4044 let Inst{19-16} = RdHi; 4045 let Inst{15-12} = RdLo; 4046 let Inst{11-8} = Rm; 4047 let Inst{3-0} = Rn; 4048} 4049class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin, 4050 string opc, string asm, list<dag> pattern> 4051 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> { 4052 bits<4> RdLo; 4053 bits<4> RdHi; 4054 bits<4> Rm; 4055 bits<4> Rn; 4056 let Inst{19-16} = RdHi; 4057 let Inst{15-12} = RdLo; 4058 let Inst{11-8} = Rm; 4059 let Inst{3-0} = Rn; 4060} 4061 4062// FIXME: The v5 pseudos are only necessary for the additional Constraint 4063// property. Remove them when it's possible to add those properties 4064// on an individual MachineInstr, not just an instruction description. 4065let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in { 4066def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd), 4067 (ins GPRnopc:$Rn, GPRnopc:$Rm), 4068 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", 4069 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>, 4070 Requires<[IsARM, HasV6]>, 4071 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4072 let Inst{15-12} = 0b0000; 4073 let Unpredictable{15-12} = 0b1111; 4074} 4075 4076let Constraints = "@earlyclobber $Rd" in 4077def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm, 4078 pred:$p, cc_out:$s), 4079 4, IIC_iMUL32, 4080 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))], 4081 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>, 4082 Requires<[IsARM, NoV6, UseMulOps]>, 4083 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4084} 4085 4086def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd), 4087 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra), 4088 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra", 4089 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>, 4090 Requires<[IsARM, HasV6, UseMulOps]>, 4091 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 4092 bits<4> Ra; 4093 let Inst{15-12} = Ra; 4094} 4095 4096let Constraints = "@earlyclobber $Rd" in 4097def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd), 4098 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 4099 pred:$p, cc_out:$s), 4, IIC_iMAC32, 4100 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))], 4101 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>, 4102 Requires<[IsARM, NoV6]>, 4103 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4104 4105def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4106 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra", 4107 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>, 4108 Requires<[IsARM, HasV6T2, UseMulOps]>, 4109 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 4110 bits<4> Rd; 4111 bits<4> Rm; 4112 bits<4> Rn; 4113 bits<4> Ra; 4114 let Inst{19-16} = Rd; 4115 let Inst{15-12} = Ra; 4116 let Inst{11-8} = Rm; 4117 let Inst{3-0} = Rn; 4118} 4119 4120// Extra precision multiplies with low / high results 4121let hasSideEffects = 0 in { 4122let isCommutable = 1 in { 4123def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi), 4124 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 4125 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", 4126 [(set GPR:$RdLo, GPR:$RdHi, 4127 (smullohi GPR:$Rn, GPR:$Rm))]>, 4128 Requires<[IsARM, HasV6]>, 4129 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4130 4131def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi), 4132 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64, 4133 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", 4134 [(set GPR:$RdLo, GPR:$RdHi, 4135 (umullohi GPR:$Rn, GPR:$Rm))]>, 4136 Requires<[IsARM, HasV6]>, 4137 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL]>; 4138 4139let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in { 4140def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4141 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 4142 4, IIC_iMUL64, 4143 [(set GPR:$RdLo, GPR:$RdHi, 4144 (smullohi GPR:$Rn, GPR:$Rm))], 4145 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 4146 Requires<[IsARM, NoV6]>, 4147 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4148 4149def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4150 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 4151 4, IIC_iMUL64, 4152 [(set GPR:$RdLo, GPR:$RdHi, 4153 (umullohi GPR:$Rn, GPR:$Rm))], 4154 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>, 4155 Requires<[IsARM, NoV6]>, 4156 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4157} 4158} 4159 4160// Multiply + accumulate 4161def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi), 4162 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 4163 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4164 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4165 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4166def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi), 4167 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64, 4168 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4169 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4170 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4171 4172def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi), 4173 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4174 IIC_iMAC64, 4175 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4176 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>, 4177 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]> { 4178 bits<4> RdLo; 4179 bits<4> RdHi; 4180 bits<4> Rm; 4181 bits<4> Rn; 4182 let Inst{19-16} = RdHi; 4183 let Inst{15-12} = RdLo; 4184 let Inst{11-8} = Rm; 4185 let Inst{3-0} = Rn; 4186} 4187 4188let Constraints = 4189 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in { 4190def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4191 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4192 4, IIC_iMAC64, [], 4193 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 4194 pred:$p, cc_out:$s)>, 4195 Requires<[IsARM, NoV6]>, 4196 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4197def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi), 4198 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s), 4199 4, IIC_iMAC64, [], 4200 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, 4201 pred:$p, cc_out:$s)>, 4202 Requires<[IsARM, NoV6]>, 4203 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4204} 4205 4206} // hasSideEffects 4207 4208// Most significant word multiply 4209def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4210 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm", 4211 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>, 4212 Requires<[IsARM, HasV6]>, 4213 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4214 let Inst{15-12} = 0b1111; 4215} 4216 4217def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4218 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", 4219 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, (i32 0)))]>, 4220 Requires<[IsARM, HasV6]>, 4221 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 4222 let Inst{15-12} = 0b1111; 4223} 4224 4225def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd), 4226 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4227 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra", 4228 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>, 4229 Requires<[IsARM, HasV6, UseMulOps]>, 4230 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4231 4232def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd), 4233 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4234 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", 4235 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 4236 Requires<[IsARM, HasV6]>, 4237 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4238 4239def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd), 4240 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4241 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>, 4242 Requires<[IsARM, HasV6, UseMulOps]>, 4243 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4244 4245def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd), 4246 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra), 4247 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", 4248 [(set GPR:$Rd, (ARMsmmlsr GPR:$Rn, GPR:$Rm, GPR:$Ra))]>, 4249 Requires<[IsARM, HasV6]>, 4250 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4251 4252multiclass AI_smul<string opc> { 4253 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4254 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", 4255 [(set GPR:$Rd, (bb_mul GPR:$Rn, GPR:$Rm))]>, 4256 Requires<[IsARM, HasV5TE]>, 4257 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4258 4259 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4260 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm", 4261 [(set GPR:$Rd, (bt_mul GPR:$Rn, GPR:$Rm))]>, 4262 Requires<[IsARM, HasV5TE]>, 4263 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4264 4265 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4266 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm", 4267 [(set GPR:$Rd, (tb_mul GPR:$Rn, GPR:$Rm))]>, 4268 Requires<[IsARM, HasV5TE]>, 4269 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4270 4271 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4272 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm", 4273 [(set GPR:$Rd, (tt_mul GPR:$Rn, GPR:$Rm))]>, 4274 Requires<[IsARM, HasV5TE]>, 4275 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4276 4277 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4278 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", 4279 [(set GPR:$Rd, (ARMsmulwb GPR:$Rn, GPR:$Rm))]>, 4280 Requires<[IsARM, HasV5TE]>, 4281 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4282 4283 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 4284 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", 4285 [(set GPR:$Rd, (ARMsmulwt GPR:$Rn, GPR:$Rm))]>, 4286 Requires<[IsARM, HasV5TE]>, 4287 Sched<[WriteMUL16, ReadMUL, ReadMUL]>; 4288} 4289 4290 4291multiclass AI_smla<string opc> { 4292 let DecoderMethod = "DecodeSMLAInstruction" in { 4293 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd), 4294 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4295 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", 4296 [(set GPRnopc:$Rd, (add GPR:$Ra, 4297 (bb_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4298 Requires<[IsARM, HasV5TE, UseMulOps]>, 4299 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4300 4301 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd), 4302 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4303 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", 4304 [(set GPRnopc:$Rd, (add GPR:$Ra, 4305 (bt_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4306 Requires<[IsARM, HasV5TE, UseMulOps]>, 4307 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4308 4309 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd), 4310 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4311 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", 4312 [(set GPRnopc:$Rd, (add GPR:$Ra, 4313 (tb_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4314 Requires<[IsARM, HasV5TE, UseMulOps]>, 4315 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4316 4317 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd), 4318 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4319 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", 4320 [(set GPRnopc:$Rd, (add GPR:$Ra, 4321 (tt_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4322 Requires<[IsARM, HasV5TE, UseMulOps]>, 4323 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4324 4325 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd), 4326 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4327 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", 4328 [(set GPRnopc:$Rd, 4329 (add GPR:$Ra, (ARMsmulwb GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4330 Requires<[IsARM, HasV5TE, UseMulOps]>, 4331 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4332 4333 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd), 4334 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4335 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", 4336 [(set GPRnopc:$Rd, 4337 (add GPR:$Ra, (ARMsmulwt GPRnopc:$Rn, GPRnopc:$Rm)))]>, 4338 Requires<[IsARM, HasV5TE, UseMulOps]>, 4339 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>; 4340 } 4341} 4342 4343defm SMUL : AI_smul<"smul">; 4344defm SMLA : AI_smla<"smla">; 4345 4346// Halfword multiply accumulate long: SMLAL<x><y>. 4347class SMLAL<bits<2> opc1, string asm> 4348 : AMulxyI64<0b0001010, opc1, 4349 (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4350 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4351 IIC_iMAC64, asm, "\t$RdLo, $RdHi, $Rn, $Rm", []>, 4352 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4353 Requires<[IsARM, HasV5TE]>, 4354 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4355 4356def SMLALBB : SMLAL<0b00, "smlalbb">; 4357def SMLALBT : SMLAL<0b10, "smlalbt">; 4358def SMLALTB : SMLAL<0b01, "smlaltb">; 4359def SMLALTT : SMLAL<0b11, "smlaltt">; 4360 4361def : ARMV5TEPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4362 (SMLALBB $Rn, $Rm, $RLo, $RHi)>; 4363def : ARMV5TEPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4364 (SMLALBT $Rn, $Rm, $RLo, $RHi)>; 4365def : ARMV5TEPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4366 (SMLALTB $Rn, $Rm, $RLo, $RHi)>; 4367def : ARMV5TEPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 4368 (SMLALTT $Rn, $Rm, $RLo, $RHi)>; 4369 4370// Helper class for AI_smld. 4371class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops, 4372 InstrItinClass itin, string opc, string asm> 4373 : AI<oops, iops, MulFrm, itin, opc, asm, []>, 4374 Requires<[IsARM, HasV6]> { 4375 bits<4> Rn; 4376 bits<4> Rm; 4377 let Inst{27-23} = 0b01110; 4378 let Inst{22} = long; 4379 let Inst{21-20} = 0b00; 4380 let Inst{11-8} = Rm; 4381 let Inst{7} = 0; 4382 let Inst{6} = sub; 4383 let Inst{5} = swap; 4384 let Inst{4} = 1; 4385 let Inst{3-0} = Rn; 4386} 4387class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops, 4388 InstrItinClass itin, string opc, string asm> 4389 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4390 bits<4> Rd; 4391 let Inst{15-12} = 0b1111; 4392 let Inst{19-16} = Rd; 4393} 4394class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops, 4395 InstrItinClass itin, string opc, string asm> 4396 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4397 bits<4> Ra; 4398 bits<4> Rd; 4399 let Inst{19-16} = Rd; 4400 let Inst{15-12} = Ra; 4401} 4402class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops, 4403 InstrItinClass itin, string opc, string asm> 4404 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { 4405 bits<4> RdLo; 4406 bits<4> RdHi; 4407 let Inst{19-16} = RdHi; 4408 let Inst{15-12} = RdLo; 4409} 4410 4411multiclass AI_smld<bit sub, string opc> { 4412 4413 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd), 4414 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4415 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">, 4416 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4417 4418 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd), 4419 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4420 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">, 4421 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>; 4422 4423 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4424 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4425 NoItinerary, 4426 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">, 4427 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4428 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 4429 4430 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi), 4431 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4432 NoItinerary, 4433 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">, 4434 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 4435 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>; 4436} 4437 4438defm SMLA : AI_smld<0, "smla">; 4439defm SMLS : AI_smld<1, "smls">; 4440 4441def : ARMV6Pat<(int_arm_smlad GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4442 (SMLAD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4443def : ARMV6Pat<(int_arm_smladx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4444 (SMLADX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4445def : ARMV6Pat<(int_arm_smlsd GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4446 (SMLSD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4447def : ARMV6Pat<(int_arm_smlsdx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra), 4448 (SMLSDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>; 4449def : ARMV6Pat<(ARMSmlald GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4450 (SMLALD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4451def : ARMV6Pat<(ARMSmlaldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4452 (SMLALDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4453def : ARMV6Pat<(ARMSmlsld GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4454 (SMLSLD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4455def : ARMV6Pat<(ARMSmlsldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi), 4456 (SMLSLDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>; 4457 4458multiclass AI_sdml<bit sub, string opc> { 4459 4460 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), 4461 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">, 4462 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4463 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm), 4464 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">, 4465 Sched<[WriteMUL32, ReadMUL, ReadMUL]>; 4466} 4467 4468defm SMUA : AI_sdml<0, "smua">; 4469defm SMUS : AI_sdml<1, "smus">; 4470 4471def : ARMV6Pat<(int_arm_smuad GPRnopc:$Rn, GPRnopc:$Rm), 4472 (SMUAD GPRnopc:$Rn, GPRnopc:$Rm)>; 4473def : ARMV6Pat<(int_arm_smuadx GPRnopc:$Rn, GPRnopc:$Rm), 4474 (SMUADX GPRnopc:$Rn, GPRnopc:$Rm)>; 4475def : ARMV6Pat<(int_arm_smusd GPRnopc:$Rn, GPRnopc:$Rm), 4476 (SMUSD GPRnopc:$Rn, GPRnopc:$Rm)>; 4477def : ARMV6Pat<(int_arm_smusdx GPRnopc:$Rn, GPRnopc:$Rm), 4478 (SMUSDX GPRnopc:$Rn, GPRnopc:$Rm)>; 4479 4480//===----------------------------------------------------------------------===// 4481// Division Instructions (ARMv7-A with virtualization extension) 4482// 4483def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4484 "sdiv", "\t$Rd, $Rn, $Rm", 4485 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>, 4486 Requires<[IsARM, HasDivideInARM]>, 4487 Sched<[WriteDIV]>; 4488 4489def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV, 4490 "udiv", "\t$Rd, $Rn, $Rm", 4491 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>, 4492 Requires<[IsARM, HasDivideInARM]>, 4493 Sched<[WriteDIV]>; 4494 4495//===----------------------------------------------------------------------===// 4496// Misc. Arithmetic Instructions. 4497// 4498 4499def CLZ : AMiscA1I<0b00010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm), 4500 IIC_iUNAr, "clz", "\t$Rd, $Rm", 4501 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>, 4502 Sched<[WriteALU]>; 4503 4504def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4505 IIC_iUNAr, "rbit", "\t$Rd, $Rm", 4506 [(set GPR:$Rd, (bitreverse GPR:$Rm))]>, 4507 Requires<[IsARM, HasV6T2]>, 4508 Sched<[WriteALU]>; 4509 4510def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm), 4511 IIC_iUNAr, "rev", "\t$Rd, $Rm", 4512 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>, 4513 Sched<[WriteALU]>; 4514 4515let AddedComplexity = 5 in 4516def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4517 IIC_iUNAr, "rev16", "\t$Rd, $Rm", 4518 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>, 4519 Requires<[IsARM, HasV6]>, 4520 Sched<[WriteALU]>; 4521 4522def : ARMV6Pat<(srl (bswap (extloadi16 addrmode3:$addr)), (i32 16)), 4523 (REV16 (LDRH addrmode3:$addr))>; 4524def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr), 4525 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>; 4526 4527let AddedComplexity = 5 in 4528def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm), 4529 IIC_iUNAr, "revsh", "\t$Rd, $Rm", 4530 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>, 4531 Requires<[IsARM, HasV6]>, 4532 Sched<[WriteALU]>; 4533 4534def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)), 4535 (and (srl GPR:$Rm, (i32 8)), 0xFF)), 4536 (REVSH GPR:$Rm)>; 4537 4538def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd), 4539 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh), 4540 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", 4541 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF), 4542 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh), 4543 0xFFFF0000)))]>, 4544 Requires<[IsARM, HasV6]>, 4545 Sched<[WriteALUsi, ReadALU]>; 4546 4547// Alternate cases for PKHBT where identities eliminate some nodes. 4548def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)), 4549 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>; 4550def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)), 4551 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>; 4552 4553// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 4554// will match the pattern below. 4555def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd), 4556 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh), 4557 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", 4558 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000), 4559 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh), 4560 0xFFFF)))]>, 4561 Requires<[IsARM, HasV6]>, 4562 Sched<[WriteALUsi, ReadALU]>; 4563 4564// Alternate cases for PKHTB where identities eliminate some nodes. Note that 4565// a shift amount of 0 is *not legal* here, it is PKHBT instead. 4566// We also can not replace a srl (17..31) by an arithmetic shift we would use in 4567// pkhtb src1, src2, asr (17..31). 4568def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4569 (srl GPRnopc:$src2, imm16:$sh)), 4570 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>; 4571def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4572 (sra GPRnopc:$src2, imm16_31:$sh)), 4573 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>; 4574def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000), 4575 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)), 4576 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>; 4577 4578//===----------------------------------------------------------------------===// 4579// CRC Instructions 4580// 4581// Polynomials: 4582// + CRC32{B,H,W} 0x04C11DB7 4583// + CRC32C{B,H,W} 0x1EDC6F41 4584// 4585 4586class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin> 4587 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary, 4588 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm", 4589 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>, 4590 Requires<[IsARM, HasV8, HasCRC]> { 4591 bits<4> Rd; 4592 bits<4> Rn; 4593 bits<4> Rm; 4594 4595 let Inst{31-28} = 0b1110; 4596 let Inst{27-23} = 0b00010; 4597 let Inst{22-21} = sz; 4598 let Inst{20} = 0; 4599 let Inst{19-16} = Rn; 4600 let Inst{15-12} = Rd; 4601 let Inst{11-10} = 0b00; 4602 let Inst{9} = C; 4603 let Inst{8} = 0; 4604 let Inst{7-4} = 0b0100; 4605 let Inst{3-0} = Rm; 4606 4607 let Unpredictable{11-8} = 0b1101; 4608} 4609 4610def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>; 4611def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>; 4612def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>; 4613def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>; 4614def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>; 4615def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>; 4616 4617//===----------------------------------------------------------------------===// 4618// ARMv8.1a Privilege Access Never extension 4619// 4620// SETPAN #imm1 4621 4622def SETPAN : AInoP<(outs), (ins imm0_1:$imm), MiscFrm, NoItinerary, "setpan", 4623 "\t$imm", []>, Requires<[IsARM, HasV8, HasV8_1a]> { 4624 bits<1> imm; 4625 4626 let Inst{31-28} = 0b1111; 4627 let Inst{27-20} = 0b00010001; 4628 let Inst{19-16} = 0b0000; 4629 let Inst{15-10} = 0b000000; 4630 let Inst{9} = imm; 4631 let Inst{8} = 0b0; 4632 let Inst{7-4} = 0b0000; 4633 let Inst{3-0} = 0b0000; 4634 4635 let Unpredictable{19-16} = 0b1111; 4636 let Unpredictable{15-10} = 0b111111; 4637 let Unpredictable{8} = 0b1; 4638 let Unpredictable{3-0} = 0b1111; 4639} 4640 4641//===----------------------------------------------------------------------===// 4642// Comparison Instructions... 4643// 4644 4645defm CMP : AI1_cmp_irs<0b1010, "cmp", 4646 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, ARMcmp>; 4647 4648// ARMcmpZ can re-use the above instruction definitions. 4649def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm), 4650 (CMPri GPR:$src, mod_imm:$imm)>; 4651def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs), 4652 (CMPrr GPR:$src, GPR:$rhs)>; 4653def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs), 4654 (CMPrsi GPR:$src, so_reg_imm:$rhs)>; 4655def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs), 4656 (CMPrsr GPR:$src, so_reg_reg:$rhs)>; 4657 4658// CMN register-integer 4659let isCompare = 1, Defs = [CPSR] in { 4660def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi, 4661 "cmn", "\t$Rn, $imm", 4662 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>, 4663 Sched<[WriteCMP, ReadALU]> { 4664 bits<4> Rn; 4665 bits<12> imm; 4666 let Inst{25} = 1; 4667 let Inst{20} = 1; 4668 let Inst{19-16} = Rn; 4669 let Inst{15-12} = 0b0000; 4670 let Inst{11-0} = imm; 4671 4672 let Unpredictable{15-12} = 0b1111; 4673} 4674 4675// CMN register-register/shift 4676def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr, 4677 "cmn", "\t$Rn, $Rm", 4678 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4679 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> { 4680 bits<4> Rn; 4681 bits<4> Rm; 4682 let isCommutable = 1; 4683 let Inst{25} = 0; 4684 let Inst{20} = 1; 4685 let Inst{19-16} = Rn; 4686 let Inst{15-12} = 0b0000; 4687 let Inst{11-4} = 0b00000000; 4688 let Inst{3-0} = Rm; 4689 4690 let Unpredictable{15-12} = 0b1111; 4691} 4692 4693def CMNzrsi : AI1<0b1011, (outs), 4694 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr, 4695 "cmn", "\t$Rn, $shift", 4696 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4697 GPR:$Rn, so_reg_imm:$shift)]>, 4698 Sched<[WriteCMPsi, ReadALU]> { 4699 bits<4> Rn; 4700 bits<12> shift; 4701 let Inst{25} = 0; 4702 let Inst{20} = 1; 4703 let Inst{19-16} = Rn; 4704 let Inst{15-12} = 0b0000; 4705 let Inst{11-5} = shift{11-5}; 4706 let Inst{4} = 0; 4707 let Inst{3-0} = shift{3-0}; 4708 4709 let Unpredictable{15-12} = 0b1111; 4710} 4711 4712def CMNzrsr : AI1<0b1011, (outs), 4713 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr, 4714 "cmn", "\t$Rn, $shift", 4715 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 4716 GPRnopc:$Rn, so_reg_reg:$shift)]>, 4717 Sched<[WriteCMPsr, ReadALU]> { 4718 bits<4> Rn; 4719 bits<12> shift; 4720 let Inst{25} = 0; 4721 let Inst{20} = 1; 4722 let Inst{19-16} = Rn; 4723 let Inst{15-12} = 0b0000; 4724 let Inst{11-8} = shift{11-8}; 4725 let Inst{7} = 0; 4726 let Inst{6-5} = shift{6-5}; 4727 let Inst{4} = 1; 4728 let Inst{3-0} = shift{3-0}; 4729 4730 let Unpredictable{15-12} = 0b1111; 4731} 4732 4733} 4734 4735def : ARMPat<(ARMcmp GPR:$src, mod_imm_neg:$imm), 4736 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4737 4738def : ARMPat<(ARMcmpZ GPR:$src, mod_imm_neg:$imm), 4739 (CMNri GPR:$src, mod_imm_neg:$imm)>; 4740 4741// Note that TST/TEQ don't set all the same flags that CMP does! 4742defm TST : AI1_cmp_irs<0b1000, "tst", 4743 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4744 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1, 4745 "DecodeTSTInstruction">; 4746defm TEQ : AI1_cmp_irs<0b1001, "teq", 4747 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr, 4748 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>; 4749 4750// Pseudo i64 compares for some floating point compares. 4751let usesCustomInserter = 1, isBranch = 1, isTerminator = 1, 4752 Defs = [CPSR] in { 4753def BCCi64 : PseudoInst<(outs), 4754 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst), 4755 IIC_Br, 4756 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>, 4757 Sched<[WriteBr]>; 4758 4759def BCCZi64 : PseudoInst<(outs), 4760 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br, 4761 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>, 4762 Sched<[WriteBr]>; 4763} // usesCustomInserter 4764 4765 4766// Conditional moves 4767let hasSideEffects = 0 in { 4768 4769let isCommutable = 1, isSelect = 1 in 4770def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), 4771 (ins GPR:$false, GPR:$Rm, cmovpred:$p), 4772 4, IIC_iCMOVr, 4773 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, 4774 cmovpred:$p))]>, 4775 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4776 4777def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd), 4778 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p), 4779 4, IIC_iCMOVsr, 4780 [(set GPR:$Rd, 4781 (ARMcmov GPR:$false, so_reg_imm:$shift, 4782 cmovpred:$p))]>, 4783 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4784def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd), 4785 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p), 4786 4, IIC_iCMOVsr, 4787 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift, 4788 cmovpred:$p))]>, 4789 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4790 4791 4792let isMoveImm = 1 in 4793def MOVCCi16 4794 : ARMPseudoInst<(outs GPR:$Rd), 4795 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p), 4796 4, IIC_iMOVi, 4797 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm, 4798 cmovpred:$p))]>, 4799 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>, 4800 Sched<[WriteALU]>; 4801 4802let isMoveImm = 1 in 4803def MOVCCi : ARMPseudoInst<(outs GPR:$Rd), 4804 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 4805 4, IIC_iCMOVi, 4806 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm:$imm, 4807 cmovpred:$p))]>, 4808 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4809 4810// Two instruction predicate mov immediate. 4811let isMoveImm = 1 in 4812def MOVCCi32imm 4813 : ARMPseudoInst<(outs GPR:$Rd), 4814 (ins GPR:$false, i32imm:$src, cmovpred:$p), 4815 8, IIC_iCMOVix2, 4816 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src, 4817 cmovpred:$p))]>, 4818 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>; 4819 4820let isMoveImm = 1 in 4821def MVNCCi : ARMPseudoInst<(outs GPR:$Rd), 4822 (ins GPR:$false, mod_imm:$imm, cmovpred:$p), 4823 4, IIC_iCMOVi, 4824 [(set GPR:$Rd, (ARMcmov GPR:$false, mod_imm_not:$imm, 4825 cmovpred:$p))]>, 4826 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 4827 4828} // hasSideEffects 4829 4830 4831//===----------------------------------------------------------------------===// 4832// Atomic operations intrinsics 4833// 4834 4835def MemBarrierOptOperand : AsmOperandClass { 4836 let Name = "MemBarrierOpt"; 4837 let ParserMethod = "parseMemBarrierOptOperand"; 4838} 4839def memb_opt : Operand<i32> { 4840 let PrintMethod = "printMemBOption"; 4841 let ParserMatchClass = MemBarrierOptOperand; 4842 let DecoderMethod = "DecodeMemBarrierOption"; 4843} 4844 4845def InstSyncBarrierOptOperand : AsmOperandClass { 4846 let Name = "InstSyncBarrierOpt"; 4847 let ParserMethod = "parseInstSyncBarrierOptOperand"; 4848} 4849def instsyncb_opt : Operand<i32> { 4850 let PrintMethod = "printInstSyncBOption"; 4851 let ParserMatchClass = InstSyncBarrierOptOperand; 4852 let DecoderMethod = "DecodeInstSyncBarrierOption"; 4853} 4854 4855def TraceSyncBarrierOptOperand : AsmOperandClass { 4856 let Name = "TraceSyncBarrierOpt"; 4857 let ParserMethod = "parseTraceSyncBarrierOptOperand"; 4858} 4859def tsb_opt : Operand<i32> { 4860 let PrintMethod = "printTraceSyncBOption"; 4861 let ParserMatchClass = TraceSyncBarrierOptOperand; 4862} 4863 4864// Memory barriers protect the atomic sequences 4865let hasSideEffects = 1 in { 4866def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4867 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>, 4868 Requires<[IsARM, HasDB]> { 4869 bits<4> opt; 4870 let Inst{31-4} = 0xf57ff05; 4871 let Inst{3-0} = opt; 4872} 4873 4874def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary, 4875 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>, 4876 Requires<[IsARM, HasDB]> { 4877 bits<4> opt; 4878 let Inst{31-4} = 0xf57ff04; 4879 let Inst{3-0} = opt; 4880} 4881 4882// ISB has only full system option 4883def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary, 4884 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>, 4885 Requires<[IsARM, HasDB]> { 4886 bits<4> opt; 4887 let Inst{31-4} = 0xf57ff06; 4888 let Inst{3-0} = opt; 4889} 4890 4891let hasNoSchedulingInfo = 1 in 4892def TSB : AInoP<(outs), (ins tsb_opt:$opt), MiscFrm, NoItinerary, 4893 "tsb", "\t$opt", []>, Requires<[IsARM, HasV8_4a]> { 4894 let Inst{31-0} = 0xe320f012; 4895} 4896 4897} 4898 4899// Armv8.5-A speculation barrier 4900def SB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "sb", "", []>, 4901 Requires<[IsARM, HasSB]>, Sched<[]> { 4902 let Inst{31-0} = 0xf57ff070; 4903 let Unpredictable = 0x000fff0f; 4904 let hasSideEffects = 1; 4905} 4906 4907let usesCustomInserter = 1, Defs = [CPSR] in { 4908 4909// Pseudo instruction that combines movs + predicated rsbmi 4910// to implement integer ABS 4911 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>; 4912} 4913 4914let usesCustomInserter = 1, Defs = [CPSR] in { 4915 def COPY_STRUCT_BYVAL_I32 : PseudoInst< 4916 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment), 4917 NoItinerary, 4918 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>; 4919} 4920 4921let hasPostISelHook = 1, Constraints = "$newdst = $dst, $newsrc = $src" in { 4922 // %newsrc, %newdst = MEMCPY %dst, %src, N, ...N scratch regs... 4923 // Copies N registers worth of memory from address %src to address %dst 4924 // and returns the incremented addresses. N scratch register will 4925 // be attached for the copy to use. 4926 def MEMCPY : PseudoInst< 4927 (outs GPR:$newdst, GPR:$newsrc), 4928 (ins GPR:$dst, GPR:$src, i32imm:$nreg, variable_ops), 4929 NoItinerary, 4930 [(set GPR:$newdst, GPR:$newsrc, 4931 (ARMmemcopy GPR:$dst, GPR:$src, imm:$nreg))]>; 4932} 4933 4934def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4935 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4936}]>; 4937 4938def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4939 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4940}]>; 4941 4942def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{ 4943 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4944}]>; 4945 4946def strex_1 : PatFrag<(ops node:$val, node:$ptr), 4947 (int_arm_strex node:$val, node:$ptr), [{ 4948 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4949}]>; 4950 4951def strex_2 : PatFrag<(ops node:$val, node:$ptr), 4952 (int_arm_strex node:$val, node:$ptr), [{ 4953 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4954}]>; 4955 4956def strex_4 : PatFrag<(ops node:$val, node:$ptr), 4957 (int_arm_strex node:$val, node:$ptr), [{ 4958 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4959}]>; 4960 4961def ldaex_1 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4962 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4963}]>; 4964 4965def ldaex_2 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4966 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4967}]>; 4968 4969def ldaex_4 : PatFrag<(ops node:$ptr), (int_arm_ldaex node:$ptr), [{ 4970 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4971}]>; 4972 4973def stlex_1 : PatFrag<(ops node:$val, node:$ptr), 4974 (int_arm_stlex node:$val, node:$ptr), [{ 4975 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8; 4976}]>; 4977 4978def stlex_2 : PatFrag<(ops node:$val, node:$ptr), 4979 (int_arm_stlex node:$val, node:$ptr), [{ 4980 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 4981}]>; 4982 4983def stlex_4 : PatFrag<(ops node:$val, node:$ptr), 4984 (int_arm_stlex node:$val, node:$ptr), [{ 4985 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 4986}]>; 4987 4988let mayLoad = 1 in { 4989def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4990 NoItinerary, "ldrexb", "\t$Rt, $addr", 4991 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>; 4992def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4993 NoItinerary, "ldrexh", "\t$Rt, $addr", 4994 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>; 4995def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 4996 NoItinerary, "ldrex", "\t$Rt, $addr", 4997 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>; 4998let hasExtraDefRegAllocReq = 1 in 4999def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 5000 NoItinerary, "ldrexd", "\t$Rt, $addr", []> { 5001 let DecoderMethod = "DecodeDoubleRegLoad"; 5002} 5003 5004def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5005 NoItinerary, "ldaexb", "\t$Rt, $addr", 5006 [(set GPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>; 5007def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5008 NoItinerary, "ldaexh", "\t$Rt, $addr", 5009 [(set GPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>; 5010def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), 5011 NoItinerary, "ldaex", "\t$Rt, $addr", 5012 [(set GPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>; 5013let hasExtraDefRegAllocReq = 1 in 5014def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr), 5015 NoItinerary, "ldaexd", "\t$Rt, $addr", []> { 5016 let DecoderMethod = "DecodeDoubleRegLoad"; 5017} 5018} 5019 5020let mayStore = 1, Constraints = "@earlyclobber $Rd" in { 5021def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5022 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", 5023 [(set GPR:$Rd, (strex_1 GPR:$Rt, 5024 addr_offset_none:$addr))]>; 5025def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5026 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", 5027 [(set GPR:$Rd, (strex_2 GPR:$Rt, 5028 addr_offset_none:$addr))]>; 5029def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5030 NoItinerary, "strex", "\t$Rd, $Rt, $addr", 5031 [(set GPR:$Rd, (strex_4 GPR:$Rt, 5032 addr_offset_none:$addr))]>; 5033let hasExtraSrcRegAllocReq = 1 in 5034def STREXD : AIstrex<0b01, (outs GPR:$Rd), 5035 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 5036 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> { 5037 let DecoderMethod = "DecodeDoubleRegStore"; 5038} 5039def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5040 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr", 5041 [(set GPR:$Rd, 5042 (stlex_1 GPR:$Rt, addr_offset_none:$addr))]>; 5043def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5044 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr", 5045 [(set GPR:$Rd, 5046 (stlex_2 GPR:$Rt, addr_offset_none:$addr))]>; 5047def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), 5048 NoItinerary, "stlex", "\t$Rd, $Rt, $addr", 5049 [(set GPR:$Rd, 5050 (stlex_4 GPR:$Rt, addr_offset_none:$addr))]>; 5051let hasExtraSrcRegAllocReq = 1 in 5052def STLEXD : AIstlex<0b01, (outs GPR:$Rd), 5053 (ins GPRPairOp:$Rt, addr_offset_none:$addr), 5054 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> { 5055 let DecoderMethod = "DecodeDoubleRegStore"; 5056} 5057} 5058 5059def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", 5060 [(int_arm_clrex)]>, 5061 Requires<[IsARM, HasV6K]> { 5062 let Inst{31-0} = 0b11110101011111111111000000011111; 5063} 5064 5065def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 5066 (STREXB GPR:$Rt, addr_offset_none:$addr)>; 5067def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 5068 (STREXH GPR:$Rt, addr_offset_none:$addr)>; 5069 5070def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 5071 (STLEXB GPR:$Rt, addr_offset_none:$addr)>; 5072def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 5073 (STLEXH GPR:$Rt, addr_offset_none:$addr)>; 5074 5075class acquiring_load<PatFrag base> 5076 : PatFrag<(ops node:$ptr), (base node:$ptr), [{ 5077 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 5078 return isAcquireOrStronger(Ordering); 5079}]>; 5080 5081def atomic_load_acquire_8 : acquiring_load<atomic_load_8>; 5082def atomic_load_acquire_16 : acquiring_load<atomic_load_16>; 5083def atomic_load_acquire_32 : acquiring_load<atomic_load_32>; 5084 5085class releasing_store<PatFrag base> 5086 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{ 5087 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering(); 5088 return isReleaseOrStronger(Ordering); 5089}]>; 5090 5091def atomic_store_release_8 : releasing_store<atomic_store_8>; 5092def atomic_store_release_16 : releasing_store<atomic_store_16>; 5093def atomic_store_release_32 : releasing_store<atomic_store_32>; 5094 5095let AddedComplexity = 8 in { 5096 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>; 5097 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>; 5098 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>; 5099 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>; 5100 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>; 5101 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>; 5102} 5103 5104// SWP/SWPB are deprecated in V6/V7 and optional in v7VE. 5105// FIXME Use InstAlias to generate LDREX/STREX pairs instead. 5106let mayLoad = 1, mayStore = 1 in { 5107def SWP : AIswp<0, (outs GPRnopc:$Rt), 5108 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>, 5109 Requires<[IsARM,PreV8]>; 5110def SWPB: AIswp<1, (outs GPRnopc:$Rt), 5111 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>, 5112 Requires<[IsARM,PreV8]>; 5113} 5114 5115//===----------------------------------------------------------------------===// 5116// Coprocessor Instructions. 5117// 5118 5119def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5120 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 5121 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5122 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 5123 imm:$CRm, imm:$opc2)]>, 5124 Requires<[IsARM,PreV8]> { 5125 bits<4> opc1; 5126 bits<4> CRn; 5127 bits<4> CRd; 5128 bits<4> cop; 5129 bits<3> opc2; 5130 bits<4> CRm; 5131 5132 let Inst{3-0} = CRm; 5133 let Inst{4} = 0; 5134 let Inst{7-5} = opc2; 5135 let Inst{11-8} = cop; 5136 let Inst{15-12} = CRd; 5137 let Inst{19-16} = CRn; 5138 let Inst{23-20} = opc1; 5139 5140 let DecoderNamespace = "CoProc"; 5141} 5142 5143def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 5144 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 5145 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 5146 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 5147 imm:$CRm, imm:$opc2)]>, 5148 Requires<[IsARM,PreV8]> { 5149 let Inst{31-28} = 0b1111; 5150 bits<4> opc1; 5151 bits<4> CRn; 5152 bits<4> CRd; 5153 bits<4> cop; 5154 bits<3> opc2; 5155 bits<4> CRm; 5156 5157 let Inst{3-0} = CRm; 5158 let Inst{4} = 0; 5159 let Inst{7-5} = opc2; 5160 let Inst{11-8} = cop; 5161 let Inst{15-12} = CRd; 5162 let Inst{19-16} = CRn; 5163 let Inst{23-20} = opc1; 5164 5165 let DecoderNamespace = "CoProc"; 5166} 5167 5168class ACI<dag oops, dag iops, string opc, string asm, 5169 list<dag> pattern, IndexMode im = IndexModeNone> 5170 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 5171 opc, asm, "", pattern> { 5172 let Inst{27-25} = 0b110; 5173} 5174class ACInoP<dag oops, dag iops, string opc, string asm, 5175 list<dag> pattern, IndexMode im = IndexModeNone> 5176 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary, 5177 opc, asm, "", pattern> { 5178 let Inst{31-28} = 0b1111; 5179 let Inst{27-25} = 0b110; 5180} 5181 5182let DecoderNamespace = "CoProc" in { 5183multiclass LdStCop<bit load, bit Dbit, string asm, list<dag> pattern> { 5184 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 5185 asm, "\t$cop, $CRd, $addr", pattern> { 5186 bits<13> addr; 5187 bits<4> cop; 5188 bits<4> CRd; 5189 let Inst{24} = 1; // P = 1 5190 let Inst{23} = addr{8}; 5191 let Inst{22} = Dbit; 5192 let Inst{21} = 0; // W = 0 5193 let Inst{20} = load; 5194 let Inst{19-16} = addr{12-9}; 5195 let Inst{15-12} = CRd; 5196 let Inst{11-8} = cop; 5197 let Inst{7-0} = addr{7-0}; 5198 let DecoderMethod = "DecodeCopMemInstruction"; 5199 } 5200 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 5201 asm, "\t$cop, $CRd, $addr!", [], IndexModePre> { 5202 bits<13> addr; 5203 bits<4> cop; 5204 bits<4> CRd; 5205 let Inst{24} = 1; // P = 1 5206 let Inst{23} = addr{8}; 5207 let Inst{22} = Dbit; 5208 let Inst{21} = 1; // W = 1 5209 let Inst{20} = load; 5210 let Inst{19-16} = addr{12-9}; 5211 let Inst{15-12} = CRd; 5212 let Inst{11-8} = cop; 5213 let Inst{7-0} = addr{7-0}; 5214 let DecoderMethod = "DecodeCopMemInstruction"; 5215 } 5216 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5217 postidx_imm8s4:$offset), 5218 asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> { 5219 bits<9> offset; 5220 bits<4> addr; 5221 bits<4> cop; 5222 bits<4> CRd; 5223 let Inst{24} = 0; // P = 0 5224 let Inst{23} = offset{8}; 5225 let Inst{22} = Dbit; 5226 let Inst{21} = 1; // W = 1 5227 let Inst{20} = load; 5228 let Inst{19-16} = addr; 5229 let Inst{15-12} = CRd; 5230 let Inst{11-8} = cop; 5231 let Inst{7-0} = offset{7-0}; 5232 let DecoderMethod = "DecodeCopMemInstruction"; 5233 } 5234 def _OPTION : ACI<(outs), 5235 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5236 coproc_option_imm:$option), 5237 asm, "\t$cop, $CRd, $addr, $option", []> { 5238 bits<8> option; 5239 bits<4> addr; 5240 bits<4> cop; 5241 bits<4> CRd; 5242 let Inst{24} = 0; // P = 0 5243 let Inst{23} = 1; // U = 1 5244 let Inst{22} = Dbit; 5245 let Inst{21} = 0; // W = 0 5246 let Inst{20} = load; 5247 let Inst{19-16} = addr; 5248 let Inst{15-12} = CRd; 5249 let Inst{11-8} = cop; 5250 let Inst{7-0} = option; 5251 let DecoderMethod = "DecodeCopMemInstruction"; 5252 } 5253} 5254multiclass LdSt2Cop<bit load, bit Dbit, string asm, list<dag> pattern> { 5255 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 5256 asm, "\t$cop, $CRd, $addr", pattern> { 5257 bits<13> addr; 5258 bits<4> cop; 5259 bits<4> CRd; 5260 let Inst{24} = 1; // P = 1 5261 let Inst{23} = addr{8}; 5262 let Inst{22} = Dbit; 5263 let Inst{21} = 0; // W = 0 5264 let Inst{20} = load; 5265 let Inst{19-16} = addr{12-9}; 5266 let Inst{15-12} = CRd; 5267 let Inst{11-8} = cop; 5268 let Inst{7-0} = addr{7-0}; 5269 let DecoderMethod = "DecodeCopMemInstruction"; 5270 } 5271 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 5272 asm, "\t$cop, $CRd, $addr!", [], IndexModePre> { 5273 bits<13> addr; 5274 bits<4> cop; 5275 bits<4> CRd; 5276 let Inst{24} = 1; // P = 1 5277 let Inst{23} = addr{8}; 5278 let Inst{22} = Dbit; 5279 let Inst{21} = 1; // W = 1 5280 let Inst{20} = load; 5281 let Inst{19-16} = addr{12-9}; 5282 let Inst{15-12} = CRd; 5283 let Inst{11-8} = cop; 5284 let Inst{7-0} = addr{7-0}; 5285 let DecoderMethod = "DecodeCopMemInstruction"; 5286 } 5287 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5288 postidx_imm8s4:$offset), 5289 asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> { 5290 bits<9> offset; 5291 bits<4> addr; 5292 bits<4> cop; 5293 bits<4> CRd; 5294 let Inst{24} = 0; // P = 0 5295 let Inst{23} = offset{8}; 5296 let Inst{22} = Dbit; 5297 let Inst{21} = 1; // W = 1 5298 let Inst{20} = load; 5299 let Inst{19-16} = addr; 5300 let Inst{15-12} = CRd; 5301 let Inst{11-8} = cop; 5302 let Inst{7-0} = offset{7-0}; 5303 let DecoderMethod = "DecodeCopMemInstruction"; 5304 } 5305 def _OPTION : ACInoP<(outs), 5306 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 5307 coproc_option_imm:$option), 5308 asm, "\t$cop, $CRd, $addr, $option", []> { 5309 bits<8> option; 5310 bits<4> addr; 5311 bits<4> cop; 5312 bits<4> CRd; 5313 let Inst{24} = 0; // P = 0 5314 let Inst{23} = 1; // U = 1 5315 let Inst{22} = Dbit; 5316 let Inst{21} = 0; // W = 0 5317 let Inst{20} = load; 5318 let Inst{19-16} = addr; 5319 let Inst{15-12} = CRd; 5320 let Inst{11-8} = cop; 5321 let Inst{7-0} = option; 5322 let DecoderMethod = "DecodeCopMemInstruction"; 5323 } 5324} 5325 5326defm LDC : LdStCop <1, 0, "ldc", [(int_arm_ldc imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5327defm LDCL : LdStCop <1, 1, "ldcl", [(int_arm_ldcl imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5328defm LDC2 : LdSt2Cop<1, 0, "ldc2", [(int_arm_ldc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5329defm LDC2L : LdSt2Cop<1, 1, "ldc2l", [(int_arm_ldc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5330 5331defm STC : LdStCop <0, 0, "stc", [(int_arm_stc imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5332defm STCL : LdStCop <0, 1, "stcl", [(int_arm_stcl imm:$cop, imm:$CRd, addrmode5:$addr)]>; 5333defm STC2 : LdSt2Cop<0, 0, "stc2", [(int_arm_stc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5334defm STC2L : LdSt2Cop<0, 1, "stc2l", [(int_arm_stc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[IsARM,PreV8]>; 5335 5336} // DecoderNamespace = "CoProc" 5337 5338//===----------------------------------------------------------------------===// 5339// Move between coprocessor and ARM core register. 5340// 5341 5342class MovRCopro<string opc, bit direction, dag oops, dag iops, 5343 list<dag> pattern> 5344 : ABI<0b1110, oops, iops, NoItinerary, opc, 5345 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> { 5346 let Inst{20} = direction; 5347 let Inst{4} = 1; 5348 5349 bits<4> Rt; 5350 bits<4> cop; 5351 bits<3> opc1; 5352 bits<3> opc2; 5353 bits<4> CRm; 5354 bits<4> CRn; 5355 5356 let Inst{15-12} = Rt; 5357 let Inst{11-8} = cop; 5358 let Inst{23-21} = opc1; 5359 let Inst{7-5} = opc2; 5360 let Inst{3-0} = CRm; 5361 let Inst{19-16} = CRn; 5362 5363 let DecoderNamespace = "CoProc"; 5364} 5365 5366def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */, 5367 (outs), 5368 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5369 c_imm:$CRm, imm0_7:$opc2), 5370 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 5371 imm:$CRm, imm:$opc2)]>, 5372 ComplexDeprecationPredicate<"MCR">; 5373def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 5374 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5375 c_imm:$CRm, 0, pred:$p)>; 5376def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */, 5377 (outs GPRwithAPSR:$Rt), 5378 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5379 imm0_7:$opc2), []>; 5380def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm", 5381 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5382 c_imm:$CRm, 0, pred:$p)>; 5383 5384def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), 5385 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 5386 5387class MovRCopro2<string opc, bit direction, dag oops, dag iops, 5388 list<dag> pattern> 5389 : ABXI<0b1110, oops, iops, NoItinerary, 5390 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> { 5391 let Inst{31-24} = 0b11111110; 5392 let Inst{20} = direction; 5393 let Inst{4} = 1; 5394 5395 bits<4> Rt; 5396 bits<4> cop; 5397 bits<3> opc1; 5398 bits<3> opc2; 5399 bits<4> CRm; 5400 bits<4> CRn; 5401 5402 let Inst{15-12} = Rt; 5403 let Inst{11-8} = cop; 5404 let Inst{23-21} = opc1; 5405 let Inst{7-5} = opc2; 5406 let Inst{3-0} = CRm; 5407 let Inst{19-16} = CRn; 5408 5409 let DecoderNamespace = "CoProc"; 5410} 5411 5412def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */, 5413 (outs), 5414 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5415 c_imm:$CRm, imm0_7:$opc2), 5416 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 5417 imm:$CRm, imm:$opc2)]>, 5418 Requires<[IsARM,PreV8]>; 5419def : ARMInstAlias<"mcr2 $cop, $opc1, $Rt, $CRn, $CRm", 5420 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 5421 c_imm:$CRm, 0)>; 5422def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */, 5423 (outs GPRwithAPSR:$Rt), 5424 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 5425 imm0_7:$opc2), []>, 5426 Requires<[IsARM,PreV8]>; 5427def : ARMInstAlias<"mrc2 $cop, $opc1, $Rt, $CRn, $CRm", 5428 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 5429 c_imm:$CRm, 0)>; 5430 5431def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, 5432 imm:$CRm, imm:$opc2), 5433 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 5434 5435class MovRRCopro<string opc, bit direction, dag oops, dag iops, list<dag> 5436 pattern = []> 5437 : ABI<0b1100, oops, iops, NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", 5438 pattern> { 5439 5440 let Inst{23-21} = 0b010; 5441 let Inst{20} = direction; 5442 5443 bits<4> Rt; 5444 bits<4> Rt2; 5445 bits<4> cop; 5446 bits<4> opc1; 5447 bits<4> CRm; 5448 5449 let Inst{15-12} = Rt; 5450 let Inst{19-16} = Rt2; 5451 let Inst{11-8} = cop; 5452 let Inst{7-4} = opc1; 5453 let Inst{3-0} = CRm; 5454} 5455 5456def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */, 5457 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, 5458 GPRnopc:$Rt2, c_imm:$CRm), 5459 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt, 5460 GPRnopc:$Rt2, imm:$CRm)]>; 5461def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */, 5462 (outs GPRnopc:$Rt, GPRnopc:$Rt2), 5463 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; 5464 5465class MovRRCopro2<string opc, bit direction, dag oops, dag iops, 5466 list<dag> pattern = []> 5467 : ABXI<0b1100, oops, iops, NoItinerary, 5468 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>, 5469 Requires<[IsARM,PreV8]> { 5470 let Inst{31-28} = 0b1111; 5471 let Inst{23-21} = 0b010; 5472 let Inst{20} = direction; 5473 5474 bits<4> Rt; 5475 bits<4> Rt2; 5476 bits<4> cop; 5477 bits<4> opc1; 5478 bits<4> CRm; 5479 5480 let Inst{15-12} = Rt; 5481 let Inst{19-16} = Rt2; 5482 let Inst{11-8} = cop; 5483 let Inst{7-4} = opc1; 5484 let Inst{3-0} = CRm; 5485 5486 let DecoderMethod = "DecoderForMRRC2AndMCRR2"; 5487} 5488 5489def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */, 5490 (outs), (ins p_imm:$cop, imm0_15:$opc1, GPRnopc:$Rt, 5491 GPRnopc:$Rt2, c_imm:$CRm), 5492 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt, 5493 GPRnopc:$Rt2, imm:$CRm)]>; 5494 5495def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */, 5496 (outs GPRnopc:$Rt, GPRnopc:$Rt2), 5497 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; 5498 5499//===----------------------------------------------------------------------===// 5500// Move between special register and ARM core register 5501// 5502 5503// Move to ARM core register from Special Register 5504def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5505 "mrs", "\t$Rd, apsr", []> { 5506 bits<4> Rd; 5507 let Inst{23-16} = 0b00001111; 5508 let Unpredictable{19-17} = 0b111; 5509 5510 let Inst{15-12} = Rd; 5511 5512 let Inst{11-0} = 0b000000000000; 5513 let Unpredictable{11-0} = 0b110100001111; 5514} 5515 5516def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p), 0>, 5517 Requires<[IsARM]>; 5518 5519// The MRSsys instruction is the MRS instruction from the ARM ARM, 5520// section B9.3.9, with the R bit set to 1. 5521def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary, 5522 "mrs", "\t$Rd, spsr", []> { 5523 bits<4> Rd; 5524 let Inst{23-16} = 0b01001111; 5525 let Unpredictable{19-16} = 0b1111; 5526 5527 let Inst{15-12} = Rd; 5528 5529 let Inst{11-0} = 0b000000000000; 5530 let Unpredictable{11-0} = 0b110100001111; 5531} 5532 5533// However, the MRS (banked register) system instruction (ARMv7VE) *does* have a 5534// separate encoding (distinguished by bit 5. 5535def MRSbanked : ABI<0b0001, (outs GPRnopc:$Rd), (ins banked_reg:$banked), 5536 NoItinerary, "mrs", "\t$Rd, $banked", []>, 5537 Requires<[IsARM, HasVirtualization]> { 5538 bits<6> banked; 5539 bits<4> Rd; 5540 5541 let Inst{23} = 0; 5542 let Inst{22} = banked{5}; // R bit 5543 let Inst{21-20} = 0b00; 5544 let Inst{19-16} = banked{3-0}; 5545 let Inst{15-12} = Rd; 5546 let Inst{11-9} = 0b001; 5547 let Inst{8} = banked{4}; 5548 let Inst{7-0} = 0b00000000; 5549} 5550 5551// Move from ARM core register to Special Register 5552// 5553// No need to have both system and application versions of MSR (immediate) or 5554// MSR (register), the encodings are the same and the assembly parser has no way 5555// to distinguish between them. The mask operand contains the special register 5556// (R Bit) in bit 4 and bits 3-0 contains the mask with the fields to be 5557// accessed in the special register. 5558let Defs = [CPSR] in 5559def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, 5560 "msr", "\t$mask, $Rn", []> { 5561 bits<5> mask; 5562 bits<4> Rn; 5563 5564 let Inst{23} = 0; 5565 let Inst{22} = mask{4}; // R bit 5566 let Inst{21-20} = 0b10; 5567 let Inst{19-16} = mask{3-0}; 5568 let Inst{15-12} = 0b1111; 5569 let Inst{11-4} = 0b00000000; 5570 let Inst{3-0} = Rn; 5571} 5572 5573let Defs = [CPSR] in 5574def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary, 5575 "msr", "\t$mask, $imm", []> { 5576 bits<5> mask; 5577 bits<12> imm; 5578 5579 let Inst{23} = 0; 5580 let Inst{22} = mask{4}; // R bit 5581 let Inst{21-20} = 0b10; 5582 let Inst{19-16} = mask{3-0}; 5583 let Inst{15-12} = 0b1111; 5584 let Inst{11-0} = imm; 5585} 5586 5587// However, the MSR (banked register) system instruction (ARMv7VE) *does* have a 5588// separate encoding (distinguished by bit 5. 5589def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn), 5590 NoItinerary, "msr", "\t$banked, $Rn", []>, 5591 Requires<[IsARM, HasVirtualization]> { 5592 bits<6> banked; 5593 bits<4> Rn; 5594 5595 let Inst{23} = 0; 5596 let Inst{22} = banked{5}; // R bit 5597 let Inst{21-20} = 0b10; 5598 let Inst{19-16} = banked{3-0}; 5599 let Inst{15-12} = 0b1111; 5600 let Inst{11-9} = 0b001; 5601 let Inst{8} = banked{4}; 5602 let Inst{7-4} = 0b0000; 5603 let Inst{3-0} = Rn; 5604} 5605 5606// Dynamic stack allocation yields a _chkstk for Windows targets. These calls 5607// are needed to probe the stack when allocating more than 5608// 4k bytes in one go. Touching the stack at 4K increments is necessary to 5609// ensure that the guard pages used by the OS virtual memory manager are 5610// allocated in correct sequence. 5611// The main point of having separate instruction are extra unmodelled effects 5612// (compared to ordinary calls) like stack pointer change. 5613 5614def win__chkstk : SDNode<"ARMISD::WIN__CHKSTK", SDTNone, 5615 [SDNPHasChain, SDNPSideEffect]>; 5616let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in 5617 def WIN__CHKSTK : PseudoInst<(outs), (ins), NoItinerary, [(win__chkstk)]>; 5618 5619def win__dbzchk : SDNode<"ARMISD::WIN__DBZCHK", SDT_WIN__DBZCHK, 5620 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 5621let usesCustomInserter = 1, Defs = [CPSR] in 5622 def WIN__DBZCHK : PseudoInst<(outs), (ins tGPR:$divisor), NoItinerary, 5623 [(win__dbzchk tGPR:$divisor)]>; 5624 5625//===----------------------------------------------------------------------===// 5626// TLS Instructions 5627// 5628 5629// __aeabi_read_tp preserves the registers r1-r3. 5630// This is a pseudo inst so that we can get the encoding right, 5631// complete with fixup for the aeabi_read_tp function. 5632// TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern 5633// is defined in "ARMInstrThumb.td". 5634let isCall = 1, 5635 Defs = [R0, R12, LR, CPSR], Uses = [SP] in { 5636 def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br, 5637 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>, 5638 Requires<[IsARM, IsReadTPSoft]>; 5639} 5640 5641// Reading thread pointer from coprocessor register 5642def : ARMPat<(ARMthread_pointer), (MRC 15, 0, 13, 0, 3)>, 5643 Requires<[IsARM, IsReadTPHard]>; 5644 5645//===----------------------------------------------------------------------===// 5646// SJLJ Exception handling intrinsics 5647// eh_sjlj_setjmp() is an instruction sequence to store the return 5648// address and save #0 in R0 for the non-longjmp case. 5649// Since by its nature we may be coming from some other function to get 5650// here, and we're using the stack frame for the containing function to 5651// save/restore registers, we can't keep anything live in regs across 5652// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 5653// when we get here from a longjmp(). We force everything out of registers 5654// except for our own input by listing the relevant registers in Defs. By 5655// doing so, we also cause the prologue/epilogue code to actively preserve 5656// all of the callee-saved resgisters, which is exactly what we want. 5657// A constant value is passed in $val, and we use the location as a scratch. 5658// 5659// These are pseudo-instructions and are lowered to individual MC-insts, so 5660// no encoding information is necessary. 5661let Defs = 5662 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 5663 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ], 5664 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5665 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5666 NoItinerary, 5667 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5668 Requires<[IsARM, HasVFP2]>; 5669} 5670 5671let Defs = 5672 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 5673 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 5674 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val), 5675 NoItinerary, 5676 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>, 5677 Requires<[IsARM, NoVFP]>; 5678} 5679 5680// FIXME: Non-IOS version(s) 5681let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, 5682 Defs = [ R7, LR, SP ] in { 5683def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch), 5684 NoItinerary, 5685 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 5686 Requires<[IsARM]>; 5687} 5688 5689let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1 in 5690def Int_eh_sjlj_setup_dispatch : PseudoInst<(outs), (ins), NoItinerary, 5691 [(ARMeh_sjlj_setup_dispatch)]>; 5692 5693// eh.sjlj.dispatchsetup pseudo-instruction. 5694// This pseudo is used for both ARM and Thumb. Any differences are handled when 5695// the pseudo is expanded (which happens before any passes that need the 5696// instruction size). 5697let isBarrier = 1 in 5698def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>; 5699 5700 5701//===----------------------------------------------------------------------===// 5702// Non-Instruction Patterns 5703// 5704 5705// ARMv4 indirect branch using (MOVr PC, dst) 5706let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in 5707 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst), 5708 4, IIC_Br, [(brind GPR:$dst)], 5709 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5710 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5711 5712let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in 5713 def TAILJMPr4 : ARMPseudoExpand<(outs), (ins GPR:$dst), 5714 4, IIC_Br, [], 5715 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>, 5716 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>; 5717 5718// Large immediate handling. 5719 5720// 32-bit immediate using two piece mod_imms or movw + movt. 5721// This is a single pseudo instruction, the benefit is that it can be remat'd 5722// as a single unit instead of having to handle reg inputs. 5723// FIXME: Remove this when we can do generalized remat. 5724let isReMaterializable = 1, isMoveImm = 1 in 5725def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 5726 [(set GPR:$dst, (arm_i32imm:$src))]>, 5727 Requires<[IsARM]>; 5728 5729def LDRLIT_ga_abs : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iLoad_i, 5730 [(set GPR:$dst, (ARMWrapper tglobaladdr:$src))]>, 5731 Requires<[IsARM, DontUseMovt]>; 5732 5733// Pseudo instruction that combines movw + movt + add pc (if PIC). 5734// It also makes it possible to rematerialize the instructions. 5735// FIXME: Remove this when we can do generalized remat and when machine licm 5736// can properly the instructions. 5737let isReMaterializable = 1 in { 5738def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5739 IIC_iMOVix2addpc, 5740 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, 5741 Requires<[IsARM, UseMovtInPic]>; 5742 5743def LDRLIT_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5744 IIC_iLoadiALU, 5745 [(set GPR:$dst, 5746 (ARMWrapperPIC tglobaladdr:$addr))]>, 5747 Requires<[IsARM, DontUseMovtInPic]>; 5748 5749let AddedComplexity = 10 in 5750def LDRLIT_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5751 NoItinerary, 5752 [(set GPR:$dst, 5753 (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5754 Requires<[IsARM, DontUseMovtInPic]>; 5755 5756let AddedComplexity = 10 in 5757def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr), 5758 IIC_iMOVix2ld, 5759 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>, 5760 Requires<[IsARM, UseMovtInPic]>; 5761} // isReMaterializable 5762 5763// The many different faces of TLS access. 5764def : ARMPat<(ARMWrapper tglobaltlsaddr :$dst), 5765 (MOVi32imm tglobaltlsaddr :$dst)>, 5766 Requires<[IsARM, UseMovt]>; 5767 5768def : Pat<(ARMWrapper tglobaltlsaddr:$src), 5769 (LDRLIT_ga_abs tglobaltlsaddr:$src)>, 5770 Requires<[IsARM, DontUseMovt]>; 5771 5772def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 5773 (MOV_ga_pcrel tglobaltlsaddr:$addr)>, Requires<[IsARM, UseMovtInPic]>; 5774 5775def : Pat<(ARMWrapperPIC tglobaltlsaddr:$addr), 5776 (LDRLIT_ga_pcrel tglobaltlsaddr:$addr)>, 5777 Requires<[IsARM, DontUseMovtInPic]>; 5778let AddedComplexity = 10 in 5779def : Pat<(load (ARMWrapperPIC tglobaltlsaddr:$addr)), 5780 (MOV_ga_pcrel_ldr tglobaltlsaddr:$addr)>, 5781 Requires<[IsARM, UseMovtInPic]>; 5782 5783 5784// ConstantPool, GlobalAddress, and JumpTable 5785def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>; 5786def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>, 5787 Requires<[IsARM, UseMovt]>; 5788def : ARMPat<(ARMWrapper texternalsym :$dst), (MOVi32imm texternalsym :$dst)>, 5789 Requires<[IsARM, UseMovt]>; 5790def : ARMPat<(ARMWrapperJT tjumptable:$dst), 5791 (LEApcrelJT tjumptable:$dst)>; 5792 5793// TODO: add,sub,and, 3-instr forms? 5794 5795// Tail calls. These patterns also apply to Thumb mode. 5796def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>; 5797def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>; 5798def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>; 5799 5800// Direct calls 5801def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>; 5802def : ARMPat<(ARMcall_nolink texternalsym:$func), 5803 (BMOVPCB_CALL texternalsym:$func)>; 5804 5805// zextload i1 -> zextload i8 5806def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5807def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5808 5809// extload -> zextload 5810def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5811def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5812def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>; 5813def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>; 5814 5815def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; 5816 5817def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>; 5818def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>; 5819 5820// smul* and smla* 5821def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b), 5822 (SMULBB GPR:$a, GPR:$b)>; 5823def : ARMV5TEPat<(mul sext_16_node:$a, (sext_bottom_16 GPR:$b)), 5824 (SMULBB GPR:$a, GPR:$b)>; 5825def : ARMV5TEPat<(mul sext_16_node:$a, (sext_top_16 GPR:$b)), 5826 (SMULBT GPR:$a, GPR:$b)>; 5827def : ARMV5TEPat<(mul (sext_top_16 GPR:$a), sext_16_node:$b), 5828 (SMULTB GPR:$a, GPR:$b)>; 5829def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, sext_16_node:$b)), 5830 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5831def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, (sext_bottom_16 GPR:$b))), 5832 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5833def : ARMV5MOPat<(add GPR:$acc, (mul sext_16_node:$a, (sext_top_16 GPR:$b))), 5834 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 5835def : ARMV5MOPat<(add GPR:$acc, (mul (sext_top_16 GPR:$a), sext_16_node:$b)), 5836 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 5837 5838def : ARMV5TEPat<(int_arm_smulbb GPR:$a, GPR:$b), 5839 (SMULBB GPR:$a, GPR:$b)>; 5840def : ARMV5TEPat<(int_arm_smulbt GPR:$a, GPR:$b), 5841 (SMULBT GPR:$a, GPR:$b)>; 5842def : ARMV5TEPat<(int_arm_smultb GPR:$a, GPR:$b), 5843 (SMULTB GPR:$a, GPR:$b)>; 5844def : ARMV5TEPat<(int_arm_smultt GPR:$a, GPR:$b), 5845 (SMULTT GPR:$a, GPR:$b)>; 5846def : ARMV5TEPat<(int_arm_smulwb GPR:$a, GPR:$b), 5847 (SMULWB GPR:$a, GPR:$b)>; 5848def : ARMV5TEPat<(int_arm_smulwt GPR:$a, GPR:$b), 5849 (SMULWT GPR:$a, GPR:$b)>; 5850 5851def : ARMV5TEPat<(int_arm_smlabb GPR:$a, GPR:$b, GPR:$acc), 5852 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 5853def : ARMV5TEPat<(int_arm_smlabt GPR:$a, GPR:$b, GPR:$acc), 5854 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 5855def : ARMV5TEPat<(int_arm_smlatb GPR:$a, GPR:$b, GPR:$acc), 5856 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 5857def : ARMV5TEPat<(int_arm_smlatt GPR:$a, GPR:$b, GPR:$acc), 5858 (SMLATT GPR:$a, GPR:$b, GPR:$acc)>; 5859def : ARMV5TEPat<(int_arm_smlawb GPR:$a, GPR:$b, GPR:$acc), 5860 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 5861def : ARMV5TEPat<(int_arm_smlawt GPR:$a, GPR:$b, GPR:$acc), 5862 (SMLAWT GPR:$a, GPR:$b, GPR:$acc)>; 5863 5864// Pre-v7 uses MCR for synchronization barriers. 5865def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>, 5866 Requires<[IsARM, HasV6]>; 5867 5868// SXT/UXT with no rotate 5869let AddedComplexity = 16 in { 5870def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>; 5871def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>; 5872def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>; 5873def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)), 5874 (UXTAB GPR:$Rn, GPR:$Rm, 0)>; 5875def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)), 5876 (UXTAH GPR:$Rn, GPR:$Rm, 0)>; 5877} 5878 5879def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>; 5880def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>; 5881 5882def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)), 5883 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>; 5884def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)), 5885 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>; 5886 5887// Atomic load/store patterns 5888def : ARMPat<(atomic_load_8 ldst_so_reg:$src), 5889 (LDRBrs ldst_so_reg:$src)>; 5890def : ARMPat<(atomic_load_8 addrmode_imm12:$src), 5891 (LDRBi12 addrmode_imm12:$src)>; 5892def : ARMPat<(atomic_load_16 addrmode3:$src), 5893 (LDRH addrmode3:$src)>; 5894def : ARMPat<(atomic_load_32 ldst_so_reg:$src), 5895 (LDRrs ldst_so_reg:$src)>; 5896def : ARMPat<(atomic_load_32 addrmode_imm12:$src), 5897 (LDRi12 addrmode_imm12:$src)>; 5898def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val), 5899 (STRBrs GPR:$val, ldst_so_reg:$ptr)>; 5900def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val), 5901 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>; 5902def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val), 5903 (STRH GPR:$val, addrmode3:$ptr)>; 5904def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val), 5905 (STRrs GPR:$val, ldst_so_reg:$ptr)>; 5906def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val), 5907 (STRi12 GPR:$val, addrmode_imm12:$ptr)>; 5908 5909 5910//===----------------------------------------------------------------------===// 5911// Thumb Support 5912// 5913 5914include "ARMInstrThumb.td" 5915 5916//===----------------------------------------------------------------------===// 5917// Thumb2 Support 5918// 5919 5920include "ARMInstrThumb2.td" 5921 5922//===----------------------------------------------------------------------===// 5923// Floating Point Support 5924// 5925 5926include "ARMInstrVFP.td" 5927 5928//===----------------------------------------------------------------------===// 5929// Advanced SIMD (NEON) Support 5930// 5931 5932include "ARMInstrNEON.td" 5933 5934//===----------------------------------------------------------------------===// 5935// Assembler aliases 5936// 5937 5938// Memory barriers 5939def : InstAlias<"dmb", (DMB 0xf), 0>, Requires<[IsARM, HasDB]>; 5940def : InstAlias<"dsb", (DSB 0xf), 0>, Requires<[IsARM, HasDB]>; 5941def : InstAlias<"ssbb", (DSB 0x0), 1>, Requires<[IsARM, HasDB]>; 5942def : InstAlias<"pssbb", (DSB 0x4), 1>, Requires<[IsARM, HasDB]>; 5943def : InstAlias<"isb", (ISB 0xf), 0>, Requires<[IsARM, HasDB]>; 5944// Armv8-R 'Data Full Barrier' 5945def : InstAlias<"dfb", (DSB 0xc), 1>, Requires<[IsARM, HasDFB]>; 5946 5947// System instructions 5948def : MnemonicAlias<"swi", "svc">; 5949 5950// Load / Store Multiple 5951def : MnemonicAlias<"ldmfd", "ldm">; 5952def : MnemonicAlias<"ldmia", "ldm">; 5953def : MnemonicAlias<"ldmea", "ldmdb">; 5954def : MnemonicAlias<"stmfd", "stmdb">; 5955def : MnemonicAlias<"stmia", "stm">; 5956def : MnemonicAlias<"stmea", "stm">; 5957 5958// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the 5959// input operands swapped when the shift amount is zero (i.e., unspecified). 5960def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", 5961 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p), 0>, 5962 Requires<[IsARM, HasV6]>; 5963def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", 5964 (PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p), 0>, 5965 Requires<[IsARM, HasV6]>; 5966 5967// PUSH/POP aliases for STM/LDM 5968def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>; 5969def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>; 5970 5971// SSAT/USAT optional shift operand. 5972def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn", 5973 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5974def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn", 5975 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>; 5976 5977 5978// Extend instruction optional rotate operand. 5979def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm", 5980 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5981def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm", 5982 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5983def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm", 5984 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5985def : ARMInstAlias<"sxtb${p} $Rd, $Rm", 5986 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5987def : ARMInstAlias<"sxtb16${p} $Rd, $Rm", 5988 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5989def : ARMInstAlias<"sxth${p} $Rd, $Rm", 5990 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 5991 5992def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm", 5993 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5994def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm", 5995 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5996def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm", 5997 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>; 5998def : ARMInstAlias<"uxtb${p} $Rd, $Rm", 5999 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6000def : ARMInstAlias<"uxtb16${p} $Rd, $Rm", 6001 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6002def : ARMInstAlias<"uxth${p} $Rd, $Rm", 6003 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>; 6004 6005 6006// RFE aliases 6007def : MnemonicAlias<"rfefa", "rfeda">; 6008def : MnemonicAlias<"rfeea", "rfedb">; 6009def : MnemonicAlias<"rfefd", "rfeia">; 6010def : MnemonicAlias<"rfeed", "rfeib">; 6011def : MnemonicAlias<"rfe", "rfeia">; 6012 6013// SRS aliases 6014def : MnemonicAlias<"srsfa", "srsib">; 6015def : MnemonicAlias<"srsea", "srsia">; 6016def : MnemonicAlias<"srsfd", "srsdb">; 6017def : MnemonicAlias<"srsed", "srsda">; 6018def : MnemonicAlias<"srs", "srsia">; 6019 6020// QSAX == QSUBADDX 6021def : MnemonicAlias<"qsubaddx", "qsax">; 6022// SASX == SADDSUBX 6023def : MnemonicAlias<"saddsubx", "sasx">; 6024// SHASX == SHADDSUBX 6025def : MnemonicAlias<"shaddsubx", "shasx">; 6026// SHSAX == SHSUBADDX 6027def : MnemonicAlias<"shsubaddx", "shsax">; 6028// SSAX == SSUBADDX 6029def : MnemonicAlias<"ssubaddx", "ssax">; 6030// UASX == UADDSUBX 6031def : MnemonicAlias<"uaddsubx", "uasx">; 6032// UHASX == UHADDSUBX 6033def : MnemonicAlias<"uhaddsubx", "uhasx">; 6034// UHSAX == UHSUBADDX 6035def : MnemonicAlias<"uhsubaddx", "uhsax">; 6036// UQASX == UQADDSUBX 6037def : MnemonicAlias<"uqaddsubx", "uqasx">; 6038// UQSAX == UQSUBADDX 6039def : MnemonicAlias<"uqsubaddx", "uqsax">; 6040// USAX == USUBADDX 6041def : MnemonicAlias<"usubaddx", "usax">; 6042 6043// "mov Rd, mod_imm_not" can be handled via "mvn" in assembly, just like 6044// for isel. 6045def : ARMInstSubst<"mov${s}${p} $Rd, $imm", 6046 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6047def : ARMInstSubst<"mvn${s}${p} $Rd, $imm", 6048 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6049// Same for AND <--> BIC 6050def : ARMInstSubst<"bic${s}${p} $Rd, $Rn, $imm", 6051 (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 6052 pred:$p, cc_out:$s)>; 6053def : ARMInstSubst<"bic${s}${p} $Rdn, $imm", 6054 (ANDri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 6055 pred:$p, cc_out:$s)>; 6056def : ARMInstSubst<"and${s}${p} $Rd, $Rn, $imm", 6057 (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, 6058 pred:$p, cc_out:$s)>; 6059def : ARMInstSubst<"and${s}${p} $Rdn, $imm", 6060 (BICri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, 6061 pred:$p, cc_out:$s)>; 6062 6063// Likewise, "add Rd, mod_imm_neg" -> sub 6064def : ARMInstSubst<"add${s}${p} $Rd, $Rn, $imm", 6065 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6066def : ARMInstSubst<"add${s}${p} $Rd, $imm", 6067 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6068// Likewise, "sub Rd, mod_imm_neg" -> add 6069def : ARMInstSubst<"sub${s}${p} $Rd, $Rn, $imm", 6070 (ADDri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6071def : ARMInstSubst<"sub${s}${p} $Rd, $imm", 6072 (ADDri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>; 6073 6074 6075def : ARMInstSubst<"adc${s}${p} $Rd, $Rn, $imm", 6076 (SBCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6077def : ARMInstSubst<"adc${s}${p} $Rdn, $imm", 6078 (SBCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6079def : ARMInstSubst<"sbc${s}${p} $Rd, $Rn, $imm", 6080 (ADCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6081def : ARMInstSubst<"sbc${s}${p} $Rdn, $imm", 6082 (ADCri GPR:$Rdn, GPR:$Rdn, mod_imm_not:$imm, pred:$p, cc_out:$s)>; 6083 6084// Same for CMP <--> CMN via mod_imm_neg 6085def : ARMInstSubst<"cmp${p} $Rd, $imm", 6086 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 6087def : ARMInstSubst<"cmn${p} $Rd, $imm", 6088 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>; 6089 6090// The shifter forms of the MOV instruction are aliased to the ASR, LSL, 6091// LSR, ROR, and RRX instructions. 6092// FIXME: We need C++ parser hooks to map the alias to the MOV 6093// encoding. It seems we should be able to do that sort of thing 6094// in tblgen, but it could get ugly. 6095let TwoOperandAliasConstraint = "$Rm = $Rd" in { 6096def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm", 6097 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 6098 cc_out:$s)>; 6099def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm", 6100 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p, 6101 cc_out:$s)>; 6102def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm", 6103 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 6104 cc_out:$s)>; 6105def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm", 6106 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p, 6107 cc_out:$s)>; 6108} 6109def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm", 6110 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>; 6111let TwoOperandAliasConstraint = "$Rn = $Rd" in { 6112def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm", 6113 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6114 cc_out:$s)>; 6115def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm", 6116 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6117 cc_out:$s)>; 6118def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm", 6119 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6120 cc_out:$s)>; 6121def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm", 6122 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, 6123 cc_out:$s)>; 6124} 6125 6126// "neg" is and alias for "rsb rd, rn, #0" 6127def : ARMInstAlias<"neg${s}${p} $Rd, $Rm", 6128 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>; 6129 6130// Pre-v6, 'mov r0, r0' was used as a NOP encoding. 6131def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>, 6132 Requires<[IsARM, NoV6]>; 6133 6134// MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but 6135// the instruction definitions need difference constraints pre-v6. 6136// Use these aliases for the assembly parsing on pre-v6. 6137def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm", 6138 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s), 0>, 6139 Requires<[IsARM, NoV6]>; 6140def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra", 6141 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, 6142 pred:$p, cc_out:$s), 0>, 6143 Requires<[IsARM, NoV6]>; 6144def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6145 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6146 Requires<[IsARM, NoV6]>; 6147def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6148 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6149 Requires<[IsARM, NoV6]>; 6150def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6151 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6152 Requires<[IsARM, NoV6]>; 6153def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm", 6154 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>, 6155 Requires<[IsARM, NoV6]>; 6156 6157// 'it' blocks in ARM mode just validate the predicates. The IT itself 6158// is discarded. 6159def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>, 6160 ComplexDeprecationPredicate<"IT">; 6161 6162let mayLoad = 1, mayStore =1, hasSideEffects = 1 in 6163def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn), 6164 NoItinerary, 6165 [(set GPR:$Rd, (int_arm_space imm:$size, GPR:$Rn))]>; 6166 6167//===---------------------------------- 6168// Atomic cmpxchg for -O0 6169//===---------------------------------- 6170 6171// The fast register allocator used during -O0 inserts spills to cover any VRegs 6172// live across basic block boundaries. When this happens between an LDXR and an 6173// STXR it can clear the exclusive monitor, causing all cmpxchg attempts to 6174// fail. 6175 6176// Unfortunately, this means we have to have an alternative (expanded 6177// post-regalloc) path for -O0 compilations. Fortunately this path can be 6178// significantly more naive than the standard expansion: we conservatively 6179// assume seq_cst, strong cmpxchg and omit clrex on failure. 6180 6181let Constraints = "@earlyclobber $Rd,@earlyclobber $temp", 6182 mayLoad = 1, mayStore = 1 in { 6183def CMP_SWAP_8 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6184 (ins GPR:$addr, GPR:$desired, GPR:$new), 6185 NoItinerary, []>, Sched<[]>; 6186 6187def CMP_SWAP_16 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6188 (ins GPR:$addr, GPR:$desired, GPR:$new), 6189 NoItinerary, []>, Sched<[]>; 6190 6191def CMP_SWAP_32 : PseudoInst<(outs GPR:$Rd, GPR:$temp), 6192 (ins GPR:$addr, GPR:$desired, GPR:$new), 6193 NoItinerary, []>, Sched<[]>; 6194 6195def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPR:$temp), 6196 (ins GPR:$addr, GPRPair:$desired, GPRPair:$new), 6197 NoItinerary, []>, Sched<[]>; 6198} 6199 6200def CompilerBarrier : PseudoInst<(outs), (ins i32imm:$ordering), NoItinerary, 6201 [(atomic_fence imm:$ordering, 0)]> { 6202 let hasSideEffects = 1; 6203 let Size = 0; 6204 let AsmString = "@ COMPILER BARRIER"; 6205} 6206