1//===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb2 instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14// IT block predicate field 15def it_pred_asmoperand : AsmOperandClass { 16 let Name = "ITCondCode"; 17 let ParserMethod = "parseITCondCode"; 18} 19def it_pred : Operand<i32> { 20 let PrintMethod = "printMandatoryPredicateOperand"; 21 let ParserMatchClass = it_pred_asmoperand; 22} 23 24// IT block condition mask 25def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; } 26def it_mask : Operand<i32> { 27 let PrintMethod = "printThumbITMask"; 28 let ParserMatchClass = it_mask_asmoperand; 29} 30 31// t2_shift_imm: An integer that encodes a shift amount and the type of shift 32// (asr or lsl). The 6-bit immediate encodes as: 33// {5} 0 ==> lsl 34// 1 asr 35// {4-0} imm5 shift amount. 36// asr #32 not allowed 37def t2_shift_imm : Operand<i32> { 38 let PrintMethod = "printShiftImmOperand"; 39 let ParserMatchClass = ShifterImmAsmOperand; 40 let DecoderMethod = "DecodeT2ShifterImmOperand"; 41} 42 43// Shifted operands. No register controlled shifts for Thumb2. 44// Note: We do not support rrx shifted operands yet. 45def t2_so_reg : Operand<i32>, // reg imm 46 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand", 47 [shl,srl,sra,rotr]> { 48 let EncoderMethod = "getT2SORegOpValue"; 49 let PrintMethod = "printT2SOOperand"; 50 let DecoderMethod = "DecodeSORegImmOperand"; 51 let ParserMatchClass = ShiftedImmAsmOperand; 52 let MIOperandInfo = (ops rGPR, i32imm); 53} 54 55// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value 56def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{ 57 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), SDLoc(N), 58 MVT::i32); 59}]>; 60 61// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value 62def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{ 63 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), SDLoc(N), 64 MVT::i32); 65}]>; 66 67// so_imm_notSext_XFORM - Return a so_imm value packed into the format 68// described for so_imm_notSext def below, with sign extension from 16 69// bits. 70def t2_so_imm_notSext16_XFORM : SDNodeXForm<imm, [{ 71 APInt apIntN = N->getAPIntValue(); 72 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue(); 73 return CurDAG->getTargetConstant(~N16bitSignExt, SDLoc(N), MVT::i32); 74}]>; 75 76// t2_so_imm - Match a 32-bit immediate operand, which is an 77// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit 78// immediate splatted into multiple bytes of the word. 79def t2_so_imm_asmoperand : AsmOperandClass { 80 let Name = "T2SOImm"; 81 let RenderMethod = "addImmOperands"; 82 83} 84def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{ 85 return ARM_AM::getT2SOImmVal(Imm) != -1; 86 }]> { 87 let ParserMatchClass = t2_so_imm_asmoperand; 88 let EncoderMethod = "getT2SOImmOpValue"; 89 let DecoderMethod = "DecodeT2SOImm"; 90} 91 92// t2_so_imm_not - Match an immediate that is a complement 93// of a t2_so_imm. 94// Note: this pattern doesn't require an encoder method and such, as it's 95// only used on aliases (Pat<> and InstAlias<>). The actual encoding 96// is handled by the destination instructions, which use t2_so_imm. 97def t2_so_imm_not_asmoperand : AsmOperandClass { let Name = "T2SOImmNot"; } 98def t2_so_imm_not : Operand<i32>, PatLeaf<(imm), [{ 99 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1; 100}], t2_so_imm_not_XFORM> { 101 let ParserMatchClass = t2_so_imm_not_asmoperand; 102} 103 104// t2_so_imm_notSext - match an immediate that is a complement of a t2_so_imm 105// if the upper 16 bits are zero. 106def t2_so_imm_notSext : Operand<i32>, PatLeaf<(imm), [{ 107 APInt apIntN = N->getAPIntValue(); 108 if (!apIntN.isIntN(16)) return false; 109 unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue(); 110 return ARM_AM::getT2SOImmVal(~N16bitSignExt) != -1; 111 }], t2_so_imm_notSext16_XFORM> { 112 let ParserMatchClass = t2_so_imm_not_asmoperand; 113} 114 115// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm. 116def t2_so_imm_neg_asmoperand : AsmOperandClass { let Name = "T2SOImmNeg"; } 117def t2_so_imm_neg : Operand<i32>, ImmLeaf<i32, [{ 118 return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1; 119}], t2_so_imm_neg_XFORM> { 120 let ParserMatchClass = t2_so_imm_neg_asmoperand; 121} 122 123/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0,4095]. 124def imm0_4095_asmoperand: ImmAsmOperand<0,4095> { let Name = "Imm0_4095"; } 125def imm0_4095 : Operand<i32>, ImmLeaf<i32, [{ 126 return Imm >= 0 && Imm < 4096; 127}]> { 128 let ParserMatchClass = imm0_4095_asmoperand; 129} 130 131def imm0_4095_neg_asmoperand: AsmOperandClass { let Name = "Imm0_4095Neg"; } 132def imm0_4095_neg : Operand<i32>, PatLeaf<(i32 imm), [{ 133 return (uint32_t)(-N->getZExtValue()) < 4096; 134}], imm_neg_XFORM> { 135 let ParserMatchClass = imm0_4095_neg_asmoperand; 136} 137 138def imm1_255_neg : PatLeaf<(i32 imm), [{ 139 uint32_t Val = -N->getZExtValue(); 140 return (Val > 0 && Val < 255); 141}], imm_neg_XFORM>; 142 143def imm0_255_not : PatLeaf<(i32 imm), [{ 144 return (uint32_t)(~N->getZExtValue()) < 255; 145}], imm_not_XFORM>; 146 147def lo5AllOne : PatLeaf<(i32 imm), [{ 148 // Returns true if all low 5-bits are 1. 149 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL; 150}]>; 151 152// Define Thumb2 specific addressing modes. 153 154// t2addrmode_imm12 := reg + imm12 155def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";} 156def t2addrmode_imm12 : MemOperand, 157 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> { 158 let PrintMethod = "printAddrModeImm12Operand<false>"; 159 let EncoderMethod = "getAddrModeImm12OpValue"; 160 let DecoderMethod = "DecodeT2AddrModeImm12"; 161 let ParserMatchClass = t2addrmode_imm12_asmoperand; 162 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 163} 164 165// t2ldrlabel := imm12 166def t2ldrlabel : Operand<i32> { 167 let EncoderMethod = "getAddrModeImm12OpValue"; 168 let PrintMethod = "printThumbLdrLabelOperand"; 169} 170 171def t2ldr_pcrel_imm12_asmoperand : AsmOperandClass {let Name = "MemPCRelImm12";} 172def t2ldr_pcrel_imm12 : Operand<i32> { 173 let ParserMatchClass = t2ldr_pcrel_imm12_asmoperand; 174 // used for assembler pseudo instruction and maps to t2ldrlabel, so 175 // doesn't need encoder or print methods of its own. 176} 177 178// ADR instruction labels. 179def t2adrlabel : Operand<i32> { 180 let EncoderMethod = "getT2AdrLabelOpValue"; 181 let PrintMethod = "printAdrLabelOperand<0>"; 182} 183 184// t2addrmode_posimm8 := reg + imm8 185def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";} 186def t2addrmode_posimm8 : MemOperand { 187 let PrintMethod = "printT2AddrModeImm8Operand<false>"; 188 let EncoderMethod = "getT2AddrModeImm8OpValue"; 189 let DecoderMethod = "DecodeT2AddrModeImm8"; 190 let ParserMatchClass = MemPosImm8OffsetAsmOperand; 191 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 192} 193 194// t2addrmode_negimm8 := reg - imm8 195def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";} 196def t2addrmode_negimm8 : MemOperand, 197 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> { 198 let PrintMethod = "printT2AddrModeImm8Operand<false>"; 199 let EncoderMethod = "getT2AddrModeImm8OpValue"; 200 let DecoderMethod = "DecodeT2AddrModeImm8"; 201 let ParserMatchClass = MemNegImm8OffsetAsmOperand; 202 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 203} 204 205// t2addrmode_imm8 := reg +/- imm8 206def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; } 207class T2AddrMode_Imm8 : MemOperand, 208 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> { 209 let EncoderMethod = "getT2AddrModeImm8OpValue"; 210 let DecoderMethod = "DecodeT2AddrModeImm8"; 211 let ParserMatchClass = MemImm8OffsetAsmOperand; 212 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 213} 214 215def t2addrmode_imm8 : T2AddrMode_Imm8 { 216 let PrintMethod = "printT2AddrModeImm8Operand<false>"; 217} 218 219def t2addrmode_imm8_pre : T2AddrMode_Imm8 { 220 let PrintMethod = "printT2AddrModeImm8Operand<true>"; 221} 222 223def t2am_imm8_offset : MemOperand, 224 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", 225 [], [SDNPWantRoot]> { 226 let PrintMethod = "printT2AddrModeImm8OffsetOperand"; 227 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue"; 228 let DecoderMethod = "DecodeT2Imm8"; 229} 230 231// t2addrmode_imm8s4 := reg +/- (imm8 << 2) 232def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";} 233class T2AddrMode_Imm8s4 : MemOperand { 234 let EncoderMethod = "getT2AddrModeImm8s4OpValue"; 235 let DecoderMethod = "DecodeT2AddrModeImm8s4"; 236 let ParserMatchClass = MemImm8s4OffsetAsmOperand; 237 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 238} 239 240def t2addrmode_imm8s4 : T2AddrMode_Imm8s4 { 241 let PrintMethod = "printT2AddrModeImm8s4Operand<false>"; 242} 243 244def t2addrmode_imm8s4_pre : T2AddrMode_Imm8s4 { 245 let PrintMethod = "printT2AddrModeImm8s4Operand<true>"; 246} 247 248def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; } 249def t2am_imm8s4_offset : MemOperand { 250 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand"; 251 let EncoderMethod = "getT2Imm8s4OpValue"; 252 let DecoderMethod = "DecodeT2Imm8S4"; 253} 254 255// t2addrmode_imm0_1020s4 := reg + (imm8 << 2) 256def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass { 257 let Name = "MemImm0_1020s4Offset"; 258} 259def t2addrmode_imm0_1020s4 : MemOperand, 260 ComplexPattern<i32, 2, "SelectT2AddrModeExclusive"> { 261 let PrintMethod = "printT2AddrModeImm0_1020s4Operand"; 262 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue"; 263 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4"; 264 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand; 265 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm); 266} 267 268// t2addrmode_so_reg := reg + (reg << imm2) 269def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";} 270def t2addrmode_so_reg : MemOperand, 271 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> { 272 let PrintMethod = "printT2AddrModeSoRegOperand"; 273 let EncoderMethod = "getT2AddrModeSORegOpValue"; 274 let DecoderMethod = "DecodeT2AddrModeSOReg"; 275 let ParserMatchClass = t2addrmode_so_reg_asmoperand; 276 let MIOperandInfo = (ops GPRnopc:$base, rGPR:$offsreg, i32imm:$offsimm); 277} 278 279// Addresses for the TBB/TBH instructions. 280def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; } 281def addrmode_tbb : MemOperand { 282 let PrintMethod = "printAddrModeTBB"; 283 let ParserMatchClass = addrmode_tbb_asmoperand; 284 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm); 285} 286def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; } 287def addrmode_tbh : MemOperand { 288 let PrintMethod = "printAddrModeTBH"; 289 let ParserMatchClass = addrmode_tbh_asmoperand; 290 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm); 291} 292 293//===----------------------------------------------------------------------===// 294// Multiclass helpers... 295// 296 297 298class T2OneRegImm<dag oops, dag iops, InstrItinClass itin, 299 string opc, string asm, list<dag> pattern> 300 : T2I<oops, iops, itin, opc, asm, pattern> { 301 bits<4> Rd; 302 bits<12> imm; 303 304 let Inst{11-8} = Rd; 305 let Inst{26} = imm{11}; 306 let Inst{14-12} = imm{10-8}; 307 let Inst{7-0} = imm{7-0}; 308} 309 310 311class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin, 312 string opc, string asm, list<dag> pattern> 313 : T2sI<oops, iops, itin, opc, asm, pattern> { 314 bits<4> Rd; 315 bits<4> Rn; 316 bits<12> imm; 317 318 let Inst{11-8} = Rd; 319 let Inst{26} = imm{11}; 320 let Inst{14-12} = imm{10-8}; 321 let Inst{7-0} = imm{7-0}; 322} 323 324class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin, 325 string opc, string asm, list<dag> pattern> 326 : T2I<oops, iops, itin, opc, asm, pattern> { 327 bits<4> Rn; 328 bits<12> imm; 329 330 let Inst{19-16} = Rn; 331 let Inst{26} = imm{11}; 332 let Inst{14-12} = imm{10-8}; 333 let Inst{7-0} = imm{7-0}; 334} 335 336 337class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin, 338 string opc, string asm, list<dag> pattern> 339 : T2I<oops, iops, itin, opc, asm, pattern> { 340 bits<4> Rd; 341 bits<12> ShiftedRm; 342 343 let Inst{11-8} = Rd; 344 let Inst{3-0} = ShiftedRm{3-0}; 345 let Inst{5-4} = ShiftedRm{6-5}; 346 let Inst{14-12} = ShiftedRm{11-9}; 347 let Inst{7-6} = ShiftedRm{8-7}; 348} 349 350class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin, 351 string opc, string asm, list<dag> pattern> 352 : T2sI<oops, iops, itin, opc, asm, pattern> { 353 bits<4> Rd; 354 bits<12> ShiftedRm; 355 356 let Inst{11-8} = Rd; 357 let Inst{3-0} = ShiftedRm{3-0}; 358 let Inst{5-4} = ShiftedRm{6-5}; 359 let Inst{14-12} = ShiftedRm{11-9}; 360 let Inst{7-6} = ShiftedRm{8-7}; 361} 362 363class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin, 364 string opc, string asm, list<dag> pattern> 365 : T2I<oops, iops, itin, opc, asm, pattern> { 366 bits<4> Rn; 367 bits<12> ShiftedRm; 368 369 let Inst{19-16} = Rn; 370 let Inst{3-0} = ShiftedRm{3-0}; 371 let Inst{5-4} = ShiftedRm{6-5}; 372 let Inst{14-12} = ShiftedRm{11-9}; 373 let Inst{7-6} = ShiftedRm{8-7}; 374} 375 376class T2TwoReg<dag oops, dag iops, InstrItinClass itin, 377 string opc, string asm, list<dag> pattern> 378 : T2I<oops, iops, itin, opc, asm, pattern> { 379 bits<4> Rd; 380 bits<4> Rm; 381 382 let Inst{11-8} = Rd; 383 let Inst{3-0} = Rm; 384} 385 386class T2sTwoReg<dag oops, dag iops, InstrItinClass itin, 387 string opc, string asm, list<dag> pattern> 388 : T2sI<oops, iops, itin, opc, asm, pattern> { 389 bits<4> Rd; 390 bits<4> Rm; 391 392 let Inst{11-8} = Rd; 393 let Inst{3-0} = Rm; 394} 395 396class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin, 397 string opc, string asm, list<dag> pattern> 398 : T2I<oops, iops, itin, opc, asm, pattern> { 399 bits<4> Rn; 400 bits<4> Rm; 401 402 let Inst{19-16} = Rn; 403 let Inst{3-0} = Rm; 404} 405 406 407class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin, 408 string opc, string asm, list<dag> pattern> 409 : T2I<oops, iops, itin, opc, asm, pattern> { 410 bits<4> Rd; 411 bits<4> Rn; 412 bits<12> imm; 413 414 let Inst{11-8} = Rd; 415 let Inst{19-16} = Rn; 416 let Inst{26} = imm{11}; 417 let Inst{14-12} = imm{10-8}; 418 let Inst{7-0} = imm{7-0}; 419} 420 421class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin, 422 string opc, string asm, list<dag> pattern> 423 : T2sI<oops, iops, itin, opc, asm, pattern> { 424 bits<4> Rd; 425 bits<4> Rn; 426 bits<12> imm; 427 428 let Inst{11-8} = Rd; 429 let Inst{19-16} = Rn; 430 let Inst{26} = imm{11}; 431 let Inst{14-12} = imm{10-8}; 432 let Inst{7-0} = imm{7-0}; 433} 434 435class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin, 436 string opc, string asm, list<dag> pattern> 437 : T2I<oops, iops, itin, opc, asm, pattern> { 438 bits<4> Rd; 439 bits<4> Rm; 440 bits<5> imm; 441 442 let Inst{11-8} = Rd; 443 let Inst{3-0} = Rm; 444 let Inst{14-12} = imm{4-2}; 445 let Inst{7-6} = imm{1-0}; 446} 447 448class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin, 449 string opc, string asm, list<dag> pattern> 450 : T2sI<oops, iops, itin, opc, asm, pattern> { 451 bits<4> Rd; 452 bits<4> Rm; 453 bits<5> imm; 454 455 let Inst{11-8} = Rd; 456 let Inst{3-0} = Rm; 457 let Inst{14-12} = imm{4-2}; 458 let Inst{7-6} = imm{1-0}; 459} 460 461class T2ThreeReg<dag oops, dag iops, InstrItinClass itin, 462 string opc, string asm, list<dag> pattern> 463 : T2I<oops, iops, itin, opc, asm, pattern> { 464 bits<4> Rd; 465 bits<4> Rn; 466 bits<4> Rm; 467 468 let Inst{11-8} = Rd; 469 let Inst{19-16} = Rn; 470 let Inst{3-0} = Rm; 471} 472 473class T2ThreeRegNoP<dag oops, dag iops, InstrItinClass itin, 474 string asm, list<dag> pattern> 475 : T2XI<oops, iops, itin, asm, pattern> { 476 bits<4> Rd; 477 bits<4> Rn; 478 bits<4> Rm; 479 480 let Inst{11-8} = Rd; 481 let Inst{19-16} = Rn; 482 let Inst{3-0} = Rm; 483} 484 485class T2sThreeReg<dag oops, dag iops, InstrItinClass itin, 486 string opc, string asm, list<dag> pattern> 487 : T2sI<oops, iops, itin, opc, asm, pattern> { 488 bits<4> Rd; 489 bits<4> Rn; 490 bits<4> Rm; 491 492 let Inst{11-8} = Rd; 493 let Inst{19-16} = Rn; 494 let Inst{3-0} = Rm; 495} 496 497class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin, 498 string opc, string asm, list<dag> pattern> 499 : T2I<oops, iops, itin, opc, asm, pattern> { 500 bits<4> Rd; 501 bits<4> Rn; 502 bits<12> ShiftedRm; 503 504 let Inst{11-8} = Rd; 505 let Inst{19-16} = Rn; 506 let Inst{3-0} = ShiftedRm{3-0}; 507 let Inst{5-4} = ShiftedRm{6-5}; 508 let Inst{14-12} = ShiftedRm{11-9}; 509 let Inst{7-6} = ShiftedRm{8-7}; 510} 511 512class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin, 513 string opc, string asm, list<dag> pattern> 514 : T2sI<oops, iops, itin, opc, asm, pattern> { 515 bits<4> Rd; 516 bits<4> Rn; 517 bits<12> ShiftedRm; 518 519 let Inst{11-8} = Rd; 520 let Inst{19-16} = Rn; 521 let Inst{3-0} = ShiftedRm{3-0}; 522 let Inst{5-4} = ShiftedRm{6-5}; 523 let Inst{14-12} = ShiftedRm{11-9}; 524 let Inst{7-6} = ShiftedRm{8-7}; 525} 526 527class T2FourReg<dag oops, dag iops, InstrItinClass itin, 528 string opc, string asm, list<dag> pattern> 529 : T2I<oops, iops, itin, opc, asm, pattern> { 530 bits<4> Rd; 531 bits<4> Rn; 532 bits<4> Rm; 533 bits<4> Ra; 534 535 let Inst{19-16} = Rn; 536 let Inst{15-12} = Ra; 537 let Inst{11-8} = Rd; 538 let Inst{3-0} = Rm; 539} 540 541class T2MulLong<bits<3> opc22_20, bits<4> opc7_4, 542 string opc, list<dag> pattern> 543 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64, 544 opc, "\t$RdLo, $RdHi, $Rn, $Rm", pattern>, 545 Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]> { 546 bits<4> RdLo; 547 bits<4> RdHi; 548 bits<4> Rn; 549 bits<4> Rm; 550 551 let Inst{31-23} = 0b111110111; 552 let Inst{22-20} = opc22_20; 553 let Inst{19-16} = Rn; 554 let Inst{15-12} = RdLo; 555 let Inst{11-8} = RdHi; 556 let Inst{7-4} = opc7_4; 557 let Inst{3-0} = Rm; 558} 559class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4, string opc> 560 : T2I<(outs rGPR:$RdLo, rGPR:$RdHi), 561 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64, 562 opc, "\t$RdLo, $RdHi, $Rn, $Rm", []>, 563 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, 564 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]> { 565 bits<4> RdLo; 566 bits<4> RdHi; 567 bits<4> Rn; 568 bits<4> Rm; 569 570 let Inst{31-23} = 0b111110111; 571 let Inst{22-20} = opc22_20; 572 let Inst{19-16} = Rn; 573 let Inst{15-12} = RdLo; 574 let Inst{11-8} = RdHi; 575 let Inst{7-4} = opc7_4; 576 let Inst{3-0} = Rm; 577} 578 579 580/// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 581/// binary operation that produces a value. These are predicable and can be 582/// changed to modify CPSR. 583multiclass T2I_bin_irs<bits<4> opcod, string opc, 584 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 585 SDPatternOperator opnode, bit Commutable = 0, 586 string wide = ""> { 587 // shifted imm 588 def ri : T2sTwoRegImm< 589 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii, 590 opc, "\t$Rd, $Rn, $imm", 591 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>, 592 Sched<[WriteALU, ReadALU]> { 593 let Inst{31-27} = 0b11110; 594 let Inst{25} = 0; 595 let Inst{24-21} = opcod; 596 let Inst{15} = 0; 597 } 598 // register 599 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir, 600 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"), 601 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>, 602 Sched<[WriteALU, ReadALU, ReadALU]> { 603 let isCommutable = Commutable; 604 let Inst{31-27} = 0b11101; 605 let Inst{26-25} = 0b01; 606 let Inst{24-21} = opcod; 607 let Inst{14-12} = 0b000; // imm3 608 let Inst{7-6} = 0b00; // imm2 609 let Inst{5-4} = 0b00; // type 610 } 611 // shifted register 612 def rs : T2sTwoRegShiftedReg< 613 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis, 614 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"), 615 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>, 616 Sched<[WriteALUsi, ReadALU]> { 617 let Inst{31-27} = 0b11101; 618 let Inst{26-25} = 0b01; 619 let Inst{24-21} = opcod; 620 } 621 // Assembly aliases for optional destination operand when it's the same 622 // as the source operand. 623 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"), 624 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, 625 t2_so_imm:$imm, pred:$p, 626 cc_out:$s)>; 627 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"), 628 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, 629 rGPR:$Rm, pred:$p, 630 cc_out:$s)>; 631 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"), 632 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn, 633 t2_so_reg:$shift, pred:$p, 634 cc_out:$s)>; 635} 636 637/// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need 638// the ".w" suffix to indicate that they are wide. 639multiclass T2I_bin_w_irs<bits<4> opcod, string opc, 640 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 641 SDPatternOperator opnode, bit Commutable = 0> : 642 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, Commutable, ".w"> { 643 // Assembler aliases w/ the ".w" suffix. 644 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"), 645 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, 646 cc_out:$s)>; 647 // Assembler aliases w/o the ".w" suffix. 648 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"), 649 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, 650 cc_out:$s)>; 651 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"), 652 (!cast<Instruction>(NAME#"rs") rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift, 653 pred:$p, cc_out:$s)>; 654 655 // and with the optional destination operand, too. 656 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rdn, $imm"), 657 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, 658 pred:$p, cc_out:$s)>; 659 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"), 660 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, 661 cc_out:$s)>; 662 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"), 663 (!cast<Instruction>(NAME#"rs") rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$shift, 664 pred:$p, cc_out:$s)>; 665} 666 667/// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are 668/// reversed. The 'rr' form is only defined for the disassembler; for codegen 669/// it is equivalent to the T2I_bin_irs counterpart. 670multiclass T2I_rbin_irs<bits<4> opcod, string opc, SDNode opnode> { 671 // shifted imm 672 def ri : T2sTwoRegImm< 673 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi, 674 opc, ".w\t$Rd, $Rn, $imm", 675 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]>, 676 Sched<[WriteALU, ReadALU]> { 677 let Inst{31-27} = 0b11110; 678 let Inst{25} = 0; 679 let Inst{24-21} = opcod; 680 let Inst{15} = 0; 681 } 682 // register 683 def rr : T2sThreeReg< 684 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr, 685 opc, "\t$Rd, $Rn, $Rm", 686 [/* For disassembly only; pattern left blank */]>, 687 Sched<[WriteALU, ReadALU, ReadALU]> { 688 let Inst{31-27} = 0b11101; 689 let Inst{26-25} = 0b01; 690 let Inst{24-21} = opcod; 691 let Inst{14-12} = 0b000; // imm3 692 let Inst{7-6} = 0b00; // imm2 693 let Inst{5-4} = 0b00; // type 694 } 695 // shifted register 696 def rs : T2sTwoRegShiftedReg< 697 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), 698 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm", 699 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]>, 700 Sched<[WriteALUsi, ReadALU]> { 701 let Inst{31-27} = 0b11101; 702 let Inst{26-25} = 0b01; 703 let Inst{24-21} = opcod; 704 } 705} 706 707/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the 708/// instruction modifies the CPSR register. 709/// 710/// These opcodes will be converted to the real non-S opcodes by 711/// AdjustInstrPostInstrSelection after giving then an optional CPSR operand. 712let hasPostISelHook = 1, Defs = [CPSR] in { 713multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir, 714 InstrItinClass iis, SDNode opnode, 715 bit Commutable = 0> { 716 // shifted imm 717 def ri : t2PseudoInst<(outs rGPR:$Rd), 718 (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p), 719 4, iii, 720 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn, 721 t2_so_imm:$imm))]>, 722 Sched<[WriteALU, ReadALU]>; 723 // register 724 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p), 725 4, iir, 726 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn, 727 rGPR:$Rm))]>, 728 Sched<[WriteALU, ReadALU, ReadALU]> { 729 let isCommutable = Commutable; 730 } 731 // shifted register 732 def rs : t2PseudoInst<(outs rGPR:$Rd), 733 (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p), 734 4, iis, 735 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn, 736 t2_so_reg:$ShiftedRm))]>, 737 Sched<[WriteALUsi, ReadALUsr]>; 738} 739} 740 741/// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG 742/// operands are reversed. 743let hasPostISelHook = 1, Defs = [CPSR] in { 744multiclass T2I_rbin_s_is<SDNode opnode> { 745 // shifted imm 746 def ri : t2PseudoInst<(outs rGPR:$Rd), 747 (ins rGPR:$Rn, t2_so_imm:$imm, pred:$p), 748 4, IIC_iALUi, 749 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm, 750 rGPR:$Rn))]>, 751 Sched<[WriteALU, ReadALU]>; 752 // shifted register 753 def rs : t2PseudoInst<(outs rGPR:$Rd), 754 (ins rGPR:$Rn, t2_so_reg:$ShiftedRm, pred:$p), 755 4, IIC_iALUsi, 756 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm, 757 rGPR:$Rn))]>, 758 Sched<[WriteALUsi, ReadALU]>; 759} 760} 761 762/// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg}) 763/// patterns for a binary operation that produces a value. 764multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, SDNode opnode, 765 bit Commutable = 0> { 766 // shifted imm 767 // The register-immediate version is re-materializable. This is useful 768 // in particular for taking the address of a local. 769 let isReMaterializable = 1 in { 770 def ri : T2sTwoRegImm< 771 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi, 772 opc, ".w\t$Rd, $Rn, $imm", 773 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]>, 774 Sched<[WriteALU, ReadALU]> { 775 let Inst{31-27} = 0b11110; 776 let Inst{25} = 0; 777 let Inst{24} = 1; 778 let Inst{23-21} = op23_21; 779 let Inst{15} = 0; 780 } 781 } 782 // 12-bit imm 783 def ri12 : T2I< 784 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi, 785 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm", 786 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]>, 787 Sched<[WriteALU, ReadALU]> { 788 bits<4> Rd; 789 bits<4> Rn; 790 bits<12> imm; 791 let Inst{31-27} = 0b11110; 792 let Inst{26} = imm{11}; 793 let Inst{25-24} = 0b10; 794 let Inst{23-21} = op23_21; 795 let Inst{20} = 0; // The S bit. 796 let Inst{19-16} = Rn; 797 let Inst{15} = 0; 798 let Inst{14-12} = imm{10-8}; 799 let Inst{11-8} = Rd; 800 let Inst{7-0} = imm{7-0}; 801 } 802 // register 803 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm), 804 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm", 805 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]>, 806 Sched<[WriteALU, ReadALU, ReadALU]> { 807 let isCommutable = Commutable; 808 let Inst{31-27} = 0b11101; 809 let Inst{26-25} = 0b01; 810 let Inst{24} = 1; 811 let Inst{23-21} = op23_21; 812 let Inst{14-12} = 0b000; // imm3 813 let Inst{7-6} = 0b00; // imm2 814 let Inst{5-4} = 0b00; // type 815 } 816 // shifted register 817 def rs : T2sTwoRegShiftedReg< 818 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), 819 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm", 820 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]>, 821 Sched<[WriteALUsi, ReadALU]> { 822 let Inst{31-27} = 0b11101; 823 let Inst{26-25} = 0b01; 824 let Inst{24} = 1; 825 let Inst{23-21} = op23_21; 826 } 827} 828 829/// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns 830/// for a binary operation that produces a value and use the carry 831/// bit. It's not predicable. 832let Defs = [CPSR], Uses = [CPSR] in { 833multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, SDNode opnode, 834 bit Commutable = 0> { 835 // shifted imm 836 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), 837 IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 838 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>, 839 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> { 840 let Inst{31-27} = 0b11110; 841 let Inst{25} = 0; 842 let Inst{24-21} = opcod; 843 let Inst{15} = 0; 844 } 845 // register 846 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr, 847 opc, ".w\t$Rd, $Rn, $Rm", 848 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>, 849 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU, ReadALU]> { 850 let isCommutable = Commutable; 851 let Inst{31-27} = 0b11101; 852 let Inst{26-25} = 0b01; 853 let Inst{24-21} = opcod; 854 let Inst{14-12} = 0b000; // imm3 855 let Inst{7-6} = 0b00; // imm2 856 let Inst{5-4} = 0b00; // type 857 } 858 // shifted register 859 def rs : T2sTwoRegShiftedReg< 860 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), 861 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm", 862 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>, 863 Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> { 864 let Inst{31-27} = 0b11101; 865 let Inst{26-25} = 0b01; 866 let Inst{24-21} = opcod; 867 } 868} 869} 870 871/// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift / 872// rotate operation that produces a value. 873multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, SDNode opnode> { 874 // 5-bit imm 875 def ri : T2sTwoRegShiftImm< 876 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi, 877 opc, ".w\t$Rd, $Rm, $imm", 878 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]>, 879 Sched<[WriteALU]> { 880 let Inst{31-27} = 0b11101; 881 let Inst{26-21} = 0b010010; 882 let Inst{19-16} = 0b1111; // Rn 883 let Inst{5-4} = opcod; 884 } 885 // register 886 def rr : T2sThreeReg< 887 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr, 888 opc, ".w\t$Rd, $Rn, $Rm", 889 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>, 890 Sched<[WriteALU]> { 891 let Inst{31-27} = 0b11111; 892 let Inst{26-23} = 0b0100; 893 let Inst{22-21} = opcod; 894 let Inst{15-12} = 0b1111; 895 let Inst{7-4} = 0b0000; 896 } 897 898 // Optional destination register 899 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"), 900 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p, 901 cc_out:$s)>; 902 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"), 903 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, 904 cc_out:$s)>; 905 906 // Assembler aliases w/o the ".w" suffix. 907 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"), 908 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, ty:$imm, pred:$p, 909 cc_out:$s)>; 910 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"), 911 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, 912 cc_out:$s)>; 913 914 // and with the optional destination operand, too. 915 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"), 916 (!cast<Instruction>(NAME#"ri") rGPR:$Rdn, rGPR:$Rdn, ty:$imm, pred:$p, 917 cc_out:$s)>; 918 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"), 919 (!cast<Instruction>(NAME#"rr") rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, 920 cc_out:$s)>; 921} 922 923/// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 924/// patterns. Similar to T2I_bin_irs except the instruction does not produce 925/// a explicit result, only implicitly set CPSR. 926multiclass T2I_cmp_irs<bits<4> opcod, string opc, 927 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 928 SDPatternOperator opnode> { 929let isCompare = 1, Defs = [CPSR] in { 930 // shifted imm 931 def ri : T2OneRegCmpImm< 932 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii, 933 opc, ".w\t$Rn, $imm", 934 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]>, Sched<[WriteCMP]> { 935 let Inst{31-27} = 0b11110; 936 let Inst{25} = 0; 937 let Inst{24-21} = opcod; 938 let Inst{20} = 1; // The S bit. 939 let Inst{15} = 0; 940 let Inst{11-8} = 0b1111; // Rd 941 } 942 // register 943 def rr : T2TwoRegCmp< 944 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir, 945 opc, ".w\t$Rn, $Rm", 946 [(opnode GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP]> { 947 let Inst{31-27} = 0b11101; 948 let Inst{26-25} = 0b01; 949 let Inst{24-21} = opcod; 950 let Inst{20} = 1; // The S bit. 951 let Inst{14-12} = 0b000; // imm3 952 let Inst{11-8} = 0b1111; // Rd 953 let Inst{7-6} = 0b00; // imm2 954 let Inst{5-4} = 0b00; // type 955 } 956 // shifted register 957 def rs : T2OneRegCmpShiftedReg< 958 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis, 959 opc, ".w\t$Rn, $ShiftedRm", 960 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>, 961 Sched<[WriteCMPsi]> { 962 let Inst{31-27} = 0b11101; 963 let Inst{26-25} = 0b01; 964 let Inst{24-21} = opcod; 965 let Inst{20} = 1; // The S bit. 966 let Inst{11-8} = 0b1111; // Rd 967 } 968} 969 970 // Assembler aliases w/o the ".w" suffix. 971 // No alias here for 'rr' version as not all instantiations of this 972 // multiclass want one (CMP in particular, does not). 973 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"), 974 (!cast<Instruction>(NAME#"ri") GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>; 975 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"), 976 (!cast<Instruction>(NAME#"rs") GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>; 977} 978 979/// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns. 980multiclass T2I_ld<bit signed, bits<2> opcod, string opc, 981 InstrItinClass iii, InstrItinClass iis, RegisterClass target, 982 PatFrag opnode> { 983 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii, 984 opc, ".w\t$Rt, $addr", 985 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]>, 986 Sched<[WriteLd]> { 987 bits<4> Rt; 988 bits<17> addr; 989 let Inst{31-25} = 0b1111100; 990 let Inst{24} = signed; 991 let Inst{23} = 1; 992 let Inst{22-21} = opcod; 993 let Inst{20} = 1; // load 994 let Inst{19-16} = addr{16-13}; // Rn 995 let Inst{15-12} = Rt; 996 let Inst{11-0} = addr{11-0}; // imm 997 998 let DecoderMethod = "DecodeT2LoadImm12"; 999 } 1000 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii, 1001 opc, "\t$Rt, $addr", 1002 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]>, 1003 Sched<[WriteLd]> { 1004 bits<4> Rt; 1005 bits<13> addr; 1006 let Inst{31-27} = 0b11111; 1007 let Inst{26-25} = 0b00; 1008 let Inst{24} = signed; 1009 let Inst{23} = 0; 1010 let Inst{22-21} = opcod; 1011 let Inst{20} = 1; // load 1012 let Inst{19-16} = addr{12-9}; // Rn 1013 let Inst{15-12} = Rt; 1014 let Inst{11} = 1; 1015 // Offset: index==TRUE, wback==FALSE 1016 let Inst{10} = 1; // The P bit. 1017 let Inst{9} = addr{8}; // U 1018 let Inst{8} = 0; // The W bit. 1019 let Inst{7-0} = addr{7-0}; // imm 1020 1021 let DecoderMethod = "DecodeT2LoadImm8"; 1022 } 1023 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis, 1024 opc, ".w\t$Rt, $addr", 1025 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]>, 1026 Sched<[WriteLd]> { 1027 let Inst{31-27} = 0b11111; 1028 let Inst{26-25} = 0b00; 1029 let Inst{24} = signed; 1030 let Inst{23} = 0; 1031 let Inst{22-21} = opcod; 1032 let Inst{20} = 1; // load 1033 let Inst{11-6} = 0b000000; 1034 1035 bits<4> Rt; 1036 let Inst{15-12} = Rt; 1037 1038 bits<10> addr; 1039 let Inst{19-16} = addr{9-6}; // Rn 1040 let Inst{3-0} = addr{5-2}; // Rm 1041 let Inst{5-4} = addr{1-0}; // imm 1042 1043 let DecoderMethod = "DecodeT2LoadShift"; 1044 } 1045 1046 // pci variant is very similar to i12, but supports negative offsets 1047 // from the PC. 1048 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii, 1049 opc, ".w\t$Rt, $addr", 1050 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]>, 1051 Sched<[WriteLd]> { 1052 let isReMaterializable = 1; 1053 let Inst{31-27} = 0b11111; 1054 let Inst{26-25} = 0b00; 1055 let Inst{24} = signed; 1056 let Inst{22-21} = opcod; 1057 let Inst{20} = 1; // load 1058 let Inst{19-16} = 0b1111; // Rn 1059 1060 bits<4> Rt; 1061 let Inst{15-12} = Rt{3-0}; 1062 1063 bits<13> addr; 1064 let Inst{23} = addr{12}; // add = (U == '1') 1065 let Inst{11-0} = addr{11-0}; 1066 1067 let DecoderMethod = "DecodeT2LoadLabel"; 1068 } 1069} 1070 1071/// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns. 1072multiclass T2I_st<bits<2> opcod, string opc, 1073 InstrItinClass iii, InstrItinClass iis, RegisterClass target, 1074 PatFrag opnode> { 1075 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii, 1076 opc, ".w\t$Rt, $addr", 1077 [(opnode target:$Rt, t2addrmode_imm12:$addr)]>, 1078 Sched<[WriteST]> { 1079 let Inst{31-27} = 0b11111; 1080 let Inst{26-23} = 0b0001; 1081 let Inst{22-21} = opcod; 1082 let Inst{20} = 0; // !load 1083 1084 bits<4> Rt; 1085 let Inst{15-12} = Rt; 1086 1087 bits<17> addr; 1088 let addr{12} = 1; // add = TRUE 1089 let Inst{19-16} = addr{16-13}; // Rn 1090 let Inst{23} = addr{12}; // U 1091 let Inst{11-0} = addr{11-0}; // imm 1092 } 1093 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii, 1094 opc, "\t$Rt, $addr", 1095 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]>, 1096 Sched<[WriteST]> { 1097 let Inst{31-27} = 0b11111; 1098 let Inst{26-23} = 0b0000; 1099 let Inst{22-21} = opcod; 1100 let Inst{20} = 0; // !load 1101 let Inst{11} = 1; 1102 // Offset: index==TRUE, wback==FALSE 1103 let Inst{10} = 1; // The P bit. 1104 let Inst{8} = 0; // The W bit. 1105 1106 bits<4> Rt; 1107 let Inst{15-12} = Rt; 1108 1109 bits<13> addr; 1110 let Inst{19-16} = addr{12-9}; // Rn 1111 let Inst{9} = addr{8}; // U 1112 let Inst{7-0} = addr{7-0}; // imm 1113 } 1114 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis, 1115 opc, ".w\t$Rt, $addr", 1116 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]>, 1117 Sched<[WriteST]> { 1118 let Inst{31-27} = 0b11111; 1119 let Inst{26-23} = 0b0000; 1120 let Inst{22-21} = opcod; 1121 let Inst{20} = 0; // !load 1122 let Inst{11-6} = 0b000000; 1123 1124 bits<4> Rt; 1125 let Inst{15-12} = Rt; 1126 1127 bits<10> addr; 1128 let Inst{19-16} = addr{9-6}; // Rn 1129 let Inst{3-0} = addr{5-2}; // Rm 1130 let Inst{5-4} = addr{1-0}; // imm 1131 } 1132} 1133 1134/// T2I_ext_rrot - A unary operation with two forms: one whose operand is a 1135/// register and one whose operand is a register rotated by 8/16/24. 1136class T2I_ext_rrot_base<bits<3> opcod, dag iops, dag oops, 1137 string opc, string oprs, 1138 list<dag> pattern> 1139 : T2TwoReg<iops, oops, IIC_iEXTr, opc, oprs, pattern> { 1140 bits<2> rot; 1141 let Inst{31-27} = 0b11111; 1142 let Inst{26-23} = 0b0100; 1143 let Inst{22-20} = opcod; 1144 let Inst{19-16} = 0b1111; // Rn 1145 let Inst{15-12} = 0b1111; 1146 let Inst{7} = 1; 1147 let Inst{5-4} = rot; // rotate 1148} 1149 1150class T2I_ext_rrot<bits<3> opcod, string opc> 1151 : T2I_ext_rrot_base<opcod, 1152 (outs rGPR:$Rd), 1153 (ins rGPR:$Rm, rot_imm:$rot), 1154 opc, ".w\t$Rd, $Rm$rot", []>, 1155 Requires<[IsThumb2]>, 1156 Sched<[WriteALU, ReadALU]>; 1157 1158// UXTB16, SXTB16 - Requires HasDSP, does not need the .w qualifier. 1159class T2I_ext_rrot_xtb16<bits<3> opcod, string opc> 1160 : T2I_ext_rrot_base<opcod, 1161 (outs rGPR:$Rd), 1162 (ins rGPR:$Rm, rot_imm:$rot), 1163 opc, "\t$Rd, $Rm$rot", []>, 1164 Requires<[HasDSP, IsThumb2]>, 1165 Sched<[WriteALU, ReadALU]>; 1166 1167/// T2I_exta_rrot - A binary operation with two forms: one whose operand is a 1168/// register and one whose operand is a register rotated by 8/16/24. 1169class T2I_exta_rrot<bits<3> opcod, string opc> 1170 : T2ThreeReg<(outs rGPR:$Rd), 1171 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot), 1172 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []>, 1173 Requires<[HasDSP, IsThumb2]>, 1174 Sched<[WriteALU, ReadALU]> { 1175 bits<2> rot; 1176 let Inst{31-27} = 0b11111; 1177 let Inst{26-23} = 0b0100; 1178 let Inst{22-20} = opcod; 1179 let Inst{15-12} = 0b1111; 1180 let Inst{7} = 1; 1181 let Inst{5-4} = rot; 1182} 1183 1184//===----------------------------------------------------------------------===// 1185// Instructions 1186//===----------------------------------------------------------------------===// 1187 1188//===----------------------------------------------------------------------===// 1189// Miscellaneous Instructions. 1190// 1191 1192class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin, 1193 string asm, list<dag> pattern> 1194 : T2XI<oops, iops, itin, asm, pattern> { 1195 bits<4> Rd; 1196 bits<12> label; 1197 1198 let Inst{11-8} = Rd; 1199 let Inst{26} = label{11}; 1200 let Inst{14-12} = label{10-8}; 1201 let Inst{7-0} = label{7-0}; 1202} 1203 1204// LEApcrel - Load a pc-relative address into a register without offending the 1205// assembler. 1206def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd), 1207 (ins t2adrlabel:$addr, pred:$p), 1208 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []>, 1209 Sched<[WriteALU, ReadALU]> { 1210 let Inst{31-27} = 0b11110; 1211 let Inst{25-24} = 0b10; 1212 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE) 1213 let Inst{22} = 0; 1214 let Inst{20} = 0; 1215 let Inst{19-16} = 0b1111; // Rn 1216 let Inst{15} = 0; 1217 1218 bits<4> Rd; 1219 bits<13> addr; 1220 let Inst{11-8} = Rd; 1221 let Inst{23} = addr{12}; 1222 let Inst{21} = addr{12}; 1223 let Inst{26} = addr{11}; 1224 let Inst{14-12} = addr{10-8}; 1225 let Inst{7-0} = addr{7-0}; 1226 1227 let DecoderMethod = "DecodeT2Adr"; 1228} 1229 1230let hasSideEffects = 0, isReMaterializable = 1 in 1231def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p), 1232 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; 1233let hasSideEffects = 1 in 1234def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd), 1235 (ins i32imm:$label, pred:$p), 1236 4, IIC_iALUi, 1237 []>, Sched<[WriteALU, ReadALU]>; 1238 1239 1240//===----------------------------------------------------------------------===// 1241// Load / store Instructions. 1242// 1243 1244// Load 1245let canFoldAsLoad = 1, isReMaterializable = 1 in 1246defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR, load>; 1247 1248// Loads with zero extension 1249defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si, 1250 GPRnopc, zextloadi16>; 1251defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si, 1252 GPRnopc, zextloadi8>; 1253 1254// Loads with sign extension 1255defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si, 1256 GPRnopc, sextloadi16>; 1257defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si, 1258 GPRnopc, sextloadi8>; 1259 1260let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in { 1261// Load doubleword 1262def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2), 1263 (ins t2addrmode_imm8s4:$addr), 1264 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>, 1265 Sched<[WriteLd]>; 1266} // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 1267 1268// zextload i1 -> zextload i8 1269def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr), 1270 (t2LDRBi12 t2addrmode_imm12:$addr)>; 1271def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr), 1272 (t2LDRBi8 t2addrmode_negimm8:$addr)>; 1273def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr), 1274 (t2LDRBs t2addrmode_so_reg:$addr)>; 1275def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)), 1276 (t2LDRBpci tconstpool:$addr)>; 1277 1278// extload -> zextload 1279// FIXME: Reduce the number of patterns by legalizing extload to zextload 1280// earlier? 1281def : T2Pat<(extloadi1 t2addrmode_imm12:$addr), 1282 (t2LDRBi12 t2addrmode_imm12:$addr)>; 1283def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr), 1284 (t2LDRBi8 t2addrmode_negimm8:$addr)>; 1285def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr), 1286 (t2LDRBs t2addrmode_so_reg:$addr)>; 1287def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)), 1288 (t2LDRBpci tconstpool:$addr)>; 1289 1290def : T2Pat<(extloadi8 t2addrmode_imm12:$addr), 1291 (t2LDRBi12 t2addrmode_imm12:$addr)>; 1292def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr), 1293 (t2LDRBi8 t2addrmode_negimm8:$addr)>; 1294def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr), 1295 (t2LDRBs t2addrmode_so_reg:$addr)>; 1296def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)), 1297 (t2LDRBpci tconstpool:$addr)>; 1298 1299def : T2Pat<(extloadi16 t2addrmode_imm12:$addr), 1300 (t2LDRHi12 t2addrmode_imm12:$addr)>; 1301def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr), 1302 (t2LDRHi8 t2addrmode_negimm8:$addr)>; 1303def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr), 1304 (t2LDRHs t2addrmode_so_reg:$addr)>; 1305def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)), 1306 (t2LDRHpci tconstpool:$addr)>; 1307 1308// FIXME: The destination register of the loads and stores can't be PC, but 1309// can be SP. We need another regclass (similar to rGPR) to represent 1310// that. Not a pressing issue since these are selected manually, 1311// not via pattern. 1312 1313// Indexed loads 1314 1315let mayLoad = 1, hasSideEffects = 0 in { 1316def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 1317 (ins t2addrmode_imm8_pre:$addr), 1318 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu, 1319 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>, 1320 Sched<[WriteLd]>; 1321 1322def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 1323 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), 1324 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu, 1325 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>, 1326 Sched<[WriteLd]>; 1327 1328def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 1329 (ins t2addrmode_imm8_pre:$addr), 1330 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, 1331 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>, 1332 Sched<[WriteLd]>; 1333 1334def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 1335 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), 1336 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, 1337 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>; 1338 1339def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 1340 (ins t2addrmode_imm8_pre:$addr), 1341 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, 1342 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>, 1343 Sched<[WriteLd]>; 1344 1345def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 1346 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), 1347 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, 1348 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>, 1349 Sched<[WriteLd]>; 1350 1351def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 1352 (ins t2addrmode_imm8_pre:$addr), 1353 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, 1354 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", 1355 []>, Sched<[WriteLd]>; 1356 1357def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 1358 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), 1359 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, 1360 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>, 1361 Sched<[WriteLd]>; 1362 1363def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 1364 (ins t2addrmode_imm8_pre:$addr), 1365 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, 1366 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", 1367 []>, Sched<[WriteLd]>; 1368 1369def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 1370 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), 1371 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, 1372 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>, 1373 Sched<[WriteLd]>; 1374} // mayLoad = 1, hasSideEffects = 0 1375 1376// LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110). 1377// Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4 1378class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii> 1379 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc, 1380 "\t$Rt, $addr", []>, Sched<[WriteLd]> { 1381 bits<4> Rt; 1382 bits<13> addr; 1383 let Inst{31-27} = 0b11111; 1384 let Inst{26-25} = 0b00; 1385 let Inst{24} = signed; 1386 let Inst{23} = 0; 1387 let Inst{22-21} = type; 1388 let Inst{20} = 1; // load 1389 let Inst{19-16} = addr{12-9}; 1390 let Inst{15-12} = Rt; 1391 let Inst{11} = 1; 1392 let Inst{10-8} = 0b110; // PUW. 1393 let Inst{7-0} = addr{7-0}; 1394 1395 let DecoderMethod = "DecodeT2LoadT"; 1396} 1397 1398def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>; 1399def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>; 1400def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>; 1401def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>; 1402def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>; 1403 1404class T2Ildacq<bits<4> bits23_20, bits<2> bit54, dag oops, dag iops, 1405 string opc, string asm, list<dag> pattern> 1406 : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary, 1407 opc, asm, "", pattern>, Requires<[IsThumb, HasAcquireRelease]> { 1408 bits<4> Rt; 1409 bits<4> addr; 1410 1411 let Inst{31-27} = 0b11101; 1412 let Inst{26-24} = 0b000; 1413 let Inst{23-20} = bits23_20; 1414 let Inst{11-6} = 0b111110; 1415 let Inst{5-4} = bit54; 1416 let Inst{3-0} = 0b1111; 1417 1418 // Encode instruction operands 1419 let Inst{19-16} = addr; 1420 let Inst{15-12} = Rt; 1421} 1422 1423def t2LDA : T2Ildacq<0b1101, 0b10, (outs rGPR:$Rt), 1424 (ins addr_offset_none:$addr), "lda", "\t$Rt, $addr", []>, 1425 Sched<[WriteLd]>; 1426def t2LDAB : T2Ildacq<0b1101, 0b00, (outs rGPR:$Rt), 1427 (ins addr_offset_none:$addr), "ldab", "\t$Rt, $addr", []>, 1428 Sched<[WriteLd]>; 1429def t2LDAH : T2Ildacq<0b1101, 0b01, (outs rGPR:$Rt), 1430 (ins addr_offset_none:$addr), "ldah", "\t$Rt, $addr", []>, 1431 Sched<[WriteLd]>; 1432 1433// Store 1434defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR, store>; 1435defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si, 1436 rGPR, truncstorei8>; 1437defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si, 1438 rGPR, truncstorei16>; 1439 1440// Store doubleword 1441let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in 1442def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs), 1443 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr), 1444 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>, 1445 Sched<[WriteST]>; 1446 1447// Indexed stores 1448 1449let mayStore = 1, hasSideEffects = 0 in { 1450def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb), 1451 (ins GPRnopc:$Rt, t2addrmode_imm8_pre:$addr), 1452 AddrModeT2_i8, IndexModePre, IIC_iStore_iu, 1453 "str", "\t$Rt, $addr!", 1454 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>, 1455 Sched<[WriteST]>; 1456 1457def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb), 1458 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr), 1459 AddrModeT2_i8, IndexModePre, IIC_iStore_iu, 1460 "strh", "\t$Rt, $addr!", 1461 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>, 1462 Sched<[WriteST]>; 1463 1464def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb), 1465 (ins rGPR:$Rt, t2addrmode_imm8_pre:$addr), 1466 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu, 1467 "strb", "\t$Rt, $addr!", 1468 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>, 1469 Sched<[WriteST]>; 1470} // mayStore = 1, hasSideEffects = 0 1471 1472def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb), 1473 (ins GPRnopc:$Rt, addr_offset_none:$Rn, 1474 t2am_imm8_offset:$offset), 1475 AddrModeT2_i8, IndexModePost, IIC_iStore_iu, 1476 "str", "\t$Rt, $Rn$offset", 1477 "$Rn = $Rn_wb,@earlyclobber $Rn_wb", 1478 [(set GPRnopc:$Rn_wb, 1479 (post_store GPRnopc:$Rt, addr_offset_none:$Rn, 1480 t2am_imm8_offset:$offset))]>, 1481 Sched<[WriteST]>; 1482 1483def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb), 1484 (ins rGPR:$Rt, addr_offset_none:$Rn, 1485 t2am_imm8_offset:$offset), 1486 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu, 1487 "strh", "\t$Rt, $Rn$offset", 1488 "$Rn = $Rn_wb,@earlyclobber $Rn_wb", 1489 [(set GPRnopc:$Rn_wb, 1490 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn, 1491 t2am_imm8_offset:$offset))]>, 1492 Sched<[WriteST]>; 1493 1494def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb), 1495 (ins rGPR:$Rt, addr_offset_none:$Rn, 1496 t2am_imm8_offset:$offset), 1497 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu, 1498 "strb", "\t$Rt, $Rn$offset", 1499 "$Rn = $Rn_wb,@earlyclobber $Rn_wb", 1500 [(set GPRnopc:$Rn_wb, 1501 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn, 1502 t2am_imm8_offset:$offset))]>, 1503 Sched<[WriteST]>; 1504 1505// Pseudo-instructions for pattern matching the pre-indexed stores. We can't 1506// put the patterns on the instruction definitions directly as ISel wants 1507// the address base and offset to be separate operands, not a single 1508// complex operand like we represent the instructions themselves. The 1509// pseudos map between the two. 1510let usesCustomInserter = 1, 1511 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in { 1512def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb), 1513 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p), 1514 4, IIC_iStore_ru, 1515 [(set GPRnopc:$Rn_wb, 1516 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>, 1517 Sched<[WriteST]>; 1518def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb), 1519 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p), 1520 4, IIC_iStore_ru, 1521 [(set GPRnopc:$Rn_wb, 1522 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>, 1523 Sched<[WriteST]>; 1524def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb), 1525 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p), 1526 4, IIC_iStore_ru, 1527 [(set GPRnopc:$Rn_wb, 1528 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>, 1529 Sched<[WriteST]>; 1530} 1531 1532// STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly 1533// only. 1534// Ref: A8.6.193 STR (immediate, Thumb) Encoding T4 1535class T2IstT<bits<2> type, string opc, InstrItinClass ii> 1536 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc, 1537 "\t$Rt, $addr", []>, Sched<[WriteST]> { 1538 let Inst{31-27} = 0b11111; 1539 let Inst{26-25} = 0b00; 1540 let Inst{24} = 0; // not signed 1541 let Inst{23} = 0; 1542 let Inst{22-21} = type; 1543 let Inst{20} = 0; // store 1544 let Inst{11} = 1; 1545 let Inst{10-8} = 0b110; // PUW 1546 1547 bits<4> Rt; 1548 bits<13> addr; 1549 let Inst{15-12} = Rt; 1550 let Inst{19-16} = addr{12-9}; 1551 let Inst{7-0} = addr{7-0}; 1552} 1553 1554def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>; 1555def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>; 1556def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>; 1557 1558// ldrd / strd pre / post variants 1559 1560let mayLoad = 1 in 1561def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb), 1562 (ins t2addrmode_imm8s4_pre:$addr), IIC_iLoad_d_ru, 1563 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []>, 1564 Sched<[WriteLd]> { 1565 let DecoderMethod = "DecodeT2LDRDPreInstruction"; 1566} 1567 1568let mayLoad = 1 in 1569def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb), 1570 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm), 1571 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm", 1572 "$addr.base = $wb", []>, Sched<[WriteLd]>; 1573 1574let mayStore = 1 in 1575def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb), 1576 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr), 1577 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!", 1578 "$addr.base = $wb", []>, Sched<[WriteST]> { 1579 let DecoderMethod = "DecodeT2STRDPreInstruction"; 1580} 1581 1582let mayStore = 1 in 1583def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb), 1584 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr, 1585 t2am_imm8s4_offset:$imm), 1586 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm", 1587 "$addr.base = $wb", []>, Sched<[WriteST]>; 1588 1589class T2Istrrel<bits<2> bit54, dag oops, dag iops, 1590 string opc, string asm, list<dag> pattern> 1591 : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary, opc, 1592 asm, "", pattern>, Requires<[IsThumb, HasAcquireRelease]>, 1593 Sched<[WriteST]> { 1594 bits<4> Rt; 1595 bits<4> addr; 1596 1597 let Inst{31-27} = 0b11101; 1598 let Inst{26-20} = 0b0001100; 1599 let Inst{11-6} = 0b111110; 1600 let Inst{5-4} = bit54; 1601 let Inst{3-0} = 0b1111; 1602 1603 // Encode instruction operands 1604 let Inst{19-16} = addr; 1605 let Inst{15-12} = Rt; 1606} 1607 1608def t2STL : T2Istrrel<0b10, (outs), (ins rGPR:$Rt, addr_offset_none:$addr), 1609 "stl", "\t$Rt, $addr", []>; 1610def t2STLB : T2Istrrel<0b00, (outs), (ins rGPR:$Rt, addr_offset_none:$addr), 1611 "stlb", "\t$Rt, $addr", []>; 1612def t2STLH : T2Istrrel<0b01, (outs), (ins rGPR:$Rt, addr_offset_none:$addr), 1613 "stlh", "\t$Rt, $addr", []>; 1614 1615// T2Ipl (Preload Data/Instruction) signals the memory system of possible future 1616// data/instruction access. 1617// instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0), 1618// (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1). 1619multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> { 1620 1621 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc, 1622 "\t$addr", 1623 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]>, 1624 Sched<[WritePreLd]> { 1625 let Inst{31-25} = 0b1111100; 1626 let Inst{24} = instr; 1627 let Inst{23} = 1; 1628 let Inst{22} = 0; 1629 let Inst{21} = write; 1630 let Inst{20} = 1; 1631 let Inst{15-12} = 0b1111; 1632 1633 bits<17> addr; 1634 let Inst{19-16} = addr{16-13}; // Rn 1635 let Inst{11-0} = addr{11-0}; // imm12 1636 1637 let DecoderMethod = "DecodeT2LoadImm12"; 1638 } 1639 1640 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc, 1641 "\t$addr", 1642 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]>, 1643 Sched<[WritePreLd]> { 1644 let Inst{31-25} = 0b1111100; 1645 let Inst{24} = instr; 1646 let Inst{23} = 0; // U = 0 1647 let Inst{22} = 0; 1648 let Inst{21} = write; 1649 let Inst{20} = 1; 1650 let Inst{15-12} = 0b1111; 1651 let Inst{11-8} = 0b1100; 1652 1653 bits<13> addr; 1654 let Inst{19-16} = addr{12-9}; // Rn 1655 let Inst{7-0} = addr{7-0}; // imm8 1656 1657 let DecoderMethod = "DecodeT2LoadImm8"; 1658 } 1659 1660 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc, 1661 "\t$addr", 1662 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]>, 1663 Sched<[WritePreLd]> { 1664 let Inst{31-25} = 0b1111100; 1665 let Inst{24} = instr; 1666 let Inst{23} = 0; // add = TRUE for T1 1667 let Inst{22} = 0; 1668 let Inst{21} = write; 1669 let Inst{20} = 1; 1670 let Inst{15-12} = 0b1111; 1671 let Inst{11-6} = 0b000000; 1672 1673 bits<10> addr; 1674 let Inst{19-16} = addr{9-6}; // Rn 1675 let Inst{3-0} = addr{5-2}; // Rm 1676 let Inst{5-4} = addr{1-0}; // imm2 1677 1678 let DecoderMethod = "DecodeT2LoadShift"; 1679 } 1680} 1681 1682defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>; 1683defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>; 1684defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>; 1685 1686// pci variant is very similar to i12, but supports negative offsets 1687// from the PC. Only PLD and PLI have pci variants (not PLDW) 1688class T2Iplpci<bits<1> inst, string opc> : T2Iso<(outs), (ins t2ldrlabel:$addr), 1689 IIC_Preload, opc, "\t$addr", 1690 [(ARMPreload (ARMWrapper tconstpool:$addr), 1691 (i32 0), (i32 inst))]>, Sched<[WritePreLd]> { 1692 let Inst{31-25} = 0b1111100; 1693 let Inst{24} = inst; 1694 let Inst{22-20} = 0b001; 1695 let Inst{19-16} = 0b1111; 1696 let Inst{15-12} = 0b1111; 1697 1698 bits<13> addr; 1699 let Inst{23} = addr{12}; // add = (U == '1') 1700 let Inst{11-0} = addr{11-0}; // imm12 1701 1702 let DecoderMethod = "DecodeT2LoadLabel"; 1703} 1704 1705def t2PLDpci : T2Iplpci<0, "pld">, Requires<[IsThumb2]>; 1706def t2PLIpci : T2Iplpci<1, "pli">, Requires<[IsThumb2,HasV7]>; 1707 1708//===----------------------------------------------------------------------===// 1709// Load / store multiple Instructions. 1710// 1711 1712multiclass thumb2_ld_mult<string asm, InstrItinClass itin, 1713 InstrItinClass itin_upd, bit L_bit> { 1714 def IA : 1715 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1716 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> { 1717 bits<4> Rn; 1718 bits<16> regs; 1719 1720 let Inst{31-27} = 0b11101; 1721 let Inst{26-25} = 0b00; 1722 let Inst{24-23} = 0b01; // Increment After 1723 let Inst{22} = 0; 1724 let Inst{21} = 0; // No writeback 1725 let Inst{20} = L_bit; 1726 let Inst{19-16} = Rn; 1727 let Inst{15-0} = regs; 1728 } 1729 def IA_UPD : 1730 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1731 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> { 1732 bits<4> Rn; 1733 bits<16> regs; 1734 1735 let Inst{31-27} = 0b11101; 1736 let Inst{26-25} = 0b00; 1737 let Inst{24-23} = 0b01; // Increment After 1738 let Inst{22} = 0; 1739 let Inst{21} = 1; // Writeback 1740 let Inst{20} = L_bit; 1741 let Inst{19-16} = Rn; 1742 let Inst{15-0} = regs; 1743 } 1744 def DB : 1745 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1746 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> { 1747 bits<4> Rn; 1748 bits<16> regs; 1749 1750 let Inst{31-27} = 0b11101; 1751 let Inst{26-25} = 0b00; 1752 let Inst{24-23} = 0b10; // Decrement Before 1753 let Inst{22} = 0; 1754 let Inst{21} = 0; // No writeback 1755 let Inst{20} = L_bit; 1756 let Inst{19-16} = Rn; 1757 let Inst{15-0} = regs; 1758 } 1759 def DB_UPD : 1760 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1761 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 1762 bits<4> Rn; 1763 bits<16> regs; 1764 1765 let Inst{31-27} = 0b11101; 1766 let Inst{26-25} = 0b00; 1767 let Inst{24-23} = 0b10; // Decrement Before 1768 let Inst{22} = 0; 1769 let Inst{21} = 1; // Writeback 1770 let Inst{20} = L_bit; 1771 let Inst{19-16} = Rn; 1772 let Inst{15-0} = regs; 1773 } 1774} 1775 1776let hasSideEffects = 0 in { 1777 1778let mayLoad = 1, hasExtraDefRegAllocReq = 1, variadicOpsAreDefs = 1 in 1779defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>; 1780 1781multiclass thumb2_st_mult<string asm, InstrItinClass itin, 1782 InstrItinClass itin_upd, bit L_bit> { 1783 def IA : 1784 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1785 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> { 1786 bits<4> Rn; 1787 bits<16> regs; 1788 1789 let Inst{31-27} = 0b11101; 1790 let Inst{26-25} = 0b00; 1791 let Inst{24-23} = 0b01; // Increment After 1792 let Inst{22} = 0; 1793 let Inst{21} = 0; // No writeback 1794 let Inst{20} = L_bit; 1795 let Inst{19-16} = Rn; 1796 let Inst{15} = 0; 1797 let Inst{14} = regs{14}; 1798 let Inst{13} = 0; 1799 let Inst{12-0} = regs{12-0}; 1800 } 1801 def IA_UPD : 1802 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1803 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> { 1804 bits<4> Rn; 1805 bits<16> regs; 1806 1807 let Inst{31-27} = 0b11101; 1808 let Inst{26-25} = 0b00; 1809 let Inst{24-23} = 0b01; // Increment After 1810 let Inst{22} = 0; 1811 let Inst{21} = 1; // Writeback 1812 let Inst{20} = L_bit; 1813 let Inst{19-16} = Rn; 1814 let Inst{15} = 0; 1815 let Inst{14} = regs{14}; 1816 let Inst{13} = 0; 1817 let Inst{12-0} = regs{12-0}; 1818 } 1819 def DB : 1820 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1821 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> { 1822 bits<4> Rn; 1823 bits<16> regs; 1824 1825 let Inst{31-27} = 0b11101; 1826 let Inst{26-25} = 0b00; 1827 let Inst{24-23} = 0b10; // Decrement Before 1828 let Inst{22} = 0; 1829 let Inst{21} = 0; // No writeback 1830 let Inst{20} = L_bit; 1831 let Inst{19-16} = Rn; 1832 let Inst{15} = 0; 1833 let Inst{14} = regs{14}; 1834 let Inst{13} = 0; 1835 let Inst{12-0} = regs{12-0}; 1836 } 1837 def DB_UPD : 1838 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1839 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 1840 bits<4> Rn; 1841 bits<16> regs; 1842 1843 let Inst{31-27} = 0b11101; 1844 let Inst{26-25} = 0b00; 1845 let Inst{24-23} = 0b10; // Decrement Before 1846 let Inst{22} = 0; 1847 let Inst{21} = 1; // Writeback 1848 let Inst{20} = L_bit; 1849 let Inst{19-16} = Rn; 1850 let Inst{15} = 0; 1851 let Inst{14} = regs{14}; 1852 let Inst{13} = 0; 1853 let Inst{12-0} = regs{12-0}; 1854 } 1855} 1856 1857 1858let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 1859defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>; 1860 1861} // hasSideEffects 1862 1863 1864//===----------------------------------------------------------------------===// 1865// Move Instructions. 1866// 1867 1868let hasSideEffects = 0 in 1869def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rm), IIC_iMOVr, 1870 "mov", ".w\t$Rd, $Rm", []>, Sched<[WriteALU]> { 1871 let Inst{31-27} = 0b11101; 1872 let Inst{26-25} = 0b01; 1873 let Inst{24-21} = 0b0010; 1874 let Inst{19-16} = 0b1111; // Rn 1875 let Inst{14-12} = 0b000; 1876 let Inst{7-4} = 0b0000; 1877} 1878def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, 1879 pred:$p, zero_reg)>; 1880def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, 1881 pred:$p, CPSR)>; 1882def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, 1883 pred:$p, CPSR)>; 1884 1885// AddedComplexity to ensure isel tries t2MOVi before t2MOVi16. 1886let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1, 1887 AddedComplexity = 1 in 1888def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi, 1889 "mov", ".w\t$Rd, $imm", 1890 [(set rGPR:$Rd, t2_so_imm:$imm)]>, Sched<[WriteALU]> { 1891 let Inst{31-27} = 0b11110; 1892 let Inst{25} = 0; 1893 let Inst{24-21} = 0b0010; 1894 let Inst{19-16} = 0b1111; // Rn 1895 let Inst{15} = 0; 1896} 1897 1898// cc_out is handled as part of the explicit mnemonic in the parser for 'mov'. 1899// Use aliases to get that to play nice here. 1900def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm, 1901 pred:$p, CPSR)>; 1902def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm, 1903 pred:$p, CPSR)>; 1904 1905def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm, 1906 pred:$p, zero_reg)>; 1907def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm, 1908 pred:$p, zero_reg)>; 1909 1910let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 1911def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi, 1912 "movw", "\t$Rd, $imm", 1913 [(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]>, 1914 Requires<[IsThumb, HasV8MBaseline]> { 1915 let Inst{31-27} = 0b11110; 1916 let Inst{25} = 1; 1917 let Inst{24-21} = 0b0010; 1918 let Inst{20} = 0; // The S bit. 1919 let Inst{15} = 0; 1920 1921 bits<4> Rd; 1922 bits<16> imm; 1923 1924 let Inst{11-8} = Rd; 1925 let Inst{19-16} = imm{15-12}; 1926 let Inst{26} = imm{11}; 1927 let Inst{14-12} = imm{10-8}; 1928 let Inst{7-0} = imm{7-0}; 1929 let DecoderMethod = "DecodeT2MOVTWInstruction"; 1930} 1931 1932def : InstAlias<"mov${p} $Rd, $imm", 1933 (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p), 0>, 1934 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteALU]>; 1935 1936def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd), 1937 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 1938 Sched<[WriteALU]>; 1939 1940let Constraints = "$src = $Rd" in { 1941def t2MOVTi16 : T2I<(outs rGPR:$Rd), 1942 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi, 1943 "movt", "\t$Rd, $imm", 1944 [(set rGPR:$Rd, 1945 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]>, 1946 Sched<[WriteALU]>, 1947 Requires<[IsThumb, HasV8MBaseline]> { 1948 let Inst{31-27} = 0b11110; 1949 let Inst{25} = 1; 1950 let Inst{24-21} = 0b0110; 1951 let Inst{20} = 0; // The S bit. 1952 let Inst{15} = 0; 1953 1954 bits<4> Rd; 1955 bits<16> imm; 1956 1957 let Inst{11-8} = Rd; 1958 let Inst{19-16} = imm{15-12}; 1959 let Inst{26} = imm{11}; 1960 let Inst{14-12} = imm{10-8}; 1961 let Inst{7-0} = imm{7-0}; 1962 let DecoderMethod = "DecodeT2MOVTWInstruction"; 1963} 1964 1965def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd), 1966 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, 1967 Sched<[WriteALU]>, Requires<[IsThumb, HasV8MBaseline]>; 1968} // Constraints 1969 1970def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>; 1971 1972//===----------------------------------------------------------------------===// 1973// Extend Instructions. 1974// 1975 1976// Sign extenders 1977 1978def t2SXTB : T2I_ext_rrot<0b100, "sxtb">; 1979def t2SXTH : T2I_ext_rrot<0b000, "sxth">; 1980def t2SXTB16 : T2I_ext_rrot_xtb16<0b010, "sxtb16">; 1981 1982def t2SXTAB : T2I_exta_rrot<0b100, "sxtab">; 1983def t2SXTAH : T2I_exta_rrot<0b000, "sxtah">; 1984def t2SXTAB16 : T2I_exta_rrot<0b010, "sxtab16">; 1985 1986def : T2Pat<(sext_inreg (rotr rGPR:$Rn, rot_imm:$rot), i8), 1987 (t2SXTB rGPR:$Rn, rot_imm:$rot)>; 1988def : T2Pat<(sext_inreg (rotr rGPR:$Rn, rot_imm:$rot), i16), 1989 (t2SXTH rGPR:$Rn, rot_imm:$rot)>; 1990def : Thumb2DSPPat<(add rGPR:$Rn, 1991 (sext_inreg (rotr rGPR:$Rm, rot_imm:$rot), i8)), 1992 (t2SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 1993def : Thumb2DSPPat<(add rGPR:$Rn, 1994 (sext_inreg (rotr rGPR:$Rm, rot_imm:$rot), i16)), 1995 (t2SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 1996def : Thumb2DSPPat<(int_arm_sxtb16 rGPR:$Rn), 1997 (t2SXTB16 rGPR:$Rn, 0)>; 1998def : Thumb2DSPPat<(int_arm_sxtab16 rGPR:$Rn, rGPR:$Rm), 1999 (t2SXTAB16 rGPR:$Rn, rGPR:$Rm, 0)>; 2000def : Thumb2DSPPat<(int_arm_sxtb16 (rotr rGPR:$Rn, rot_imm:$rot)), 2001 (t2SXTB16 rGPR:$Rn, rot_imm:$rot)>; 2002def : Thumb2DSPPat<(int_arm_sxtab16 rGPR:$Rn, (rotr rGPR:$Rm, rot_imm:$rot)), 2003 (t2SXTAB16 rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 2004 2005 2006// A simple right-shift can also be used in most cases (the exception is the 2007// SXTH operations with a rotate of 24: there the non-contiguous bits are 2008// relevant). 2009def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg 2010 (srl rGPR:$Rm, rot_imm:$rot), i8)), 2011 (t2SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 2012def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg 2013 (srl rGPR:$Rm, imm8_or_16:$rot), i16)), 2014 (t2SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 2015def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg 2016 (rotr rGPR:$Rm, (i32 24)), i16)), 2017 (t2SXTAH rGPR:$Rn, rGPR:$Rm, (i32 3))>; 2018def : Thumb2DSPPat<(add rGPR:$Rn, (sext_inreg 2019 (or (srl rGPR:$Rm, (i32 24)), 2020 (shl rGPR:$Rm, (i32 8))), i16)), 2021 (t2SXTAH rGPR:$Rn, rGPR:$Rm, (i32 3))>; 2022 2023// Zero extenders 2024 2025let AddedComplexity = 16 in { 2026def t2UXTB : T2I_ext_rrot<0b101, "uxtb">; 2027def t2UXTH : T2I_ext_rrot<0b001, "uxth">; 2028def t2UXTB16 : T2I_ext_rrot_xtb16<0b011, "uxtb16">; 2029 2030def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x000000FF), 2031 (t2UXTB rGPR:$Rm, rot_imm:$rot)>; 2032def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x0000FFFF), 2033 (t2UXTH rGPR:$Rm, rot_imm:$rot)>; 2034def : Thumb2DSPPat<(and (rotr rGPR:$Rm, rot_imm:$rot), 0x00FF00FF), 2035 (t2UXTB16 rGPR:$Rm, rot_imm:$rot)>; 2036 2037def : Thumb2DSPPat<(int_arm_uxtb16 rGPR:$Rm), 2038 (t2UXTB16 rGPR:$Rm, 0)>; 2039def : Thumb2DSPPat<(int_arm_uxtb16 (rotr rGPR:$Rn, rot_imm:$rot)), 2040 (t2UXTB16 rGPR:$Rn, rot_imm:$rot)>; 2041 2042// FIXME: This pattern incorrectly assumes the shl operator is a rotate. 2043// The transformation should probably be done as a combiner action 2044// instead so we can include a check for masking back in the upper 2045// eight bits of the source into the lower eight bits of the result. 2046//def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF), 2047// (t2UXTB16 rGPR:$Src, 3)>, 2048// Requires<[HasDSP, IsThumb2]>; 2049def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF), 2050 (t2UXTB16 rGPR:$Src, 1)>, 2051 Requires<[HasDSP, IsThumb2]>; 2052 2053def t2UXTAB : T2I_exta_rrot<0b101, "uxtab">; 2054def t2UXTAH : T2I_exta_rrot<0b001, "uxtah">; 2055def t2UXTAB16 : T2I_exta_rrot<0b011, "uxtab16">; 2056 2057def : Thumb2DSPPat<(add rGPR:$Rn, (and (rotr rGPR:$Rm, rot_imm:$rot), 2058 0x00FF)), 2059 (t2UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 2060def : Thumb2DSPPat<(add rGPR:$Rn, (and (rotr rGPR:$Rm, rot_imm:$rot), 2061 0xFFFF)), 2062 (t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 2063def : Thumb2DSPPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 2064 0xFF)), 2065 (t2UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 2066def : Thumb2DSPPat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 2067 0xFFFF)), 2068 (t2UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 2069def : Thumb2DSPPat<(int_arm_uxtab16 rGPR:$Rn, rGPR:$Rm), 2070 (t2UXTAB16 rGPR:$Rn, rGPR:$Rm, 0)>; 2071def : Thumb2DSPPat<(int_arm_uxtab16 rGPR:$Rn, (rotr rGPR:$Rm, rot_imm:$rot)), 2072 (t2UXTAB16 rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>; 2073} 2074 2075 2076//===----------------------------------------------------------------------===// 2077// Arithmetic Instructions. 2078// 2079 2080let isAdd = 1 in 2081defm t2ADD : T2I_bin_ii12rs<0b000, "add", add, 1>; 2082defm t2SUB : T2I_bin_ii12rs<0b101, "sub", sub>; 2083 2084// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants. 2085// 2086// Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the 2087// selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by 2088// AdjustInstrPostInstrSelection where we determine whether or not to 2089// set the "s" bit based on CPSR liveness. 2090// 2091// FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen 2092// support for an optional CPSR definition that corresponds to the DAG 2093// node's second value. We can then eliminate the implicit def of CPSR. 2094defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, ARMaddc, 1>; 2095defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi, ARMsubc>; 2096 2097def : T2Pat<(ARMsubs GPRnopc:$Rn, t2_so_imm:$imm), 2098 (t2SUBSri $Rn, t2_so_imm:$imm)>; 2099def : T2Pat<(ARMsubs GPRnopc:$Rn, rGPR:$Rm), (t2SUBSrr $Rn, $Rm)>; 2100def : T2Pat<(ARMsubs GPRnopc:$Rn, t2_so_reg:$ShiftedRm), 2101 (t2SUBSrs $Rn, t2_so_reg:$ShiftedRm)>; 2102 2103let hasPostISelHook = 1 in { 2104defm t2ADC : T2I_adde_sube_irs<0b1010, "adc", ARMadde, 1>; 2105defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc", ARMsube>; 2106} 2107 2108def : t2InstSubst<"adc${s}${p} $rd, $rn, $imm", 2109 (t2SBCri rGPR:$rd, rGPR:$rn, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>; 2110def : t2InstSubst<"sbc${s}${p} $rd, $rn, $imm", 2111 (t2ADCri rGPR:$rd, rGPR:$rn, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>; 2112 2113def : t2InstSubst<"add${s}${p}.w $rd, $rn, $imm", 2114 (t2SUBri GPRnopc:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>; 2115def : t2InstSubst<"addw${p} $rd, $rn, $imm", 2116 (t2SUBri12 GPRnopc:$rd, GPR:$rn, t2_so_imm_neg:$imm, pred:$p)>; 2117def : t2InstSubst<"sub${s}${p}.w $rd, $rn, $imm", 2118 (t2ADDri GPRnopc:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>; 2119def : t2InstSubst<"subw${p} $rd, $rn, $imm", 2120 (t2ADDri12 GPRnopc:$rd, GPR:$rn, t2_so_imm_neg:$imm, pred:$p)>; 2121def : t2InstSubst<"subw${p} $Rd, $Rn, $imm", 2122 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>; 2123def : t2InstSubst<"sub${s}${p} $rd, $rn, $imm", 2124 (t2ADDri GPRnopc:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>; 2125def : t2InstSubst<"sub${p} $rd, $rn, $imm", 2126 (t2ADDri12 GPRnopc:$rd, GPR:$rn, t2_so_imm_neg:$imm, pred:$p)>; 2127// RSB 2128defm t2RSB : T2I_rbin_irs <0b1110, "rsb", sub>; 2129 2130// FIXME: Eliminate them if we can write def : Pat patterns which defines 2131// CPSR and the implicit def of CPSR is not needed. 2132defm t2RSBS : T2I_rbin_s_is <ARMsubc>; 2133 2134// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 2135// The assume-no-carry-in form uses the negation of the input since add/sub 2136// assume opposite meanings of the carry flag (i.e., carry == !borrow). 2137// See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 2138// details. 2139// The AddedComplexity preferences the first variant over the others since 2140// it can be shrunk to a 16-bit wide encoding, while the others cannot. 2141let AddedComplexity = 1 in 2142def : T2Pat<(add GPR:$src, imm1_255_neg:$imm), 2143 (t2SUBri GPR:$src, imm1_255_neg:$imm)>; 2144def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm), 2145 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>; 2146def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm), 2147 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>; 2148def : T2Pat<(add GPR:$src, imm0_65535_neg:$imm), 2149 (t2SUBrr GPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>; 2150 2151let AddedComplexity = 1 in 2152def : T2Pat<(ARMaddc rGPR:$src, imm1_255_neg:$imm), 2153 (t2SUBSri rGPR:$src, imm1_255_neg:$imm)>; 2154def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm), 2155 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>; 2156def : T2Pat<(ARMaddc rGPR:$src, imm0_65535_neg:$imm), 2157 (t2SUBSrr rGPR:$src, (t2MOVi16 (imm_neg_XFORM imm:$imm)))>; 2158// The with-carry-in form matches bitwise not instead of the negation. 2159// Effectively, the inverse interpretation of the carry flag already accounts 2160// for part of the negation. 2161let AddedComplexity = 1 in 2162def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR), 2163 (t2SBCri rGPR:$src, imm0_255_not:$imm)>; 2164def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR), 2165 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>; 2166def : T2Pat<(ARMadde rGPR:$src, imm0_65535_neg:$imm, CPSR), 2167 (t2SBCrr rGPR:$src, (t2MOVi16 (imm_not_XFORM imm:$imm)))>; 2168 2169def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 2170 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", 2171 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>, 2172 Requires<[IsThumb2, HasDSP]> { 2173 let Inst{31-27} = 0b11111; 2174 let Inst{26-24} = 0b010; 2175 let Inst{23} = 0b1; 2176 let Inst{22-20} = 0b010; 2177 let Inst{15-12} = 0b1111; 2178 let Inst{7} = 0b1; 2179 let Inst{6-4} = 0b000; 2180} 2181 2182// A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned) 2183// And Miscellaneous operations -- for disassembly only 2184class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc, 2185 list<dag> pat, dag iops, string asm> 2186 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>, 2187 Requires<[IsThumb2, HasDSP]> { 2188 let Inst{31-27} = 0b11111; 2189 let Inst{26-23} = 0b0101; 2190 let Inst{22-20} = op22_20; 2191 let Inst{15-12} = 0b1111; 2192 let Inst{7-4} = op7_4; 2193 2194 bits<4> Rd; 2195 bits<4> Rn; 2196 bits<4> Rm; 2197 2198 let Inst{11-8} = Rd; 2199 let Inst{19-16} = Rn; 2200 let Inst{3-0} = Rm; 2201} 2202 2203class T2I_pam_intrinsics<bits<3> op22_20, bits<4> op7_4, string opc, 2204 Intrinsic intrinsic> 2205 : T2I_pam<op22_20, op7_4, opc, 2206 [(set rGPR:$Rd, (intrinsic rGPR:$Rn, rGPR:$Rm))], 2207 (ins rGPR:$Rn, rGPR:$Rm), "\t$Rd, $Rn, $Rm">; 2208 2209class T2I_pam_intrinsics_rev<bits<3> op22_20, bits<4> op7_4, string opc> 2210 : T2I_pam<op22_20, op7_4, opc, [], 2211 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">; 2212 2213// Saturating add/subtract 2214def t2QADD16 : T2I_pam_intrinsics<0b001, 0b0001, "qadd16", int_arm_qadd16>; 2215def t2QADD8 : T2I_pam_intrinsics<0b000, 0b0001, "qadd8", int_arm_qadd8>; 2216def t2QASX : T2I_pam_intrinsics<0b010, 0b0001, "qasx", int_arm_qasx>; 2217def t2UQSUB8 : T2I_pam_intrinsics<0b100, 0b0101, "uqsub8", int_arm_uqsub8>; 2218def t2QSAX : T2I_pam_intrinsics<0b110, 0b0001, "qsax", int_arm_qsax>; 2219def t2QSUB16 : T2I_pam_intrinsics<0b101, 0b0001, "qsub16", int_arm_qsub16>; 2220def t2QSUB8 : T2I_pam_intrinsics<0b100, 0b0001, "qsub8", int_arm_qsub8>; 2221def t2UQADD16 : T2I_pam_intrinsics<0b001, 0b0101, "uqadd16", int_arm_uqadd16>; 2222def t2UQADD8 : T2I_pam_intrinsics<0b000, 0b0101, "uqadd8", int_arm_uqadd8>; 2223def t2UQASX : T2I_pam_intrinsics<0b010, 0b0101, "uqasx", int_arm_uqasx>; 2224def t2UQSAX : T2I_pam_intrinsics<0b110, 0b0101, "uqsax", int_arm_uqsax>; 2225def t2UQSUB16 : T2I_pam_intrinsics<0b101, 0b0101, "uqsub16", int_arm_uqsub16>; 2226def t2QADD : T2I_pam_intrinsics_rev<0b000, 0b1000, "qadd">; 2227def t2QSUB : T2I_pam_intrinsics_rev<0b000, 0b1010, "qsub">; 2228def t2QDADD : T2I_pam_intrinsics_rev<0b000, 0b1001, "qdadd">; 2229def t2QDSUB : T2I_pam_intrinsics_rev<0b000, 0b1011, "qdsub">; 2230 2231def : Thumb2DSPPat<(int_arm_qadd rGPR:$Rm, rGPR:$Rn), 2232 (t2QADD rGPR:$Rm, rGPR:$Rn)>; 2233def : Thumb2DSPPat<(int_arm_qsub rGPR:$Rm, rGPR:$Rn), 2234 (t2QSUB rGPR:$Rm, rGPR:$Rn)>; 2235def : Thumb2DSPPat<(int_arm_qadd(int_arm_qadd rGPR:$Rm, rGPR:$Rm), rGPR:$Rn), 2236 (t2QDADD rGPR:$Rm, rGPR:$Rn)>; 2237def : Thumb2DSPPat<(int_arm_qsub rGPR:$Rm, (int_arm_qadd rGPR:$Rn, rGPR:$Rn)), 2238 (t2QDSUB rGPR:$Rm, rGPR:$Rn)>; 2239 2240// Signed/Unsigned add/subtract 2241 2242def t2SASX : T2I_pam_intrinsics<0b010, 0b0000, "sasx", int_arm_sasx>; 2243def t2SADD16 : T2I_pam_intrinsics<0b001, 0b0000, "sadd16", int_arm_sadd16>; 2244def t2SADD8 : T2I_pam_intrinsics<0b000, 0b0000, "sadd8", int_arm_sadd8>; 2245def t2SSAX : T2I_pam_intrinsics<0b110, 0b0000, "ssax", int_arm_ssax>; 2246def t2SSUB16 : T2I_pam_intrinsics<0b101, 0b0000, "ssub16", int_arm_ssub16>; 2247def t2SSUB8 : T2I_pam_intrinsics<0b100, 0b0000, "ssub8", int_arm_ssub8>; 2248def t2UASX : T2I_pam_intrinsics<0b010, 0b0100, "uasx", int_arm_uasx>; 2249def t2UADD16 : T2I_pam_intrinsics<0b001, 0b0100, "uadd16", int_arm_uadd16>; 2250def t2UADD8 : T2I_pam_intrinsics<0b000, 0b0100, "uadd8", int_arm_uadd8>; 2251def t2USAX : T2I_pam_intrinsics<0b110, 0b0100, "usax", int_arm_usax>; 2252def t2USUB16 : T2I_pam_intrinsics<0b101, 0b0100, "usub16", int_arm_usub16>; 2253def t2USUB8 : T2I_pam_intrinsics<0b100, 0b0100, "usub8", int_arm_usub8>; 2254 2255// Signed/Unsigned halving add/subtract 2256 2257def t2SHASX : T2I_pam_intrinsics<0b010, 0b0010, "shasx", int_arm_shasx>; 2258def t2SHADD16 : T2I_pam_intrinsics<0b001, 0b0010, "shadd16", int_arm_shadd16>; 2259def t2SHADD8 : T2I_pam_intrinsics<0b000, 0b0010, "shadd8", int_arm_shadd8>; 2260def t2SHSAX : T2I_pam_intrinsics<0b110, 0b0010, "shsax", int_arm_shsax>; 2261def t2SHSUB16 : T2I_pam_intrinsics<0b101, 0b0010, "shsub16", int_arm_shsub16>; 2262def t2SHSUB8 : T2I_pam_intrinsics<0b100, 0b0010, "shsub8", int_arm_shsub8>; 2263def t2UHASX : T2I_pam_intrinsics<0b010, 0b0110, "uhasx", int_arm_uhasx>; 2264def t2UHADD16 : T2I_pam_intrinsics<0b001, 0b0110, "uhadd16", int_arm_uhadd16>; 2265def t2UHADD8 : T2I_pam_intrinsics<0b000, 0b0110, "uhadd8", int_arm_uhadd8>; 2266def t2UHSAX : T2I_pam_intrinsics<0b110, 0b0110, "uhsax", int_arm_uhsax>; 2267def t2UHSUB16 : T2I_pam_intrinsics<0b101, 0b0110, "uhsub16", int_arm_uhsub16>; 2268def t2UHSUB8 : T2I_pam_intrinsics<0b100, 0b0110, "uhsub8", int_arm_uhsub8>; 2269 2270// Helper class for disassembly only 2271// A6.3.16 & A6.3.17 2272// T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions. 2273class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, 2274 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern> 2275 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> { 2276 let Inst{31-27} = 0b11111; 2277 let Inst{26-24} = 0b011; 2278 let Inst{23} = long; 2279 let Inst{22-20} = op22_20; 2280 let Inst{7-4} = op7_4; 2281} 2282 2283class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, 2284 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern> 2285 : T2FourReg<oops, iops, itin, opc, asm, pattern> { 2286 let Inst{31-27} = 0b11111; 2287 let Inst{26-24} = 0b011; 2288 let Inst{23} = long; 2289 let Inst{22-20} = op22_20; 2290 let Inst{7-4} = op7_4; 2291} 2292 2293// Unsigned Sum of Absolute Differences [and Accumulate]. 2294def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd), 2295 (ins rGPR:$Rn, rGPR:$Rm), 2296 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", 2297 [(set rGPR:$Rd, (int_arm_usad8 rGPR:$Rn, rGPR:$Rm))]>, 2298 Requires<[IsThumb2, HasDSP]> { 2299 let Inst{15-12} = 0b1111; 2300} 2301def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd), 2302 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary, 2303 "usada8", "\t$Rd, $Rn, $Rm, $Ra", 2304 [(set rGPR:$Rd, (int_arm_usada8 rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>, 2305 Requires<[IsThumb2, HasDSP]>; 2306 2307// Signed/Unsigned saturate. 2308let hasSideEffects = 1 in 2309class T2SatI<dag iops, string opc, string asm> 2310 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, []> { 2311 bits<4> Rd; 2312 bits<4> Rn; 2313 bits<5> sat_imm; 2314 bits<6> sh; 2315 2316 let Inst{31-24} = 0b11110011; 2317 let Inst{21} = sh{5}; 2318 let Inst{20} = 0; 2319 let Inst{19-16} = Rn; 2320 let Inst{15} = 0; 2321 let Inst{14-12} = sh{4-2}; 2322 let Inst{11-8} = Rd; 2323 let Inst{7-6} = sh{1-0}; 2324 let Inst{5} = 0; 2325 let Inst{4-0} = sat_imm; 2326} 2327 2328def t2SSAT: T2SatI<(ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh), 2329 "ssat", "\t$Rd, $sat_imm, $Rn$sh">, 2330 Requires<[IsThumb2]> { 2331 let Inst{23-22} = 0b00; 2332 let Inst{5} = 0; 2333} 2334 2335def t2SSAT16: T2SatI<(ins imm1_16:$sat_imm, rGPR:$Rn), 2336 "ssat16", "\t$Rd, $sat_imm, $Rn">, 2337 Requires<[IsThumb2, HasDSP]> { 2338 let Inst{23-22} = 0b00; 2339 let sh = 0b100000; 2340 let Inst{4} = 0; 2341} 2342 2343def t2USAT: T2SatI<(ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh), 2344 "usat", "\t$Rd, $sat_imm, $Rn$sh">, 2345 Requires<[IsThumb2]> { 2346 let Inst{23-22} = 0b10; 2347} 2348 2349def t2USAT16: T2SatI<(ins imm0_15:$sat_imm, rGPR:$Rn), 2350 "usat16", "\t$Rd, $sat_imm, $Rn">, 2351 Requires<[IsThumb2, HasDSP]> { 2352 let Inst{23-22} = 0b10; 2353 let sh = 0b100000; 2354 let Inst{4} = 0; 2355} 2356 2357def : T2Pat<(ARMssatnoshift GPRnopc:$Rn, imm0_31:$imm), 2358 (t2SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>; 2359def : T2Pat<(ARMusatnoshift GPRnopc:$Rn, imm0_31:$imm), 2360 (t2USAT imm0_31:$imm, GPRnopc:$Rn, 0)>; 2361def : T2Pat<(int_arm_ssat GPR:$a, imm1_32:$pos), 2362 (t2SSAT imm1_32:$pos, GPR:$a, 0)>; 2363def : T2Pat<(int_arm_usat GPR:$a, imm0_31:$pos), 2364 (t2USAT imm0_31:$pos, GPR:$a, 0)>; 2365def : T2Pat<(int_arm_ssat16 GPR:$a, imm1_16:$pos), 2366 (t2SSAT16 imm1_16:$pos, GPR:$a)>; 2367def : T2Pat<(int_arm_usat16 GPR:$a, imm0_15:$pos), 2368 (t2USAT16 imm0_15:$pos, GPR:$a)>; 2369 2370//===----------------------------------------------------------------------===// 2371// Shift and rotate Instructions. 2372// 2373 2374defm t2LSL : T2I_sh_ir<0b00, "lsl", imm1_31, shl>; 2375defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr, srl>; 2376defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr, sra>; 2377defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31, rotr>; 2378 2379// LSL #0 is actually MOV, and has slightly different permitted registers to 2380// LSL with non-zero shift 2381def : t2InstAlias<"lsl${s}${p} $Rd, $Rm, #0", 2382 (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>; 2383def : t2InstAlias<"lsl${s}${p}.w $Rd, $Rm, #0", 2384 (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>; 2385 2386// (rotr x, (and y, 0x...1f)) ==> (ROR x, y) 2387def : T2Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)), 2388 (t2RORrr rGPR:$lhs, rGPR:$rhs)>; 2389 2390let Uses = [CPSR] in { 2391def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi, 2392 "rrx", "\t$Rd, $Rm", 2393 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]>, Sched<[WriteALU]> { 2394 let Inst{31-27} = 0b11101; 2395 let Inst{26-25} = 0b01; 2396 let Inst{24-21} = 0b0010; 2397 let Inst{19-16} = 0b1111; // Rn 2398 let Inst{14-12} = 0b000; 2399 let Inst{7-4} = 0b0011; 2400} 2401} 2402 2403let isCodeGenOnly = 1, Defs = [CPSR] in { 2404def t2MOVsrl_flag : T2TwoRegShiftImm< 2405 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi, 2406 "lsrs", ".w\t$Rd, $Rm, #1", 2407 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]>, 2408 Sched<[WriteALU]> { 2409 let Inst{31-27} = 0b11101; 2410 let Inst{26-25} = 0b01; 2411 let Inst{24-21} = 0b0010; 2412 let Inst{20} = 1; // The S bit. 2413 let Inst{19-16} = 0b1111; // Rn 2414 let Inst{5-4} = 0b01; // Shift type. 2415 // Shift amount = Inst{14-12:7-6} = 1. 2416 let Inst{14-12} = 0b000; 2417 let Inst{7-6} = 0b01; 2418} 2419def t2MOVsra_flag : T2TwoRegShiftImm< 2420 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi, 2421 "asrs", ".w\t$Rd, $Rm, #1", 2422 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]>, 2423 Sched<[WriteALU]> { 2424 let Inst{31-27} = 0b11101; 2425 let Inst{26-25} = 0b01; 2426 let Inst{24-21} = 0b0010; 2427 let Inst{20} = 1; // The S bit. 2428 let Inst{19-16} = 0b1111; // Rn 2429 let Inst{5-4} = 0b10; // Shift type. 2430 // Shift amount = Inst{14-12:7-6} = 1. 2431 let Inst{14-12} = 0b000; 2432 let Inst{7-6} = 0b01; 2433} 2434} 2435 2436//===----------------------------------------------------------------------===// 2437// Bitwise Instructions. 2438// 2439 2440defm t2AND : T2I_bin_w_irs<0b0000, "and", 2441 IIC_iBITi, IIC_iBITr, IIC_iBITsi, and, 1>; 2442defm t2ORR : T2I_bin_w_irs<0b0010, "orr", 2443 IIC_iBITi, IIC_iBITr, IIC_iBITsi, or, 1>; 2444defm t2EOR : T2I_bin_w_irs<0b0100, "eor", 2445 IIC_iBITi, IIC_iBITr, IIC_iBITsi, xor, 1>; 2446 2447defm t2BIC : T2I_bin_w_irs<0b0001, "bic", 2448 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 2449 BinOpFrag<(and node:$LHS, (not node:$RHS))>>; 2450 2451class T2BitFI<dag oops, dag iops, InstrItinClass itin, 2452 string opc, string asm, list<dag> pattern> 2453 : T2I<oops, iops, itin, opc, asm, pattern> { 2454 bits<4> Rd; 2455 bits<5> msb; 2456 bits<5> lsb; 2457 2458 let Inst{11-8} = Rd; 2459 let Inst{4-0} = msb{4-0}; 2460 let Inst{14-12} = lsb{4-2}; 2461 let Inst{7-6} = lsb{1-0}; 2462} 2463 2464class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin, 2465 string opc, string asm, list<dag> pattern> 2466 : T2BitFI<oops, iops, itin, opc, asm, pattern> { 2467 bits<4> Rn; 2468 2469 let Inst{19-16} = Rn; 2470} 2471 2472let Constraints = "$src = $Rd" in 2473def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm), 2474 IIC_iUNAsi, "bfc", "\t$Rd, $imm", 2475 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> { 2476 let Inst{31-27} = 0b11110; 2477 let Inst{26} = 0; // should be 0. 2478 let Inst{25} = 1; 2479 let Inst{24-20} = 0b10110; 2480 let Inst{19-16} = 0b1111; // Rn 2481 let Inst{15} = 0; 2482 let Inst{5} = 0; // should be 0. 2483 2484 bits<10> imm; 2485 let msb{4-0} = imm{9-5}; 2486 let lsb{4-0} = imm{4-0}; 2487} 2488 2489def t2SBFX: T2TwoRegBitFI< 2490 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb), 2491 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> { 2492 let Inst{31-27} = 0b11110; 2493 let Inst{25} = 1; 2494 let Inst{24-20} = 0b10100; 2495 let Inst{15} = 0; 2496} 2497 2498def t2UBFX: T2TwoRegBitFI< 2499 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb), 2500 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> { 2501 let Inst{31-27} = 0b11110; 2502 let Inst{25} = 1; 2503 let Inst{24-20} = 0b11100; 2504 let Inst{15} = 0; 2505} 2506 2507// A8.8.247 UDF - Undefined (Encoding T2) 2508def t2UDF : T2XI<(outs), (ins imm0_65535:$imm16), IIC_Br, "udf.w\t$imm16", 2509 [(int_arm_undefined imm0_65535:$imm16)]> { 2510 bits<16> imm16; 2511 let Inst{31-29} = 0b111; 2512 let Inst{28-27} = 0b10; 2513 let Inst{26-20} = 0b1111111; 2514 let Inst{19-16} = imm16{15-12}; 2515 let Inst{15} = 0b1; 2516 let Inst{14-12} = 0b010; 2517 let Inst{11-0} = imm16{11-0}; 2518} 2519 2520// A8.6.18 BFI - Bitfield insert (Encoding T1) 2521let Constraints = "$src = $Rd" in { 2522 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd), 2523 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm), 2524 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm", 2525 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn, 2526 bf_inv_mask_imm:$imm))]> { 2527 let Inst{31-27} = 0b11110; 2528 let Inst{26} = 0; // should be 0. 2529 let Inst{25} = 1; 2530 let Inst{24-20} = 0b10110; 2531 let Inst{15} = 0; 2532 let Inst{5} = 0; // should be 0. 2533 2534 bits<10> imm; 2535 let msb{4-0} = imm{9-5}; 2536 let lsb{4-0} = imm{4-0}; 2537 } 2538} 2539 2540defm t2ORN : T2I_bin_irs<0b0011, "orn", 2541 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 2542 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">; 2543 2544/// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 2545/// unary operation that produces a value. These are predicable and can be 2546/// changed to modify CPSR. 2547multiclass T2I_un_irs<bits<4> opcod, string opc, 2548 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 2549 PatFrag opnode, 2550 bit Cheap = 0, bit ReMat = 0, bit MoveImm = 0> { 2551 // shifted imm 2552 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii, 2553 opc, "\t$Rd, $imm", 2554 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]>, Sched<[WriteALU]> { 2555 let isAsCheapAsAMove = Cheap; 2556 let isReMaterializable = ReMat; 2557 let isMoveImm = MoveImm; 2558 let Inst{31-27} = 0b11110; 2559 let Inst{25} = 0; 2560 let Inst{24-21} = opcod; 2561 let Inst{19-16} = 0b1111; // Rn 2562 let Inst{15} = 0; 2563 } 2564 // register 2565 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir, 2566 opc, ".w\t$Rd, $Rm", 2567 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>, Sched<[WriteALU]> { 2568 let Inst{31-27} = 0b11101; 2569 let Inst{26-25} = 0b01; 2570 let Inst{24-21} = opcod; 2571 let Inst{19-16} = 0b1111; // Rn 2572 let Inst{14-12} = 0b000; // imm3 2573 let Inst{7-6} = 0b00; // imm2 2574 let Inst{5-4} = 0b00; // type 2575 } 2576 // shifted register 2577 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis, 2578 opc, ".w\t$Rd, $ShiftedRm", 2579 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]>, 2580 Sched<[WriteALU]> { 2581 let Inst{31-27} = 0b11101; 2582 let Inst{26-25} = 0b01; 2583 let Inst{24-21} = opcod; 2584 let Inst{19-16} = 0b1111; // Rn 2585 } 2586} 2587 2588// Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version 2589let AddedComplexity = 1 in 2590defm t2MVN : T2I_un_irs <0b0011, "mvn", 2591 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi, 2592 not, 1, 1, 1>; 2593 2594let AddedComplexity = 1 in 2595def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm), 2596 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>; 2597 2598// top16Zero - answer true if the upper 16 bits of $src are 0, false otherwise 2599def top16Zero: PatLeaf<(i32 rGPR:$src), [{ 2600 return CurDAG->MaskedValueIsZero(SDValue(N,0), APInt::getHighBitsSet(32, 16)); 2601 }]>; 2602 2603// so_imm_notSext is needed instead of so_imm_not, as the value of imm 2604// will match the extended, not the original bitWidth for $src. 2605def : T2Pat<(and top16Zero:$src, t2_so_imm_notSext:$imm), 2606 (t2BICri rGPR:$src, t2_so_imm_notSext:$imm)>; 2607 2608 2609// FIXME: Disable this pattern on Darwin to workaround an assembler bug. 2610def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm), 2611 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>, 2612 Requires<[IsThumb2]>; 2613 2614def : T2Pat<(t2_so_imm_not:$src), 2615 (t2MVNi t2_so_imm_not:$src)>; 2616 2617// There are shorter Thumb encodings for ADD than ORR, so to increase 2618// Thumb2SizeReduction's chances later on we select a t2ADD for an or where 2619// possible. 2620def : T2Pat<(or AddLikeOrOp:$Rn, t2_so_imm:$imm), 2621 (t2ADDri $Rn, t2_so_imm:$imm)>; 2622 2623def : T2Pat<(or AddLikeOrOp:$Rn, imm0_4095:$Rm), 2624 (t2ADDri12 $Rn, imm0_4095:$Rm)>; 2625 2626def : T2Pat<(or AddLikeOrOp:$Rn, non_imm32:$Rm), 2627 (t2ADDrr $Rn, $Rm)>; 2628 2629//===----------------------------------------------------------------------===// 2630// Multiply Instructions. 2631// 2632let isCommutable = 1 in 2633def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32, 2634 "mul", "\t$Rd, $Rn, $Rm", 2635 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]>, 2636 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 2637 let Inst{31-27} = 0b11111; 2638 let Inst{26-23} = 0b0110; 2639 let Inst{22-20} = 0b000; 2640 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2641 let Inst{7-4} = 0b0000; // Multiply 2642} 2643 2644class T2FourRegMLA<bits<4> op7_4, string opc, list<dag> pattern> 2645 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2646 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>, 2647 Requires<[IsThumb2, UseMulOps]>, 2648 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 2649 let Inst{31-27} = 0b11111; 2650 let Inst{26-23} = 0b0110; 2651 let Inst{22-20} = 0b000; 2652 let Inst{7-4} = op7_4; 2653} 2654 2655def t2MLA : T2FourRegMLA<0b0000, "mla", 2656 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), 2657 rGPR:$Ra))]>; 2658def t2MLS: T2FourRegMLA<0b0001, "mls", 2659 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, 2660 rGPR:$Rm)))]>; 2661 2662// Extra precision multiplies with low / high results 2663let hasSideEffects = 0 in { 2664let isCommutable = 1 in { 2665def t2SMULL : T2MulLong<0b000, 0b0000, "smull", 2666 [(set rGPR:$RdLo, rGPR:$RdHi, 2667 (smullohi rGPR:$Rn, rGPR:$Rm))]>; 2668def t2UMULL : T2MulLong<0b010, 0b0000, "umull", 2669 [(set rGPR:$RdLo, rGPR:$RdHi, 2670 (umullohi rGPR:$Rn, rGPR:$Rm))]>; 2671} // isCommutable 2672 2673// Multiply + accumulate 2674def t2SMLAL : T2MlaLong<0b100, 0b0000, "smlal">; 2675def t2UMLAL : T2MlaLong<0b110, 0b0000, "umlal">; 2676def t2UMAAL : T2MlaLong<0b110, 0b0110, "umaal">, Requires<[IsThumb2, HasDSP]>; 2677} // hasSideEffects 2678 2679// Rounding variants of the below included for disassembly only 2680 2681// Most significant word multiply 2682class T2SMMUL<bits<4> op7_4, string opc, list<dag> pattern> 2683 : T2ThreeReg<(outs rGPR:$Rd), 2684 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32, 2685 opc, "\t$Rd, $Rn, $Rm", pattern>, 2686 Requires<[IsThumb2, HasDSP]>, 2687 Sched<[WriteMUL32, ReadMUL, ReadMUL]> { 2688 let Inst{31-27} = 0b11111; 2689 let Inst{26-23} = 0b0110; 2690 let Inst{22-20} = 0b101; 2691 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2692 let Inst{7-4} = op7_4; 2693} 2694def t2SMMUL : T2SMMUL<0b0000, "smmul", [(set rGPR:$Rd, (mulhs rGPR:$Rn, 2695 rGPR:$Rm))]>; 2696def t2SMMULR : 2697 T2SMMUL<0b0001, "smmulr", 2698 [(set rGPR:$Rd, (ARMsmmlar rGPR:$Rn, rGPR:$Rm, (i32 0)))]>; 2699 2700class T2FourRegSMMLA<bits<3> op22_20, bits<4> op7_4, string opc, 2701 list<dag> pattern> 2702 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2703 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>, 2704 Requires<[IsThumb2, HasDSP, UseMulOps]>, 2705 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 2706 let Inst{31-27} = 0b11111; 2707 let Inst{26-23} = 0b0110; 2708 let Inst{22-20} = op22_20; 2709 let Inst{7-4} = op7_4; 2710} 2711 2712def t2SMMLA : T2FourRegSMMLA<0b101, 0b0000, "smmla", 2713 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>; 2714def t2SMMLAR: T2FourRegSMMLA<0b101, 0b0001, "smmlar", 2715 [(set rGPR:$Rd, (ARMsmmlar rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>; 2716def t2SMMLS: T2FourRegSMMLA<0b110, 0b0000, "smmls", []>; 2717def t2SMMLSR: T2FourRegSMMLA<0b110, 0b0001, "smmlsr", 2718 [(set rGPR:$Rd, (ARMsmmlsr rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>; 2719 2720class T2ThreeRegSMUL<bits<3> op22_20, bits<2> op5_4, string opc, 2721 list<dag> pattern> 2722 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, opc, 2723 "\t$Rd, $Rn, $Rm", pattern>, 2724 Requires<[IsThumb2, HasDSP]>, 2725 Sched<[WriteMUL16, ReadMUL, ReadMUL]> { 2726 let Inst{31-27} = 0b11111; 2727 let Inst{26-23} = 0b0110; 2728 let Inst{22-20} = op22_20; 2729 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2730 let Inst{7-6} = 0b00; 2731 let Inst{5-4} = op5_4; 2732} 2733 2734def t2SMULBB : T2ThreeRegSMUL<0b001, 0b00, "smulbb", 2735 [(set rGPR:$Rd, (bb_mul rGPR:$Rn, rGPR:$Rm))]>; 2736def t2SMULBT : T2ThreeRegSMUL<0b001, 0b01, "smulbt", 2737 [(set rGPR:$Rd, (bt_mul rGPR:$Rn, rGPR:$Rm))]>; 2738def t2SMULTB : T2ThreeRegSMUL<0b001, 0b10, "smultb", 2739 [(set rGPR:$Rd, (tb_mul rGPR:$Rn, rGPR:$Rm))]>; 2740def t2SMULTT : T2ThreeRegSMUL<0b001, 0b11, "smultt", 2741 [(set rGPR:$Rd, (tt_mul rGPR:$Rn, rGPR:$Rm))]>; 2742def t2SMULWB : T2ThreeRegSMUL<0b011, 0b00, "smulwb", 2743 [(set rGPR:$Rd, (ARMsmulwb rGPR:$Rn, rGPR:$Rm))]>; 2744def t2SMULWT : T2ThreeRegSMUL<0b011, 0b01, "smulwt", 2745 [(set rGPR:$Rd, (ARMsmulwt rGPR:$Rn, rGPR:$Rm))]>; 2746 2747def : Thumb2DSPPat<(mul sext_16_node:$Rn, (sext_bottom_16 rGPR:$Rm)), 2748 (t2SMULBB rGPR:$Rn, rGPR:$Rm)>; 2749def : Thumb2DSPPat<(mul sext_16_node:$Rn, (sext_top_16 rGPR:$Rm)), 2750 (t2SMULBT rGPR:$Rn, rGPR:$Rm)>; 2751def : Thumb2DSPPat<(mul (sext_top_16 rGPR:$Rn), sext_16_node:$Rm), 2752 (t2SMULTB rGPR:$Rn, rGPR:$Rm)>; 2753 2754def : Thumb2DSPPat<(int_arm_smulbb rGPR:$Rn, rGPR:$Rm), 2755 (t2SMULBB rGPR:$Rn, rGPR:$Rm)>; 2756def : Thumb2DSPPat<(int_arm_smulbt rGPR:$Rn, rGPR:$Rm), 2757 (t2SMULBT rGPR:$Rn, rGPR:$Rm)>; 2758def : Thumb2DSPPat<(int_arm_smultb rGPR:$Rn, rGPR:$Rm), 2759 (t2SMULTB rGPR:$Rn, rGPR:$Rm)>; 2760def : Thumb2DSPPat<(int_arm_smultt rGPR:$Rn, rGPR:$Rm), 2761 (t2SMULTT rGPR:$Rn, rGPR:$Rm)>; 2762def : Thumb2DSPPat<(int_arm_smulwb rGPR:$Rn, rGPR:$Rm), 2763 (t2SMULWB rGPR:$Rn, rGPR:$Rm)>; 2764def : Thumb2DSPPat<(int_arm_smulwt rGPR:$Rn, rGPR:$Rm), 2765 (t2SMULWT rGPR:$Rn, rGPR:$Rm)>; 2766 2767class T2FourRegSMLA<bits<3> op22_20, bits<2> op5_4, string opc, 2768 list<dag> pattern> 2769 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMUL16, 2770 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>, 2771 Requires<[IsThumb2, HasDSP, UseMulOps]>, 2772 Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]> { 2773 let Inst{31-27} = 0b11111; 2774 let Inst{26-23} = 0b0110; 2775 let Inst{22-20} = op22_20; 2776 let Inst{7-6} = 0b00; 2777 let Inst{5-4} = op5_4; 2778} 2779 2780def t2SMLABB : T2FourRegSMLA<0b001, 0b00, "smlabb", 2781 [(set rGPR:$Rd, (add rGPR:$Ra, (bb_mul rGPR:$Rn, rGPR:$Rm)))]>; 2782def t2SMLABT : T2FourRegSMLA<0b001, 0b01, "smlabt", 2783 [(set rGPR:$Rd, (add rGPR:$Ra, (bt_mul rGPR:$Rn, rGPR:$Rm)))]>; 2784def t2SMLATB : T2FourRegSMLA<0b001, 0b10, "smlatb", 2785 [(set rGPR:$Rd, (add rGPR:$Ra, (tb_mul rGPR:$Rn, rGPR:$Rm)))]>; 2786def t2SMLATT : T2FourRegSMLA<0b001, 0b11, "smlatt", 2787 [(set rGPR:$Rd, (add rGPR:$Ra, (tt_mul rGPR:$Rn, rGPR:$Rm)))]>; 2788def t2SMLAWB : T2FourRegSMLA<0b011, 0b00, "smlawb", 2789 [(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwb rGPR:$Rn, rGPR:$Rm)))]>; 2790def t2SMLAWT : T2FourRegSMLA<0b011, 0b01, "smlawt", 2791 [(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwt rGPR:$Rn, rGPR:$Rm)))]>; 2792 2793def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn, sext_16_node:$Rm)), 2794 (t2SMLABB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>; 2795def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn, 2796 (sext_bottom_16 rGPR:$Rm))), 2797 (t2SMLABB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>; 2798def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul sext_16_node:$Rn, 2799 (sext_top_16 rGPR:$Rm))), 2800 (t2SMLABT rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>; 2801def : Thumb2DSPMulPat<(add rGPR:$Ra, (mul (sext_top_16 rGPR:$Rn), 2802 sext_16_node:$Rm)), 2803 (t2SMLATB rGPR:$Rn, rGPR:$Rm, rGPR:$Ra)>; 2804 2805def : Thumb2DSPPat<(int_arm_smlabb GPR:$a, GPR:$b, GPR:$acc), 2806 (t2SMLABB GPR:$a, GPR:$b, GPR:$acc)>; 2807def : Thumb2DSPPat<(int_arm_smlabt GPR:$a, GPR:$b, GPR:$acc), 2808 (t2SMLABT GPR:$a, GPR:$b, GPR:$acc)>; 2809def : Thumb2DSPPat<(int_arm_smlatb GPR:$a, GPR:$b, GPR:$acc), 2810 (t2SMLATB GPR:$a, GPR:$b, GPR:$acc)>; 2811def : Thumb2DSPPat<(int_arm_smlatt GPR:$a, GPR:$b, GPR:$acc), 2812 (t2SMLATT GPR:$a, GPR:$b, GPR:$acc)>; 2813def : Thumb2DSPPat<(int_arm_smlawb GPR:$a, GPR:$b, GPR:$acc), 2814 (t2SMLAWB GPR:$a, GPR:$b, GPR:$acc)>; 2815def : Thumb2DSPPat<(int_arm_smlawt GPR:$a, GPR:$b, GPR:$acc), 2816 (t2SMLAWT GPR:$a, GPR:$b, GPR:$acc)>; 2817 2818// Halfword multiple accumulate long: SMLAL<x><y> 2819def t2SMLALBB : T2MlaLong<0b100, 0b1000, "smlalbb">, 2820 Requires<[IsThumb2, HasDSP]>; 2821def t2SMLALBT : T2MlaLong<0b100, 0b1001, "smlalbt">, 2822 Requires<[IsThumb2, HasDSP]>; 2823def t2SMLALTB : T2MlaLong<0b100, 0b1010, "smlaltb">, 2824 Requires<[IsThumb2, HasDSP]>; 2825def t2SMLALTT : T2MlaLong<0b100, 0b1011, "smlaltt">, 2826 Requires<[IsThumb2, HasDSP]>; 2827 2828def : Thumb2DSPPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 2829 (t2SMLALBB $Rn, $Rm, $RLo, $RHi)>; 2830def : Thumb2DSPPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 2831 (t2SMLALBT $Rn, $Rm, $RLo, $RHi)>; 2832def : Thumb2DSPPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 2833 (t2SMLALTB $Rn, $Rm, $RLo, $RHi)>; 2834def : Thumb2DSPPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), 2835 (t2SMLALTT $Rn, $Rm, $RLo, $RHi)>; 2836 2837class T2DualHalfMul<bits<3> op22_20, bits<4> op7_4, string opc, 2838 Intrinsic intrinsic> 2839 : T2ThreeReg_mac<0, op22_20, op7_4, 2840 (outs rGPR:$Rd), 2841 (ins rGPR:$Rn, rGPR:$Rm), 2842 IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm", 2843 [(set rGPR:$Rd, (intrinsic rGPR:$Rn, rGPR:$Rm))]>, 2844 Requires<[IsThumb2, HasDSP]>, 2845 Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> { 2846 let Inst{15-12} = 0b1111; 2847} 2848 2849// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD 2850def t2SMUAD: T2DualHalfMul<0b010, 0b0000, "smuad", int_arm_smuad>; 2851def t2SMUADX: T2DualHalfMul<0b010, 0b0001, "smuadx", int_arm_smuadx>; 2852def t2SMUSD: T2DualHalfMul<0b100, 0b0000, "smusd", int_arm_smusd>; 2853def t2SMUSDX: T2DualHalfMul<0b100, 0b0001, "smusdx", int_arm_smusdx>; 2854 2855class T2DualHalfMulAdd<bits<3> op22_20, bits<4> op7_4, string opc, 2856 Intrinsic intrinsic> 2857 : T2FourReg_mac<0, op22_20, op7_4, 2858 (outs rGPR:$Rd), 2859 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), 2860 IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm, $Ra", 2861 [(set rGPR:$Rd, (intrinsic rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>, 2862 Requires<[IsThumb2, HasDSP]>; 2863 2864def t2SMLAD : T2DualHalfMulAdd<0b010, 0b0000, "smlad", int_arm_smlad>; 2865def t2SMLADX : T2DualHalfMulAdd<0b010, 0b0001, "smladx", int_arm_smladx>; 2866def t2SMLSD : T2DualHalfMulAdd<0b100, 0b0000, "smlsd", int_arm_smlsd>; 2867def t2SMLSDX : T2DualHalfMulAdd<0b100, 0b0001, "smlsdx", int_arm_smlsdx>; 2868 2869class T2DualHalfMulAddLong<bits<3> op22_20, bits<4> op7_4, string opc> 2870 : T2FourReg_mac<1, op22_20, op7_4, 2871 (outs rGPR:$Ra, rGPR:$Rd), 2872 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), 2873 IIC_iMAC64, opc, "\t$Ra, $Rd, $Rn, $Rm", []>, 2874 RegConstraint<"$Ra = $RLo, $Rd = $RHi">, 2875 Requires<[IsThumb2, HasDSP]>, 2876 Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>; 2877 2878def t2SMLALD : T2DualHalfMulAddLong<0b100, 0b1100, "smlald">; 2879def t2SMLALDX : T2DualHalfMulAddLong<0b100, 0b1101, "smlaldx">; 2880def t2SMLSLD : T2DualHalfMulAddLong<0b101, 0b1100, "smlsld">; 2881def t2SMLSLDX : T2DualHalfMulAddLong<0b101, 0b1101, "smlsldx">; 2882 2883def : Thumb2DSPPat<(ARMSmlald rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), 2884 (t2SMLALD rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi)>; 2885def : Thumb2DSPPat<(ARMSmlaldx rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), 2886 (t2SMLALDX rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi)>; 2887def : Thumb2DSPPat<(ARMSmlsld rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), 2888 (t2SMLSLD rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi)>; 2889def : Thumb2DSPPat<(ARMSmlsldx rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), 2890 (t2SMLSLDX rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi)>; 2891 2892//===----------------------------------------------------------------------===// 2893// Division Instructions. 2894// Signed and unsigned division on v7-M 2895// 2896def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV, 2897 "sdiv", "\t$Rd, $Rn, $Rm", 2898 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>, 2899 Requires<[HasDivideInThumb, IsThumb, HasV8MBaseline]>, 2900 Sched<[WriteDIV]> { 2901 let Inst{31-27} = 0b11111; 2902 let Inst{26-21} = 0b011100; 2903 let Inst{20} = 0b1; 2904 let Inst{15-12} = 0b1111; 2905 let Inst{7-4} = 0b1111; 2906} 2907 2908def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV, 2909 "udiv", "\t$Rd, $Rn, $Rm", 2910 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>, 2911 Requires<[HasDivideInThumb, IsThumb, HasV8MBaseline]>, 2912 Sched<[WriteDIV]> { 2913 let Inst{31-27} = 0b11111; 2914 let Inst{26-21} = 0b011101; 2915 let Inst{20} = 0b1; 2916 let Inst{15-12} = 0b1111; 2917 let Inst{7-4} = 0b1111; 2918} 2919 2920//===----------------------------------------------------------------------===// 2921// Misc. Arithmetic Instructions. 2922// 2923 2924class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops, 2925 InstrItinClass itin, string opc, string asm, list<dag> pattern> 2926 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> { 2927 let Inst{31-27} = 0b11111; 2928 let Inst{26-22} = 0b01010; 2929 let Inst{21-20} = op1; 2930 let Inst{15-12} = 0b1111; 2931 let Inst{7-6} = 0b10; 2932 let Inst{5-4} = op2; 2933 let Rn{3-0} = Rm; 2934} 2935 2936def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 2937 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>, 2938 Sched<[WriteALU]>; 2939 2940def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 2941 "rbit", "\t$Rd, $Rm", 2942 [(set rGPR:$Rd, (bitreverse rGPR:$Rm))]>, 2943 Sched<[WriteALU]>; 2944 2945def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 2946 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>, 2947 Sched<[WriteALU]>; 2948 2949def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 2950 "rev16", ".w\t$Rd, $Rm", 2951 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>, 2952 Sched<[WriteALU]>; 2953 2954def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 2955 "revsh", ".w\t$Rd, $Rm", 2956 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>, 2957 Sched<[WriteALU]>; 2958 2959def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)), 2960 (and (srl rGPR:$Rm, (i32 8)), 0xFF)), 2961 (t2REVSH rGPR:$Rm)>; 2962 2963def t2PKHBT : T2ThreeReg< 2964 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh), 2965 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", 2966 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF), 2967 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh), 2968 0xFFFF0000)))]>, 2969 Requires<[HasDSP, IsThumb2]>, 2970 Sched<[WriteALUsi, ReadALU]> { 2971 let Inst{31-27} = 0b11101; 2972 let Inst{26-25} = 0b01; 2973 let Inst{24-20} = 0b01100; 2974 let Inst{5} = 0; // BT form 2975 let Inst{4} = 0; 2976 2977 bits<5> sh; 2978 let Inst{14-12} = sh{4-2}; 2979 let Inst{7-6} = sh{1-0}; 2980} 2981 2982// Alternate cases for PKHBT where identities eliminate some nodes. 2983def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)), 2984 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>, 2985 Requires<[HasDSP, IsThumb2]>; 2986def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)), 2987 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>, 2988 Requires<[HasDSP, IsThumb2]>; 2989 2990// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 2991// will match the pattern below. 2992def t2PKHTB : T2ThreeReg< 2993 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh), 2994 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", 2995 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000), 2996 (and (sra rGPR:$Rm, pkh_asr_amt:$sh), 2997 0xFFFF)))]>, 2998 Requires<[HasDSP, IsThumb2]>, 2999 Sched<[WriteALUsi, ReadALU]> { 3000 let Inst{31-27} = 0b11101; 3001 let Inst{26-25} = 0b01; 3002 let Inst{24-20} = 0b01100; 3003 let Inst{5} = 1; // TB form 3004 let Inst{4} = 0; 3005 3006 bits<5> sh; 3007 let Inst{14-12} = sh{4-2}; 3008 let Inst{7-6} = sh{1-0}; 3009} 3010 3011// Alternate cases for PKHTB where identities eliminate some nodes. Note that 3012// a shift amount of 0 is *not legal* here, it is PKHBT instead. 3013// We also can not replace a srl (17..31) by an arithmetic shift we would use in 3014// pkhtb src1, src2, asr (17..31). 3015def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16:$sh)), 3016 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16:$sh)>, 3017 Requires<[HasDSP, IsThumb2]>; 3018def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (sra rGPR:$src2, imm16_31:$sh)), 3019 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>, 3020 Requires<[HasDSP, IsThumb2]>; 3021def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), 3022 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)), 3023 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>, 3024 Requires<[HasDSP, IsThumb2]>; 3025 3026//===----------------------------------------------------------------------===// 3027// CRC32 Instructions 3028// 3029// Polynomials: 3030// + CRC32{B,H,W} 0x04C11DB7 3031// + CRC32C{B,H,W} 0x1EDC6F41 3032// 3033 3034class T2I_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin> 3035 : T2ThreeRegNoP<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), NoItinerary, 3036 !strconcat("crc32", suffix, "\t$Rd, $Rn, $Rm"), 3037 [(set rGPR:$Rd, (builtin rGPR:$Rn, rGPR:$Rm))]>, 3038 Requires<[IsThumb2, HasV8, HasCRC]> { 3039 let Inst{31-27} = 0b11111; 3040 let Inst{26-21} = 0b010110; 3041 let Inst{20} = C; 3042 let Inst{15-12} = 0b1111; 3043 let Inst{7-6} = 0b10; 3044 let Inst{5-4} = sz; 3045} 3046 3047def t2CRC32B : T2I_crc32<0, 0b00, "b", int_arm_crc32b>; 3048def t2CRC32CB : T2I_crc32<1, 0b00, "cb", int_arm_crc32cb>; 3049def t2CRC32H : T2I_crc32<0, 0b01, "h", int_arm_crc32h>; 3050def t2CRC32CH : T2I_crc32<1, 0b01, "ch", int_arm_crc32ch>; 3051def t2CRC32W : T2I_crc32<0, 0b10, "w", int_arm_crc32w>; 3052def t2CRC32CW : T2I_crc32<1, 0b10, "cw", int_arm_crc32cw>; 3053 3054//===----------------------------------------------------------------------===// 3055// Comparison Instructions... 3056// 3057defm t2CMP : T2I_cmp_irs<0b1101, "cmp", 3058 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi, ARMcmp>; 3059 3060def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm), 3061 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>; 3062def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs), 3063 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>; 3064def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs), 3065 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>; 3066 3067let isCompare = 1, Defs = [CPSR] in { 3068 // shifted imm 3069 def t2CMNri : T2OneRegCmpImm< 3070 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iCMPi, 3071 "cmn", ".w\t$Rn, $imm", 3072 [(ARMcmn GPRnopc:$Rn, (ineg t2_so_imm:$imm))]>, 3073 Sched<[WriteCMP, ReadALU]> { 3074 let Inst{31-27} = 0b11110; 3075 let Inst{25} = 0; 3076 let Inst{24-21} = 0b1000; 3077 let Inst{20} = 1; // The S bit. 3078 let Inst{15} = 0; 3079 let Inst{11-8} = 0b1111; // Rd 3080 } 3081 // register 3082 def t2CMNzrr : T2TwoRegCmp< 3083 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), IIC_iCMPr, 3084 "cmn", ".w\t$Rn, $Rm", 3085 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 3086 GPRnopc:$Rn, rGPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> { 3087 let Inst{31-27} = 0b11101; 3088 let Inst{26-25} = 0b01; 3089 let Inst{24-21} = 0b1000; 3090 let Inst{20} = 1; // The S bit. 3091 let Inst{14-12} = 0b000; // imm3 3092 let Inst{11-8} = 0b1111; // Rd 3093 let Inst{7-6} = 0b00; // imm2 3094 let Inst{5-4} = 0b00; // type 3095 } 3096 // shifted register 3097 def t2CMNzrs : T2OneRegCmpShiftedReg< 3098 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), IIC_iCMPsi, 3099 "cmn", ".w\t$Rn, $ShiftedRm", 3100 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))> 3101 GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]>, 3102 Sched<[WriteCMPsi, ReadALU, ReadALU]> { 3103 let Inst{31-27} = 0b11101; 3104 let Inst{26-25} = 0b01; 3105 let Inst{24-21} = 0b1000; 3106 let Inst{20} = 1; // The S bit. 3107 let Inst{11-8} = 0b1111; // Rd 3108 } 3109} 3110 3111// Assembler aliases w/o the ".w" suffix. 3112// No alias here for 'rr' version as not all instantiations of this multiclass 3113// want one (CMP in particular, does not). 3114def : t2InstAlias<"cmn${p} $Rn, $imm", 3115 (t2CMNri GPRnopc:$Rn, t2_so_imm:$imm, pred:$p)>; 3116def : t2InstAlias<"cmn${p} $Rn, $shift", 3117 (t2CMNzrs GPRnopc:$Rn, t2_so_reg:$shift, pred:$p)>; 3118 3119def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm), 3120 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>; 3121 3122def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm), 3123 (t2CMNri GPRnopc:$src, t2_so_imm_neg:$imm)>; 3124 3125defm t2TST : T2I_cmp_irs<0b0000, "tst", 3126 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi, 3127 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>>; 3128defm t2TEQ : T2I_cmp_irs<0b0100, "teq", 3129 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi, 3130 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>>; 3131 3132// Conditional moves 3133let hasSideEffects = 0 in { 3134 3135let isCommutable = 1, isSelect = 1 in 3136def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd), 3137 (ins rGPR:$false, rGPR:$Rm, cmovpred:$p), 3138 4, IIC_iCMOVr, 3139 [(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, 3140 cmovpred:$p))]>, 3141 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 3142 3143let isMoveImm = 1 in 3144def t2MOVCCi 3145 : t2PseudoInst<(outs rGPR:$Rd), 3146 (ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p), 3147 4, IIC_iCMOVi, 3148 [(set rGPR:$Rd, (ARMcmov rGPR:$false,t2_so_imm:$imm, 3149 cmovpred:$p))]>, 3150 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 3151 3152let isCodeGenOnly = 1 in { 3153let isMoveImm = 1 in 3154def t2MOVCCi16 3155 : t2PseudoInst<(outs rGPR:$Rd), 3156 (ins rGPR:$false, imm0_65535_expr:$imm, cmovpred:$p), 3157 4, IIC_iCMOVi, 3158 [(set rGPR:$Rd, (ARMcmov rGPR:$false, imm0_65535:$imm, 3159 cmovpred:$p))]>, 3160 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 3161 3162let isMoveImm = 1 in 3163def t2MVNCCi 3164 : t2PseudoInst<(outs rGPR:$Rd), 3165 (ins rGPR:$false, t2_so_imm:$imm, cmovpred:$p), 3166 4, IIC_iCMOVi, 3167 [(set rGPR:$Rd, 3168 (ARMcmov rGPR:$false, t2_so_imm_not:$imm, 3169 cmovpred:$p))]>, 3170 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 3171 3172class MOVCCShPseudo<SDPatternOperator opnode, Operand ty> 3173 : t2PseudoInst<(outs rGPR:$Rd), 3174 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm, cmovpred:$p), 3175 4, IIC_iCMOVsi, 3176 [(set rGPR:$Rd, (ARMcmov rGPR:$false, 3177 (opnode rGPR:$Rm, (i32 ty:$imm)), 3178 cmovpred:$p))]>, 3179 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>; 3180 3181def t2MOVCClsl : MOVCCShPseudo<shl, imm0_31>; 3182def t2MOVCClsr : MOVCCShPseudo<srl, imm_sr>; 3183def t2MOVCCasr : MOVCCShPseudo<sra, imm_sr>; 3184def t2MOVCCror : MOVCCShPseudo<rotr, imm0_31>; 3185 3186let isMoveImm = 1 in 3187def t2MOVCCi32imm 3188 : t2PseudoInst<(outs rGPR:$dst), 3189 (ins rGPR:$false, i32imm:$src, cmovpred:$p), 3190 8, IIC_iCMOVix2, 3191 [(set rGPR:$dst, (ARMcmov rGPR:$false, imm:$src, 3192 cmovpred:$p))]>, 3193 RegConstraint<"$false = $dst">; 3194} // isCodeGenOnly = 1 3195 3196} // hasSideEffects 3197 3198//===----------------------------------------------------------------------===// 3199// Atomic operations intrinsics 3200// 3201 3202// memory barriers protect the atomic sequences 3203let hasSideEffects = 1 in { 3204def t2DMB : T2I<(outs), (ins memb_opt:$opt), NoItinerary, 3205 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>, 3206 Requires<[IsThumb, HasDB]> { 3207 bits<4> opt; 3208 let Inst{31-4} = 0xf3bf8f5; 3209 let Inst{3-0} = opt; 3210} 3211 3212def t2DSB : T2I<(outs), (ins memb_opt:$opt), NoItinerary, 3213 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>, 3214 Requires<[IsThumb, HasDB]> { 3215 bits<4> opt; 3216 let Inst{31-4} = 0xf3bf8f4; 3217 let Inst{3-0} = opt; 3218} 3219 3220def t2ISB : T2I<(outs), (ins instsyncb_opt:$opt), NoItinerary, 3221 "isb", "\t$opt", [(int_arm_isb (i32 imm0_15:$opt))]>, 3222 Requires<[IsThumb, HasDB]> { 3223 bits<4> opt; 3224 let Inst{31-4} = 0xf3bf8f6; 3225 let Inst{3-0} = opt; 3226} 3227 3228let hasNoSchedulingInfo = 1 in 3229def t2TSB : T2I<(outs), (ins tsb_opt:$opt), NoItinerary, 3230 "tsb", "\t$opt", []>, Requires<[IsThumb, HasV8_4a]> { 3231 let Inst{31-0} = 0xf3af8012; 3232} 3233} 3234 3235// Armv8.5-A speculation barrier 3236def t2SB : Thumb2XI<(outs), (ins), AddrModeNone, 4, NoItinerary, "sb", "", []>, 3237 Requires<[IsThumb2, HasSB]>, Sched<[]> { 3238 let Inst{31-0} = 0xf3bf8f70; 3239 let Unpredictable = 0x000f2f0f; 3240 let hasSideEffects = 1; 3241} 3242 3243class T2I_ldrex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz, 3244 InstrItinClass itin, string opc, string asm, string cstr, 3245 list<dag> pattern, bits<4> rt2 = 0b1111> 3246 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> { 3247 let Inst{31-27} = 0b11101; 3248 let Inst{26-20} = 0b0001101; 3249 let Inst{11-8} = rt2; 3250 let Inst{7-4} = opcod; 3251 let Inst{3-0} = 0b1111; 3252 3253 bits<4> addr; 3254 bits<4> Rt; 3255 let Inst{19-16} = addr; 3256 let Inst{15-12} = Rt; 3257} 3258class T2I_strex<bits<4> opcod, dag oops, dag iops, AddrMode am, int sz, 3259 InstrItinClass itin, string opc, string asm, string cstr, 3260 list<dag> pattern, bits<4> rt2 = 0b1111> 3261 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> { 3262 let Inst{31-27} = 0b11101; 3263 let Inst{26-20} = 0b0001100; 3264 let Inst{11-8} = rt2; 3265 let Inst{7-4} = opcod; 3266 3267 bits<4> Rd; 3268 bits<4> addr; 3269 bits<4> Rt; 3270 let Inst{3-0} = Rd; 3271 let Inst{19-16} = addr; 3272 let Inst{15-12} = Rt; 3273} 3274 3275let mayLoad = 1 in { 3276def t2LDREXB : T2I_ldrex<0b0100, (outs rGPR:$Rt), (ins addr_offset_none:$addr), 3277 AddrModeNone, 4, NoItinerary, 3278 "ldrexb", "\t$Rt, $addr", "", 3279 [(set rGPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>, 3280 Requires<[IsThumb, HasV8MBaseline]>; 3281def t2LDREXH : T2I_ldrex<0b0101, (outs rGPR:$Rt), (ins addr_offset_none:$addr), 3282 AddrModeNone, 4, NoItinerary, 3283 "ldrexh", "\t$Rt, $addr", "", 3284 [(set rGPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>, 3285 Requires<[IsThumb, HasV8MBaseline]>; 3286def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr), 3287 AddrModeT2_ldrex, 4, NoItinerary, 3288 "ldrex", "\t$Rt, $addr", "", 3289 [(set rGPR:$Rt, (ldrex_4 t2addrmode_imm0_1020s4:$addr))]>, 3290 Requires<[IsThumb, HasV8MBaseline]> { 3291 bits<4> Rt; 3292 bits<12> addr; 3293 let Inst{31-27} = 0b11101; 3294 let Inst{26-20} = 0b0000101; 3295 let Inst{19-16} = addr{11-8}; 3296 let Inst{15-12} = Rt; 3297 let Inst{11-8} = 0b1111; 3298 let Inst{7-0} = addr{7-0}; 3299} 3300let hasExtraDefRegAllocReq = 1 in 3301def t2LDREXD : T2I_ldrex<0b0111, (outs rGPR:$Rt, rGPR:$Rt2), 3302 (ins addr_offset_none:$addr), 3303 AddrModeNone, 4, NoItinerary, 3304 "ldrexd", "\t$Rt, $Rt2, $addr", "", 3305 [], {?, ?, ?, ?}>, 3306 Requires<[IsThumb2, IsNotMClass]> { 3307 bits<4> Rt2; 3308 let Inst{11-8} = Rt2; 3309} 3310def t2LDAEXB : T2I_ldrex<0b1100, (outs rGPR:$Rt), (ins addr_offset_none:$addr), 3311 AddrModeNone, 4, NoItinerary, 3312 "ldaexb", "\t$Rt, $addr", "", 3313 [(set rGPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>, 3314 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>; 3315def t2LDAEXH : T2I_ldrex<0b1101, (outs rGPR:$Rt), (ins addr_offset_none:$addr), 3316 AddrModeNone, 4, NoItinerary, 3317 "ldaexh", "\t$Rt, $addr", "", 3318 [(set rGPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>, 3319 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>; 3320def t2LDAEX : Thumb2I<(outs rGPR:$Rt), (ins addr_offset_none:$addr), 3321 AddrModeNone, 4, NoItinerary, 3322 "ldaex", "\t$Rt, $addr", "", 3323 [(set rGPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>, 3324 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]> { 3325 bits<4> Rt; 3326 bits<4> addr; 3327 let Inst{31-27} = 0b11101; 3328 let Inst{26-20} = 0b0001101; 3329 let Inst{19-16} = addr; 3330 let Inst{15-12} = Rt; 3331 let Inst{11-8} = 0b1111; 3332 let Inst{7-0} = 0b11101111; 3333} 3334let hasExtraDefRegAllocReq = 1 in 3335def t2LDAEXD : T2I_ldrex<0b1111, (outs rGPR:$Rt, rGPR:$Rt2), 3336 (ins addr_offset_none:$addr), 3337 AddrModeNone, 4, NoItinerary, 3338 "ldaexd", "\t$Rt, $Rt2, $addr", "", 3339 [], {?, ?, ?, ?}>, Requires<[IsThumb, 3340 HasAcquireRelease, HasV7Clrex, IsNotMClass]> { 3341 bits<4> Rt2; 3342 let Inst{11-8} = Rt2; 3343 3344 let Inst{7} = 1; 3345} 3346} 3347 3348let mayStore = 1, Constraints = "@earlyclobber $Rd" in { 3349def t2STREXB : T2I_strex<0b0100, (outs rGPR:$Rd), 3350 (ins rGPR:$Rt, addr_offset_none:$addr), 3351 AddrModeNone, 4, NoItinerary, 3352 "strexb", "\t$Rd, $Rt, $addr", "", 3353 [(set rGPR:$Rd, 3354 (strex_1 rGPR:$Rt, addr_offset_none:$addr))]>, 3355 Requires<[IsThumb, HasV8MBaseline]>; 3356def t2STREXH : T2I_strex<0b0101, (outs rGPR:$Rd), 3357 (ins rGPR:$Rt, addr_offset_none:$addr), 3358 AddrModeNone, 4, NoItinerary, 3359 "strexh", "\t$Rd, $Rt, $addr", "", 3360 [(set rGPR:$Rd, 3361 (strex_2 rGPR:$Rt, addr_offset_none:$addr))]>, 3362 Requires<[IsThumb, HasV8MBaseline]>; 3363 3364def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, 3365 t2addrmode_imm0_1020s4:$addr), 3366 AddrModeT2_ldrex, 4, NoItinerary, 3367 "strex", "\t$Rd, $Rt, $addr", "", 3368 [(set rGPR:$Rd, 3369 (strex_4 rGPR:$Rt, t2addrmode_imm0_1020s4:$addr))]>, 3370 Requires<[IsThumb, HasV8MBaseline]> { 3371 bits<4> Rd; 3372 bits<4> Rt; 3373 bits<12> addr; 3374 let Inst{31-27} = 0b11101; 3375 let Inst{26-20} = 0b0000100; 3376 let Inst{19-16} = addr{11-8}; 3377 let Inst{15-12} = Rt; 3378 let Inst{11-8} = Rd; 3379 let Inst{7-0} = addr{7-0}; 3380} 3381let hasExtraSrcRegAllocReq = 1 in 3382def t2STREXD : T2I_strex<0b0111, (outs rGPR:$Rd), 3383 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr), 3384 AddrModeNone, 4, NoItinerary, 3385 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [], 3386 {?, ?, ?, ?}>, 3387 Requires<[IsThumb2, IsNotMClass]> { 3388 bits<4> Rt2; 3389 let Inst{11-8} = Rt2; 3390} 3391def t2STLEXB : T2I_strex<0b1100, (outs rGPR:$Rd), 3392 (ins rGPR:$Rt, addr_offset_none:$addr), 3393 AddrModeNone, 4, NoItinerary, 3394 "stlexb", "\t$Rd, $Rt, $addr", "", 3395 [(set rGPR:$Rd, 3396 (stlex_1 rGPR:$Rt, addr_offset_none:$addr))]>, 3397 Requires<[IsThumb, HasAcquireRelease, 3398 HasV7Clrex]>; 3399 3400def t2STLEXH : T2I_strex<0b1101, (outs rGPR:$Rd), 3401 (ins rGPR:$Rt, addr_offset_none:$addr), 3402 AddrModeNone, 4, NoItinerary, 3403 "stlexh", "\t$Rd, $Rt, $addr", "", 3404 [(set rGPR:$Rd, 3405 (stlex_2 rGPR:$Rt, addr_offset_none:$addr))]>, 3406 Requires<[IsThumb, HasAcquireRelease, 3407 HasV7Clrex]>; 3408 3409def t2STLEX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, 3410 addr_offset_none:$addr), 3411 AddrModeNone, 4, NoItinerary, 3412 "stlex", "\t$Rd, $Rt, $addr", "", 3413 [(set rGPR:$Rd, 3414 (stlex_4 rGPR:$Rt, addr_offset_none:$addr))]>, 3415 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]> { 3416 bits<4> Rd; 3417 bits<4> Rt; 3418 bits<4> addr; 3419 let Inst{31-27} = 0b11101; 3420 let Inst{26-20} = 0b0001100; 3421 let Inst{19-16} = addr; 3422 let Inst{15-12} = Rt; 3423 let Inst{11-4} = 0b11111110; 3424 let Inst{3-0} = Rd; 3425} 3426let hasExtraSrcRegAllocReq = 1 in 3427def t2STLEXD : T2I_strex<0b1111, (outs rGPR:$Rd), 3428 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr), 3429 AddrModeNone, 4, NoItinerary, 3430 "stlexd", "\t$Rd, $Rt, $Rt2, $addr", "", [], 3431 {?, ?, ?, ?}>, Requires<[IsThumb, HasAcquireRelease, 3432 HasV7Clrex, IsNotMClass]> { 3433 bits<4> Rt2; 3434 let Inst{11-8} = Rt2; 3435} 3436} 3437 3438def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", [(int_arm_clrex)]>, 3439 Requires<[IsThumb, HasV7Clrex]> { 3440 let Inst{31-16} = 0xf3bf; 3441 let Inst{15-14} = 0b10; 3442 let Inst{13} = 0; 3443 let Inst{12} = 0; 3444 let Inst{11-8} = 0b1111; 3445 let Inst{7-4} = 0b0010; 3446 let Inst{3-0} = 0b1111; 3447} 3448 3449def : T2Pat<(and (ldrex_1 addr_offset_none:$addr), 0xff), 3450 (t2LDREXB addr_offset_none:$addr)>, 3451 Requires<[IsThumb, HasV8MBaseline]>; 3452def : T2Pat<(and (ldrex_2 addr_offset_none:$addr), 0xffff), 3453 (t2LDREXH addr_offset_none:$addr)>, 3454 Requires<[IsThumb, HasV8MBaseline]>; 3455def : T2Pat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 3456 (t2STREXB GPR:$Rt, addr_offset_none:$addr)>, 3457 Requires<[IsThumb, HasV8MBaseline]>; 3458def : T2Pat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 3459 (t2STREXH GPR:$Rt, addr_offset_none:$addr)>, 3460 Requires<[IsThumb, HasV8MBaseline]>; 3461 3462def : T2Pat<(and (ldaex_1 addr_offset_none:$addr), 0xff), 3463 (t2LDAEXB addr_offset_none:$addr)>, 3464 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>; 3465def : T2Pat<(and (ldaex_2 addr_offset_none:$addr), 0xffff), 3466 (t2LDAEXH addr_offset_none:$addr)>, 3467 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>; 3468def : T2Pat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr), 3469 (t2STLEXB GPR:$Rt, addr_offset_none:$addr)>, 3470 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>; 3471def : T2Pat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr), 3472 (t2STLEXH GPR:$Rt, addr_offset_none:$addr)>, 3473 Requires<[IsThumb, HasAcquireRelease, HasV7Clrex]>; 3474 3475//===----------------------------------------------------------------------===// 3476// SJLJ Exception handling intrinsics 3477// eh_sjlj_setjmp() is an instruction sequence to store the return 3478// address and save #0 in R0 for the non-longjmp case. 3479// Since by its nature we may be coming from some other function to get 3480// here, and we're using the stack frame for the containing function to 3481// save/restore registers, we can't keep anything live in regs across 3482// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 3483// when we get here from a longjmp(). We force everything out of registers 3484// except for our own input by listing the relevant registers in Defs. By 3485// doing so, we also cause the prologue/epilogue code to actively preserve 3486// all of the callee-saved resgisters, which is exactly what we want. 3487// $val is a scratch register for our use. 3488let Defs = 3489 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 3490 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15], 3491 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 3492 usesCustomInserter = 1 in { 3493 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val), 3494 AddrModeNone, 0, NoItinerary, "", "", 3495 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>, 3496 Requires<[IsThumb2, HasVFP2]>; 3497} 3498 3499let Defs = 3500 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 3501 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 3502 usesCustomInserter = 1 in { 3503 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val), 3504 AddrModeNone, 0, NoItinerary, "", "", 3505 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>, 3506 Requires<[IsThumb2, NoVFP]>; 3507} 3508 3509 3510//===----------------------------------------------------------------------===// 3511// Control-Flow Instructions 3512// 3513 3514// FIXME: remove when we have a way to marking a MI with these properties. 3515// FIXME: Should pc be an implicit operand like PICADD, etc? 3516let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 3517 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in 3518def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, 3519 reglist:$regs, variable_ops), 3520 4, IIC_iLoad_mBr, [], 3521 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, 3522 RegConstraint<"$Rn = $wb">; 3523 3524let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 3525let isPredicable = 1 in 3526def t2B : T2I<(outs), (ins thumb_br_target:$target), IIC_Br, 3527 "b", ".w\t$target", 3528 [(br bb:$target)]>, Sched<[WriteBr]>, 3529 Requires<[IsThumb, HasV8MBaseline]> { 3530 let Inst{31-27} = 0b11110; 3531 let Inst{15-14} = 0b10; 3532 let Inst{12} = 1; 3533 3534 bits<24> target; 3535 let Inst{26} = target{23}; 3536 let Inst{13} = target{22}; 3537 let Inst{11} = target{21}; 3538 let Inst{25-16} = target{20-11}; 3539 let Inst{10-0} = target{10-0}; 3540 let DecoderMethod = "DecodeT2BInstruction"; 3541 let AsmMatchConverter = "cvtThumbBranches"; 3542} 3543 3544let Size = 4, isNotDuplicable = 1, isBranch = 1, isTerminator = 1, 3545 isBarrier = 1, isIndirectBranch = 1 in { 3546 3547// available in both v8-M.Baseline and Thumb2 targets 3548def t2BR_JT : t2basePseudoInst<(outs), 3549 (ins GPR:$target, GPR:$index, i32imm:$jt), 3550 0, IIC_Br, 3551 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt)]>, 3552 Sched<[WriteBr]>; 3553 3554// FIXME: Add a case that can be predicated. 3555def t2TBB_JT : t2PseudoInst<(outs), 3556 (ins GPR:$base, GPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>, 3557 Sched<[WriteBr]>; 3558 3559def t2TBH_JT : t2PseudoInst<(outs), 3560 (ins GPR:$base, GPR:$index, i32imm:$jt, i32imm:$pclbl), 0, IIC_Br, []>, 3561 Sched<[WriteBr]>; 3562 3563def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br, 3564 "tbb", "\t$addr", []>, Sched<[WriteBrTbl]> { 3565 bits<4> Rn; 3566 bits<4> Rm; 3567 let Inst{31-20} = 0b111010001101; 3568 let Inst{19-16} = Rn; 3569 let Inst{15-5} = 0b11110000000; 3570 let Inst{4} = 0; // B form 3571 let Inst{3-0} = Rm; 3572 3573 let DecoderMethod = "DecodeThumbTableBranch"; 3574} 3575 3576def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br, 3577 "tbh", "\t$addr", []>, Sched<[WriteBrTbl]> { 3578 bits<4> Rn; 3579 bits<4> Rm; 3580 let Inst{31-20} = 0b111010001101; 3581 let Inst{19-16} = Rn; 3582 let Inst{15-5} = 0b11110000000; 3583 let Inst{4} = 1; // H form 3584 let Inst{3-0} = Rm; 3585 3586 let DecoderMethod = "DecodeThumbTableBranch"; 3587} 3588} // isNotDuplicable, isIndirectBranch 3589 3590} // isBranch, isTerminator, isBarrier 3591 3592// FIXME: should be able to write a pattern for ARMBrcond, but can't use 3593// a two-value operand where a dag node expects ", "two operands. :( 3594let isBranch = 1, isTerminator = 1 in 3595def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br, 3596 "b", ".w\t$target", 3597 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, Sched<[WriteBr]> { 3598 let Inst{31-27} = 0b11110; 3599 let Inst{15-14} = 0b10; 3600 let Inst{12} = 0; 3601 3602 bits<4> p; 3603 let Inst{25-22} = p; 3604 3605 bits<21> target; 3606 let Inst{26} = target{20}; 3607 let Inst{11} = target{19}; 3608 let Inst{13} = target{18}; 3609 let Inst{21-16} = target{17-12}; 3610 let Inst{10-0} = target{11-1}; 3611 3612 let DecoderMethod = "DecodeThumb2BCCInstruction"; 3613 let AsmMatchConverter = "cvtThumbBranches"; 3614} 3615 3616// Tail calls. The MachO version of thumb tail calls uses a t2 branch, so 3617// it goes here. 3618let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 3619 // IOS version. 3620 let Uses = [SP] in 3621 def tTAILJMPd: tPseudoExpand<(outs), 3622 (ins thumb_br_target:$dst, pred:$p), 3623 4, IIC_Br, [], 3624 (t2B thumb_br_target:$dst, pred:$p)>, 3625 Requires<[IsThumb2, IsMachO]>, Sched<[WriteBr]>; 3626} 3627 3628// IT block 3629let Defs = [ITSTATE] in 3630def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask), 3631 AddrModeNone, 2, IIC_iALUx, 3632 "it$mask\t$cc", "", []>, 3633 ComplexDeprecationPredicate<"IT"> { 3634 // 16-bit instruction. 3635 let Inst{31-16} = 0x0000; 3636 let Inst{15-8} = 0b10111111; 3637 3638 bits<4> cc; 3639 bits<4> mask; 3640 let Inst{7-4} = cc; 3641 let Inst{3-0} = mask; 3642 3643 let DecoderMethod = "DecodeIT"; 3644} 3645 3646// Branch and Exchange Jazelle -- for disassembly only 3647// Rm = Inst{19-16} 3648let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in 3649def t2BXJ : T2I<(outs), (ins GPRnopc:$func), NoItinerary, "bxj", "\t$func", []>, 3650 Sched<[WriteBr]>, Requires<[IsThumb2, IsNotMClass]> { 3651 bits<4> func; 3652 let Inst{31-27} = 0b11110; 3653 let Inst{26} = 0; 3654 let Inst{25-20} = 0b111100; 3655 let Inst{19-16} = func; 3656 let Inst{15-0} = 0b1000111100000000; 3657} 3658 3659// Compare and branch on zero / non-zero 3660let isBranch = 1, isTerminator = 1 in { 3661 def tCBZ : T1I<(outs), (ins tGPR:$Rn, thumb_cb_target:$target), IIC_Br, 3662 "cbz\t$Rn, $target", []>, 3663 T1Misc<{0,0,?,1,?,?,?}>, 3664 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteBr]> { 3665 // A8.6.27 3666 bits<6> target; 3667 bits<3> Rn; 3668 let Inst{9} = target{5}; 3669 let Inst{7-3} = target{4-0}; 3670 let Inst{2-0} = Rn; 3671 } 3672 3673 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, thumb_cb_target:$target), IIC_Br, 3674 "cbnz\t$Rn, $target", []>, 3675 T1Misc<{1,0,?,1,?,?,?}>, 3676 Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteBr]> { 3677 // A8.6.27 3678 bits<6> target; 3679 bits<3> Rn; 3680 let Inst{9} = target{5}; 3681 let Inst{7-3} = target{4-0}; 3682 let Inst{2-0} = Rn; 3683 } 3684} 3685 3686 3687// Change Processor State is a system instruction. 3688// FIXME: Since the asm parser has currently no clean way to handle optional 3689// operands, create 3 versions of the same instruction. Once there's a clean 3690// framework to represent optional operands, change this behavior. 3691class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary, 3692 !strconcat("cps", asm_op), []>, 3693 Requires<[IsThumb2, IsNotMClass]> { 3694 bits<2> imod; 3695 bits<3> iflags; 3696 bits<5> mode; 3697 bit M; 3698 3699 let Inst{31-11} = 0b111100111010111110000; 3700 let Inst{10-9} = imod; 3701 let Inst{8} = M; 3702 let Inst{7-5} = iflags; 3703 let Inst{4-0} = mode; 3704 let DecoderMethod = "DecodeT2CPSInstruction"; 3705} 3706 3707let M = 1 in 3708 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode), 3709 "$imod\t$iflags, $mode">; 3710let mode = 0, M = 0 in 3711 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags), 3712 "$imod.w\t$iflags">; 3713let imod = 0, iflags = 0, M = 1 in 3714 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">; 3715 3716def : t2InstAlias<"cps$imod.w $iflags, $mode", 3717 (t2CPS3p imod_op:$imod, iflags_op:$iflags, i32imm:$mode), 0>; 3718def : t2InstAlias<"cps.w $mode", (t2CPS1p imm0_31:$mode), 0>; 3719 3720// A6.3.4 Branches and miscellaneous control 3721// Table A6-14 Change Processor State, and hint instructions 3722def t2HINT : T2I<(outs), (ins imm0_239:$imm), NoItinerary, "hint", ".w\t$imm", 3723 [(int_arm_hint imm0_239:$imm)]> { 3724 bits<8> imm; 3725 let Inst{31-3} = 0b11110011101011111000000000000; 3726 let Inst{7-0} = imm; 3727} 3728 3729def : t2InstAlias<"hint$p $imm", (t2HINT imm0_239:$imm, pred:$p), 0>; 3730def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p), 1>; 3731def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p), 1>; 3732def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p), 1>; 3733def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p), 1>; 3734def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p), 1>; 3735def : t2InstAlias<"sevl$p.w", (t2HINT 5, pred:$p), 1> { 3736 let Predicates = [IsThumb2, HasV8]; 3737} 3738def : t2InstAlias<"esb$p.w", (t2HINT 16, pred:$p), 1> { 3739 let Predicates = [IsThumb2, HasRAS]; 3740} 3741def : t2InstAlias<"esb$p", (t2HINT 16, pred:$p), 0> { 3742 let Predicates = [IsThumb2, HasRAS]; 3743} 3744def : t2InstAlias<"csdb$p.w", (t2HINT 20, pred:$p), 0>; 3745def : t2InstAlias<"csdb$p", (t2HINT 20, pred:$p), 1>; 3746 3747def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", 3748 [(int_arm_dbg imm0_15:$opt)]> { 3749 bits<4> opt; 3750 let Inst{31-20} = 0b111100111010; 3751 let Inst{19-16} = 0b1111; 3752 let Inst{15-8} = 0b10000000; 3753 let Inst{7-4} = 0b1111; 3754 let Inst{3-0} = opt; 3755} 3756 3757// Secure Monitor Call is a system instruction. 3758// Option = Inst{19-16} 3759let isCall = 1, Uses = [SP] in 3760def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", 3761 []>, Requires<[IsThumb2, HasTrustZone]> { 3762 let Inst{31-27} = 0b11110; 3763 let Inst{26-20} = 0b1111111; 3764 let Inst{15-12} = 0b1000; 3765 3766 bits<4> opt; 3767 let Inst{19-16} = opt; 3768} 3769 3770class T2DCPS<bits<2> opt, string opc> 3771 : T2I<(outs), (ins), NoItinerary, opc, "", []>, Requires<[IsThumb2, HasV8]> { 3772 let Inst{31-27} = 0b11110; 3773 let Inst{26-20} = 0b1111000; 3774 let Inst{19-16} = 0b1111; 3775 let Inst{15-12} = 0b1000; 3776 let Inst{11-2} = 0b0000000000; 3777 let Inst{1-0} = opt; 3778} 3779 3780def t2DCPS1 : T2DCPS<0b01, "dcps1">; 3781def t2DCPS2 : T2DCPS<0b10, "dcps2">; 3782def t2DCPS3 : T2DCPS<0b11, "dcps3">; 3783 3784class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin, 3785 string opc, string asm, list<dag> pattern> 3786 : T2I<oops, iops, itin, opc, asm, pattern>, 3787 Requires<[IsThumb2,IsNotMClass]> { 3788 bits<5> mode; 3789 let Inst{31-25} = 0b1110100; 3790 let Inst{24-23} = Op; 3791 let Inst{22} = 0; 3792 let Inst{21} = W; 3793 let Inst{20-16} = 0b01101; 3794 let Inst{15-5} = 0b11000000000; 3795 let Inst{4-0} = mode{4-0}; 3796} 3797 3798// Store Return State is a system instruction. 3799def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary, 3800 "srsdb", "\tsp!, $mode", []>; 3801def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary, 3802 "srsdb","\tsp, $mode", []>; 3803def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary, 3804 "srsia","\tsp!, $mode", []>; 3805def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary, 3806 "srsia","\tsp, $mode", []>; 3807 3808 3809def : t2InstAlias<"srsdb${p} $mode", (t2SRSDB imm0_31:$mode, pred:$p)>; 3810def : t2InstAlias<"srsdb${p} $mode!", (t2SRSDB_UPD imm0_31:$mode, pred:$p)>; 3811 3812def : t2InstAlias<"srsia${p} $mode", (t2SRSIA imm0_31:$mode, pred:$p)>; 3813def : t2InstAlias<"srsia${p} $mode!", (t2SRSIA_UPD imm0_31:$mode, pred:$p)>; 3814 3815// Return From Exception is a system instruction. 3816let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in 3817class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin, 3818 string opc, string asm, list<dag> pattern> 3819 : T2I<oops, iops, itin, opc, asm, pattern>, 3820 Requires<[IsThumb2,IsNotMClass]> { 3821 let Inst{31-20} = op31_20{11-0}; 3822 3823 bits<4> Rn; 3824 let Inst{19-16} = Rn; 3825 let Inst{15-0} = 0xc000; 3826} 3827 3828def t2RFEDBW : T2RFE<0b111010000011, 3829 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!", 3830 [/* For disassembly only; pattern left blank */]>; 3831def t2RFEDB : T2RFE<0b111010000001, 3832 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn", 3833 [/* For disassembly only; pattern left blank */]>; 3834def t2RFEIAW : T2RFE<0b111010011011, 3835 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!", 3836 [/* For disassembly only; pattern left blank */]>; 3837def t2RFEIA : T2RFE<0b111010011001, 3838 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn", 3839 [/* For disassembly only; pattern left blank */]>; 3840 3841// B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction. 3842// Exception return instruction is "subs pc, lr, #imm". 3843let isReturn = 1, isBarrier = 1, isTerminator = 1, Defs = [PC] in 3844def t2SUBS_PC_LR : T2I <(outs), (ins imm0_255:$imm), NoItinerary, 3845 "subs", "\tpc, lr, $imm", 3846 [(ARMintretflag imm0_255:$imm)]>, 3847 Requires<[IsThumb2,IsNotMClass]> { 3848 let Inst{31-8} = 0b111100111101111010001111; 3849 3850 bits<8> imm; 3851 let Inst{7-0} = imm; 3852} 3853 3854// Hypervisor Call is a system instruction. 3855let isCall = 1 in { 3856def t2HVC : T2XI <(outs), (ins imm0_65535:$imm16), IIC_Br, "hvc.w\t$imm16", []>, 3857 Requires<[IsThumb2, HasVirtualization]>, Sched<[WriteBr]> { 3858 bits<16> imm16; 3859 let Inst{31-20} = 0b111101111110; 3860 let Inst{19-16} = imm16{15-12}; 3861 let Inst{15-12} = 0b1000; 3862 let Inst{11-0} = imm16{11-0}; 3863} 3864} 3865 3866// Alias for HVC without the ".w" optional width specifier 3867def : t2InstAlias<"hvc\t$imm16", (t2HVC imm0_65535:$imm16)>; 3868 3869// ERET - Return from exception in Hypervisor mode. 3870// B9.3.3, B9.3.20: ERET is an alias for "SUBS PC, LR, #0" in an implementation that 3871// includes virtualization extensions. 3872def t2ERET : InstAlias<"eret${p}", (t2SUBS_PC_LR 0, pred:$p), 1>, 3873 Requires<[IsThumb2, HasVirtualization]>; 3874 3875//===----------------------------------------------------------------------===// 3876// Non-Instruction Patterns 3877// 3878 3879// 32-bit immediate using movw + movt. 3880// This is a single pseudo instruction to make it re-materializable. 3881// FIXME: Remove this when we can do generalized remat. 3882let isReMaterializable = 1, isMoveImm = 1 in 3883def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 3884 [(set rGPR:$dst, (i32 imm:$src))]>, 3885 Requires<[IsThumb, UseMovt]>; 3886 3887// Pseudo instruction that combines movw + movt + add pc (if pic). 3888// It also makes it possible to rematerialize the instructions. 3889// FIXME: Remove this when we can do generalized remat and when machine licm 3890// can properly the instructions. 3891let isReMaterializable = 1 in { 3892def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr), 3893 IIC_iMOVix2addpc, 3894 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, 3895 Requires<[IsThumb, HasV8MBaseline, UseMovtInPic]>; 3896 3897} 3898 3899def : T2Pat<(ARMWrapperPIC tglobaltlsaddr :$dst), 3900 (t2MOV_ga_pcrel tglobaltlsaddr:$dst)>, 3901 Requires<[IsThumb2, UseMovtInPic]>; 3902def : T2Pat<(ARMWrapper tglobaltlsaddr:$dst), 3903 (t2MOVi32imm tglobaltlsaddr:$dst)>, 3904 Requires<[IsThumb2, UseMovt]>; 3905 3906// ConstantPool, GlobalAddress, and JumpTable 3907def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>; 3908def : T2Pat<(ARMWrapper texternalsym :$dst), (t2MOVi32imm texternalsym :$dst)>, 3909 Requires<[IsThumb, HasV8MBaseline, UseMovt]>; 3910def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>, 3911 Requires<[IsThumb, HasV8MBaseline, UseMovt]>; 3912 3913def : T2Pat<(ARMWrapperJT tjumptable:$dst), (t2LEApcrelJT tjumptable:$dst)>; 3914 3915// Pseudo instruction that combines ldr from constpool and add pc. This should 3916// be expanded into two instructions late to allow if-conversion and 3917// scheduling. 3918let canFoldAsLoad = 1, isReMaterializable = 1 in 3919def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp), 3920 IIC_iLoadiALU, 3921 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 3922 imm:$cp))]>, 3923 Requires<[IsThumb2]>; 3924 3925// Pseudo isntruction that combines movs + predicated rsbmi 3926// to implement integer ABS 3927let usesCustomInserter = 1, Defs = [CPSR] in { 3928def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src), 3929 NoItinerary, []>, Requires<[IsThumb2]>; 3930} 3931 3932//===----------------------------------------------------------------------===// 3933// Coprocessor load/store -- for disassembly only 3934// 3935class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm, list<dag> pattern> 3936 : T2I<oops, iops, NoItinerary, opc, asm, pattern> { 3937 let Inst{31-28} = op31_28; 3938 let Inst{27-25} = 0b110; 3939} 3940 3941multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm, list<dag> pattern> { 3942 def _OFFSET : T2CI<op31_28, 3943 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 3944 asm, "\t$cop, $CRd, $addr", pattern> { 3945 bits<13> addr; 3946 bits<4> cop; 3947 bits<4> CRd; 3948 let Inst{24} = 1; // P = 1 3949 let Inst{23} = addr{8}; 3950 let Inst{22} = Dbit; 3951 let Inst{21} = 0; // W = 0 3952 let Inst{20} = load; 3953 let Inst{19-16} = addr{12-9}; 3954 let Inst{15-12} = CRd; 3955 let Inst{11-8} = cop; 3956 let Inst{7-0} = addr{7-0}; 3957 let DecoderMethod = "DecodeCopMemInstruction"; 3958 } 3959 def _PRE : T2CI<op31_28, 3960 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr), 3961 asm, "\t$cop, $CRd, $addr!", []> { 3962 bits<13> addr; 3963 bits<4> cop; 3964 bits<4> CRd; 3965 let Inst{24} = 1; // P = 1 3966 let Inst{23} = addr{8}; 3967 let Inst{22} = Dbit; 3968 let Inst{21} = 1; // W = 1 3969 let Inst{20} = load; 3970 let Inst{19-16} = addr{12-9}; 3971 let Inst{15-12} = CRd; 3972 let Inst{11-8} = cop; 3973 let Inst{7-0} = addr{7-0}; 3974 let DecoderMethod = "DecodeCopMemInstruction"; 3975 } 3976 def _POST: T2CI<op31_28, 3977 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 3978 postidx_imm8s4:$offset), 3979 asm, "\t$cop, $CRd, $addr, $offset", []> { 3980 bits<9> offset; 3981 bits<4> addr; 3982 bits<4> cop; 3983 bits<4> CRd; 3984 let Inst{24} = 0; // P = 0 3985 let Inst{23} = offset{8}; 3986 let Inst{22} = Dbit; 3987 let Inst{21} = 1; // W = 1 3988 let Inst{20} = load; 3989 let Inst{19-16} = addr; 3990 let Inst{15-12} = CRd; 3991 let Inst{11-8} = cop; 3992 let Inst{7-0} = offset{7-0}; 3993 let DecoderMethod = "DecodeCopMemInstruction"; 3994 } 3995 def _OPTION : T2CI<op31_28, (outs), 3996 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 3997 coproc_option_imm:$option), 3998 asm, "\t$cop, $CRd, $addr, $option", []> { 3999 bits<8> option; 4000 bits<4> addr; 4001 bits<4> cop; 4002 bits<4> CRd; 4003 let Inst{24} = 0; // P = 0 4004 let Inst{23} = 1; // U = 1 4005 let Inst{22} = Dbit; 4006 let Inst{21} = 0; // W = 0 4007 let Inst{20} = load; 4008 let Inst{19-16} = addr; 4009 let Inst{15-12} = CRd; 4010 let Inst{11-8} = cop; 4011 let Inst{7-0} = option; 4012 let DecoderMethod = "DecodeCopMemInstruction"; 4013 } 4014} 4015 4016let DecoderNamespace = "Thumb2CoProc" in { 4017defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc", [(int_arm_ldc imm:$cop, imm:$CRd, addrmode5:$addr)]>; 4018defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl", [(int_arm_ldcl imm:$cop, imm:$CRd, addrmode5:$addr)]>; 4019defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2", [(int_arm_ldc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>; 4020defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l", [(int_arm_ldc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>; 4021 4022defm t2STC : t2LdStCop<0b1110, 0, 0, "stc", [(int_arm_stc imm:$cop, imm:$CRd, addrmode5:$addr)]>; 4023defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl", [(int_arm_stcl imm:$cop, imm:$CRd, addrmode5:$addr)]>; 4024defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2", [(int_arm_stc2 imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>; 4025defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l", [(int_arm_stc2l imm:$cop, imm:$CRd, addrmode5:$addr)]>, Requires<[PreV8,IsThumb2]>; 4026} 4027 4028 4029//===----------------------------------------------------------------------===// 4030// Move between special register and ARM core register -- for disassembly only 4031// 4032// Move to ARM core register from Special Register 4033 4034// A/R class MRS. 4035// 4036// A/R class can only move from CPSR or SPSR. 4037def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", 4038 []>, Requires<[IsThumb2,IsNotMClass]> { 4039 bits<4> Rd; 4040 let Inst{31-12} = 0b11110011111011111000; 4041 let Inst{11-8} = Rd; 4042 let Inst{7-0} = 0b00000000; 4043} 4044 4045def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>; 4046 4047def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", 4048 []>, Requires<[IsThumb2,IsNotMClass]> { 4049 bits<4> Rd; 4050 let Inst{31-12} = 0b11110011111111111000; 4051 let Inst{11-8} = Rd; 4052 let Inst{7-0} = 0b00000000; 4053} 4054 4055def t2MRSbanked : T2I<(outs rGPR:$Rd), (ins banked_reg:$banked), 4056 NoItinerary, "mrs", "\t$Rd, $banked", []>, 4057 Requires<[IsThumb, HasVirtualization]> { 4058 bits<6> banked; 4059 bits<4> Rd; 4060 4061 let Inst{31-21} = 0b11110011111; 4062 let Inst{20} = banked{5}; // R bit 4063 let Inst{19-16} = banked{3-0}; 4064 let Inst{15-12} = 0b1000; 4065 let Inst{11-8} = Rd; 4066 let Inst{7-5} = 0b001; 4067 let Inst{4} = banked{4}; 4068 let Inst{3-0} = 0b0000; 4069} 4070 4071 4072// M class MRS. 4073// 4074// This MRS has a mask field in bits 7-0 and can take more values than 4075// the A/R class (a full msr_mask). 4076def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$SYSm), NoItinerary, 4077 "mrs", "\t$Rd, $SYSm", []>, 4078 Requires<[IsThumb,IsMClass]> { 4079 bits<4> Rd; 4080 bits<8> SYSm; 4081 let Inst{31-12} = 0b11110011111011111000; 4082 let Inst{11-8} = Rd; 4083 let Inst{7-0} = SYSm; 4084 4085 let Unpredictable{20-16} = 0b11111; 4086 let Unpredictable{13} = 0b1; 4087} 4088 4089 4090// Move from ARM core register to Special Register 4091// 4092// A/R class MSR. 4093// 4094// No need to have both system and application versions, the encodings are the 4095// same and the assembly parser has no way to distinguish between them. The mask 4096// operand contains the special register (R Bit) in bit 4 and bits 3-0 contains 4097// the mask with the fields to be accessed in the special register. 4098let Defs = [CPSR] in 4099def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn), 4100 NoItinerary, "msr", "\t$mask, $Rn", []>, 4101 Requires<[IsThumb2,IsNotMClass]> { 4102 bits<5> mask; 4103 bits<4> Rn; 4104 let Inst{31-21} = 0b11110011100; 4105 let Inst{20} = mask{4}; // R Bit 4106 let Inst{19-16} = Rn; 4107 let Inst{15-12} = 0b1000; 4108 let Inst{11-8} = mask{3-0}; 4109 let Inst{7-0} = 0; 4110} 4111 4112// However, the MSR (banked register) system instruction (ARMv7VE) *does* have a 4113// separate encoding (distinguished by bit 5. 4114def t2MSRbanked : T2I<(outs), (ins banked_reg:$banked, rGPR:$Rn), 4115 NoItinerary, "msr", "\t$banked, $Rn", []>, 4116 Requires<[IsThumb, HasVirtualization]> { 4117 bits<6> banked; 4118 bits<4> Rn; 4119 4120 let Inst{31-21} = 0b11110011100; 4121 let Inst{20} = banked{5}; // R bit 4122 let Inst{19-16} = Rn; 4123 let Inst{15-12} = 0b1000; 4124 let Inst{11-8} = banked{3-0}; 4125 let Inst{7-5} = 0b001; 4126 let Inst{4} = banked{4}; 4127 let Inst{3-0} = 0b0000; 4128} 4129 4130 4131// M class MSR. 4132// 4133// Move from ARM core register to Special Register 4134let Defs = [CPSR] in 4135def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn), 4136 NoItinerary, "msr", "\t$SYSm, $Rn", []>, 4137 Requires<[IsThumb,IsMClass]> { 4138 bits<12> SYSm; 4139 bits<4> Rn; 4140 let Inst{31-21} = 0b11110011100; 4141 let Inst{20} = 0b0; 4142 let Inst{19-16} = Rn; 4143 let Inst{15-12} = 0b1000; 4144 let Inst{11-10} = SYSm{11-10}; 4145 let Inst{9-8} = 0b00; 4146 let Inst{7-0} = SYSm{7-0}; 4147 4148 let Unpredictable{20} = 0b1; 4149 let Unpredictable{13} = 0b1; 4150 let Unpredictable{9-8} = 0b11; 4151} 4152 4153 4154//===----------------------------------------------------------------------===// 4155// Move between coprocessor and ARM core register 4156// 4157 4158class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops, 4159 list<dag> pattern> 4160 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", 4161 pattern> { 4162 let Inst{27-24} = 0b1110; 4163 let Inst{20} = direction; 4164 let Inst{4} = 1; 4165 4166 bits<4> Rt; 4167 bits<4> cop; 4168 bits<3> opc1; 4169 bits<3> opc2; 4170 bits<4> CRm; 4171 bits<4> CRn; 4172 4173 let Inst{15-12} = Rt; 4174 let Inst{11-8} = cop; 4175 let Inst{23-21} = opc1; 4176 let Inst{7-5} = opc2; 4177 let Inst{3-0} = CRm; 4178 let Inst{19-16} = CRn; 4179 4180 let DecoderNamespace = "Thumb2CoProc"; 4181} 4182 4183class t2MovRRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops, 4184 list<dag> pattern = []> 4185 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> { 4186 let Inst{27-24} = 0b1100; 4187 let Inst{23-21} = 0b010; 4188 let Inst{20} = direction; 4189 4190 bits<4> Rt; 4191 bits<4> Rt2; 4192 bits<4> cop; 4193 bits<4> opc1; 4194 bits<4> CRm; 4195 4196 let Inst{15-12} = Rt; 4197 let Inst{19-16} = Rt2; 4198 let Inst{11-8} = cop; 4199 let Inst{7-4} = opc1; 4200 let Inst{3-0} = CRm; 4201 4202 let DecoderNamespace = "Thumb2CoProc"; 4203} 4204 4205/* from ARM core register to coprocessor */ 4206def t2MCR : t2MovRCopro<0b1110, "mcr", 0, 4207 (outs), 4208 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4209 c_imm:$CRm, imm0_7:$opc2), 4210 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 4211 imm:$CRm, imm:$opc2)]>, 4212 ComplexDeprecationPredicate<"MCR">; 4213def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm", 4214 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4215 c_imm:$CRm, 0, pred:$p)>; 4216def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0, 4217 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4218 c_imm:$CRm, imm0_7:$opc2), 4219 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 4220 imm:$CRm, imm:$opc2)]> { 4221 let Predicates = [IsThumb2, PreV8]; 4222} 4223def : t2InstAlias<"mcr2${p} $cop, $opc1, $Rt, $CRn, $CRm", 4224 (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 4225 c_imm:$CRm, 0, pred:$p)>; 4226 4227/* from coprocessor to ARM core register */ 4228def t2MRC : t2MovRCopro<0b1110, "mrc", 1, 4229 (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 4230 c_imm:$CRm, imm0_7:$opc2), []>; 4231def : t2InstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm", 4232 (t2MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 4233 c_imm:$CRm, 0, pred:$p)>; 4234 4235def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1, 4236 (outs GPRwithAPSR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 4237 c_imm:$CRm, imm0_7:$opc2), []> { 4238 let Predicates = [IsThumb2, PreV8]; 4239} 4240def : t2InstAlias<"mrc2${p} $cop, $opc1, $Rt, $CRn, $CRm", 4241 (t2MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 4242 c_imm:$CRm, 0, pred:$p)>; 4243 4244def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), 4245 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 4246 4247def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), 4248 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 4249 4250 4251/* from ARM core register to coprocessor */ 4252def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0, (outs), 4253 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, 4254 c_imm:$CRm), 4255 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, 4256 imm:$CRm)]>; 4257def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0, (outs), 4258 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, 4259 c_imm:$CRm), 4260 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, 4261 GPR:$Rt2, imm:$CRm)]> { 4262 let Predicates = [IsThumb2, PreV8]; 4263} 4264 4265/* from coprocessor to ARM core register */ 4266def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1, (outs GPR:$Rt, GPR:$Rt2), 4267 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm)>; 4268 4269def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1, (outs GPR:$Rt, GPR:$Rt2), 4270 (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm)> { 4271 let Predicates = [IsThumb2, PreV8]; 4272} 4273 4274//===----------------------------------------------------------------------===// 4275// Other Coprocessor Instructions. 4276// 4277 4278def t2CDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4279 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4280 "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4281 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4282 imm:$CRm, imm:$opc2)]> { 4283 let Inst{27-24} = 0b1110; 4284 4285 bits<4> opc1; 4286 bits<4> CRn; 4287 bits<4> CRd; 4288 bits<4> cop; 4289 bits<3> opc2; 4290 bits<4> CRm; 4291 4292 let Inst{3-0} = CRm; 4293 let Inst{4} = 0; 4294 let Inst{7-5} = opc2; 4295 let Inst{11-8} = cop; 4296 let Inst{15-12} = CRd; 4297 let Inst{19-16} = CRn; 4298 let Inst{23-20} = opc1; 4299 4300 let Predicates = [IsThumb2, PreV8]; 4301 let DecoderNamespace = "Thumb2CoProc"; 4302} 4303 4304def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1, 4305 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 4306 "cdp2", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 4307 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 4308 imm:$CRm, imm:$opc2)]> { 4309 let Inst{27-24} = 0b1110; 4310 4311 bits<4> opc1; 4312 bits<4> CRn; 4313 bits<4> CRd; 4314 bits<4> cop; 4315 bits<3> opc2; 4316 bits<4> CRm; 4317 4318 let Inst{3-0} = CRm; 4319 let Inst{4} = 0; 4320 let Inst{7-5} = opc2; 4321 let Inst{11-8} = cop; 4322 let Inst{15-12} = CRd; 4323 let Inst{19-16} = CRn; 4324 let Inst{23-20} = opc1; 4325 4326 let Predicates = [IsThumb2, PreV8]; 4327 let DecoderNamespace = "Thumb2CoProc"; 4328} 4329 4330 4331 4332//===----------------------------------------------------------------------===// 4333// ARMv8.1 Privilege Access Never extension 4334// 4335// SETPAN #imm1 4336 4337def t2SETPAN : T1I<(outs), (ins imm0_1:$imm), NoItinerary, "setpan\t$imm", []>, 4338 T1Misc<0b0110000>, Requires<[IsThumb2, HasV8, HasV8_1a]> { 4339 bits<1> imm; 4340 4341 let Inst{4} = 0b1; 4342 let Inst{3} = imm; 4343 let Inst{2-0} = 0b000; 4344 4345 let Unpredictable{4} = 0b1; 4346 let Unpredictable{2-0} = 0b111; 4347} 4348 4349//===----------------------------------------------------------------------===// 4350// ARMv8-M Security Extensions instructions 4351// 4352 4353let hasSideEffects = 1 in 4354def t2SG : T2I<(outs), (ins), NoItinerary, "sg", "", []>, 4355 Requires<[Has8MSecExt]> { 4356 let Inst = 0xe97fe97f; 4357} 4358 4359class T2TT<bits<2> at, string asm, list<dag> pattern> 4360 : T2I<(outs rGPR:$Rt), (ins GPRnopc:$Rn), NoItinerary, asm, "\t$Rt, $Rn", 4361 pattern> { 4362 bits<4> Rn; 4363 bits<4> Rt; 4364 4365 let Inst{31-20} = 0b111010000100; 4366 let Inst{19-16} = Rn; 4367 let Inst{15-12} = 0b1111; 4368 let Inst{11-8} = Rt; 4369 let Inst{7-6} = at; 4370 let Inst{5-0} = 0b000000; 4371 4372 let Unpredictable{5-0} = 0b111111; 4373} 4374 4375def t2TT : T2TT<0b00, "tt", []>, Requires<[IsThumb,Has8MSecExt]>; 4376def t2TTT : T2TT<0b01, "ttt", []>, Requires<[IsThumb,Has8MSecExt]>; 4377def t2TTA : T2TT<0b10, "tta", []>, Requires<[IsThumb,Has8MSecExt]>; 4378def t2TTAT : T2TT<0b11, "ttat", []>, Requires<[IsThumb,Has8MSecExt]>; 4379 4380//===----------------------------------------------------------------------===// 4381// Non-Instruction Patterns 4382// 4383 4384// SXT/UXT with no rotate 4385let AddedComplexity = 16 in { 4386def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>, 4387 Requires<[IsThumb2]>; 4388def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>, 4389 Requires<[IsThumb2]>; 4390def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>, 4391 Requires<[HasDSP, IsThumb2]>; 4392def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)), 4393 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>, 4394 Requires<[HasDSP, IsThumb2]>; 4395def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)), 4396 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>, 4397 Requires<[HasDSP, IsThumb2]>; 4398} 4399 4400def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>, 4401 Requires<[IsThumb2]>; 4402def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>, 4403 Requires<[IsThumb2]>; 4404def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)), 4405 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>, 4406 Requires<[HasDSP, IsThumb2]>; 4407def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)), 4408 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>, 4409 Requires<[HasDSP, IsThumb2]>; 4410 4411// Atomic load/store patterns 4412def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr), 4413 (t2LDRBi12 t2addrmode_imm12:$addr)>; 4414def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr), 4415 (t2LDRBi8 t2addrmode_negimm8:$addr)>; 4416def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr), 4417 (t2LDRBs t2addrmode_so_reg:$addr)>; 4418def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr), 4419 (t2LDRHi12 t2addrmode_imm12:$addr)>; 4420def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr), 4421 (t2LDRHi8 t2addrmode_negimm8:$addr)>; 4422def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr), 4423 (t2LDRHs t2addrmode_so_reg:$addr)>; 4424def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr), 4425 (t2LDRi12 t2addrmode_imm12:$addr)>; 4426def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr), 4427 (t2LDRi8 t2addrmode_negimm8:$addr)>; 4428def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr), 4429 (t2LDRs t2addrmode_so_reg:$addr)>; 4430def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val), 4431 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>; 4432def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val), 4433 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>; 4434def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val), 4435 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>; 4436def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val), 4437 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>; 4438def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val), 4439 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>; 4440def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val), 4441 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>; 4442def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val), 4443 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>; 4444def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val), 4445 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>; 4446def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val), 4447 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>; 4448 4449let AddedComplexity = 8, Predicates = [IsThumb, HasAcquireRelease, HasV7Clrex] in { 4450 def : Pat<(atomic_load_acquire_8 addr_offset_none:$addr), (t2LDAB addr_offset_none:$addr)>; 4451 def : Pat<(atomic_load_acquire_16 addr_offset_none:$addr), (t2LDAH addr_offset_none:$addr)>; 4452 def : Pat<(atomic_load_acquire_32 addr_offset_none:$addr), (t2LDA addr_offset_none:$addr)>; 4453 def : Pat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (t2STLB GPR:$val, addr_offset_none:$addr)>; 4454 def : Pat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (t2STLH GPR:$val, addr_offset_none:$addr)>; 4455 def : Pat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (t2STL GPR:$val, addr_offset_none:$addr)>; 4456} 4457 4458 4459//===----------------------------------------------------------------------===// 4460// Assembler aliases 4461// 4462 4463// Aliases for ADC without the ".w" optional width specifier. 4464def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm", 4465 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4466def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm", 4467 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, 4468 pred:$p, cc_out:$s)>; 4469 4470// Aliases for SBC without the ".w" optional width specifier. 4471def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm", 4472 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4473def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm", 4474 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, 4475 pred:$p, cc_out:$s)>; 4476 4477// Aliases for ADD without the ".w" optional width specifier. 4478def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm", 4479 (t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, 4480 cc_out:$s)>; 4481def : t2InstAlias<"add${p} $Rd, $Rn, $imm", 4482 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>; 4483def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm", 4484 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4485def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm", 4486 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm, 4487 pred:$p, cc_out:$s)>; 4488// ... and with the destination and source register combined. 4489def : t2InstAlias<"add${s}${p} $Rdn, $imm", 4490 (t2ADDri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4491def : t2InstAlias<"add${p} $Rdn, $imm", 4492 (t2ADDri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>; 4493def : t2InstAlias<"add${s}${p} $Rdn, $Rm", 4494 (t2ADDrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4495def : t2InstAlias<"add${s}${p} $Rdn, $ShiftedRm", 4496 (t2ADDrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm, 4497 pred:$p, cc_out:$s)>; 4498 4499// add w/ negative immediates is just a sub. 4500def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm", 4501 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p, 4502 cc_out:$s)>; 4503def : t2InstSubst<"add${p} $Rd, $Rn, $imm", 4504 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>; 4505def : t2InstSubst<"add${s}${p} $Rdn, $imm", 4506 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p, 4507 cc_out:$s)>; 4508def : t2InstSubst<"add${p} $Rdn, $imm", 4509 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>; 4510 4511def : t2InstSubst<"add${s}${p}.w $Rd, $Rn, $imm", 4512 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p, 4513 cc_out:$s)>; 4514def : t2InstSubst<"addw${p} $Rd, $Rn, $imm", 4515 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>; 4516def : t2InstSubst<"add${s}${p}.w $Rdn, $imm", 4517 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm_neg:$imm, pred:$p, 4518 cc_out:$s)>; 4519def : t2InstSubst<"addw${p} $Rdn, $imm", 4520 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095_neg:$imm, pred:$p)>; 4521 4522 4523// Aliases for SUB without the ".w" optional width specifier. 4524def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm", 4525 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4526def : t2InstAlias<"sub${p} $Rd, $Rn, $imm", 4527 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>; 4528def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm", 4529 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4530def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm", 4531 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm, 4532 pred:$p, cc_out:$s)>; 4533// ... and with the destination and source register combined. 4534def : t2InstAlias<"sub${s}${p} $Rdn, $imm", 4535 (t2SUBri GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4536def : t2InstAlias<"sub${p} $Rdn, $imm", 4537 (t2SUBri12 GPRnopc:$Rdn, GPRnopc:$Rdn, imm0_4095:$imm, pred:$p)>; 4538def : t2InstAlias<"sub${s}${p}.w $Rdn, $Rm", 4539 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4540def : t2InstAlias<"sub${s}${p} $Rdn, $Rm", 4541 (t2SUBrr GPRnopc:$Rdn, GPRnopc:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4542def : t2InstAlias<"sub${s}${p} $Rdn, $ShiftedRm", 4543 (t2SUBrs GPRnopc:$Rdn, GPRnopc:$Rdn, t2_so_reg:$ShiftedRm, 4544 pred:$p, cc_out:$s)>; 4545 4546// Alias for compares without the ".w" optional width specifier. 4547def : t2InstAlias<"cmn${p} $Rn, $Rm", 4548 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>; 4549def : t2InstAlias<"teq${p} $Rn, $Rm", 4550 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>; 4551def : t2InstAlias<"tst${p} $Rn, $Rm", 4552 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>; 4553 4554// Memory barriers 4555def : InstAlias<"dmb${p}", (t2DMB 0xf, pred:$p), 0>, Requires<[HasDB]>; 4556def : InstAlias<"dsb${p}", (t2DSB 0xf, pred:$p), 0>, Requires<[HasDB]>; 4557def : InstAlias<"isb${p}", (t2ISB 0xf, pred:$p), 0>, Requires<[HasDB]>; 4558 4559// Non-predicable aliases of a predicable DSB: the predicate is (14, 0) where 4560// 14 = AL (always execute) and 0 = "instruction doesn't read the CPSR". 4561def : InstAlias<"ssbb", (t2DSB 0x0, 14, 0), 1>, Requires<[HasDB, IsThumb2]>; 4562def : InstAlias<"pssbb", (t2DSB 0x4, 14, 0), 1>, Requires<[HasDB, IsThumb2]>; 4563 4564// Armv8-R 'Data Full Barrier' 4565def : InstAlias<"dfb${p}", (t2DSB 0xc, pred:$p), 1>, Requires<[HasDFB]>; 4566 4567// Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional 4568// width specifier. 4569def : t2InstAlias<"ldr${p} $Rt, $addr", 4570 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4571def : t2InstAlias<"ldrb${p} $Rt, $addr", 4572 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4573def : t2InstAlias<"ldrh${p} $Rt, $addr", 4574 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4575def : t2InstAlias<"ldrsb${p} $Rt, $addr", 4576 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4577def : t2InstAlias<"ldrsh${p} $Rt, $addr", 4578 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4579 4580def : t2InstAlias<"ldr${p} $Rt, $addr", 4581 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4582def : t2InstAlias<"ldrb${p} $Rt, $addr", 4583 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4584def : t2InstAlias<"ldrh${p} $Rt, $addr", 4585 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4586def : t2InstAlias<"ldrsb${p} $Rt, $addr", 4587 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4588def : t2InstAlias<"ldrsh${p} $Rt, $addr", 4589 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4590 4591def : t2InstAlias<"ldr${p} $Rt, $addr", 4592 (t2LDRpci GPR:$Rt, t2ldrlabel:$addr, pred:$p)>; 4593def : t2InstAlias<"ldrb${p} $Rt, $addr", 4594 (t2LDRBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>; 4595def : t2InstAlias<"ldrh${p} $Rt, $addr", 4596 (t2LDRHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>; 4597def : t2InstAlias<"ldrsb${p} $Rt, $addr", 4598 (t2LDRSBpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>; 4599def : t2InstAlias<"ldrsh${p} $Rt, $addr", 4600 (t2LDRSHpci rGPR:$Rt, t2ldrlabel:$addr, pred:$p)>; 4601 4602// Alias for MVN with(out) the ".w" optional width specifier. 4603def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm", 4604 (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4605def : t2InstAlias<"mvn${s}${p} $Rd, $Rm", 4606 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>; 4607def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm", 4608 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>; 4609 4610// PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT with the 4611// input operands swapped when the shift amount is zero (i.e., unspecified). 4612def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", 4613 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>, 4614 Requires<[HasDSP, IsThumb2]>; 4615def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", 4616 (t2PKHBT rGPR:$Rd, rGPR:$Rm, rGPR:$Rn, 0, pred:$p), 0>, 4617 Requires<[HasDSP, IsThumb2]>; 4618 4619// PUSH/POP aliases for STM/LDM 4620def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>; 4621def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>; 4622def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>; 4623def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>; 4624 4625// STMIA/STMIA_UPD aliases w/o the optional .w suffix 4626def : t2InstAlias<"stm${p} $Rn, $regs", 4627 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>; 4628def : t2InstAlias<"stm${p} $Rn!, $regs", 4629 (t2STMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>; 4630 4631// LDMIA/LDMIA_UPD aliases w/o the optional .w suffix 4632def : t2InstAlias<"ldm${p} $Rn, $regs", 4633 (t2LDMIA GPR:$Rn, pred:$p, reglist:$regs)>; 4634def : t2InstAlias<"ldm${p} $Rn!, $regs", 4635 (t2LDMIA_UPD GPR:$Rn, pred:$p, reglist:$regs)>; 4636 4637// STMDB/STMDB_UPD aliases w/ the optional .w suffix 4638def : t2InstAlias<"stmdb${p}.w $Rn, $regs", 4639 (t2STMDB GPR:$Rn, pred:$p, reglist:$regs)>; 4640def : t2InstAlias<"stmdb${p}.w $Rn!, $regs", 4641 (t2STMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>; 4642 4643// LDMDB/LDMDB_UPD aliases w/ the optional .w suffix 4644def : t2InstAlias<"ldmdb${p}.w $Rn, $regs", 4645 (t2LDMDB GPR:$Rn, pred:$p, reglist:$regs)>; 4646def : t2InstAlias<"ldmdb${p}.w $Rn!, $regs", 4647 (t2LDMDB_UPD GPR:$Rn, pred:$p, reglist:$regs)>; 4648 4649// Alias for REV/REV16/REVSH without the ".w" optional width specifier. 4650def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>; 4651def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>; 4652def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>; 4653 4654 4655// Alias for RSB without the ".w" optional width specifier, and with optional 4656// implied destination register. 4657def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm", 4658 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4659def : t2InstAlias<"rsb${s}${p} $Rdn, $imm", 4660 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 4661def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm", 4662 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>; 4663def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm", 4664 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p, 4665 cc_out:$s)>; 4666 4667// SSAT/USAT optional shift operand. 4668def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn", 4669 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>; 4670def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn", 4671 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>; 4672 4673// STM w/o the .w suffix. 4674def : t2InstAlias<"stm${p} $Rn, $regs", 4675 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>; 4676 4677// Alias for STR, STRB, and STRH without the ".w" optional 4678// width specifier. 4679def : t2InstAlias<"str${p} $Rt, $addr", 4680 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4681def : t2InstAlias<"strb${p} $Rt, $addr", 4682 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4683def : t2InstAlias<"strh${p} $Rt, $addr", 4684 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 4685 4686def : t2InstAlias<"str${p} $Rt, $addr", 4687 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4688def : t2InstAlias<"strb${p} $Rt, $addr", 4689 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4690def : t2InstAlias<"strh${p} $Rt, $addr", 4691 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 4692 4693// Extend instruction optional rotate operand. 4694def : InstAlias<"sxtab${p} $Rd, $Rn, $Rm", 4695 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>, 4696 Requires<[HasDSP, IsThumb2]>; 4697def : InstAlias<"sxtah${p} $Rd, $Rn, $Rm", 4698 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>, 4699 Requires<[HasDSP, IsThumb2]>; 4700def : InstAlias<"sxtab16${p} $Rd, $Rn, $Rm", 4701 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>, 4702 Requires<[HasDSP, IsThumb2]>; 4703def : InstAlias<"sxtb16${p} $Rd, $Rm", 4704 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>, 4705 Requires<[HasDSP, IsThumb2]>; 4706 4707def : t2InstAlias<"sxtb${p} $Rd, $Rm", 4708 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4709def : t2InstAlias<"sxth${p} $Rd, $Rm", 4710 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4711def : t2InstAlias<"sxtb${p}.w $Rd, $Rm", 4712 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4713def : t2InstAlias<"sxth${p}.w $Rd, $Rm", 4714 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4715 4716def : InstAlias<"uxtab${p} $Rd, $Rn, $Rm", 4717 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>, 4718 Requires<[HasDSP, IsThumb2]>; 4719def : InstAlias<"uxtah${p} $Rd, $Rn, $Rm", 4720 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>, 4721 Requires<[HasDSP, IsThumb2]>; 4722def : InstAlias<"uxtab16${p} $Rd, $Rn, $Rm", 4723 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>, 4724 Requires<[HasDSP, IsThumb2]>; 4725def : InstAlias<"uxtb16${p} $Rd, $Rm", 4726 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>, 4727 Requires<[HasDSP, IsThumb2]>; 4728 4729def : t2InstAlias<"uxtb${p} $Rd, $Rm", 4730 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4731def : t2InstAlias<"uxth${p} $Rd, $Rm", 4732 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4733def : t2InstAlias<"uxtb${p}.w $Rd, $Rm", 4734 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4735def : t2InstAlias<"uxth${p}.w $Rd, $Rm", 4736 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4737 4738// Extend instruction w/o the ".w" optional width specifier. 4739def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot", 4740 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 4741def : InstAlias<"uxtb16${p} $Rd, $Rm$rot", 4742 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>, 4743 Requires<[HasDSP, IsThumb2]>; 4744def : t2InstAlias<"uxth${p} $Rd, $Rm$rot", 4745 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 4746 4747def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot", 4748 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 4749def : InstAlias<"sxtb16${p} $Rd, $Rm$rot", 4750 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>, 4751 Requires<[HasDSP, IsThumb2]>; 4752def : t2InstAlias<"sxth${p} $Rd, $Rm$rot", 4753 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 4754 4755 4756// "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like 4757// for isel. 4758def : t2InstSubst<"mov${p} $Rd, $imm", 4759 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>; 4760def : t2InstSubst<"mvn${s}${p} $Rd, $imm", 4761 (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>; 4762// Same for AND <--> BIC 4763def : t2InstSubst<"bic${s}${p} $Rd, $Rn, $imm", 4764 (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm, 4765 pred:$p, cc_out:$s)>; 4766def : t2InstSubst<"bic${s}${p} $Rdn, $imm", 4767 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm, 4768 pred:$p, cc_out:$s)>; 4769def : t2InstSubst<"bic${s}${p}.w $Rd, $Rn, $imm", 4770 (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm, 4771 pred:$p, cc_out:$s)>; 4772def : t2InstSubst<"bic${s}${p}.w $Rdn, $imm", 4773 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm, 4774 pred:$p, cc_out:$s)>; 4775def : t2InstSubst<"and${s}${p} $Rd, $Rn, $imm", 4776 (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm, 4777 pred:$p, cc_out:$s)>; 4778def : t2InstSubst<"and${s}${p} $Rdn, $imm", 4779 (t2BICri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm, 4780 pred:$p, cc_out:$s)>; 4781def : t2InstSubst<"and${s}${p}.w $Rd, $Rn, $imm", 4782 (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm, 4783 pred:$p, cc_out:$s)>; 4784def : t2InstSubst<"and${s}${p}.w $Rdn, $imm", 4785 (t2BICri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm, 4786 pred:$p, cc_out:$s)>; 4787// And ORR <--> ORN 4788def : t2InstSubst<"orn${s}${p} $Rd, $Rn, $imm", 4789 (t2ORRri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm, 4790 pred:$p, cc_out:$s)>; 4791def : t2InstSubst<"orn${s}${p} $Rdn, $imm", 4792 (t2ORRri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm, 4793 pred:$p, cc_out:$s)>; 4794def : t2InstSubst<"orr${s}${p} $Rd, $Rn, $imm", 4795 (t2ORNri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm, 4796 pred:$p, cc_out:$s)>; 4797def : t2InstSubst<"orr${s}${p} $Rdn, $imm", 4798 (t2ORNri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm, 4799 pred:$p, cc_out:$s)>; 4800// Likewise, "add Rd, t2_so_imm_neg" -> sub 4801def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm", 4802 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, 4803 pred:$p, cc_out:$s)>; 4804def : t2InstSubst<"add${s}${p} $Rd, $imm", 4805 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rd, t2_so_imm_neg:$imm, 4806 pred:$p, cc_out:$s)>; 4807// Same for CMP <--> CMN via t2_so_imm_neg 4808def : t2InstSubst<"cmp${p} $Rd, $imm", 4809 (t2CMNri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>; 4810def : t2InstSubst<"cmn${p} $Rd, $imm", 4811 (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>; 4812 4813 4814// Wide 'mul' encoding can be specified with only two operands. 4815def : t2InstAlias<"mul${p} $Rn, $Rm", 4816 (t2MUL rGPR:$Rn, rGPR:$Rm, rGPR:$Rn, pred:$p)>; 4817 4818// "neg" is and alias for "rsb rd, rn, #0" 4819def : t2InstAlias<"neg${s}${p} $Rd, $Rm", 4820 (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s)>; 4821 4822// MOV so_reg assembler pseudos. InstAlias isn't expressive enough for 4823// these, unfortunately. 4824// FIXME: LSL #0 in the shift should allow SP to be used as either the 4825// source or destination (but not both). 4826def t2MOVsi: t2AsmPseudo<"mov${p} $Rd, $shift", 4827 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>; 4828def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift", 4829 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>; 4830 4831def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift", 4832 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>; 4833def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift", 4834 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>; 4835 4836// Aliases for the above with the .w qualifier 4837def : t2InstAlias<"mov${p}.w $Rd, $shift", 4838 (t2MOVsi rGPR:$Rd, t2_so_reg:$shift, pred:$p)>; 4839def : t2InstAlias<"movs${p}.w $Rd, $shift", 4840 (t2MOVSsi rGPR:$Rd, t2_so_reg:$shift, pred:$p)>; 4841def : t2InstAlias<"mov${p}.w $Rd, $shift", 4842 (t2MOVsr rGPR:$Rd, so_reg_reg:$shift, pred:$p)>; 4843def : t2InstAlias<"movs${p}.w $Rd, $shift", 4844 (t2MOVSsr rGPR:$Rd, so_reg_reg:$shift, pred:$p)>; 4845 4846// ADR w/o the .w suffix 4847def : t2InstAlias<"adr${p} $Rd, $addr", 4848 (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>; 4849 4850// LDR(literal) w/ alternate [pc, #imm] syntax. 4851def t2LDRpcrel : t2AsmPseudo<"ldr${p} $Rt, $addr", 4852 (ins GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4853def t2LDRBpcrel : t2AsmPseudo<"ldrb${p} $Rt, $addr", 4854 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4855def t2LDRHpcrel : t2AsmPseudo<"ldrh${p} $Rt, $addr", 4856 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4857def t2LDRSBpcrel : t2AsmPseudo<"ldrsb${p} $Rt, $addr", 4858 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4859def t2LDRSHpcrel : t2AsmPseudo<"ldrsh${p} $Rt, $addr", 4860 (ins GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4861 // Version w/ the .w suffix. 4862def : t2InstAlias<"ldr${p}.w $Rt, $addr", 4863 (t2LDRpcrel GPR:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p), 0>; 4864def : t2InstAlias<"ldrb${p}.w $Rt, $addr", 4865 (t2LDRBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4866def : t2InstAlias<"ldrh${p}.w $Rt, $addr", 4867 (t2LDRHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4868def : t2InstAlias<"ldrsb${p}.w $Rt, $addr", 4869 (t2LDRSBpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4870def : t2InstAlias<"ldrsh${p}.w $Rt, $addr", 4871 (t2LDRSHpcrel GPRnopc:$Rt, t2ldr_pcrel_imm12:$addr, pred:$p)>; 4872 4873def : t2InstAlias<"add${p} $Rd, pc, $imm", 4874 (t2ADR rGPR:$Rd, imm0_4095:$imm, pred:$p)>; 4875 4876// Pseudo instruction ldr Rt, =immediate 4877def t2LDRConstPool 4878 : t2AsmPseudo<"ldr${p} $Rt, $immediate", 4879 (ins GPR:$Rt, const_pool_asm_imm:$immediate, pred:$p)>; 4880// Version w/ the .w suffix. 4881def : t2InstAlias<"ldr${p}.w $Rt, $immediate", 4882 (t2LDRConstPool GPRnopc:$Rt, 4883 const_pool_asm_imm:$immediate, pred:$p)>; 4884 4885// PLD/PLDW/PLI with alternate literal form. 4886def : t2InstAlias<"pld${p} $addr", 4887 (t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>; 4888def : InstAlias<"pli${p} $addr", 4889 (t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p), 0>, 4890 Requires<[IsThumb2,HasV7]>; 4891