1//===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This is the top level entry point for the Hexagon target.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Target-independent interfaces which we are implementing
16//===----------------------------------------------------------------------===//
17
18include "llvm/Target/Target.td"
19
20//===----------------------------------------------------------------------===//
21// Hexagon Subtarget features.
22//===----------------------------------------------------------------------===//
23
24// Hexagon Architectures
25include "HexagonDepArch.td"
26
27// Hexagon ISA Extensions
28def ExtensionZReg: SubtargetFeature<"zreg", "UseZRegOps", "true",
29      "Hexagon ZReg extension instructions">;
30
31def ExtensionHVX: SubtargetFeature<"hvx", "HexagonHVXVersion",
32      "Hexagon::ArchEnum::V60", "Hexagon HVX instructions">;
33def ExtensionHVXV60: SubtargetFeature<"hvxv60", "HexagonHVXVersion",
34      "Hexagon::ArchEnum::V60", "Hexagon HVX instructions",
35      [ExtensionHVX]>;
36def ExtensionHVXV62: SubtargetFeature<"hvxv62", "HexagonHVXVersion",
37      "Hexagon::ArchEnum::V62", "Hexagon HVX instructions",
38      [ExtensionHVX, ExtensionHVXV60]>;
39def ExtensionHVXV65: SubtargetFeature<"hvxv65", "HexagonHVXVersion",
40      "Hexagon::ArchEnum::V65", "Hexagon HVX instructions",
41      [ExtensionHVX, ExtensionHVXV60, ExtensionHVXV62]>;
42def ExtensionHVXV66: SubtargetFeature<"hvxv66", "HexagonHVXVersion",
43      "Hexagon::ArchEnum::V66", "Hexagon HVX instructions",
44      [ExtensionHVX, ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65,
45       ExtensionZReg]>;
46
47def ExtensionHVX64B: SubtargetFeature<"hvx-length64b", "UseHVX64BOps",
48      "true", "Hexagon HVX 64B instructions", [ExtensionHVX]>;
49def ExtensionHVX128B: SubtargetFeature<"hvx-length128b", "UseHVX128BOps",
50      "true", "Hexagon HVX 128B instructions", [ExtensionHVX]>;
51
52def FeaturePackets: SubtargetFeature<"packets", "UsePackets", "true",
53      "Support for instruction packets">;
54def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true",
55      "Use constant-extended calls">;
56def FeatureMemNoShuf: SubtargetFeature<"mem_noshuf", "HasMemNoShuf", "false",
57      "Supports mem_noshuf feature">;
58def FeatureMemops: SubtargetFeature<"memops", "UseMemops", "true",
59      "Use memop instructions">;
60def FeatureNVJ: SubtargetFeature<"nvj", "UseNewValueJumps", "true",
61      "Support for new-value jumps", [FeaturePackets]>;
62def FeatureNVS: SubtargetFeature<"nvs", "UseNewValueStores", "true",
63      "Support for new-value stores", [FeaturePackets]>;
64def FeatureSmallData: SubtargetFeature<"small-data", "UseSmallData", "true",
65      "Allow GP-relative addressing of global variables">;
66def FeatureDuplex: SubtargetFeature<"duplex", "EnableDuplex", "true",
67      "Enable generation of duplex instruction">;
68def FeatureReservedR19: SubtargetFeature<"reserved-r19", "ReservedR19",
69      "true", "Reserve register R19">;
70def FeatureNoreturnStackElim: SubtargetFeature<"noreturn-stack-elim",
71      "NoreturnStackElim", "true",
72      "Eliminate stack allocation in a noreturn function when possible">;
73
74//===----------------------------------------------------------------------===//
75// Hexagon Instruction Predicate Definitions.
76//===----------------------------------------------------------------------===//
77
78def UseMEMOPS          : Predicate<"HST->useMemops()">;
79def UseHVX64B          : Predicate<"HST->useHVX64BOps()">,
80                         AssemblerPredicate<"ExtensionHVX64B">;
81def UseHVX128B         : Predicate<"HST->useHVX128BOps()">,
82                         AssemblerPredicate<"ExtensionHVX128B">;
83def UseHVX             : Predicate<"HST->useHVXOps()">,
84                         AssemblerPredicate<"ExtensionHVXV60">;
85def UseHVXV60          : Predicate<"HST->useHVXOps()">,
86                         AssemblerPredicate<"ExtensionHVXV60">;
87def UseHVXV62          : Predicate<"HST->useHVXOps()">,
88                         AssemblerPredicate<"ExtensionHVXV62">;
89def UseHVXV65          : Predicate<"HST->useHVXOps()">,
90                         AssemblerPredicate<"ExtensionHVXV65">;
91def UseHVXV66          : Predicate<"HST->useHVXOps()">,
92                         AssemblerPredicate<"ExtensionHVXV66">;
93def UseZReg            : Predicate<"HST->useZRegOps()">,
94                         AssemblerPredicate<"ExtensionZReg">;
95
96def Hvx64:  HwMode<"+hvx-length64b">;
97def Hvx128: HwMode<"+hvx-length128b">;
98
99//===----------------------------------------------------------------------===//
100// Classes used for relation maps.
101//===----------------------------------------------------------------------===//
102
103class ImmRegShl;
104// ImmRegRel - Filter class used to relate instructions having reg-reg form
105// with their reg-imm counterparts.
106class ImmRegRel;
107// PredRel - Filter class used to relate non-predicated instructions with their
108// predicated forms.
109class PredRel;
110// PredNewRel - Filter class used to relate predicated instructions with their
111// predicate-new forms.
112class PredNewRel: PredRel;
113// NewValueRel - Filter class used to relate regular store instructions with
114// their new-value store form.
115class NewValueRel: PredNewRel;
116// NewValueRel - Filter class used to relate load/store instructions having
117// different addressing modes with each other.
118class AddrModeRel: NewValueRel;
119class PostInc_BaseImm;
120class IntrinsicsRel;
121
122//===----------------------------------------------------------------------===//
123// Generate mapping table to relate non-predicate instructions with their
124// predicated formats - true and false.
125//
126
127def getPredOpcode : InstrMapping {
128  let FilterClass = "PredRel";
129  // Instructions with the same BaseOpcode and isNVStore values form a row.
130  let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isBrTaken", "isNT"];
131  // Instructions with the same predicate sense form a column.
132  let ColFields = ["PredSense"];
133  // The key column is the unpredicated instructions.
134  let KeyCol = [""];
135  // Value columns are PredSense=true and PredSense=false
136  let ValueCols = [["true"], ["false"]];
137}
138
139//===----------------------------------------------------------------------===//
140// Generate mapping table to relate predicate-true instructions with their
141// predicate-false forms
142//
143def getFalsePredOpcode : InstrMapping {
144  let FilterClass = "PredRel";
145  let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
146  let ColFields = ["PredSense"];
147  let KeyCol = ["true"];
148  let ValueCols = [["false"]];
149}
150
151//===----------------------------------------------------------------------===//
152// Generate mapping table to relate predicate-false instructions with their
153// predicate-true forms
154//
155def getTruePredOpcode : InstrMapping {
156  let FilterClass = "PredRel";
157  let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
158  let ColFields = ["PredSense"];
159  let KeyCol = ["false"];
160  let ValueCols = [["true"]];
161}
162
163//===----------------------------------------------------------------------===//
164// Generate mapping table to relate predicated instructions with their .new
165// format.
166//
167def getPredNewOpcode : InstrMapping {
168  let FilterClass = "PredNewRel";
169  let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
170  let ColFields = ["PNewValue"];
171  let KeyCol = [""];
172  let ValueCols = [["new"]];
173}
174
175//===----------------------------------------------------------------------===//
176// Generate mapping table to relate .new predicated instructions with their old
177// format.
178//
179def getPredOldOpcode : InstrMapping {
180  let FilterClass = "PredNewRel";
181  let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
182  let ColFields = ["PNewValue"];
183  let KeyCol = ["new"];
184  let ValueCols = [[""]];
185}
186
187//===----------------------------------------------------------------------===//
188// Generate mapping table to relate store instructions with their new-value
189// format.
190//
191def getNewValueOpcode : InstrMapping {
192  let FilterClass = "NewValueRel";
193  let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
194  let ColFields = ["NValueST"];
195  let KeyCol = ["false"];
196  let ValueCols = [["true"]];
197}
198
199//===----------------------------------------------------------------------===//
200// Generate mapping table to relate new-value store instructions with their old
201// format.
202//
203def getNonNVStore : InstrMapping {
204  let FilterClass = "NewValueRel";
205  let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
206  let ColFields = ["NValueST"];
207  let KeyCol = ["true"];
208  let ValueCols = [["false"]];
209}
210
211def changeAddrMode_abs_io: InstrMapping {
212  let FilterClass = "AddrModeRel";
213  let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore",
214                   "isFloat"];
215  let ColFields = ["addrMode"];
216  let KeyCol = ["Absolute"];
217  let ValueCols = [["BaseImmOffset"]];
218}
219
220def changeAddrMode_io_abs: InstrMapping {
221  let FilterClass = "AddrModeRel";
222  let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore",
223                   "isFloat"];
224  let ColFields = ["addrMode"];
225  let KeyCol = ["BaseImmOffset"];
226  let ValueCols = [["Absolute"]];
227}
228
229def changeAddrMode_io_rr: InstrMapping {
230  let FilterClass = "AddrModeRel";
231  let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
232  let ColFields = ["addrMode"];
233  let KeyCol = ["BaseImmOffset"];
234  let ValueCols = [["BaseRegOffset"]];
235}
236
237def changeAddrMode_rr_io: InstrMapping {
238  let FilterClass = "AddrModeRel";
239  let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
240  let ColFields = ["addrMode"];
241  let KeyCol = ["BaseRegOffset"];
242  let ValueCols = [["BaseImmOffset"]];
243}
244
245def changeAddrMode_pi_io: InstrMapping {
246  let FilterClass = "PostInc_BaseImm";
247  let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
248  let ColFields = ["addrMode"];
249  let KeyCol = ["PostInc"];
250  let ValueCols = [["BaseImmOffset"]];
251}
252
253def changeAddrMode_io_pi: InstrMapping {
254  let FilterClass = "PostInc_BaseImm";
255  let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
256  let ColFields = ["addrMode"];
257  let KeyCol = ["BaseImmOffset"];
258  let ValueCols = [["PostInc"]];
259}
260
261def changeAddrMode_rr_ur: InstrMapping {
262  let FilterClass = "ImmRegShl";
263  let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
264  let ColFields = ["addrMode"];
265  let KeyCol = ["BaseRegOffset"];
266  let ValueCols = [["BaseLongOffset"]];
267}
268
269def changeAddrMode_ur_rr : InstrMapping {
270  let FilterClass = "ImmRegShl";
271  let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
272  let ColFields = ["addrMode"];
273  let KeyCol = ["BaseLongOffset"];
274  let ValueCols = [["BaseRegOffset"]];
275}
276
277def getRegForm : InstrMapping {
278  let FilterClass = "ImmRegRel";
279  let RowFields = ["CextOpcode", "PredSense", "PNewValue"];
280  let ColFields = ["InputType"];
281  let KeyCol = ["imm"];
282  let ValueCols = [["reg"]];
283}
284
285def notTakenBranchPrediction : InstrMapping {
286  let FilterClass = "PredRel";
287  let RowFields = ["BaseOpcode", "PNewValue",  "PredSense", "isBranch", "isPredicated"];
288  let ColFields = ["isBrTaken"];
289  let KeyCol = ["true"];
290  let ValueCols = [["false"]];
291}
292
293def takenBranchPrediction : InstrMapping {
294  let FilterClass = "PredRel";
295  let RowFields = ["BaseOpcode", "PNewValue",  "PredSense", "isBranch", "isPredicated"];
296  let ColFields = ["isBrTaken"];
297  let KeyCol = ["false"];
298  let ValueCols = [["true"]];
299}
300
301def getRealHWInstr : InstrMapping {
302  let FilterClass = "IntrinsicsRel";
303  let RowFields = ["BaseOpcode"];
304  let ColFields = ["InstrType"];
305  let KeyCol = ["Pseudo"];
306  let ValueCols = [["Pseudo"], ["Real"]];
307}
308//===----------------------------------------------------------------------===//
309// Register File, Instruction Descriptions
310//===----------------------------------------------------------------------===//
311include "HexagonSchedule.td"
312include "HexagonRegisterInfo.td"
313include "HexagonOperands.td"
314include "HexagonDepOperands.td"
315include "HexagonDepITypes.td"
316include "HexagonInstrFormats.td"
317include "HexagonDepInstrFormats.td"
318include "HexagonDepInstrInfo.td"
319include "HexagonCallingConv.td"
320include "HexagonPseudo.td"
321include "HexagonPatterns.td"
322include "HexagonPatternsHVX.td"
323include "HexagonPatternsV65.td"
324include "HexagonDepMappings.td"
325include "HexagonIntrinsics.td"
326
327def HexagonInstrInfo : InstrInfo;
328
329//===----------------------------------------------------------------------===//
330// Hexagon processors supported.
331//===----------------------------------------------------------------------===//
332
333class Proc<string Name, SchedMachineModel Model,
334           list<SubtargetFeature> Features>
335 : ProcessorModel<Name, Model, Features>;
336
337def : Proc<"generic", HexagonModelV60,
338           [ArchV5, ArchV55, ArchV60,
339            FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
340            FeaturePackets, FeatureSmallData]>;
341def : Proc<"hexagonv5",  HexagonModelV5,
342           [ArchV5,
343            FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
344            FeaturePackets, FeatureSmallData]>;
345def : Proc<"hexagonv55", HexagonModelV55,
346           [ArchV5, ArchV55,
347            FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
348            FeaturePackets, FeatureSmallData]>;
349def : Proc<"hexagonv60", HexagonModelV60,
350           [ArchV5, ArchV55, ArchV60,
351            FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
352            FeaturePackets, FeatureSmallData]>;
353def : Proc<"hexagonv62", HexagonModelV62,
354           [ArchV5, ArchV55, ArchV60, ArchV62,
355            FeatureDuplex, FeatureMemops, FeatureNVJ, FeatureNVS,
356            FeaturePackets, FeatureSmallData]>;
357def : Proc<"hexagonv65", HexagonModelV65,
358           [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65,
359            FeatureDuplex, FeatureMemNoShuf, FeatureMemops, FeatureNVJ,
360            FeatureNVS, FeaturePackets, FeatureSmallData]>;
361def : Proc<"hexagonv66", HexagonModelV66,
362           [ArchV5, ArchV55, ArchV60, ArchV62, ArchV65, ArchV66,
363            FeatureDuplex, FeatureMemNoShuf, FeatureMemops, FeatureNVJ,
364            FeatureNVS, FeaturePackets, FeatureSmallData]>;
365
366//===----------------------------------------------------------------------===//
367// Declare the target which we are implementing
368//===----------------------------------------------------------------------===//
369
370def HexagonAsmParser : AsmParser {
371  let ShouldEmitMatchRegisterAltName = 1;
372  bit HasMnemonicFirst = 0;
373}
374
375def HexagonAsmParserVariant : AsmParserVariant {
376  int Variant = 0;
377  string TokenizingCharacters = "#()=:.<>!+*-|^&";
378  string BreakCharacters = "";
379}
380
381def HexagonAsmWriter : AsmWriter {
382  string AsmWriterClassName  = "InstPrinter";
383  bit isMCAsmWriter = 1;
384}
385
386def Hexagon : Target {
387  let InstructionSet = HexagonInstrInfo;
388  let AssemblyParsers = [HexagonAsmParser];
389  let AssemblyParserVariants = [HexagonAsmParserVariant];
390  let AssemblyWriters = [HexagonAsmWriter];
391  let AllowRegisterRenaming = 1;
392}
393