1//===-- HexagonRegisterInfo.td - Hexagon Register defs -----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Declarations that describe the Hexagon register file. 12//===----------------------------------------------------------------------===// 13 14let Namespace = "Hexagon" in { 15 16 class HexagonReg<bits<5> num, string n, list<string> alt = [], 17 list<Register> alias = []> : Register<n, alt> { 18 let Aliases = alias; 19 let HWEncoding{4-0} = num; 20 } 21 22 class HexagonDoubleReg<bits<5> num, string n, list<Register> subregs, 23 list<string> alt = []> : 24 RegisterWithSubRegs<n, subregs> { 25 let AltNames = alt; 26 let HWEncoding{4-0} = num; 27 } 28 29 // Registers are identified with 5-bit ID numbers. 30 // Ri - 32-bit integer registers. 31 class Ri<bits<5> num, string n, list<string> alt = []> : 32 HexagonReg<num, n, alt>; 33 34 // Rf - 32-bit floating-point registers. 35 class Rf<bits<5> num, string n> : HexagonReg<num, n>; 36 37 // Rd - 64-bit registers. 38 class Rd<bits<5> num, string n, list<Register> subregs, 39 list<string> alt = []> : 40 HexagonDoubleReg<num, n, subregs, alt> { 41 let SubRegs = subregs; 42 } 43 44 // Rp - predicate registers 45 class Rp<bits<5> num, string n> : HexagonReg<num, n>; 46 47 48 // Rq - vector predicate registers 49 class Rq<bits<3> num, string n> : Register<n, []> { 50 let HWEncoding{2-0} = num; 51 } 52 53 // Rc - control registers 54 class Rc<bits<5> num, string n, 55 list<string> alt = [], list<Register> alias = []> : 56 HexagonReg<num, n, alt, alias>; 57 58 // Rcc - 64-bit control registers. 59 class Rcc<bits<5> num, string n, list<Register> subregs, 60 list<string> alt = []> : 61 HexagonDoubleReg<num, n, subregs, alt> { 62 let SubRegs = subregs; 63 } 64 65 // Mx - address modifier registers 66 class Mx<bits<1> num, string n> : Register<n, []> { 67 let HWEncoding{0} = num; 68 } 69 70 // Rg - Guest/Hypervisor registers 71 class Rg<bits<5> num, string n, 72 list<string> alt = [], list<Register> alias = []> : 73 HexagonReg<num, n, alt, alias>; 74 75 // Rgg - 64-bit Guest/Hypervisor registers 76 class Rgg<bits<5> num, string n, list<Register> subregs> : 77 HexagonDoubleReg<num, n, subregs> { 78 let SubRegs = subregs; 79 } 80 81 def isub_lo : SubRegIndex<32>; 82 def isub_hi : SubRegIndex<32, 32>; 83 def vsub_lo : SubRegIndex<512>; 84 def vsub_hi : SubRegIndex<512, 512>; 85 def wsub_lo : SubRegIndex<1024>; 86 def wsub_hi : SubRegIndex<1024, 1024>; 87 def subreg_overflow : SubRegIndex<1, 0>; 88 89 // Integer registers. 90 foreach i = 0-28 in { 91 def R#i : Ri<i, "r"#i>, DwarfRegNum<[i]>; 92 } 93 def R29 : Ri<29, "r29", ["sp"]>, DwarfRegNum<[29]>; 94 def R30 : Ri<30, "r30", ["fp"]>, DwarfRegNum<[30]>; 95 def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>; 96 97 // Aliases of the R* registers used to hold 64-bit int values (doubles). 98 let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in { 99 def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>; 100 def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>; 101 def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>; 102 def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>; 103 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>; 104 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>; 105 def D6 : Rd<12, "r13:12", [R12, R13]>, DwarfRegNum<[44]>; 106 def D7 : Rd<14, "r15:14", [R14, R15]>, DwarfRegNum<[46]>; 107 def D8 : Rd<16, "r17:16", [R16, R17]>, DwarfRegNum<[48]>; 108 def D9 : Rd<18, "r19:18", [R18, R19]>, DwarfRegNum<[50]>; 109 def D10 : Rd<20, "r21:20", [R20, R21]>, DwarfRegNum<[52]>; 110 def D11 : Rd<22, "r23:22", [R22, R23]>, DwarfRegNum<[54]>; 111 def D12 : Rd<24, "r25:24", [R24, R25]>, DwarfRegNum<[56]>; 112 def D13 : Rd<26, "r27:26", [R26, R27]>, DwarfRegNum<[58]>; 113 def D14 : Rd<28, "r29:28", [R28, R29]>, DwarfRegNum<[60]>; 114 def D15 : Rd<30, "r31:30", [R30, R31], ["lr:fp"]>, DwarfRegNum<[62]>; 115 } 116 117 // Predicate registers. 118 def P0 : Rp<0, "p0">, DwarfRegNum<[63]>; 119 def P1 : Rp<1, "p1">, DwarfRegNum<[64]>; 120 def P2 : Rp<2, "p2">, DwarfRegNum<[65]>; 121 def P3 : Rp<3, "p3">, DwarfRegNum<[66]>; 122 123 // Fake register to represent USR.OVF bit. Artihmetic/saturating instruc- 124 // tions modify this bit, and multiple such instructions are allowed in the 125 // same packet. We need to ignore output dependencies on this bit, but not 126 // on the entire USR. 127 def USR_OVF : Rc<?, "usr.ovf">; 128 129 def USR : Rc<8, "usr", ["c8"]>, DwarfRegNum<[75]> { 130 let SubRegIndices = [subreg_overflow]; 131 let SubRegs = [USR_OVF]; 132 } 133 134 // Control registers. 135 def SA0: Rc<0, "sa0", ["c0"]>, DwarfRegNum<[67]>; 136 def LC0: Rc<1, "lc0", ["c1"]>, DwarfRegNum<[68]>; 137 def SA1: Rc<2, "sa1", ["c2"]>, DwarfRegNum<[69]>; 138 def LC1: Rc<3, "lc1", ["c3"]>, DwarfRegNum<[70]>; 139 def P3_0: Rc<4, "p3:0", ["c4"], [P0, P1, P2, P3]>, 140 DwarfRegNum<[71]>; 141 // When defining more Cn registers, make sure to explicitly mark them 142 // as reserved in HexagonRegisterInfo.cpp. 143 def C5: Rc<5, "c5", ["c5"]>, DwarfRegNum<[72]>; 144 def M0: Rc<6, "m0", ["c6"]>, DwarfRegNum<[73]>; 145 def M1: Rc<7, "m1", ["c7"]>, DwarfRegNum<[74]>; 146 // Define C8 separately and make it aliased with USR. 147 // The problem is that USR has subregisters (e.g. overflow). If USR was 148 // specified as a subregister of C9_8, it would imply that subreg_overflow 149 // and isub_lo can be composed, which leads to all kinds of issues 150 // with lane masks. 151 def C8: Rc<8, "c8", [], [USR]>, DwarfRegNum<[75]>; 152 def PC: Rc<9, "pc", ["c9"]>, DwarfRegNum<[76]>; 153 def UGP: Rc<10, "ugp", ["c10"]>, DwarfRegNum<[77]>; 154 def GP: Rc<11, "gp", ["c11"]>, DwarfRegNum<[78]>; 155 def CS0: Rc<12, "cs0", ["c12"]>, DwarfRegNum<[79]>; 156 def CS1: Rc<13, "cs1", ["c13"]>, DwarfRegNum<[80]>; 157 def UPCYCLELO: Rc<14, "upcyclelo", ["c14"]>, DwarfRegNum<[81]>; 158 def UPCYCLEHI: Rc<15, "upcyclehi", ["c15"]>, DwarfRegNum<[82]>; 159 def FRAMELIMIT: Rc<16, "framelimit", ["c16"]>, DwarfRegNum<[83]>; 160 def FRAMEKEY: Rc<17, "framekey", ["c17"]>, DwarfRegNum<[84]>; 161 def PKTCOUNTLO: Rc<18, "pktcountlo", ["c18"]>, DwarfRegNum<[85]>; 162 def PKTCOUNTHI: Rc<19, "pktcounthi", ["c19"]>, DwarfRegNum<[86]>; 163 def UTIMERLO: Rc<30, "utimerlo", ["c30"]>, DwarfRegNum<[97]>; 164 def UTIMERHI: Rc<31, "utimerhi", ["c31"]>, DwarfRegNum<[98]>; 165 166 // Control registers pairs. 167 let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in { 168 def C1_0 : Rcc<0, "c1:0", [SA0, LC0], ["lc0:sa0"]>, DwarfRegNum<[67]>; 169 def C3_2 : Rcc<2, "c3:2", [SA1, LC1], ["lc1:sa1"]>, DwarfRegNum<[69]>; 170 def C5_4 : Rcc<4, "c5:4", [P3_0, C5]>, DwarfRegNum<[71]>; 171 def C7_6 : Rcc<6, "c7:6", [M0, M1], ["m1:0"]>, DwarfRegNum<[72]>; 172 // Use C8 instead of USR as a subregister of C9_8. 173 def C9_8 : Rcc<8, "c9:8", [C8, PC]>, DwarfRegNum<[74]>; 174 def C11_10 : Rcc<10, "c11:10", [UGP, GP]>, DwarfRegNum<[76]>; 175 def CS : Rcc<12, "c13:12", [CS0, CS1], ["cs1:0"]>, DwarfRegNum<[78]>; 176 def UPCYCLE: Rcc<14, "c15:14", [UPCYCLELO, UPCYCLEHI], ["upcycle"]>, 177 DwarfRegNum<[80]>; 178 def C17_16 : Rcc<16, "c17:16", [FRAMELIMIT, FRAMEKEY]>, DwarfRegNum<[83]>; 179 def PKTCOUNT : Rcc<18, "c19:18", [PKTCOUNTLO, PKTCOUNTHI], ["pktcount"]>, 180 DwarfRegNum<[85]>; 181 def UTIMER : Rcc<30, "c31:30", [UTIMERLO, UTIMERHI], ["utimer"]>, 182 DwarfRegNum<[97]>; 183 } 184 185 foreach i = 0-31 in { 186 def V#i : Ri<i, "v"#i>, DwarfRegNum<[!add(i, 99)]>; 187 } 188 def VTMP : Ri<0, "vtmp">, DwarfRegNum<[131]>; 189 190 // Aliases of the V* registers used to hold double vec values. 191 let SubRegIndices = [vsub_lo, vsub_hi], CoveredBySubRegs = 1 in { 192 def W0 : Rd< 0, "v1:0", [V0, V1]>, DwarfRegNum<[99]>; 193 def W1 : Rd< 2, "v3:2", [V2, V3]>, DwarfRegNum<[101]>; 194 def W2 : Rd< 4, "v5:4", [V4, V5]>, DwarfRegNum<[103]>; 195 def W3 : Rd< 6, "v7:6", [V6, V7]>, DwarfRegNum<[105]>; 196 def W4 : Rd< 8, "v9:8", [V8, V9]>, DwarfRegNum<[107]>; 197 def W5 : Rd<10, "v11:10", [V10, V11]>, DwarfRegNum<[109]>; 198 def W6 : Rd<12, "v13:12", [V12, V13]>, DwarfRegNum<[111]>; 199 def W7 : Rd<14, "v15:14", [V14, V15]>, DwarfRegNum<[113]>; 200 def W8 : Rd<16, "v17:16", [V16, V17]>, DwarfRegNum<[115]>; 201 def W9 : Rd<18, "v19:18", [V18, V19]>, DwarfRegNum<[117]>; 202 def W10 : Rd<20, "v21:20", [V20, V21]>, DwarfRegNum<[119]>; 203 def W11 : Rd<22, "v23:22", [V22, V23]>, DwarfRegNum<[121]>; 204 def W12 : Rd<24, "v25:24", [V24, V25]>, DwarfRegNum<[123]>; 205 def W13 : Rd<26, "v27:26", [V26, V27]>, DwarfRegNum<[125]>; 206 def W14 : Rd<28, "v29:28", [V28, V29]>, DwarfRegNum<[127]>; 207 def W15 : Rd<30, "v31:30", [V30, V31]>, DwarfRegNum<[129]>; 208 } 209 210 // Aliases of the V* registers used to hold quad vec values. 211 let SubRegIndices = [wsub_lo, wsub_hi], CoveredBySubRegs = 1 in { 212 def VQ0 : Rd< 0, "v3:0", [W0, W1]>, DwarfRegNum<[252]>; 213 def VQ1 : Rd< 4, "v7:4", [W2, W3]>, DwarfRegNum<[253]>; 214 def VQ2 : Rd< 8, "v11:8", [W4, W5]>, DwarfRegNum<[254]>; 215 def VQ3 : Rd<12, "v15:12", [W6, W7]>, DwarfRegNum<[255]>; 216 def VQ4 : Rd<16, "v19:16", [W8, W9]>, DwarfRegNum<[256]>; 217 def VQ5 : Rd<20, "v23:20", [W10, W11]>, DwarfRegNum<[257]>; 218 def VQ6 : Rd<24, "v27:24", [W12, W13]>, DwarfRegNum<[258]>; 219 def VQ7 : Rd<28, "v31:28", [W14, W15]>, DwarfRegNum<[259]>; 220 } 221 222 // Vector Predicate registers. 223 def Q0 : Rq<0, "q0">, DwarfRegNum<[131]>; 224 def Q1 : Rq<1, "q1">, DwarfRegNum<[132]>; 225 def Q2 : Rq<2, "q2">, DwarfRegNum<[133]>; 226 def Q3 : Rq<3, "q3">, DwarfRegNum<[134]>; 227 228 // Guest Registers 229 def GELR: Rg<0, "gelr", ["g0"]>, DwarfRegNum<[220]>; 230 def GSR: Rg<1, "gsr", ["g1"]>, DwarfRegNum<[221]>; 231 def GOSP: Rg<2, "gosp", ["g2"]>, DwarfRegNum<[222]>; 232 def G3: Rg<3, "gbadva", ["g3"]>, DwarfRegNum<[223]>; 233 def G4: Rg<4, "g4">, DwarfRegNum<[224]>; 234 def G5: Rg<5, "g5">, DwarfRegNum<[225]>; 235 def G6: Rg<6, "g6">, DwarfRegNum<[226]>; 236 def G7: Rg<7, "g7">, DwarfRegNum<[227]>; 237 def G8: Rg<8, "g8">, DwarfRegNum<[228]>; 238 def G9: Rg<9, "g9">, DwarfRegNum<[229]>; 239 def G10: Rg<10, "g10">, DwarfRegNum<[230]>; 240 def G11: Rg<11, "g11">, DwarfRegNum<[231]>; 241 def G12: Rg<12, "g12">, DwarfRegNum<[232]>; 242 def G13: Rg<13, "g13">, DwarfRegNum<[233]>; 243 def G14: Rg<14, "g14">, DwarfRegNum<[234]>; 244 def G15: Rg<15, "g15">, DwarfRegNum<[235]>; 245 def GPMUCNT4: Rg<16, "gpmucnt4", ["g16"]>, DwarfRegNum<[236]>; 246 def GPMUCNT5: Rg<17, "gpmucnt5", ["g17"]>, DwarfRegNum<[237]>; 247 def GPMUCNT6: Rg<18, "gpmucnt6", ["g18"]>, DwarfRegNum<[238]>; 248 def GPMUCNT7: Rg<19, "gpmucnt7", ["g19"]>, DwarfRegNum<[239]>; 249 def G20: Rg<20, "g20">, DwarfRegNum<[240]>; 250 def G21: Rg<21, "g21">, DwarfRegNum<[241]>; 251 def G22: Rg<22, "g22">, DwarfRegNum<[242]>; 252 def G23: Rg<23, "g23">, DwarfRegNum<[243]>; 253 def GPCYCLELO: Rg<24, "gpcyclelo", ["g24"]>, DwarfRegNum<[244]>; 254 def GPCYCLEHI: Rg<25, "gpcyclehi", ["g25"]>, DwarfRegNum<[245]>; 255 def GPMUCNT0: Rg<26, "gpmucnt0", ["g26"]>, DwarfRegNum<[246]>; 256 def GPMUCNT1: Rg<27, "gpmucnt1", ["g27"]>, DwarfRegNum<[247]>; 257 def GPMUCNT2: Rg<28, "gpmucnt2", ["g28"]>, DwarfRegNum<[248]>; 258 def GPMUCNT3: Rg<29, "gpmucnt3", ["g29"]>, DwarfRegNum<[249]>; 259 def G30: Rg<30, "g30">, DwarfRegNum<[250]>; 260 def G31: Rg<31, "g31">, DwarfRegNum<[251]>; 261 262 // Guest Register Pairs 263 let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in { 264 def G1_0 : Rgg<0, "g1:0", [GELR, GSR]>, DwarfRegNum<[220]>; 265 def G3_2 : Rgg<2, "g3:2", [GOSP, G3]>, DwarfRegNum<[222]>; 266 def G5_4 : Rgg<4, "g5:4", [G4, G5]>, DwarfRegNum<[224]>; 267 def G7_6 : Rgg<6, "g7:6", [G6, G7]>, DwarfRegNum<[226]>; 268 def G9_8 : Rgg<8, "g9:8", [G8, G9]>, DwarfRegNum<[228]>; 269 def G11_10 : Rgg<10, "g11:10", [G10, G11]>, DwarfRegNum<[230]>; 270 def G13_12 : Rgg<12, "g13:12", [G12, G13]>, DwarfRegNum<[232]>; 271 def G15_14 : Rgg<14, "g15:14", [G14, G15]>, DwarfRegNum<[234]>; 272 def G17_16 : Rgg<16, "g17:16", [GPMUCNT4, GPMUCNT5]>, DwarfRegNum<[236]>; 273 def G19_18 : Rgg<18, "g19:18", [GPMUCNT6, GPMUCNT7]>, DwarfRegNum<[238]>; 274 def G21_20 : Rgg<20, "g21:20", [G20, G21]>, DwarfRegNum<[240]>; 275 def G23_22 : Rgg<22, "g23:22", [G22, G23]>, DwarfRegNum<[242]>; 276 def G25_24 : Rgg<24, "g25:24", [GPCYCLELO, GPCYCLEHI]>, DwarfRegNum<[244]>; 277 def G27_26 : Rgg<26, "g27:26", [GPMUCNT0, GPMUCNT1]>, DwarfRegNum<[246]>; 278 def G29_28 : Rgg<28, "g29:28", [GPMUCNT2, GPMUCNT3]>, DwarfRegNum<[248]>; 279 def G31_30 : Rgg<30, "g31:30", [G30, G31]>, DwarfRegNum<[250]>; 280 } 281 282} 283 284// HVX types 285 286def VecI1: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 287 [v512i1, v1024i1, v512i1]>; 288def VecI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 289 [v64i8, v128i8, v64i8]>; 290def VecI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 291 [v32i16, v64i16, v32i16]>; 292def VecI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 293 [v16i32, v32i32, v16i32]>; 294 295def VecPI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 296 [v128i8, v256i8, v128i8]>; 297def VecPI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 298 [v64i16, v128i16, v64i16]>; 299def VecPI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 300 [v32i32, v64i32, v32i32]>; 301 302def VecQ8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 303 [v64i1, v128i1, v64i1]>; 304def VecQ16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 305 [v32i1, v64i1, v32i1]>; 306def VecQ32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 307 [v16i1, v32i1, v16i1]>; 308 309// HVX register classes 310 311def HvxVR : RegisterClass<"Hexagon", [VecI8, VecI16, VecI32], 512, 312 (add (sequence "V%u", 0, 31), VTMP)> { 313 let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], 314 [RegInfo<512,512,512>, RegInfo<1024,1024,1024>, RegInfo<512,512,512>]>; 315} 316 317def HvxWR : RegisterClass<"Hexagon", [VecPI8, VecPI16, VecPI32], 1024, 318 (add (sequence "W%u", 0, 15))> { 319 let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], 320 [RegInfo<1024,1024,1024>, RegInfo<2048,2048,2048>, RegInfo<1024,1024,1024>]>; 321} 322 323def HvxQR : RegisterClass<"Hexagon", [VecI1, VecQ8, VecQ16, VecQ32], 512, 324 (add Q0, Q1, Q2, Q3)> { 325 let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], 326 [RegInfo<512,512,512>, RegInfo<1024,1024,1024>, RegInfo<512,512,512>]>; 327} 328 329def HvxVQR : RegisterClass<"Hexagon", [untyped], 2048, 330 (add (sequence "VQ%u", 0, 7))> { 331 let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], 332 [RegInfo<2048,2048,2048>, RegInfo<4096,4096,4096>, RegInfo<2048,2048,2048>]>; 333} 334 335// Core register classes 336 337def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32, 338 (add (sequence "R%u", 0, 9), (sequence "R%u", 12, 28), 339 R10, R11, R29, R30, R31)>; 340 341// Registers are listed in reverse order for allocation preference reasons. 342def GeneralSubRegs : RegisterClass<"Hexagon", [i32], 32, 343 (add R23, R22, R21, R20, R19, R18, R17, R16, 344 R7, R6, R5, R4, R3, R2, R1, R0)>; 345 346def IntRegsLow8 : RegisterClass<"Hexagon", [i32], 32, 347 (add R7, R6, R5, R4, R3, R2, R1, R0)> ; 348 349def DoubleRegs : RegisterClass<"Hexagon", [i64, f64, v8i8, v4i16, v2i32], 64, 350 (add (sequence "D%u", 0, 4), (sequence "D%u", 6, 13), D5, D14, D15)>; 351 352def GeneralDoubleLow8Regs : RegisterClass<"Hexagon", [i64], 64, 353 (add D11, D10, D9, D8, D3, D2, D1, D0)>; 354 355let Size = 32 in 356def PredRegs : RegisterClass<"Hexagon", 357 [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32, (add P0, P1, P2, P3)>; 358 359let Size = 32 in 360def ModRegs : RegisterClass<"Hexagon", [i32], 32, (add M0, M1)>; 361 362let Size = 32, isAllocatable = 0 in 363def CtrRegs : RegisterClass<"Hexagon", [i32], 32, 364 (add LC0, SA0, LC1, SA1, P3_0, C5, C8, PC, UGP, GP, CS0, CS1, 365 UPCYCLELO, UPCYCLEHI, 366 FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI, UTIMERLO, UTIMERHI, 367 M0, M1, USR)>; 368 369let isAllocatable = 0 in 370def UsrBits : RegisterClass<"Hexagon", [i1], 0, (add USR_OVF)>; 371 372let Size = 64, isAllocatable = 0 in 373def CtrRegs64 : RegisterClass<"Hexagon", [i64], 64, 374 (add C1_0, C3_2, C5_4, C7_6, C9_8, C11_10, CS, UPCYCLE, C17_16, 375 PKTCOUNT, UTIMER)>; 376 377let Size = 32, isAllocatable = 0 in 378def GuestRegs : RegisterClass<"Hexagon", [i32], 32, 379 (add GELR, GSR, GOSP, 380 (sequence "G%u", 3, 15), 381 GPMUCNT4, GPMUCNT5, GPMUCNT6, GPMUCNT7, 382 G20, G21, G22, G23, 383 GPCYCLELO, GPCYCLEHI, GPMUCNT0, GPMUCNT1, 384 GPMUCNT2, GPMUCNT3, 385 G30, G31)>; 386 387let Size = 64, isAllocatable = 0 in 388def GuestRegs64 : RegisterClass<"Hexagon", [i64], 64, 389 (add G1_0, G3_2, 390 G5_4, G7_6, G9_8, G11_10, G13_12, G15_14, 391 G17_16, G19_18, 392 G21_20, G23_22, 393 G25_24, G27_26, G29_28, 394 G31_30)>; 395 396// These registers are new for v62 and onward. 397// The function RegisterMatchesArch() uses this list for validation. 398let isAllocatable = 0 in 399def V62Regs : RegisterClass<"Hexagon", [i32], 32, 400 (add FRAMELIMIT, FRAMEKEY, C17_16, PKTCOUNTLO, PKTCOUNTHI, PKTCOUNT, 401 UTIMERLO, UTIMERHI, UTIMER)>; 402 403// These registers are new for v65 and onward. 404let Size = 32, isAllocatable = 0 in 405def V65Regs : RegisterClass<"Hexagon", [i32], 32, (add VTMP)>; 406 407 408def HexagonCSR 409 : CalleeSavedRegs<(add R16, R17, R18, R19, R20, R21, R22, R23, 410 R24, R25, R26, R27)>; 411