1 //===- HexagonBaseInfo.h - Top level definitions for Hexagon ----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains small standalone helper functions and enum definitions for 11 // the Hexagon target useful for the compiler back-end and the MC libraries. 12 // As such, it deliberately does not include references to LLVM core 13 // code gen types, passes, etc.. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H 18 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H 19 20 #include "HexagonDepITypes.h" 21 #include "MCTargetDesc/HexagonMCTargetDesc.h" 22 23 namespace llvm { 24 25 /// HexagonII - This namespace holds all of the target specific flags that 26 /// instruction info tracks. 27 namespace HexagonII { 28 unsigned const TypeCVI_FIRST = TypeCVI_4SLOT_MPY; 29 unsigned const TypeCVI_LAST = TypeCVI_ZW; 30 31 enum SubTarget { 32 HasV55SubT = 0x3c, 33 HasV60SubT = 0x38, 34 }; 35 36 enum AddrMode { 37 NoAddrMode = 0, // No addressing mode 38 Absolute = 1, // Absolute addressing mode 39 AbsoluteSet = 2, // Absolute set addressing mode 40 BaseImmOffset = 3, // Indirect with offset 41 BaseLongOffset = 4, // Indirect with long offset 42 BaseRegOffset = 5, // Indirect with register offset 43 PostInc = 6 // Post increment addressing mode 44 }; 45 46 enum MemAccessSize { 47 NoMemAccess = 0, 48 ByteAccess, 49 HalfWordAccess, 50 WordAccess, 51 DoubleWordAccess, 52 HVXVectorAccess 53 }; 54 55 // MCInstrDesc TSFlags 56 // *** Must match HexagonInstrFormat*.td *** 57 enum { 58 // This 7-bit field describes the insn type. 59 TypePos = 0, 60 TypeMask = 0x7f, 61 62 // Solo instructions. 63 SoloPos = 7, 64 SoloMask = 0x1, 65 // Packed only with A or X-type instructions. 66 SoloAXPos = 8, 67 SoloAXMask = 0x1, 68 // Only A-type instruction in first slot or nothing. 69 RestrictSlot1AOKPos = 9, 70 RestrictSlot1AOKMask = 0x1, 71 72 // Predicated instructions. 73 PredicatedPos = 10, 74 PredicatedMask = 0x1, 75 PredicatedFalsePos = 11, 76 PredicatedFalseMask = 0x1, 77 PredicatedNewPos = 12, 78 PredicatedNewMask = 0x1, 79 PredicateLatePos = 13, 80 PredicateLateMask = 0x1, 81 82 // New-Value consumer instructions. 83 NewValuePos = 14, 84 NewValueMask = 0x1, 85 // New-Value producer instructions. 86 hasNewValuePos = 15, 87 hasNewValueMask = 0x1, 88 // Which operand consumes or produces a new value. 89 NewValueOpPos = 16, 90 NewValueOpMask = 0x7, 91 // Stores that can become new-value stores. 92 mayNVStorePos = 19, 93 mayNVStoreMask = 0x1, 94 // New-value store instructions. 95 NVStorePos = 20, 96 NVStoreMask = 0x1, 97 // Loads that can become current-value loads. 98 mayCVLoadPos = 21, 99 mayCVLoadMask = 0x1, 100 // Current-value load instructions. 101 CVLoadPos = 22, 102 CVLoadMask = 0x1, 103 104 // Extendable insns. 105 ExtendablePos = 23, 106 ExtendableMask = 0x1, 107 // Insns must be extended. 108 ExtendedPos = 24, 109 ExtendedMask = 0x1, 110 // Which operand may be extended. 111 ExtendableOpPos = 25, 112 ExtendableOpMask = 0x7, 113 // Signed or unsigned range. 114 ExtentSignedPos = 28, 115 ExtentSignedMask = 0x1, 116 // Number of bits of range before extending operand. 117 ExtentBitsPos = 29, 118 ExtentBitsMask = 0x1f, 119 // Alignment power-of-two before extending operand. 120 ExtentAlignPos = 34, 121 ExtentAlignMask = 0x3, 122 123 CofMax1Pos = 36, 124 CofMax1Mask = 0x1, 125 CofRelax1Pos = 37, 126 CofRelax1Mask = 0x1, 127 CofRelax2Pos = 38, 128 CofRelax2Mask = 0x1, 129 130 RestrictNoSlot1StorePos = 39, 131 RestrictNoSlot1StoreMask = 0x1, 132 133 // Addressing mode for load/store instructions. 134 AddrModePos = 42, 135 AddrModeMask = 0x7, 136 // Access size for load/store instructions. 137 MemAccessSizePos = 45, 138 MemAccesSizeMask = 0xf, 139 140 // Branch predicted taken. 141 TakenPos = 49, 142 TakenMask = 0x1, 143 144 // Floating-point instructions. 145 FPPos = 50, 146 FPMask = 0x1, 147 148 // New-Value producer-2 instructions. 149 hasNewValuePos2 = 52, 150 hasNewValueMask2 = 0x1, 151 // Which operand consumes or produces a new value. 152 NewValueOpPos2 = 53, 153 NewValueOpMask2 = 0x7, 154 155 // Accumulator instructions. 156 AccumulatorPos = 56, 157 AccumulatorMask = 0x1, 158 159 // Complex XU, prevent xu competition by preferring slot3 160 PrefersSlot3Pos = 57, 161 PrefersSlot3Mask = 0x1, 162 163 // v65 164 HasTmpDstPos = 60, 165 HasTmpDstMask = 0x1, 166 167 CVINewPos = 62, 168 CVINewMask = 0x1, 169 }; 170 171 // *** The code above must match HexagonInstrFormat*.td *** // 172 173 // Hexagon specific MO operand flag mask. 174 enum HexagonMOTargetFlagVal { 175 // Hexagon-specific MachineOperand target flags. 176 // 177 // When changing these, make sure to update 178 // getSerializableDirectMachineOperandTargetFlags and 179 // getSerializableBitmaskMachineOperandTargetFlags if needed. 180 MO_NO_FLAG, 181 182 /// MO_PCREL - On a symbol operand, indicates a PC-relative relocation 183 /// Used for computing a global address for PIC compilations 184 MO_PCREL, 185 186 /// MO_GOT - Indicates a GOT-relative relocation 187 MO_GOT, 188 189 // Low or high part of a symbol. 190 MO_LO16, 191 MO_HI16, 192 193 // Offset from the base of the SDA. 194 MO_GPREL, 195 196 // MO_GDGOT - indicates GOT relative relocation for TLS 197 // GeneralDynamic method 198 MO_GDGOT, 199 200 // MO_GDPLT - indicates PLT relative relocation for TLS 201 // GeneralDynamic method 202 MO_GDPLT, 203 204 // MO_IE - indicates non PIC relocation for TLS 205 // Initial Executable method 206 MO_IE, 207 208 // MO_IEGOT - indicates PIC relocation for TLS 209 // Initial Executable method 210 MO_IEGOT, 211 212 // MO_TPREL - indicates relocation for TLS 213 // local Executable method 214 MO_TPREL, 215 216 // HMOTF_ConstExtended 217 // Addendum to above, indicates a const extended op 218 // Can be used as a mask. 219 HMOTF_ConstExtended = 0x80, 220 221 // Union of all bitmasks (currently only HMOTF_ConstExtended). 222 MO_Bitmasks = HMOTF_ConstExtended 223 }; 224 225 // Hexagon Sub-instruction classes. 226 enum SubInstructionGroup { 227 HSIG_None = 0, 228 HSIG_L1, 229 HSIG_L2, 230 HSIG_S1, 231 HSIG_S2, 232 HSIG_A, 233 HSIG_Compound 234 }; 235 236 // Hexagon Compound classes. 237 enum CompoundGroup { 238 HCG_None = 0, 239 HCG_A, 240 HCG_B, 241 HCG_C 242 }; 243 244 enum InstParseBits { 245 INST_PARSE_MASK = 0x0000c000, 246 INST_PARSE_PACKET_END = 0x0000c000, 247 INST_PARSE_LOOP_END = 0x00008000, 248 INST_PARSE_NOT_END = 0x00004000, 249 INST_PARSE_DUPLEX = 0x00000000, 250 INST_PARSE_EXTENDER = 0x00000000 251 }; 252 253 enum InstIClassBits : unsigned { 254 INST_ICLASS_MASK = 0xf0000000, 255 INST_ICLASS_EXTENDER = 0x00000000, 256 INST_ICLASS_J_1 = 0x10000000, 257 INST_ICLASS_J_2 = 0x20000000, 258 INST_ICLASS_LD_ST_1 = 0x30000000, 259 INST_ICLASS_LD_ST_2 = 0x40000000, 260 INST_ICLASS_J_3 = 0x50000000, 261 INST_ICLASS_CR = 0x60000000, 262 INST_ICLASS_ALU32_1 = 0x70000000, 263 INST_ICLASS_XTYPE_1 = 0x80000000, 264 INST_ICLASS_LD = 0x90000000, 265 INST_ICLASS_ST = 0xa0000000, 266 INST_ICLASS_ALU32_2 = 0xb0000000, 267 INST_ICLASS_XTYPE_2 = 0xc0000000, 268 INST_ICLASS_XTYPE_3 = 0xd0000000, 269 INST_ICLASS_XTYPE_4 = 0xe0000000, 270 INST_ICLASS_ALU32_3 = 0xf0000000 271 }; 272 273 LLVM_ATTRIBUTE_UNUSED getMemAccessSizeInBytes(MemAccessSize S)274 static unsigned getMemAccessSizeInBytes(MemAccessSize S) { 275 switch (S) { 276 case ByteAccess: return 1; 277 case HalfWordAccess: return 2; 278 case WordAccess: return 4; 279 case DoubleWordAccess: return 8; 280 default: return 0; 281 } 282 } 283 } // end namespace HexagonII 284 285 } // end namespace llvm 286 287 #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H 288