1//===- NVPTX.td - Describe the NVPTX Target Machine -----------*- tblgen -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// This is the top level entry point for the NVPTX target.
10//===----------------------------------------------------------------------===//
11
12//===----------------------------------------------------------------------===//
13// Target-independent interfaces
14//===----------------------------------------------------------------------===//
15
16include "llvm/Target/Target.td"
17
18include "NVPTXRegisterInfo.td"
19include "NVPTXInstrInfo.td"
20
21//===----------------------------------------------------------------------===//
22// Subtarget Features.
23// - We use the SM version number instead of explicit feature table.
24// - Need at least one feature to avoid generating zero sized array by
25//   TableGen in NVPTXGenSubtarget.inc.
26//===----------------------------------------------------------------------===//
27
28// SM Versions
29def SM20 : SubtargetFeature<"sm_20", "SmVersion", "20",
30                            "Target SM 2.0">;
31def SM21 : SubtargetFeature<"sm_21", "SmVersion", "21",
32                            "Target SM 2.1">;
33def SM30 : SubtargetFeature<"sm_30", "SmVersion", "30",
34                            "Target SM 3.0">;
35def SM32 : SubtargetFeature<"sm_32", "SmVersion", "32",
36                            "Target SM 3.2">;
37def SM35 : SubtargetFeature<"sm_35", "SmVersion", "35",
38                            "Target SM 3.5">;
39def SM37 : SubtargetFeature<"sm_37", "SmVersion", "37",
40                            "Target SM 3.7">;
41def SM50 : SubtargetFeature<"sm_50", "SmVersion", "50",
42                            "Target SM 5.0">;
43def SM52 : SubtargetFeature<"sm_52", "SmVersion", "52",
44                            "Target SM 5.2">;
45def SM53 : SubtargetFeature<"sm_53", "SmVersion", "53",
46                            "Target SM 5.3">;
47def SM60 : SubtargetFeature<"sm_60", "SmVersion", "60",
48                             "Target SM 6.0">;
49def SM61 : SubtargetFeature<"sm_61", "SmVersion", "61",
50                             "Target SM 6.1">;
51def SM62 : SubtargetFeature<"sm_62", "SmVersion", "62",
52                             "Target SM 6.2">;
53def SM70 : SubtargetFeature<"sm_70", "SmVersion", "70",
54                             "Target SM 7.0">;
55def SM72 : SubtargetFeature<"sm_72", "SmVersion", "72",
56                             "Target SM 7.2">;
57def SM75 : SubtargetFeature<"sm_75", "SmVersion", "75",
58                             "Target SM 7.5">;
59
60// PTX Versions
61def PTX32 : SubtargetFeature<"ptx32", "PTXVersion", "32",
62                             "Use PTX version 3.2">;
63def PTX40 : SubtargetFeature<"ptx40", "PTXVersion", "40",
64                             "Use PTX version 4.0">;
65def PTX41 : SubtargetFeature<"ptx41", "PTXVersion", "41",
66                             "Use PTX version 4.1">;
67def PTX42 : SubtargetFeature<"ptx42", "PTXVersion", "42",
68                             "Use PTX version 4.2">;
69def PTX43 : SubtargetFeature<"ptx43", "PTXVersion", "43",
70                             "Use PTX version 4.3">;
71def PTX50 : SubtargetFeature<"ptx50", "PTXVersion", "50",
72                             "Use PTX version 5.0">;
73def PTX60 : SubtargetFeature<"ptx60", "PTXVersion", "60",
74                             "Use PTX version 6.0">;
75def PTX61 : SubtargetFeature<"ptx61", "PTXVersion", "61",
76                             "Use PTX version 6.1">;
77def PTX63 : SubtargetFeature<"ptx63", "PTXVersion", "63",
78                             "Use PTX version 6.3">;
79
80//===----------------------------------------------------------------------===//
81// NVPTX supported processors.
82//===----------------------------------------------------------------------===//
83
84class Proc<string Name, list<SubtargetFeature> Features>
85 : Processor<Name, NoItineraries, Features>;
86
87def : Proc<"sm_20", [SM20]>;
88def : Proc<"sm_21", [SM21]>;
89def : Proc<"sm_30", [SM30]>;
90def : Proc<"sm_32", [SM32, PTX40]>;
91def : Proc<"sm_35", [SM35]>;
92def : Proc<"sm_37", [SM37, PTX41]>;
93def : Proc<"sm_50", [SM50, PTX40]>;
94def : Proc<"sm_52", [SM52, PTX41]>;
95def : Proc<"sm_53", [SM53, PTX42]>;
96def : Proc<"sm_60", [SM60, PTX50]>;
97def : Proc<"sm_61", [SM61, PTX50]>;
98def : Proc<"sm_62", [SM62, PTX50]>;
99def : Proc<"sm_70", [SM70, PTX60]>;
100def : Proc<"sm_72", [SM72, PTX61]>;
101def : Proc<"sm_75", [SM75, PTX63]>;
102
103def NVPTXInstrInfo : InstrInfo {
104}
105
106def NVPTX : Target {
107  let InstructionSet = NVPTXInstrInfo;
108}
109