1//==- SystemZInstrFP.td - Floating-point SystemZ instructions --*- tblgen-*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10// TODO: Most floating-point instructions (except for simple moves and the 11// like) can raise exceptions -- should they have hasSideEffects=1 ? 12 13//===----------------------------------------------------------------------===// 14// Select instructions 15//===----------------------------------------------------------------------===// 16 17// C's ?: operator for floating-point operands. 18let Predicates = [FeatureVector] in { 19 def SelectVR32 : SelectWrapper<f32, VR32>; 20 def SelectVR64 : SelectWrapper<f64, VR64>; 21} 22def SelectF32 : SelectWrapper<f32, FP32>; 23def SelectF64 : SelectWrapper<f64, FP64>; 24let Predicates = [FeatureNoVectorEnhancements1] in 25 def SelectF128 : SelectWrapper<f128, FP128>; 26let Predicates = [FeatureVectorEnhancements1] in 27 def SelectVR128 : SelectWrapper<f128, VR128>; 28 29defm CondStoreF32 : CondStores<FP32, nonvolatile_store, 30 nonvolatile_load, bdxaddr20only>; 31defm CondStoreF64 : CondStores<FP64, nonvolatile_store, 32 nonvolatile_load, bdxaddr20only>; 33 34//===----------------------------------------------------------------------===// 35// Move instructions 36//===----------------------------------------------------------------------===// 37 38// Load zero. 39let isAsCheapAsAMove = 1, isMoveImm = 1 in { 40 def LZER : InherentRRE<"lzer", 0xB374, FP32, fpimm0>; 41 def LZDR : InherentRRE<"lzdr", 0xB375, FP64, fpimm0>; 42 def LZXR : InherentRRE<"lzxr", 0xB376, FP128, fpimm0>; 43} 44 45// Moves between two floating-point registers. 46def LER : UnaryRR <"ler", 0x38, null_frag, FP32, FP32>; 47def LDR : UnaryRR <"ldr", 0x28, null_frag, FP64, FP64>; 48def LXR : UnaryRRE<"lxr", 0xB365, null_frag, FP128, FP128>; 49 50// For z13 we prefer LDR over LER to avoid partial register dependencies. 51let isCodeGenOnly = 1 in 52 def LDR32 : UnaryRR<"ldr", 0x28, null_frag, FP32, FP32>; 53 54// Moves between two floating-point registers that also set the condition 55// codes. 56let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 57 defm LTEBR : LoadAndTestRRE<"ltebr", 0xB302, FP32>; 58 defm LTDBR : LoadAndTestRRE<"ltdbr", 0xB312, FP64>; 59 defm LTXBR : LoadAndTestRRE<"ltxbr", 0xB342, FP128>; 60} 61// Note that LTxBRCompare is not available if we have vector support, 62// since load-and-test instructions will partially clobber the target 63// (vector) register. 64let Predicates = [FeatureNoVector] in { 65 defm : CompareZeroFP<LTEBRCompare, FP32>; 66 defm : CompareZeroFP<LTDBRCompare, FP64>; 67 defm : CompareZeroFP<LTXBRCompare, FP128>; 68} 69 70// Use a normal load-and-test for compare against zero in case of 71// vector support (via a pseudo to simplify instruction selection). 72let Defs = [CC], usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { 73 def LTEBRCompare_VecPseudo : Pseudo<(outs), (ins FP32:$R1, FP32:$R2), []>; 74 def LTDBRCompare_VecPseudo : Pseudo<(outs), (ins FP64:$R1, FP64:$R2), []>; 75 def LTXBRCompare_VecPseudo : Pseudo<(outs), (ins FP128:$R1, FP128:$R2), []>; 76} 77let Predicates = [FeatureVector] in { 78 defm : CompareZeroFP<LTEBRCompare_VecPseudo, FP32>; 79 defm : CompareZeroFP<LTDBRCompare_VecPseudo, FP64>; 80} 81let Predicates = [FeatureVector, FeatureNoVectorEnhancements1] in 82 defm : CompareZeroFP<LTXBRCompare_VecPseudo, FP128>; 83 84// Moves between 64-bit integer and floating-point registers. 85def LGDR : UnaryRRE<"lgdr", 0xB3CD, bitconvert, GR64, FP64>; 86def LDGR : UnaryRRE<"ldgr", 0xB3C1, bitconvert, FP64, GR64>; 87 88// fcopysign with an FP32 result. 89let isCodeGenOnly = 1 in { 90 def CPSDRss : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP32, FP32, FP32>; 91 def CPSDRsd : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP32, FP32, FP64>; 92} 93 94// The sign of an FP128 is in the high register. 95let Predicates = [FeatureNoVectorEnhancements1] in 96 def : Pat<(fcopysign FP32:$src1, (f32 (fpround (f128 FP128:$src2)))), 97 (CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 98let Predicates = [FeatureVectorEnhancements1] in 99 def : Pat<(fcopysign FP32:$src1, (f32 (fpround (f128 VR128:$src2)))), 100 (CPSDRsd FP32:$src1, (EXTRACT_SUBREG VR128:$src2, subreg_h64))>; 101 102// fcopysign with an FP64 result. 103let isCodeGenOnly = 1 in 104 def CPSDRds : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP64, FP64, FP32>; 105def CPSDRdd : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP64, FP64, FP64>; 106 107// The sign of an FP128 is in the high register. 108let Predicates = [FeatureNoVectorEnhancements1] in 109 def : Pat<(fcopysign FP64:$src1, (f64 (fpround (f128 FP128:$src2)))), 110 (CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 111let Predicates = [FeatureVectorEnhancements1] in 112 def : Pat<(fcopysign FP64:$src1, (f64 (fpround (f128 VR128:$src2)))), 113 (CPSDRdd FP64:$src1, (EXTRACT_SUBREG VR128:$src2, subreg_h64))>; 114 115// fcopysign with an FP128 result. Use "upper" as the high half and leave 116// the low half as-is. 117class CopySign128<RegisterOperand cls, dag upper> 118 : Pat<(fcopysign FP128:$src1, cls:$src2), 119 (INSERT_SUBREG FP128:$src1, upper, subreg_h64)>; 120 121let Predicates = [FeatureNoVectorEnhancements1] in { 122 def : CopySign128<FP32, (CPSDRds (EXTRACT_SUBREG FP128:$src1, subreg_h64), 123 FP32:$src2)>; 124 def : CopySign128<FP64, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64), 125 FP64:$src2)>; 126 def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64), 127 (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 128} 129 130defm LoadStoreF32 : MVCLoadStore<load, f32, MVCSequence, 4>; 131defm LoadStoreF64 : MVCLoadStore<load, f64, MVCSequence, 8>; 132defm LoadStoreF128 : MVCLoadStore<load, f128, MVCSequence, 16>; 133 134//===----------------------------------------------------------------------===// 135// Load instructions 136//===----------------------------------------------------------------------===// 137 138let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in { 139 defm LE : UnaryRXPair<"le", 0x78, 0xED64, load, FP32, 4>; 140 defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64, 8>; 141 142 // For z13 we prefer LDE over LE to avoid partial register dependencies. 143 let isCodeGenOnly = 1 in 144 def LDE32 : UnaryRXE<"lde", 0xED24, null_frag, FP32, 4>; 145 146 // These instructions are split after register allocation, so we don't 147 // want a custom inserter. 148 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 149 def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src), 150 [(set FP128:$dst, (load bdxaddr20only128:$src))]>; 151 } 152} 153 154//===----------------------------------------------------------------------===// 155// Store instructions 156//===----------------------------------------------------------------------===// 157 158let SimpleBDXStore = 1, mayStore = 1 in { 159 defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32, 4>; 160 defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64, 8>; 161 162 // These instructions are split after register allocation, so we don't 163 // want a custom inserter. 164 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 165 def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst), 166 [(store FP128:$src, bdxaddr20only128:$dst)]>; 167 } 168} 169 170//===----------------------------------------------------------------------===// 171// Conversion instructions 172//===----------------------------------------------------------------------===// 173 174// Convert floating-point values to narrower representations, rounding 175// according to the current mode. The destination of LEXBR and LDXBR 176// is a 128-bit value, but only the first register of the pair is used. 177def LEDBR : UnaryRRE<"ledbr", 0xB344, fpround, FP32, FP64>; 178def LEXBR : UnaryRRE<"lexbr", 0xB346, null_frag, FP128, FP128>; 179def LDXBR : UnaryRRE<"ldxbr", 0xB345, null_frag, FP128, FP128>; 180 181def LEDBRA : TernaryRRFe<"ledbra", 0xB344, FP32, FP64>, 182 Requires<[FeatureFPExtension]>; 183def LEXBRA : TernaryRRFe<"lexbra", 0xB346, FP128, FP128>, 184 Requires<[FeatureFPExtension]>; 185def LDXBRA : TernaryRRFe<"ldxbra", 0xB345, FP128, FP128>, 186 Requires<[FeatureFPExtension]>; 187 188let Predicates = [FeatureNoVectorEnhancements1] in { 189 def : Pat<(f32 (fpround FP128:$src)), 190 (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_hh32)>; 191 def : Pat<(f64 (fpround FP128:$src)), 192 (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_h64)>; 193} 194 195// Extend register floating-point values to wider representations. 196def LDEBR : UnaryRRE<"ldebr", 0xB304, fpextend, FP64, FP32>; 197def LXEBR : UnaryRRE<"lxebr", 0xB306, null_frag, FP128, FP32>; 198def LXDBR : UnaryRRE<"lxdbr", 0xB305, null_frag, FP128, FP64>; 199let Predicates = [FeatureNoVectorEnhancements1] in { 200 def : Pat<(f128 (fpextend (f32 FP32:$src))), (LXEBR FP32:$src)>; 201 def : Pat<(f128 (fpextend (f64 FP64:$src))), (LXDBR FP64:$src)>; 202} 203 204// Extend memory floating-point values to wider representations. 205def LDEB : UnaryRXE<"ldeb", 0xED04, extloadf32, FP64, 4>; 206def LXEB : UnaryRXE<"lxeb", 0xED06, null_frag, FP128, 4>; 207def LXDB : UnaryRXE<"lxdb", 0xED05, null_frag, FP128, 8>; 208let Predicates = [FeatureNoVectorEnhancements1] in { 209 def : Pat<(f128 (extloadf32 bdxaddr12only:$src)), 210 (LXEB bdxaddr12only:$src)>; 211 def : Pat<(f128 (extloadf64 bdxaddr12only:$src)), 212 (LXDB bdxaddr12only:$src)>; 213} 214 215// Convert a signed integer register value to a floating-point one. 216def CEFBR : UnaryRRE<"cefbr", 0xB394, sint_to_fp, FP32, GR32>; 217def CDFBR : UnaryRRE<"cdfbr", 0xB395, sint_to_fp, FP64, GR32>; 218def CXFBR : UnaryRRE<"cxfbr", 0xB396, sint_to_fp, FP128, GR32>; 219 220def CEGBR : UnaryRRE<"cegbr", 0xB3A4, sint_to_fp, FP32, GR64>; 221def CDGBR : UnaryRRE<"cdgbr", 0xB3A5, sint_to_fp, FP64, GR64>; 222def CXGBR : UnaryRRE<"cxgbr", 0xB3A6, sint_to_fp, FP128, GR64>; 223 224// The FP extension feature provides versions of the above that allow 225// specifying rounding mode and inexact-exception suppression flags. 226let Predicates = [FeatureFPExtension] in { 227 def CEFBRA : TernaryRRFe<"cefbra", 0xB394, FP32, GR32>; 228 def CDFBRA : TernaryRRFe<"cdfbra", 0xB395, FP64, GR32>; 229 def CXFBRA : TernaryRRFe<"cxfbra", 0xB396, FP128, GR32>; 230 231 def CEGBRA : TernaryRRFe<"cegbra", 0xB3A4, FP32, GR64>; 232 def CDGBRA : TernaryRRFe<"cdgbra", 0xB3A5, FP64, GR64>; 233 def CXGBRA : TernaryRRFe<"cxgbra", 0xB3A6, FP128, GR64>; 234} 235 236// Convert am unsigned integer register value to a floating-point one. 237let Predicates = [FeatureFPExtension] in { 238 def CELFBR : TernaryRRFe<"celfbr", 0xB390, FP32, GR32>; 239 def CDLFBR : TernaryRRFe<"cdlfbr", 0xB391, FP64, GR32>; 240 def CXLFBR : TernaryRRFe<"cxlfbr", 0xB392, FP128, GR32>; 241 242 def CELGBR : TernaryRRFe<"celgbr", 0xB3A0, FP32, GR64>; 243 def CDLGBR : TernaryRRFe<"cdlgbr", 0xB3A1, FP64, GR64>; 244 def CXLGBR : TernaryRRFe<"cxlgbr", 0xB3A2, FP128, GR64>; 245 246 def : Pat<(f32 (uint_to_fp GR32:$src)), (CELFBR 0, GR32:$src, 0)>; 247 def : Pat<(f64 (uint_to_fp GR32:$src)), (CDLFBR 0, GR32:$src, 0)>; 248 def : Pat<(f128 (uint_to_fp GR32:$src)), (CXLFBR 0, GR32:$src, 0)>; 249 250 def : Pat<(f32 (uint_to_fp GR64:$src)), (CELGBR 0, GR64:$src, 0)>; 251 def : Pat<(f64 (uint_to_fp GR64:$src)), (CDLGBR 0, GR64:$src, 0)>; 252 def : Pat<(f128 (uint_to_fp GR64:$src)), (CXLGBR 0, GR64:$src, 0)>; 253} 254 255// Convert a floating-point register value to a signed integer value, 256// with the second operand (modifier M3) specifying the rounding mode. 257let Defs = [CC] in { 258 def CFEBR : BinaryRRFe<"cfebr", 0xB398, GR32, FP32>; 259 def CFDBR : BinaryRRFe<"cfdbr", 0xB399, GR32, FP64>; 260 def CFXBR : BinaryRRFe<"cfxbr", 0xB39A, GR32, FP128>; 261 262 def CGEBR : BinaryRRFe<"cgebr", 0xB3A8, GR64, FP32>; 263 def CGDBR : BinaryRRFe<"cgdbr", 0xB3A9, GR64, FP64>; 264 def CGXBR : BinaryRRFe<"cgxbr", 0xB3AA, GR64, FP128>; 265} 266 267// fp_to_sint always rounds towards zero, which is modifier value 5. 268def : Pat<(i32 (fp_to_sint FP32:$src)), (CFEBR 5, FP32:$src)>; 269def : Pat<(i32 (fp_to_sint FP64:$src)), (CFDBR 5, FP64:$src)>; 270def : Pat<(i32 (fp_to_sint FP128:$src)), (CFXBR 5, FP128:$src)>; 271 272def : Pat<(i64 (fp_to_sint FP32:$src)), (CGEBR 5, FP32:$src)>; 273def : Pat<(i64 (fp_to_sint FP64:$src)), (CGDBR 5, FP64:$src)>; 274def : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>; 275 276// The FP extension feature provides versions of the above that allow 277// also specifying the inexact-exception suppression flag. 278let Predicates = [FeatureFPExtension], Defs = [CC] in { 279 def CFEBRA : TernaryRRFe<"cfebra", 0xB398, GR32, FP32>; 280 def CFDBRA : TernaryRRFe<"cfdbra", 0xB399, GR32, FP64>; 281 def CFXBRA : TernaryRRFe<"cfxbra", 0xB39A, GR32, FP128>; 282 283 def CGEBRA : TernaryRRFe<"cgebra", 0xB3A8, GR64, FP32>; 284 def CGDBRA : TernaryRRFe<"cgdbra", 0xB3A9, GR64, FP64>; 285 def CGXBRA : TernaryRRFe<"cgxbra", 0xB3AA, GR64, FP128>; 286} 287 288// Convert a floating-point register value to an unsigned integer value. 289let Predicates = [FeatureFPExtension] in { 290 let Defs = [CC] in { 291 def CLFEBR : TernaryRRFe<"clfebr", 0xB39C, GR32, FP32>; 292 def CLFDBR : TernaryRRFe<"clfdbr", 0xB39D, GR32, FP64>; 293 def CLFXBR : TernaryRRFe<"clfxbr", 0xB39E, GR32, FP128>; 294 295 def CLGEBR : TernaryRRFe<"clgebr", 0xB3AC, GR64, FP32>; 296 def CLGDBR : TernaryRRFe<"clgdbr", 0xB3AD, GR64, FP64>; 297 def CLGXBR : TernaryRRFe<"clgxbr", 0xB3AE, GR64, FP128>; 298 } 299 300 def : Pat<(i32 (fp_to_uint FP32:$src)), (CLFEBR 5, FP32:$src, 0)>; 301 def : Pat<(i32 (fp_to_uint FP64:$src)), (CLFDBR 5, FP64:$src, 0)>; 302 def : Pat<(i32 (fp_to_uint FP128:$src)), (CLFXBR 5, FP128:$src, 0)>; 303 304 def : Pat<(i64 (fp_to_uint FP32:$src)), (CLGEBR 5, FP32:$src, 0)>; 305 def : Pat<(i64 (fp_to_uint FP64:$src)), (CLGDBR 5, FP64:$src, 0)>; 306 def : Pat<(i64 (fp_to_uint FP128:$src)), (CLGXBR 5, FP128:$src, 0)>; 307} 308 309 310//===----------------------------------------------------------------------===// 311// Unary arithmetic 312//===----------------------------------------------------------------------===// 313 314// We prefer generic instructions during isel, because they do not 315// clobber CC and therefore give the scheduler more freedom. In cases 316// the CC is actually useful, the SystemZElimCompare pass will try to 317// convert generic instructions into opcodes that also set CC. Note 318// that lcdf / lpdf / lndf only affect the sign bit, and can therefore 319// be used with fp32 as well. This could be done for fp128, in which 320// case the operands would have to be tied. 321 322// Negation (Load Complement). 323let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 324 def LCEBR : UnaryRRE<"lcebr", 0xB303, null_frag, FP32, FP32>; 325 def LCDBR : UnaryRRE<"lcdbr", 0xB313, null_frag, FP64, FP64>; 326 def LCXBR : UnaryRRE<"lcxbr", 0xB343, fneg, FP128, FP128>; 327} 328// Generic form, which does not set CC. 329def LCDFR : UnaryRRE<"lcdfr", 0xB373, fneg, FP64, FP64>; 330let isCodeGenOnly = 1 in 331 def LCDFR_32 : UnaryRRE<"lcdfr", 0xB373, fneg, FP32, FP32>; 332 333// Absolute value (Load Positive). 334let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 335 def LPEBR : UnaryRRE<"lpebr", 0xB300, null_frag, FP32, FP32>; 336 def LPDBR : UnaryRRE<"lpdbr", 0xB310, null_frag, FP64, FP64>; 337 def LPXBR : UnaryRRE<"lpxbr", 0xB340, fabs, FP128, FP128>; 338} 339// Generic form, which does not set CC. 340def LPDFR : UnaryRRE<"lpdfr", 0xB370, fabs, FP64, FP64>; 341let isCodeGenOnly = 1 in 342 def LPDFR_32 : UnaryRRE<"lpdfr", 0xB370, fabs, FP32, FP32>; 343 344// Negative absolute value (Load Negative). 345let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 346 def LNEBR : UnaryRRE<"lnebr", 0xB301, null_frag, FP32, FP32>; 347 def LNDBR : UnaryRRE<"lndbr", 0xB311, null_frag, FP64, FP64>; 348 def LNXBR : UnaryRRE<"lnxbr", 0xB341, fnabs, FP128, FP128>; 349} 350// Generic form, which does not set CC. 351def LNDFR : UnaryRRE<"lndfr", 0xB371, fnabs, FP64, FP64>; 352let isCodeGenOnly = 1 in 353 def LNDFR_32 : UnaryRRE<"lndfr", 0xB371, fnabs, FP32, FP32>; 354 355// Square root. 356def SQEBR : UnaryRRE<"sqebr", 0xB314, fsqrt, FP32, FP32>; 357def SQDBR : UnaryRRE<"sqdbr", 0xB315, fsqrt, FP64, FP64>; 358def SQXBR : UnaryRRE<"sqxbr", 0xB316, fsqrt, FP128, FP128>; 359 360def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<fsqrt>, FP32, 4>; 361def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64, 8>; 362 363// Round to an integer, with the second operand (modifier M3) specifying 364// the rounding mode. These forms always check for inexact conditions. 365def FIEBR : BinaryRRFe<"fiebr", 0xB357, FP32, FP32>; 366def FIDBR : BinaryRRFe<"fidbr", 0xB35F, FP64, FP64>; 367def FIXBR : BinaryRRFe<"fixbr", 0xB347, FP128, FP128>; 368 369// frint rounds according to the current mode (modifier 0) and detects 370// inexact conditions. 371def : Pat<(frint FP32:$src), (FIEBR 0, FP32:$src)>; 372def : Pat<(frint FP64:$src), (FIDBR 0, FP64:$src)>; 373def : Pat<(frint FP128:$src), (FIXBR 0, FP128:$src)>; 374 375let Predicates = [FeatureFPExtension] in { 376 // Extended forms of the FIxBR instructions. M4 can be set to 4 377 // to suppress detection of inexact conditions. 378 def FIEBRA : TernaryRRFe<"fiebra", 0xB357, FP32, FP32>; 379 def FIDBRA : TernaryRRFe<"fidbra", 0xB35F, FP64, FP64>; 380 def FIXBRA : TernaryRRFe<"fixbra", 0xB347, FP128, FP128>; 381 382 // fnearbyint is like frint but does not detect inexact conditions. 383 def : Pat<(fnearbyint FP32:$src), (FIEBRA 0, FP32:$src, 4)>; 384 def : Pat<(fnearbyint FP64:$src), (FIDBRA 0, FP64:$src, 4)>; 385 def : Pat<(fnearbyint FP128:$src), (FIXBRA 0, FP128:$src, 4)>; 386 387 // floor is no longer allowed to raise an inexact condition, 388 // so restrict it to the cases where the condition can be suppressed. 389 // Mode 7 is round towards -inf. 390 def : Pat<(ffloor FP32:$src), (FIEBRA 7, FP32:$src, 4)>; 391 def : Pat<(ffloor FP64:$src), (FIDBRA 7, FP64:$src, 4)>; 392 def : Pat<(ffloor FP128:$src), (FIXBRA 7, FP128:$src, 4)>; 393 394 // Same idea for ceil, where mode 6 is round towards +inf. 395 def : Pat<(fceil FP32:$src), (FIEBRA 6, FP32:$src, 4)>; 396 def : Pat<(fceil FP64:$src), (FIDBRA 6, FP64:$src, 4)>; 397 def : Pat<(fceil FP128:$src), (FIXBRA 6, FP128:$src, 4)>; 398 399 // Same idea for trunc, where mode 5 is round towards zero. 400 def : Pat<(ftrunc FP32:$src), (FIEBRA 5, FP32:$src, 4)>; 401 def : Pat<(ftrunc FP64:$src), (FIDBRA 5, FP64:$src, 4)>; 402 def : Pat<(ftrunc FP128:$src), (FIXBRA 5, FP128:$src, 4)>; 403 404 // Same idea for round, where mode 1 is round towards nearest with 405 // ties away from zero. 406 def : Pat<(fround FP32:$src), (FIEBRA 1, FP32:$src, 4)>; 407 def : Pat<(fround FP64:$src), (FIDBRA 1, FP64:$src, 4)>; 408 def : Pat<(fround FP128:$src), (FIXBRA 1, FP128:$src, 4)>; 409} 410 411//===----------------------------------------------------------------------===// 412// Binary arithmetic 413//===----------------------------------------------------------------------===// 414 415// Addition. 416let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 417 let isCommutable = 1 in { 418 def AEBR : BinaryRRE<"aebr", 0xB30A, fadd, FP32, FP32>; 419 def ADBR : BinaryRRE<"adbr", 0xB31A, fadd, FP64, FP64>; 420 def AXBR : BinaryRRE<"axbr", 0xB34A, fadd, FP128, FP128>; 421 } 422 def AEB : BinaryRXE<"aeb", 0xED0A, fadd, FP32, load, 4>; 423 def ADB : BinaryRXE<"adb", 0xED1A, fadd, FP64, load, 8>; 424} 425 426// Subtraction. 427let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 428 def SEBR : BinaryRRE<"sebr", 0xB30B, fsub, FP32, FP32>; 429 def SDBR : BinaryRRE<"sdbr", 0xB31B, fsub, FP64, FP64>; 430 def SXBR : BinaryRRE<"sxbr", 0xB34B, fsub, FP128, FP128>; 431 432 def SEB : BinaryRXE<"seb", 0xED0B, fsub, FP32, load, 4>; 433 def SDB : BinaryRXE<"sdb", 0xED1B, fsub, FP64, load, 8>; 434} 435 436// Multiplication. 437let isCommutable = 1 in { 438 def MEEBR : BinaryRRE<"meebr", 0xB317, fmul, FP32, FP32>; 439 def MDBR : BinaryRRE<"mdbr", 0xB31C, fmul, FP64, FP64>; 440 def MXBR : BinaryRRE<"mxbr", 0xB34C, fmul, FP128, FP128>; 441} 442def MEEB : BinaryRXE<"meeb", 0xED17, fmul, FP32, load, 4>; 443def MDB : BinaryRXE<"mdb", 0xED1C, fmul, FP64, load, 8>; 444 445// f64 multiplication of two FP32 registers. 446def MDEBR : BinaryRRE<"mdebr", 0xB30C, null_frag, FP64, FP32>; 447def : Pat<(fmul (f64 (fpextend FP32:$src1)), (f64 (fpextend FP32:$src2))), 448 (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 449 FP32:$src1, subreg_h32), FP32:$src2)>; 450 451// f64 multiplication of an FP32 register and an f32 memory. 452def MDEB : BinaryRXE<"mdeb", 0xED0C, null_frag, FP64, load, 4>; 453def : Pat<(fmul (f64 (fpextend FP32:$src1)), 454 (f64 (extloadf32 bdxaddr12only:$addr))), 455 (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_h32), 456 bdxaddr12only:$addr)>; 457 458// f128 multiplication of two FP64 registers. 459def MXDBR : BinaryRRE<"mxdbr", 0xB307, null_frag, FP128, FP64>; 460let Predicates = [FeatureNoVectorEnhancements1] in 461 def : Pat<(fmul (f128 (fpextend FP64:$src1)), (f128 (fpextend FP64:$src2))), 462 (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)), 463 FP64:$src1, subreg_h64), FP64:$src2)>; 464 465// f128 multiplication of an FP64 register and an f64 memory. 466def MXDB : BinaryRXE<"mxdb", 0xED07, null_frag, FP128, load, 8>; 467let Predicates = [FeatureNoVectorEnhancements1] in 468 def : Pat<(fmul (f128 (fpextend FP64:$src1)), 469 (f128 (extloadf64 bdxaddr12only:$addr))), 470 (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_h64), 471 bdxaddr12only:$addr)>; 472 473// Fused multiply-add. 474def MAEBR : TernaryRRD<"maebr", 0xB30E, z_fma, FP32, FP32>; 475def MADBR : TernaryRRD<"madbr", 0xB31E, z_fma, FP64, FP64>; 476 477def MAEB : TernaryRXF<"maeb", 0xED0E, z_fma, FP32, FP32, load, 4>; 478def MADB : TernaryRXF<"madb", 0xED1E, z_fma, FP64, FP64, load, 8>; 479 480// Fused multiply-subtract. 481def MSEBR : TernaryRRD<"msebr", 0xB30F, z_fms, FP32, FP32>; 482def MSDBR : TernaryRRD<"msdbr", 0xB31F, z_fms, FP64, FP64>; 483 484def MSEB : TernaryRXF<"mseb", 0xED0F, z_fms, FP32, FP32, load, 4>; 485def MSDB : TernaryRXF<"msdb", 0xED1F, z_fms, FP64, FP64, load, 8>; 486 487// Division. 488def DEBR : BinaryRRE<"debr", 0xB30D, fdiv, FP32, FP32>; 489def DDBR : BinaryRRE<"ddbr", 0xB31D, fdiv, FP64, FP64>; 490def DXBR : BinaryRRE<"dxbr", 0xB34D, fdiv, FP128, FP128>; 491 492def DEB : BinaryRXE<"deb", 0xED0D, fdiv, FP32, load, 4>; 493def DDB : BinaryRXE<"ddb", 0xED1D, fdiv, FP64, load, 8>; 494 495// Divide to integer. 496let Defs = [CC] in { 497 def DIEBR : TernaryRRFb<"diebr", 0xB353, FP32, FP32, FP32>; 498 def DIDBR : TernaryRRFb<"didbr", 0xB35B, FP64, FP64, FP64>; 499} 500 501//===----------------------------------------------------------------------===// 502// Comparisons 503//===----------------------------------------------------------------------===// 504 505let Defs = [CC], CCValues = 0xF in { 506 def CEBR : CompareRRE<"cebr", 0xB309, z_fcmp, FP32, FP32>; 507 def CDBR : CompareRRE<"cdbr", 0xB319, z_fcmp, FP64, FP64>; 508 def CXBR : CompareRRE<"cxbr", 0xB349, z_fcmp, FP128, FP128>; 509 510 def CEB : CompareRXE<"ceb", 0xED09, z_fcmp, FP32, load, 4>; 511 def CDB : CompareRXE<"cdb", 0xED19, z_fcmp, FP64, load, 8>; 512 513 def KEBR : CompareRRE<"kebr", 0xB308, null_frag, FP32, FP32>; 514 def KDBR : CompareRRE<"kdbr", 0xB318, null_frag, FP64, FP64>; 515 def KXBR : CompareRRE<"kxbr", 0xB348, null_frag, FP128, FP128>; 516 517 def KEB : CompareRXE<"keb", 0xED08, null_frag, FP32, load, 4>; 518 def KDB : CompareRXE<"kdb", 0xED18, null_frag, FP64, load, 8>; 519} 520 521// Test Data Class. 522let Defs = [CC], CCValues = 0xC in { 523 def TCEB : TestRXE<"tceb", 0xED10, z_tdc, FP32>; 524 def TCDB : TestRXE<"tcdb", 0xED11, z_tdc, FP64>; 525 def TCXB : TestRXE<"tcxb", 0xED12, z_tdc, FP128>; 526} 527 528//===----------------------------------------------------------------------===// 529// Floating-point control register instructions 530//===----------------------------------------------------------------------===// 531 532let hasSideEffects = 1 in { 533 let mayLoad = 1, mayStore = 1 in { 534 // TODO: EFPC and SFPC do not touch memory at all 535 def EFPC : InherentRRE<"efpc", 0xB38C, GR32, int_s390_efpc>; 536 def STFPC : StoreInherentS<"stfpc", 0xB29C, storei<int_s390_efpc>, 4>; 537 538 def SFPC : SideEffectUnaryRRE<"sfpc", 0xB384, GR32, int_s390_sfpc>; 539 def LFPC : SideEffectUnaryS<"lfpc", 0xB29D, loadu<int_s390_sfpc>, 4>; 540 } 541 542 def SFASR : SideEffectUnaryRRE<"sfasr", 0xB385, GR32, null_frag>; 543 def LFAS : SideEffectUnaryS<"lfas", 0xB2BD, null_frag, 4>; 544 545 def SRNMB : SideEffectAddressS<"srnmb", 0xB2B8, null_frag, shift12only>, 546 Requires<[FeatureFPExtension]>; 547 def SRNM : SideEffectAddressS<"srnm", 0xB299, null_frag, shift12only>; 548 def SRNMT : SideEffectAddressS<"srnmt", 0xB2B9, null_frag, shift12only>; 549} 550 551//===----------------------------------------------------------------------===// 552// Peepholes 553//===----------------------------------------------------------------------===// 554 555def : Pat<(f32 fpimmneg0), (LCDFR_32 (LZER))>; 556def : Pat<(f64 fpimmneg0), (LCDFR (LZDR))>; 557def : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>; 558