1//===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the X86 Register file, defining the registers themselves, 11// aliases between the registers, and the register classes built out of the 12// registers. 13// 14//===----------------------------------------------------------------------===// 15 16class X86Reg<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> { 17 let Namespace = "X86"; 18 let HWEncoding = Enc; 19 let SubRegs = subregs; 20} 21 22// Subregister indices. 23let Namespace = "X86" in { 24 def sub_8bit : SubRegIndex<8>; 25 def sub_8bit_hi : SubRegIndex<8, 8>; 26 def sub_8bit_hi_phony : SubRegIndex<8, 8>; 27 def sub_16bit : SubRegIndex<16>; 28 def sub_16bit_hi : SubRegIndex<16, 16>; 29 def sub_32bit : SubRegIndex<32>; 30 def sub_xmm : SubRegIndex<128>; 31 def sub_ymm : SubRegIndex<256>; 32} 33 34//===----------------------------------------------------------------------===// 35// Register definitions... 36// 37 38// In the register alias definitions below, we define which registers alias 39// which others. We only specify which registers the small registers alias, 40// because the register file generator is smart enough to figure out that 41// AL aliases AX if we tell it that AX aliased AL (for example). 42 43// Dwarf numbering is different for 32-bit and 64-bit, and there are 44// variations by target as well. Currently the first entry is for X86-64, 45// second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux 46// and debug information on X86-32/Darwin) 47 48// 8-bit registers 49// Low registers 50def AL : X86Reg<"al", 0>; 51def DL : X86Reg<"dl", 2>; 52def CL : X86Reg<"cl", 1>; 53def BL : X86Reg<"bl", 3>; 54 55// High registers. On x86-64, these cannot be used in any instruction 56// with a REX prefix. 57def AH : X86Reg<"ah", 4>; 58def DH : X86Reg<"dh", 6>; 59def CH : X86Reg<"ch", 5>; 60def BH : X86Reg<"bh", 7>; 61 62// X86-64 only, requires REX. 63let CostPerUse = 1 in { 64def SIL : X86Reg<"sil", 6>; 65def DIL : X86Reg<"dil", 7>; 66def BPL : X86Reg<"bpl", 5>; 67def SPL : X86Reg<"spl", 4>; 68def R8B : X86Reg<"r8b", 8>; 69def R9B : X86Reg<"r9b", 9>; 70def R10B : X86Reg<"r10b", 10>; 71def R11B : X86Reg<"r11b", 11>; 72def R12B : X86Reg<"r12b", 12>; 73def R13B : X86Reg<"r13b", 13>; 74def R14B : X86Reg<"r14b", 14>; 75def R15B : X86Reg<"r15b", 15>; 76} 77 78let isArtificial = 1 in { 79// High byte of the low 16 bits of the super-register: 80def SIH : X86Reg<"", -1>; 81def DIH : X86Reg<"", -1>; 82def BPH : X86Reg<"", -1>; 83def SPH : X86Reg<"", -1>; 84def R8BH : X86Reg<"", -1>; 85def R9BH : X86Reg<"", -1>; 86def R10BH : X86Reg<"", -1>; 87def R11BH : X86Reg<"", -1>; 88def R12BH : X86Reg<"", -1>; 89def R13BH : X86Reg<"", -1>; 90def R14BH : X86Reg<"", -1>; 91def R15BH : X86Reg<"", -1>; 92// High word of the low 32 bits of the super-register: 93def HAX : X86Reg<"", -1>; 94def HDX : X86Reg<"", -1>; 95def HCX : X86Reg<"", -1>; 96def HBX : X86Reg<"", -1>; 97def HSI : X86Reg<"", -1>; 98def HDI : X86Reg<"", -1>; 99def HBP : X86Reg<"", -1>; 100def HSP : X86Reg<"", -1>; 101def HIP : X86Reg<"", -1>; 102def R8WH : X86Reg<"", -1>; 103def R9WH : X86Reg<"", -1>; 104def R10WH : X86Reg<"", -1>; 105def R11WH : X86Reg<"", -1>; 106def R12WH : X86Reg<"", -1>; 107def R13WH : X86Reg<"", -1>; 108def R14WH : X86Reg<"", -1>; 109def R15WH : X86Reg<"", -1>; 110} 111 112// 16-bit registers 113let SubRegIndices = [sub_8bit, sub_8bit_hi], CoveredBySubRegs = 1 in { 114def AX : X86Reg<"ax", 0, [AL,AH]>; 115def DX : X86Reg<"dx", 2, [DL,DH]>; 116def CX : X86Reg<"cx", 1, [CL,CH]>; 117def BX : X86Reg<"bx", 3, [BL,BH]>; 118} 119let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CoveredBySubRegs = 1 in { 120def SI : X86Reg<"si", 6, [SIL,SIH]>; 121def DI : X86Reg<"di", 7, [DIL,DIH]>; 122def BP : X86Reg<"bp", 5, [BPL,BPH]>; 123def SP : X86Reg<"sp", 4, [SPL,SPH]>; 124} 125def IP : X86Reg<"ip", 0>; 126 127// X86-64 only, requires REX. 128let SubRegIndices = [sub_8bit, sub_8bit_hi_phony], CostPerUse = 1, 129 CoveredBySubRegs = 1 in { 130def R8W : X86Reg<"r8w", 8, [R8B,R8BH]>; 131def R9W : X86Reg<"r9w", 9, [R9B,R9BH]>; 132def R10W : X86Reg<"r10w", 10, [R10B,R10BH]>; 133def R11W : X86Reg<"r11w", 11, [R11B,R11BH]>; 134def R12W : X86Reg<"r12w", 12, [R12B,R12BH]>; 135def R13W : X86Reg<"r13w", 13, [R13B,R13BH]>; 136def R14W : X86Reg<"r14w", 14, [R14B,R14BH]>; 137def R15W : X86Reg<"r15w", 15, [R15B,R15BH]>; 138} 139 140// 32-bit registers 141let SubRegIndices = [sub_16bit, sub_16bit_hi], CoveredBySubRegs = 1 in { 142def EAX : X86Reg<"eax", 0, [AX, HAX]>, DwarfRegNum<[-2, 0, 0]>; 143def EDX : X86Reg<"edx", 2, [DX, HDX]>, DwarfRegNum<[-2, 2, 2]>; 144def ECX : X86Reg<"ecx", 1, [CX, HCX]>, DwarfRegNum<[-2, 1, 1]>; 145def EBX : X86Reg<"ebx", 3, [BX, HBX]>, DwarfRegNum<[-2, 3, 3]>; 146def ESI : X86Reg<"esi", 6, [SI, HSI]>, DwarfRegNum<[-2, 6, 6]>; 147def EDI : X86Reg<"edi", 7, [DI, HDI]>, DwarfRegNum<[-2, 7, 7]>; 148def EBP : X86Reg<"ebp", 5, [BP, HBP]>, DwarfRegNum<[-2, 4, 5]>; 149def ESP : X86Reg<"esp", 4, [SP, HSP]>, DwarfRegNum<[-2, 5, 4]>; 150def EIP : X86Reg<"eip", 0, [IP, HIP]>, DwarfRegNum<[-2, 8, 8]>; 151} 152 153// X86-64 only, requires REX 154let SubRegIndices = [sub_16bit, sub_16bit_hi], CostPerUse = 1, 155 CoveredBySubRegs = 1 in { 156def R8D : X86Reg<"r8d", 8, [R8W,R8WH]>; 157def R9D : X86Reg<"r9d", 9, [R9W,R9WH]>; 158def R10D : X86Reg<"r10d", 10, [R10W,R10WH]>; 159def R11D : X86Reg<"r11d", 11, [R11W,R11WH]>; 160def R12D : X86Reg<"r12d", 12, [R12W,R12WH]>; 161def R13D : X86Reg<"r13d", 13, [R13W,R13WH]>; 162def R14D : X86Reg<"r14d", 14, [R14W,R14WH]>; 163def R15D : X86Reg<"r15d", 15, [R15W,R15WH]>; 164} 165 166// 64-bit registers, X86-64 only 167let SubRegIndices = [sub_32bit] in { 168def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>; 169def RDX : X86Reg<"rdx", 2, [EDX]>, DwarfRegNum<[1, -2, -2]>; 170def RCX : X86Reg<"rcx", 1, [ECX]>, DwarfRegNum<[2, -2, -2]>; 171def RBX : X86Reg<"rbx", 3, [EBX]>, DwarfRegNum<[3, -2, -2]>; 172def RSI : X86Reg<"rsi", 6, [ESI]>, DwarfRegNum<[4, -2, -2]>; 173def RDI : X86Reg<"rdi", 7, [EDI]>, DwarfRegNum<[5, -2, -2]>; 174def RBP : X86Reg<"rbp", 5, [EBP]>, DwarfRegNum<[6, -2, -2]>; 175def RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>; 176 177// These also require REX. 178let CostPerUse = 1 in { 179def R8 : X86Reg<"r8", 8, [R8D]>, DwarfRegNum<[ 8, -2, -2]>; 180def R9 : X86Reg<"r9", 9, [R9D]>, DwarfRegNum<[ 9, -2, -2]>; 181def R10 : X86Reg<"r10", 10, [R10D]>, DwarfRegNum<[10, -2, -2]>; 182def R11 : X86Reg<"r11", 11, [R11D]>, DwarfRegNum<[11, -2, -2]>; 183def R12 : X86Reg<"r12", 12, [R12D]>, DwarfRegNum<[12, -2, -2]>; 184def R13 : X86Reg<"r13", 13, [R13D]>, DwarfRegNum<[13, -2, -2]>; 185def R14 : X86Reg<"r14", 14, [R14D]>, DwarfRegNum<[14, -2, -2]>; 186def R15 : X86Reg<"r15", 15, [R15D]>, DwarfRegNum<[15, -2, -2]>; 187def RIP : X86Reg<"rip", 0, [EIP]>, DwarfRegNum<[16, -2, -2]>; 188}} 189 190// MMX Registers. These are actually aliased to ST0 .. ST7 191def MM0 : X86Reg<"mm0", 0>, DwarfRegNum<[41, 29, 29]>; 192def MM1 : X86Reg<"mm1", 1>, DwarfRegNum<[42, 30, 30]>; 193def MM2 : X86Reg<"mm2", 2>, DwarfRegNum<[43, 31, 31]>; 194def MM3 : X86Reg<"mm3", 3>, DwarfRegNum<[44, 32, 32]>; 195def MM4 : X86Reg<"mm4", 4>, DwarfRegNum<[45, 33, 33]>; 196def MM5 : X86Reg<"mm5", 5>, DwarfRegNum<[46, 34, 34]>; 197def MM6 : X86Reg<"mm6", 6>, DwarfRegNum<[47, 35, 35]>; 198def MM7 : X86Reg<"mm7", 7>, DwarfRegNum<[48, 36, 36]>; 199 200// Pseudo Floating Point registers 201def FP0 : X86Reg<"fp0", 0>; 202def FP1 : X86Reg<"fp1", 0>; 203def FP2 : X86Reg<"fp2", 0>; 204def FP3 : X86Reg<"fp3", 0>; 205def FP4 : X86Reg<"fp4", 0>; 206def FP5 : X86Reg<"fp5", 0>; 207def FP6 : X86Reg<"fp6", 0>; 208def FP7 : X86Reg<"fp7", 0>; 209 210// XMM Registers, used by the various SSE instruction set extensions. 211def XMM0: X86Reg<"xmm0", 0>, DwarfRegNum<[17, 21, 21]>; 212def XMM1: X86Reg<"xmm1", 1>, DwarfRegNum<[18, 22, 22]>; 213def XMM2: X86Reg<"xmm2", 2>, DwarfRegNum<[19, 23, 23]>; 214def XMM3: X86Reg<"xmm3", 3>, DwarfRegNum<[20, 24, 24]>; 215def XMM4: X86Reg<"xmm4", 4>, DwarfRegNum<[21, 25, 25]>; 216def XMM5: X86Reg<"xmm5", 5>, DwarfRegNum<[22, 26, 26]>; 217def XMM6: X86Reg<"xmm6", 6>, DwarfRegNum<[23, 27, 27]>; 218def XMM7: X86Reg<"xmm7", 7>, DwarfRegNum<[24, 28, 28]>; 219 220// X86-64 only 221let CostPerUse = 1 in { 222def XMM8: X86Reg<"xmm8", 8>, DwarfRegNum<[25, -2, -2]>; 223def XMM9: X86Reg<"xmm9", 9>, DwarfRegNum<[26, -2, -2]>; 224def XMM10: X86Reg<"xmm10", 10>, DwarfRegNum<[27, -2, -2]>; 225def XMM11: X86Reg<"xmm11", 11>, DwarfRegNum<[28, -2, -2]>; 226def XMM12: X86Reg<"xmm12", 12>, DwarfRegNum<[29, -2, -2]>; 227def XMM13: X86Reg<"xmm13", 13>, DwarfRegNum<[30, -2, -2]>; 228def XMM14: X86Reg<"xmm14", 14>, DwarfRegNum<[31, -2, -2]>; 229def XMM15: X86Reg<"xmm15", 15>, DwarfRegNum<[32, -2, -2]>; 230 231def XMM16: X86Reg<"xmm16", 16>, DwarfRegNum<[67, -2, -2]>; 232def XMM17: X86Reg<"xmm17", 17>, DwarfRegNum<[68, -2, -2]>; 233def XMM18: X86Reg<"xmm18", 18>, DwarfRegNum<[69, -2, -2]>; 234def XMM19: X86Reg<"xmm19", 19>, DwarfRegNum<[70, -2, -2]>; 235def XMM20: X86Reg<"xmm20", 20>, DwarfRegNum<[71, -2, -2]>; 236def XMM21: X86Reg<"xmm21", 21>, DwarfRegNum<[72, -2, -2]>; 237def XMM22: X86Reg<"xmm22", 22>, DwarfRegNum<[73, -2, -2]>; 238def XMM23: X86Reg<"xmm23", 23>, DwarfRegNum<[74, -2, -2]>; 239def XMM24: X86Reg<"xmm24", 24>, DwarfRegNum<[75, -2, -2]>; 240def XMM25: X86Reg<"xmm25", 25>, DwarfRegNum<[76, -2, -2]>; 241def XMM26: X86Reg<"xmm26", 26>, DwarfRegNum<[77, -2, -2]>; 242def XMM27: X86Reg<"xmm27", 27>, DwarfRegNum<[78, -2, -2]>; 243def XMM28: X86Reg<"xmm28", 28>, DwarfRegNum<[79, -2, -2]>; 244def XMM29: X86Reg<"xmm29", 29>, DwarfRegNum<[80, -2, -2]>; 245def XMM30: X86Reg<"xmm30", 30>, DwarfRegNum<[81, -2, -2]>; 246def XMM31: X86Reg<"xmm31", 31>, DwarfRegNum<[82, -2, -2]>; 247 248} // CostPerUse 249 250// YMM0-15 registers, used by AVX instructions and 251// YMM16-31 registers, used by AVX-512 instructions. 252let SubRegIndices = [sub_xmm] in { 253 foreach Index = 0-31 in { 254 def YMM#Index : X86Reg<"ymm"#Index, Index, [!cast<X86Reg>("XMM"#Index)]>, 255 DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>; 256 } 257} 258 259// ZMM Registers, used by AVX-512 instructions. 260let SubRegIndices = [sub_ymm] in { 261 foreach Index = 0-31 in { 262 def ZMM#Index : X86Reg<"zmm"#Index, Index, [!cast<X86Reg>("YMM"#Index)]>, 263 DwarfRegAlias<!cast<X86Reg>("XMM"#Index)>; 264 } 265} 266 267// Mask Registers, used by AVX-512 instructions. 268def K0 : X86Reg<"k0", 0>, DwarfRegNum<[118, 93, 93]>; 269def K1 : X86Reg<"k1", 1>, DwarfRegNum<[119, 94, 94]>; 270def K2 : X86Reg<"k2", 2>, DwarfRegNum<[120, 95, 95]>; 271def K3 : X86Reg<"k3", 3>, DwarfRegNum<[121, 96, 96]>; 272def K4 : X86Reg<"k4", 4>, DwarfRegNum<[122, 97, 97]>; 273def K5 : X86Reg<"k5", 5>, DwarfRegNum<[123, 98, 98]>; 274def K6 : X86Reg<"k6", 6>, DwarfRegNum<[124, 99, 99]>; 275def K7 : X86Reg<"k7", 7>, DwarfRegNum<[125, 100, 100]>; 276 277// Floating point stack registers. These don't map one-to-one to the FP 278// pseudo registers, but we still mark them as aliasing FP registers. That 279// way both kinds can be live without exceeding the stack depth. ST registers 280// are only live around inline assembly. 281def ST0 : X86Reg<"st", 0>, DwarfRegNum<[33, 12, 11]>; 282def ST1 : X86Reg<"st(1)", 1>, DwarfRegNum<[34, 13, 12]>; 283def ST2 : X86Reg<"st(2)", 2>, DwarfRegNum<[35, 14, 13]>; 284def ST3 : X86Reg<"st(3)", 3>, DwarfRegNum<[36, 15, 14]>; 285def ST4 : X86Reg<"st(4)", 4>, DwarfRegNum<[37, 16, 15]>; 286def ST5 : X86Reg<"st(5)", 5>, DwarfRegNum<[38, 17, 16]>; 287def ST6 : X86Reg<"st(6)", 6>, DwarfRegNum<[39, 18, 17]>; 288def ST7 : X86Reg<"st(7)", 7>, DwarfRegNum<[40, 19, 18]>; 289 290// Floating-point status word 291def FPSW : X86Reg<"fpsr", 0>; 292 293// Floating-point control word 294def FPCW : X86Reg<"fpcr", 0>; 295 296// Status flags register. 297// 298// Note that some flags that are commonly thought of as part of the status 299// flags register are modeled separately. Typically this is due to instructions 300// reading and updating those flags independently of all the others. We don't 301// want to create false dependencies between these instructions and so we use 302// a separate register to model them. 303def EFLAGS : X86Reg<"flags", 0>; 304 305// The direction flag. 306def DF : X86Reg<"dirflag", 0>; 307 308 309// Segment registers 310def CS : X86Reg<"cs", 1>; 311def DS : X86Reg<"ds", 3>; 312def SS : X86Reg<"ss", 2>; 313def ES : X86Reg<"es", 0>; 314def FS : X86Reg<"fs", 4>; 315def GS : X86Reg<"gs", 5>; 316 317// Debug registers 318def DR0 : X86Reg<"dr0", 0>; 319def DR1 : X86Reg<"dr1", 1>; 320def DR2 : X86Reg<"dr2", 2>; 321def DR3 : X86Reg<"dr3", 3>; 322def DR4 : X86Reg<"dr4", 4>; 323def DR5 : X86Reg<"dr5", 5>; 324def DR6 : X86Reg<"dr6", 6>; 325def DR7 : X86Reg<"dr7", 7>; 326def DR8 : X86Reg<"dr8", 8>; 327def DR9 : X86Reg<"dr9", 9>; 328def DR10 : X86Reg<"dr10", 10>; 329def DR11 : X86Reg<"dr11", 11>; 330def DR12 : X86Reg<"dr12", 12>; 331def DR13 : X86Reg<"dr13", 13>; 332def DR14 : X86Reg<"dr14", 14>; 333def DR15 : X86Reg<"dr15", 15>; 334 335// Control registers 336def CR0 : X86Reg<"cr0", 0>; 337def CR1 : X86Reg<"cr1", 1>; 338def CR2 : X86Reg<"cr2", 2>; 339def CR3 : X86Reg<"cr3", 3>; 340def CR4 : X86Reg<"cr4", 4>; 341def CR5 : X86Reg<"cr5", 5>; 342def CR6 : X86Reg<"cr6", 6>; 343def CR7 : X86Reg<"cr7", 7>; 344def CR8 : X86Reg<"cr8", 8>; 345def CR9 : X86Reg<"cr9", 9>; 346def CR10 : X86Reg<"cr10", 10>; 347def CR11 : X86Reg<"cr11", 11>; 348def CR12 : X86Reg<"cr12", 12>; 349def CR13 : X86Reg<"cr13", 13>; 350def CR14 : X86Reg<"cr14", 14>; 351def CR15 : X86Reg<"cr15", 15>; 352 353// Pseudo index registers 354def EIZ : X86Reg<"eiz", 4>; 355def RIZ : X86Reg<"riz", 4>; 356 357// Bound registers, used in MPX instructions 358def BND0 : X86Reg<"bnd0", 0>; 359def BND1 : X86Reg<"bnd1", 1>; 360def BND2 : X86Reg<"bnd2", 2>; 361def BND3 : X86Reg<"bnd3", 3>; 362 363// CET registers - Shadow Stack Pointer 364def SSP : X86Reg<"ssp", 0>; 365 366//===----------------------------------------------------------------------===// 367// Register Class Definitions... now that we have all of the pieces, define the 368// top-level register classes. The order specified in the register list is 369// implicitly defined to be the register allocation order. 370// 371 372// List call-clobbered registers before callee-save registers. RBX, RBP, (and 373// R12, R13, R14, and R15 for X86-64) are callee-save registers. 374// In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and 375// R8B, ... R15B. 376// Allocate R12 and R13 last, as these require an extra byte when 377// encoded in x86_64 instructions. 378// FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in 379// 64-bit mode. The main complication is that they cannot be encoded in an 380// instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc. 381// require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d" 382// cannot be encoded. 383def GR8 : RegisterClass<"X86", [i8], 8, 384 (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL, 385 R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B)> { 386 let AltOrders = [(sub GR8, AH, BH, CH, DH)]; 387 let AltOrderSelect = [{ 388 return MF.getSubtarget<X86Subtarget>().is64Bit(); 389 }]; 390} 391 392let isAllocatable = 0 in 393def GRH8 : RegisterClass<"X86", [i8], 8, 394 (add SIH, DIH, BPH, SPH, R8BH, R9BH, R10BH, R11BH, 395 R12BH, R13BH, R14BH, R15BH)>; 396 397def GR16 : RegisterClass<"X86", [i16], 16, 398 (add AX, CX, DX, SI, DI, BX, BP, SP, 399 R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W)>; 400 401let isAllocatable = 0 in 402def GRH16 : RegisterClass<"X86", [i16], 16, 403 (add HAX, HCX, HDX, HSI, HDI, HBX, HBP, HSP, HIP, 404 R8WH, R9WH, R10WH, R11WH, R12WH, R13WH, R14WH, 405 R15WH)>; 406 407def GR32 : RegisterClass<"X86", [i32], 32, 408 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP, 409 R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D)>; 410 411// GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since 412// RIP isn't really a register and it can't be used anywhere except in an 413// address, but it doesn't cause trouble. 414// FIXME: it *does* cause trouble - CheckBaseRegAndIndexReg() has extra 415// tests because of the inclusion of RIP in this register class. 416def GR64 : RegisterClass<"X86", [i64], 64, 417 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, 418 RBX, R14, R15, R12, R13, RBP, RSP, RIP)>; 419 420// Segment registers for use by MOV instructions (and others) that have a 421// segment register as one operand. Always contain a 16-bit segment 422// descriptor. 423def SEGMENT_REG : RegisterClass<"X86", [i16], 16, (add CS, DS, SS, ES, FS, GS)>; 424 425// Debug registers. 426def DEBUG_REG : RegisterClass<"X86", [i32], 32, (sequence "DR%u", 0, 15)>; 427 428// Control registers. 429def CONTROL_REG : RegisterClass<"X86", [i64], 64, (sequence "CR%u", 0, 15)>; 430 431// GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of 432// GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d" 433// registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers 434// that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD, 435// and GR64_ABCD are classes for registers that support 8-bit h-register 436// operations. 437def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, (add AL, CL, DL, BL)>; 438def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>; 439def GR16_ABCD : RegisterClass<"X86", [i16], 16, (add AX, CX, DX, BX)>; 440def GR32_ABCD : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, EBX)>; 441def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>; 442def GR32_TC : RegisterClass<"X86", [i32], 32, (add EAX, ECX, EDX, ESP)>; 443def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI, 444 R8, R9, R11, RIP, RSP)>; 445def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, 446 R8, R9, R10, R11, 447 RIP, RSP)>; 448 449// GR8_NOREX - GR8 registers which do not require a REX prefix. 450def GR8_NOREX : RegisterClass<"X86", [i8], 8, 451 (add AL, CL, DL, AH, CH, DH, BL, BH)> { 452 let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)]; 453 let AltOrderSelect = [{ 454 return MF.getSubtarget<X86Subtarget>().is64Bit(); 455 }]; 456} 457// GR16_NOREX - GR16 registers which do not require a REX prefix. 458def GR16_NOREX : RegisterClass<"X86", [i16], 16, 459 (add AX, CX, DX, SI, DI, BX, BP, SP)>; 460// GR32_NOREX - GR32 registers which do not require a REX prefix. 461def GR32_NOREX : RegisterClass<"X86", [i32], 32, 462 (add EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP)>; 463// GR64_NOREX - GR64 registers which do not require a REX prefix. 464def GR64_NOREX : RegisterClass<"X86", [i64], 64, 465 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>; 466 467// GR32_NOSP - GR32 registers except ESP. 468def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>; 469 470// GR64_NOSP - GR64 registers except RSP (and RIP). 471def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>; 472 473// GR32_NOREX_NOSP - GR32 registers which do not require a REX prefix except 474// ESP. 475def GR32_NOREX_NOSP : RegisterClass<"X86", [i32], 32, 476 (and GR32_NOREX, GR32_NOSP)>; 477 478// GR64_NOREX_NOSP - GR64_NOREX registers except RSP. 479def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64, 480 (and GR64_NOREX, GR64_NOSP)>; 481 482// Register classes used for ABIs that use 32-bit address accesses, 483// while using the whole x84_64 ISA. 484 485// In such cases, it is fine to use RIP as we are sure the 32 high 486// bits are not set. We do not need variants for NOSP as RIP is not 487// allowed there. 488// RIP is not spilled anywhere for now, so stick to 32-bit alignment 489// to save on memory space. 490// FIXME: We could allow all 64bit registers, but we would need 491// something to check that the 32 high bits are not set, 492// which we do not have right now. 493def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 32, (add GR32, RIP)>; 494 495// When RBP is used as a base pointer in a 32-bit addresses environement, 496// this is also safe to use the full register to access addresses. 497// Since RBP will never be spilled, stick to a 32 alignment to save 498// on memory consumption. 499def LOW32_ADDR_ACCESS_RBP : RegisterClass<"X86", [i32], 32, 500 (add LOW32_ADDR_ACCESS, RBP)>; 501 502// A class to support the 'A' assembler constraint: [ER]AX then [ER]DX. 503def GR32_AD : RegisterClass<"X86", [i32], 32, (add EAX, EDX)>; 504def GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>; 505 506// Classes to support the 64-bit assembler constraint tied to a fixed 507// register in 32-bit mode. The second register is always the next in 508// the list. Wrap around causes an error. 509def GR32_DC : RegisterClass<"X86", [i32], 32, (add EDX, ECX)>; 510def GR32_CB : RegisterClass<"X86", [i32], 32, (add ECX, EBX)>; 511def GR32_BSI : RegisterClass<"X86", [i32], 32, (add EBX, ESI)>; 512def GR32_SIDI : RegisterClass<"X86", [i32], 32, (add ESI, EDI)>; 513def GR32_DIBP : RegisterClass<"X86", [i32], 32, (add EDI, EBP)>; 514def GR32_BPSP : RegisterClass<"X86", [i32], 32, (add EBP, ESP)>; 515 516// Scalar SSE2 floating point registers. 517def FR32 : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 15)>; 518 519def FR64 : RegisterClass<"X86", [f64], 64, (add FR32)>; 520 521 522// FIXME: This sets up the floating point register files as though they are f64 523// values, though they really are f80 values. This will cause us to spill 524// values as 64-bit quantities instead of 80-bit quantities, which is much much 525// faster on common hardware. In reality, this should be controlled by a 526// command line option or something. 527 528 529def RFP32 : RegisterClass<"X86",[f32], 32, (sequence "FP%u", 0, 6)>; 530def RFP64 : RegisterClass<"X86",[f64], 32, (add RFP32)>; 531def RFP80 : RegisterClass<"X86",[f80], 32, (add RFP32)>; 532 533// st(7) may be is not allocatable. 534def RFP80_7 : RegisterClass<"X86",[f80], 32, (add FP7)> { 535 let isAllocatable = 0; 536} 537 538// Floating point stack registers (these are not allocatable by the 539// register allocator - the floating point stackifier is responsible 540// for transforming FPn allocations to STn registers) 541def RST : RegisterClass<"X86", [f80, f64, f32], 32, (sequence "ST%u", 0, 7)> { 542 let isAllocatable = 0; 543} 544 545// Helper to allow %st to print as %st(0) when its encoded in the instruction. 546def RSTi : RegisterOperand<RST, "printSTiRegOperand">; 547 548// Generic vector registers: VR64 and VR128. 549// Ensure that float types are declared first - only float is legal on SSE1. 550def VR64: RegisterClass<"X86", [x86mmx], 64, (sequence "MM%u", 0, 7)>; 551def VR128 : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64, f128], 552 128, (add FR32)>; 553def VR256 : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64], 554 256, (sequence "YMM%u", 0, 15)>; 555 556// Special classes that help the assembly parser choose some alternate 557// instructions to favor 2-byte VEX encodings. 558def VR128L : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64, f128], 559 128, (sequence "XMM%u", 0, 7)>; 560def VR128H : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64, f128], 561 128, (sequence "XMM%u", 8, 15)>; 562def VR256L : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64], 563 256, (sequence "YMM%u", 0, 7)>; 564def VR256H : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64], 565 256, (sequence "YMM%u", 8, 15)>; 566 567// Status flags registers. 568def CCR : RegisterClass<"X86", [i32], 32, (add EFLAGS)> { 569 let CopyCost = -1; // Don't allow copying of status registers. 570 let isAllocatable = 0; 571} 572def FPCCR : RegisterClass<"X86", [i16], 16, (add FPSW)> { 573 let CopyCost = -1; // Don't allow copying of status registers. 574 let isAllocatable = 0; 575} 576def DFCCR : RegisterClass<"X86", [i32], 32, (add DF)> { 577 let CopyCost = -1; // Don't allow copying of status registers. 578 let isAllocatable = 0; 579} 580 581// AVX-512 vector/mask registers. 582def VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64], 583 512, (sequence "ZMM%u", 0, 31)>; 584 585// Scalar AVX-512 floating point registers. 586def FR32X : RegisterClass<"X86", [f32], 32, (sequence "XMM%u", 0, 31)>; 587 588def FR64X : RegisterClass<"X86", [f64], 64, (add FR32X)>; 589 590// Extended VR128 and VR256 for AVX-512 instructions 591def VR128X : RegisterClass<"X86", [v4f32, v2f64, v16i8, v8i16, v4i32, v2i64, f128], 592 128, (add FR32X)>; 593def VR256X : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64], 594 256, (sequence "YMM%u", 0, 31)>; 595 596// Mask registers 597def VK1 : RegisterClass<"X86", [v1i1], 16, (sequence "K%u", 0, 7)> {let Size = 16;} 598def VK2 : RegisterClass<"X86", [v2i1], 16, (add VK1)> {let Size = 16;} 599def VK4 : RegisterClass<"X86", [v4i1], 16, (add VK2)> {let Size = 16;} 600def VK8 : RegisterClass<"X86", [v8i1], 16, (add VK4)> {let Size = 16;} 601def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)> {let Size = 16;} 602def VK32 : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;} 603def VK64 : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let Size = 64;} 604 605def VK1WM : RegisterClass<"X86", [v1i1], 16, (sub VK1, K0)> {let Size = 16;} 606def VK2WM : RegisterClass<"X86", [v2i1], 16, (sub VK2, K0)> {let Size = 16;} 607def VK4WM : RegisterClass<"X86", [v4i1], 16, (sub VK4, K0)> {let Size = 16;} 608def VK8WM : RegisterClass<"X86", [v8i1], 16, (sub VK8, K0)> {let Size = 16;} 609def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)> {let Size = 16;} 610def VK32WM : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;} 611def VK64WM : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;} 612 613// Bound registers 614def BNDR : RegisterClass<"X86", [v2i64], 128, (sequence "BND%u", 0, 3)>; 615