1 //==- CodeGen/TargetRegisterInfo.h - Target Register Information -*- C++ -*-==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file describes an abstract interface used to get information about a 10 // target machines register file. This information is used for a variety of 11 // purposed, especially register allocation. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_CODEGEN_TARGETREGISTERINFO_H 16 #define LLVM_CODEGEN_TARGETREGISTERINFO_H 17 18 #include "llvm/ADT/ArrayRef.h" 19 #include "llvm/ADT/SmallVector.h" 20 #include "llvm/ADT/StringRef.h" 21 #include "llvm/ADT/iterator_range.h" 22 #include "llvm/CodeGen/MachineBasicBlock.h" 23 #include "llvm/IR/CallingConv.h" 24 #include "llvm/MC/LaneBitmask.h" 25 #include "llvm/MC/MCRegisterInfo.h" 26 #include "llvm/Support/ErrorHandling.h" 27 #include "llvm/Support/MachineValueType.h" 28 #include "llvm/Support/MathExtras.h" 29 #include "llvm/Support/Printable.h" 30 #include <cassert> 31 #include <cstdint> 32 #include <functional> 33 34 namespace llvm { 35 36 class BitVector; 37 class LiveRegMatrix; 38 class MachineFunction; 39 class MachineInstr; 40 class RegScavenger; 41 class VirtRegMap; 42 class LiveIntervals; 43 44 class TargetRegisterClass { 45 public: 46 using iterator = const MCPhysReg *; 47 using const_iterator = const MCPhysReg *; 48 using sc_iterator = const TargetRegisterClass* const *; 49 50 // Instance variables filled by tablegen, do not use! 51 const MCRegisterClass *MC; 52 const uint32_t *SubClassMask; 53 const uint16_t *SuperRegIndices; 54 const LaneBitmask LaneMask; 55 /// Classes with a higher priority value are assigned first by register 56 /// allocators using a greedy heuristic. The value is in the range [0,63]. 57 const uint8_t AllocationPriority; 58 /// Whether the class supports two (or more) disjunct subregister indices. 59 const bool HasDisjunctSubRegs; 60 /// Whether a combination of subregisters can cover every register in the 61 /// class. See also the CoveredBySubRegs description in Target.td. 62 const bool CoveredBySubRegs; 63 const sc_iterator SuperClasses; 64 ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&); 65 66 /// Return the register class ID number. getID()67 unsigned getID() const { return MC->getID(); } 68 69 /// begin/end - Return all of the registers in this class. 70 /// begin()71 iterator begin() const { return MC->begin(); } end()72 iterator end() const { return MC->end(); } 73 74 /// Return the number of registers in this class. getNumRegs()75 unsigned getNumRegs() const { return MC->getNumRegs(); } 76 77 iterator_range<SmallVectorImpl<MCPhysReg>::const_iterator> getRegisters()78 getRegisters() const { 79 return make_range(MC->begin(), MC->end()); 80 } 81 82 /// Return the specified register in the class. getRegister(unsigned i)83 unsigned getRegister(unsigned i) const { 84 return MC->getRegister(i); 85 } 86 87 /// Return true if the specified register is included in this register class. 88 /// This does not include virtual registers. contains(unsigned Reg)89 bool contains(unsigned Reg) const { 90 return MC->contains(Reg); 91 } 92 93 /// Return true if both registers are in this class. contains(unsigned Reg1,unsigned Reg2)94 bool contains(unsigned Reg1, unsigned Reg2) const { 95 return MC->contains(Reg1, Reg2); 96 } 97 98 /// Return the cost of copying a value between two registers in this class. 99 /// A negative number means the register class is very expensive 100 /// to copy e.g. status flag register classes. getCopyCost()101 int getCopyCost() const { return MC->getCopyCost(); } 102 103 /// Return true if this register class may be used to create virtual 104 /// registers. isAllocatable()105 bool isAllocatable() const { return MC->isAllocatable(); } 106 107 /// Return true if the specified TargetRegisterClass 108 /// is a proper sub-class of this TargetRegisterClass. hasSubClass(const TargetRegisterClass * RC)109 bool hasSubClass(const TargetRegisterClass *RC) const { 110 return RC != this && hasSubClassEq(RC); 111 } 112 113 /// Returns true if RC is a sub-class of or equal to this class. hasSubClassEq(const TargetRegisterClass * RC)114 bool hasSubClassEq(const TargetRegisterClass *RC) const { 115 unsigned ID = RC->getID(); 116 return (SubClassMask[ID / 32] >> (ID % 32)) & 1; 117 } 118 119 /// Return true if the specified TargetRegisterClass is a 120 /// proper super-class of this TargetRegisterClass. hasSuperClass(const TargetRegisterClass * RC)121 bool hasSuperClass(const TargetRegisterClass *RC) const { 122 return RC->hasSubClass(this); 123 } 124 125 /// Returns true if RC is a super-class of or equal to this class. hasSuperClassEq(const TargetRegisterClass * RC)126 bool hasSuperClassEq(const TargetRegisterClass *RC) const { 127 return RC->hasSubClassEq(this); 128 } 129 130 /// Returns a bit vector of subclasses, including this one. 131 /// The vector is indexed by class IDs. 132 /// 133 /// To use it, consider the returned array as a chunk of memory that 134 /// contains an array of bits of size NumRegClasses. Each 32-bit chunk 135 /// contains a bitset of the ID of the subclasses in big-endian style. 136 137 /// I.e., the representation of the memory from left to right at the 138 /// bit level looks like: 139 /// [31 30 ... 1 0] [ 63 62 ... 33 32] ... 140 /// [ XXX NumRegClasses NumRegClasses - 1 ... ] 141 /// Where the number represents the class ID and XXX bits that 142 /// should be ignored. 143 /// 144 /// See the implementation of hasSubClassEq for an example of how it 145 /// can be used. getSubClassMask()146 const uint32_t *getSubClassMask() const { 147 return SubClassMask; 148 } 149 150 /// Returns a 0-terminated list of sub-register indices that project some 151 /// super-register class into this register class. The list has an entry for 152 /// each Idx such that: 153 /// 154 /// There exists SuperRC where: 155 /// For all Reg in SuperRC: 156 /// this->contains(Reg:Idx) getSuperRegIndices()157 const uint16_t *getSuperRegIndices() const { 158 return SuperRegIndices; 159 } 160 161 /// Returns a NULL-terminated list of super-classes. The 162 /// classes are ordered by ID which is also a topological ordering from large 163 /// to small classes. The list does NOT include the current class. getSuperClasses()164 sc_iterator getSuperClasses() const { 165 return SuperClasses; 166 } 167 168 /// Return true if this TargetRegisterClass is a subset 169 /// class of at least one other TargetRegisterClass. isASubClass()170 bool isASubClass() const { 171 return SuperClasses[0] != nullptr; 172 } 173 174 /// Returns the preferred order for allocating registers from this register 175 /// class in MF. The raw order comes directly from the .td file and may 176 /// include reserved registers that are not allocatable. 177 /// Register allocators should also make sure to allocate 178 /// callee-saved registers only after all the volatiles are used. The 179 /// RegisterClassInfo class provides filtered allocation orders with 180 /// callee-saved registers moved to the end. 181 /// 182 /// The MachineFunction argument can be used to tune the allocatable 183 /// registers based on the characteristics of the function, subtarget, or 184 /// other criteria. 185 /// 186 /// By default, this method returns all registers in the class. getRawAllocationOrder(const MachineFunction & MF)187 ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const { 188 return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs()); 189 } 190 191 /// Returns the combination of all lane masks of register in this class. 192 /// The lane masks of the registers are the combination of all lane masks 193 /// of their subregisters. Returns 1 if there are no subregisters. getLaneMask()194 LaneBitmask getLaneMask() const { 195 return LaneMask; 196 } 197 }; 198 199 /// Extra information, not in MCRegisterDesc, about registers. 200 /// These are used by codegen, not by MC. 201 struct TargetRegisterInfoDesc { 202 unsigned CostPerUse; // Extra cost of instructions using register. 203 bool inAllocatableClass; // Register belongs to an allocatable regclass. 204 }; 205 206 /// Each TargetRegisterClass has a per register weight, and weight 207 /// limit which must be less than the limits of its pressure sets. 208 struct RegClassWeight { 209 unsigned RegWeight; 210 unsigned WeightLimit; 211 }; 212 213 /// TargetRegisterInfo base class - We assume that the target defines a static 214 /// array of TargetRegisterDesc objects that represent all of the machine 215 /// registers that the target has. As such, we simply have to track a pointer 216 /// to this array so that we can turn register number into a register 217 /// descriptor. 218 /// 219 class TargetRegisterInfo : public MCRegisterInfo { 220 public: 221 using regclass_iterator = const TargetRegisterClass * const *; 222 using vt_iterator = const MVT::SimpleValueType *; 223 struct RegClassInfo { 224 unsigned RegSize, SpillSize, SpillAlignment; 225 vt_iterator VTList; 226 }; 227 private: 228 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen 229 const char *const *SubRegIndexNames; // Names of subreg indexes. 230 // Pointer to array of lane masks, one per sub-reg index. 231 const LaneBitmask *SubRegIndexLaneMasks; 232 233 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses 234 LaneBitmask CoveringLanes; 235 const RegClassInfo *const RCInfos; 236 unsigned HwMode; 237 238 protected: 239 TargetRegisterInfo(const TargetRegisterInfoDesc *ID, 240 regclass_iterator RCB, 241 regclass_iterator RCE, 242 const char *const *SRINames, 243 const LaneBitmask *SRILaneMasks, 244 LaneBitmask CoveringLanes, 245 const RegClassInfo *const RCIs, 246 unsigned Mode = 0); 247 virtual ~TargetRegisterInfo(); 248 249 public: 250 // Register numbers can represent physical registers, virtual registers, and 251 // sometimes stack slots. The unsigned values are divided into these ranges: 252 // 253 // 0 Not a register, can be used as a sentinel. 254 // [1;2^30) Physical registers assigned by TableGen. 255 // [2^30;2^31) Stack slots. (Rarely used.) 256 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo. 257 // 258 // Further sentinels can be allocated from the small negative integers. 259 // DenseMapInfo<unsigned> uses -1u and -2u. 260 261 /// isStackSlot - Sometimes it is useful the be able to store a non-negative 262 /// frame index in a variable that normally holds a register. isStackSlot() 263 /// returns true if Reg is in the range used for stack slots. 264 /// 265 /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack 266 /// slots, so if a variable may contains a stack slot, always check 267 /// isStackSlot() first. 268 /// isStackSlot(unsigned Reg)269 static bool isStackSlot(unsigned Reg) { 270 return int(Reg) >= (1 << 30); 271 } 272 273 /// Compute the frame index from a register value representing a stack slot. stackSlot2Index(unsigned Reg)274 static int stackSlot2Index(unsigned Reg) { 275 assert(isStackSlot(Reg) && "Not a stack slot"); 276 return int(Reg - (1u << 30)); 277 } 278 279 /// Convert a non-negative frame index to a stack slot register value. index2StackSlot(int FI)280 static unsigned index2StackSlot(int FI) { 281 assert(FI >= 0 && "Cannot hold a negative frame index."); 282 return FI + (1u << 30); 283 } 284 285 /// Return true if the specified register number is in 286 /// the physical register namespace. isPhysicalRegister(unsigned Reg)287 static bool isPhysicalRegister(unsigned Reg) { 288 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 289 return int(Reg) > 0; 290 } 291 292 /// Return true if the specified register number is in 293 /// the virtual register namespace. isVirtualRegister(unsigned Reg)294 static bool isVirtualRegister(unsigned Reg) { 295 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); 296 return int(Reg) < 0; 297 } 298 299 /// Convert a virtual register number to a 0-based index. 300 /// The first virtual register in a function will get the index 0. virtReg2Index(unsigned Reg)301 static unsigned virtReg2Index(unsigned Reg) { 302 assert(isVirtualRegister(Reg) && "Not a virtual register"); 303 return Reg & ~(1u << 31); 304 } 305 306 /// Convert a 0-based index to a virtual register number. 307 /// This is the inverse operation of VirtReg2IndexFunctor below. index2VirtReg(unsigned Index)308 static unsigned index2VirtReg(unsigned Index) { 309 return Index | (1u << 31); 310 } 311 312 /// Return the size in bits of a register from class RC. getRegSizeInBits(const TargetRegisterClass & RC)313 unsigned getRegSizeInBits(const TargetRegisterClass &RC) const { 314 return getRegClassInfo(RC).RegSize; 315 } 316 317 /// Return the size in bytes of the stack slot allocated to hold a spilled 318 /// copy of a register from class RC. getSpillSize(const TargetRegisterClass & RC)319 unsigned getSpillSize(const TargetRegisterClass &RC) const { 320 return getRegClassInfo(RC).SpillSize / 8; 321 } 322 323 /// Return the minimum required alignment in bytes for a spill slot for 324 /// a register of this class. getSpillAlignment(const TargetRegisterClass & RC)325 unsigned getSpillAlignment(const TargetRegisterClass &RC) const { 326 return getRegClassInfo(RC).SpillAlignment / 8; 327 } 328 329 /// Return true if the given TargetRegisterClass has the ValueType T. isTypeLegalForClass(const TargetRegisterClass & RC,MVT T)330 bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const { 331 for (auto I = legalclasstypes_begin(RC); *I != MVT::Other; ++I) 332 if (MVT(*I) == T) 333 return true; 334 return false; 335 } 336 337 /// Loop over all of the value types that can be represented by values 338 /// in the given register class. legalclasstypes_begin(const TargetRegisterClass & RC)339 vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const { 340 return getRegClassInfo(RC).VTList; 341 } 342 legalclasstypes_end(const TargetRegisterClass & RC)343 vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const { 344 vt_iterator I = legalclasstypes_begin(RC); 345 while (*I != MVT::Other) 346 ++I; 347 return I; 348 } 349 350 /// Returns the Register Class of a physical register of the given type, 351 /// picking the most sub register class of the right type that contains this 352 /// physreg. 353 const TargetRegisterClass * 354 getMinimalPhysRegClass(unsigned Reg, MVT VT = MVT::Other) const; 355 356 /// Return the maximal subclass of the given register class that is 357 /// allocatable or NULL. 358 const TargetRegisterClass * 359 getAllocatableClass(const TargetRegisterClass *RC) const; 360 361 /// Returns a bitset indexed by register number indicating if a register is 362 /// allocatable or not. If a register class is specified, returns the subset 363 /// for the class. 364 BitVector getAllocatableSet(const MachineFunction &MF, 365 const TargetRegisterClass *RC = nullptr) const; 366 367 /// Return the additional cost of using this register instead 368 /// of other registers in its class. getCostPerUse(unsigned RegNo)369 unsigned getCostPerUse(unsigned RegNo) const { 370 return InfoDesc[RegNo].CostPerUse; 371 } 372 373 /// Return true if the register is in the allocation of any register class. isInAllocatableClass(unsigned RegNo)374 bool isInAllocatableClass(unsigned RegNo) const { 375 return InfoDesc[RegNo].inAllocatableClass; 376 } 377 378 /// Return the human-readable symbolic target-specific 379 /// name for the specified SubRegIndex. getSubRegIndexName(unsigned SubIdx)380 const char *getSubRegIndexName(unsigned SubIdx) const { 381 assert(SubIdx && SubIdx < getNumSubRegIndices() && 382 "This is not a subregister index"); 383 return SubRegIndexNames[SubIdx-1]; 384 } 385 386 /// Return a bitmask representing the parts of a register that are covered by 387 /// SubIdx \see LaneBitmask. 388 /// 389 /// SubIdx == 0 is allowed, it has the lane mask ~0u. getSubRegIndexLaneMask(unsigned SubIdx)390 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { 391 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index"); 392 return SubRegIndexLaneMasks[SubIdx]; 393 } 394 395 /// The lane masks returned by getSubRegIndexLaneMask() above can only be 396 /// used to determine if sub-registers overlap - they can't be used to 397 /// determine if a set of sub-registers completely cover another 398 /// sub-register. 399 /// 400 /// The X86 general purpose registers have two lanes corresponding to the 401 /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have 402 /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the 403 /// sub_32bit sub-register. 404 /// 405 /// On the other hand, the ARM NEON lanes fully cover their registers: The 406 /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes. 407 /// This is related to the CoveredBySubRegs property on register definitions. 408 /// 409 /// This function returns a bit mask of lanes that completely cover their 410 /// sub-registers. More precisely, given: 411 /// 412 /// Covering = getCoveringLanes(); 413 /// MaskA = getSubRegIndexLaneMask(SubA); 414 /// MaskB = getSubRegIndexLaneMask(SubB); 415 /// 416 /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by 417 /// SubB. getCoveringLanes()418 LaneBitmask getCoveringLanes() const { return CoveringLanes; } 419 420 /// Returns true if the two registers are equal or alias each other. 421 /// The registers may be virtual registers. regsOverlap(unsigned regA,unsigned regB)422 bool regsOverlap(unsigned regA, unsigned regB) const { 423 if (regA == regB) return true; 424 if (isVirtualRegister(regA) || isVirtualRegister(regB)) 425 return false; 426 427 // Regunits are numerically ordered. Find a common unit. 428 MCRegUnitIterator RUA(regA, this); 429 MCRegUnitIterator RUB(regB, this); 430 do { 431 if (*RUA == *RUB) return true; 432 if (*RUA < *RUB) ++RUA; 433 else ++RUB; 434 } while (RUA.isValid() && RUB.isValid()); 435 return false; 436 } 437 438 /// Returns true if Reg contains RegUnit. hasRegUnit(unsigned Reg,unsigned RegUnit)439 bool hasRegUnit(unsigned Reg, unsigned RegUnit) const { 440 for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units) 441 if (*Units == RegUnit) 442 return true; 443 return false; 444 } 445 446 /// Returns the original SrcReg unless it is the target of a copy-like 447 /// operation, in which case we chain backwards through all such operations 448 /// to the ultimate source register. If a physical register is encountered, 449 /// we stop the search. 450 virtual unsigned lookThruCopyLike(unsigned SrcReg, 451 const MachineRegisterInfo *MRI) const; 452 453 /// Return a null-terminated list of all of the callee-saved registers on 454 /// this target. The register should be in the order of desired callee-save 455 /// stack frame offset. The first register is closest to the incoming stack 456 /// pointer if stack grows down, and vice versa. 457 /// Notice: This function does not take into account disabled CSRs. 458 /// In most cases you will want to use instead the function 459 /// getCalleeSavedRegs that is implemented in MachineRegisterInfo. 460 virtual const MCPhysReg* 461 getCalleeSavedRegs(const MachineFunction *MF) const = 0; 462 463 /// Return a mask of call-preserved registers for the given calling convention 464 /// on the current function. The mask should include all call-preserved 465 /// aliases. This is used by the register allocator to determine which 466 /// registers can be live across a call. 467 /// 468 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries. 469 /// A set bit indicates that all bits of the corresponding register are 470 /// preserved across the function call. The bit mask is expected to be 471 /// sub-register complete, i.e. if A is preserved, so are all its 472 /// sub-registers. 473 /// 474 /// Bits are numbered from the LSB, so the bit for physical register Reg can 475 /// be found as (Mask[Reg / 32] >> Reg % 32) & 1. 476 /// 477 /// A NULL pointer means that no register mask will be used, and call 478 /// instructions should use implicit-def operands to indicate call clobbered 479 /// registers. 480 /// getCallPreservedMask(const MachineFunction & MF,CallingConv::ID)481 virtual const uint32_t *getCallPreservedMask(const MachineFunction &MF, 482 CallingConv::ID) const { 483 // The default mask clobbers everything. All targets should override. 484 return nullptr; 485 } 486 487 /// Return a register mask that clobbers everything. getNoPreservedMask()488 virtual const uint32_t *getNoPreservedMask() const { 489 llvm_unreachable("target does not provide no preserved mask"); 490 } 491 492 /// Return true if all bits that are set in mask \p mask0 are also set in 493 /// \p mask1. 494 bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const; 495 496 /// Return all the call-preserved register masks defined for this target. 497 virtual ArrayRef<const uint32_t *> getRegMasks() const = 0; 498 virtual ArrayRef<const char *> getRegMaskNames() const = 0; 499 500 /// Returns a bitset indexed by physical register number indicating if a 501 /// register is a special register that has particular uses and should be 502 /// considered unavailable at all times, e.g. stack pointer, return address. 503 /// A reserved register: 504 /// - is not allocatable 505 /// - is considered always live 506 /// - is ignored by liveness tracking 507 /// It is often necessary to reserve the super registers of a reserved 508 /// register as well, to avoid them getting allocated indirectly. You may use 509 /// markSuperRegs() and checkAllSuperRegsMarked() in this case. 510 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0; 511 512 /// Returns false if we can't guarantee that Physreg, specified as an IR asm 513 /// clobber constraint, will be preserved across the statement. isAsmClobberable(const MachineFunction & MF,unsigned PhysReg)514 virtual bool isAsmClobberable(const MachineFunction &MF, 515 unsigned PhysReg) const { 516 return true; 517 } 518 519 /// Returns true if PhysReg is unallocatable and constant throughout the 520 /// function. Used by MachineRegisterInfo::isConstantPhysReg(). isConstantPhysReg(unsigned PhysReg)521 virtual bool isConstantPhysReg(unsigned PhysReg) const { return false; } 522 523 /// Returns true if the register class is considered divergent. isDivergentRegClass(const TargetRegisterClass * RC)524 virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const { 525 return false; 526 } 527 528 /// Physical registers that may be modified within a function but are 529 /// guaranteed to be restored before any uses. This is useful for targets that 530 /// have call sequences where a GOT register may be updated by the caller 531 /// prior to a call and is guaranteed to be restored (also by the caller) 532 /// after the call. isCallerPreservedPhysReg(unsigned PhysReg,const MachineFunction & MF)533 virtual bool isCallerPreservedPhysReg(unsigned PhysReg, 534 const MachineFunction &MF) const { 535 return false; 536 } 537 538 /// Prior to adding the live-out mask to a stackmap or patchpoint 539 /// instruction, provide the target the opportunity to adjust it (mainly to 540 /// remove pseudo-registers that should be ignored). adjustStackMapLiveOutMask(uint32_t * Mask)541 virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const {} 542 543 /// Return a super-register of the specified register 544 /// Reg so its sub-register of index SubIdx is Reg. getMatchingSuperReg(unsigned Reg,unsigned SubIdx,const TargetRegisterClass * RC)545 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 546 const TargetRegisterClass *RC) const { 547 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); 548 } 549 550 /// Return a subclass of the specified register 551 /// class A so that each register in it has a sub-register of the 552 /// specified sub-register index which is in the specified register class B. 553 /// 554 /// TableGen will synthesize missing A sub-classes. 555 virtual const TargetRegisterClass * 556 getMatchingSuperRegClass(const TargetRegisterClass *A, 557 const TargetRegisterClass *B, unsigned Idx) const; 558 559 // For a copy-like instruction that defines a register of class DefRC with 560 // subreg index DefSubReg, reading from another source with class SrcRC and 561 // subregister SrcSubReg return true if this is a preferable copy 562 // instruction or an earlier use should be used. 563 virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, 564 unsigned DefSubReg, 565 const TargetRegisterClass *SrcRC, 566 unsigned SrcSubReg) const; 567 568 /// Returns the largest legal sub-class of RC that 569 /// supports the sub-register index Idx. 570 /// If no such sub-class exists, return NULL. 571 /// If all registers in RC already have an Idx sub-register, return RC. 572 /// 573 /// TableGen generates a version of this function that is good enough in most 574 /// cases. Targets can override if they have constraints that TableGen 575 /// doesn't understand. For example, the x86 sub_8bit sub-register index is 576 /// supported by the full GR32 register class in 64-bit mode, but only by the 577 /// GR32_ABCD regiister class in 32-bit mode. 578 /// 579 /// TableGen will synthesize missing RC sub-classes. 580 virtual const TargetRegisterClass * getSubClassWithSubReg(const TargetRegisterClass * RC,unsigned Idx)581 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { 582 assert(Idx == 0 && "Target has no sub-registers"); 583 return RC; 584 } 585 586 /// Return the subregister index you get from composing 587 /// two subregister indices. 588 /// 589 /// The special null sub-register index composes as the identity. 590 /// 591 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b) 592 /// returns c. Note that composeSubRegIndices does not tell you about illegal 593 /// compositions. If R does not have a subreg a, or R:a does not have a subreg 594 /// b, composeSubRegIndices doesn't tell you. 595 /// 596 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has 597 /// ssub_0:S0 - ssub_3:S3 subregs. 598 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2. composeSubRegIndices(unsigned a,unsigned b)599 unsigned composeSubRegIndices(unsigned a, unsigned b) const { 600 if (!a) return b; 601 if (!b) return a; 602 return composeSubRegIndicesImpl(a, b); 603 } 604 605 /// Transforms a LaneMask computed for one subregister to the lanemask that 606 /// would have been computed when composing the subsubregisters with IdxA 607 /// first. @sa composeSubRegIndices() composeSubRegIndexLaneMask(unsigned IdxA,LaneBitmask Mask)608 LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA, 609 LaneBitmask Mask) const { 610 if (!IdxA) 611 return Mask; 612 return composeSubRegIndexLaneMaskImpl(IdxA, Mask); 613 } 614 615 /// Transform a lanemask given for a virtual register to the corresponding 616 /// lanemask before using subregister with index \p IdxA. 617 /// This is the reverse of composeSubRegIndexLaneMask(), assuming Mask is a 618 /// valie lane mask (no invalid bits set) the following holds: 619 /// X0 = composeSubRegIndexLaneMask(Idx, Mask) 620 /// X1 = reverseComposeSubRegIndexLaneMask(Idx, X0) 621 /// => X1 == Mask reverseComposeSubRegIndexLaneMask(unsigned IdxA,LaneBitmask LaneMask)622 LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA, 623 LaneBitmask LaneMask) const { 624 if (!IdxA) 625 return LaneMask; 626 return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask); 627 } 628 629 /// Debugging helper: dump register in human readable form to dbgs() stream. 630 static void dumpReg(unsigned Reg, unsigned SubRegIndex = 0, 631 const TargetRegisterInfo* TRI = nullptr); 632 633 protected: 634 /// Overridden by TableGen in targets that have sub-registers. composeSubRegIndicesImpl(unsigned,unsigned)635 virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const { 636 llvm_unreachable("Target has no sub-registers"); 637 } 638 639 /// Overridden by TableGen in targets that have sub-registers. 640 virtual LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned,LaneBitmask)641 composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const { 642 llvm_unreachable("Target has no sub-registers"); 643 } 644 reverseComposeSubRegIndexLaneMaskImpl(unsigned,LaneBitmask)645 virtual LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, 646 LaneBitmask) const { 647 llvm_unreachable("Target has no sub-registers"); 648 } 649 650 public: 651 /// Find a common super-register class if it exists. 652 /// 653 /// Find a register class, SuperRC and two sub-register indices, PreA and 654 /// PreB, such that: 655 /// 656 /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and 657 /// 658 /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and 659 /// 660 /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()). 661 /// 662 /// SuperRC will be chosen such that no super-class of SuperRC satisfies the 663 /// requirements, and there is no register class with a smaller spill size 664 /// that satisfies the requirements. 665 /// 666 /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead. 667 /// 668 /// Either of the PreA and PreB sub-register indices may be returned as 0. In 669 /// that case, the returned register class will be a sub-class of the 670 /// corresponding argument register class. 671 /// 672 /// The function returns NULL if no register class can be found. 673 const TargetRegisterClass* 674 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, 675 const TargetRegisterClass *RCB, unsigned SubB, 676 unsigned &PreA, unsigned &PreB) const; 677 678 //===--------------------------------------------------------------------===// 679 // Register Class Information 680 // 681 protected: getRegClassInfo(const TargetRegisterClass & RC)682 const RegClassInfo &getRegClassInfo(const TargetRegisterClass &RC) const { 683 return RCInfos[getNumRegClasses() * HwMode + RC.getID()]; 684 } 685 686 public: 687 /// Register class iterators regclass_begin()688 regclass_iterator regclass_begin() const { return RegClassBegin; } regclass_end()689 regclass_iterator regclass_end() const { return RegClassEnd; } regclasses()690 iterator_range<regclass_iterator> regclasses() const { 691 return make_range(regclass_begin(), regclass_end()); 692 } 693 getNumRegClasses()694 unsigned getNumRegClasses() const { 695 return (unsigned)(regclass_end()-regclass_begin()); 696 } 697 698 /// Returns the register class associated with the enumeration value. 699 /// See class MCOperandInfo. getRegClass(unsigned i)700 const TargetRegisterClass *getRegClass(unsigned i) const { 701 assert(i < getNumRegClasses() && "Register Class ID out of range"); 702 return RegClassBegin[i]; 703 } 704 705 /// Returns the name of the register class. getRegClassName(const TargetRegisterClass * Class)706 const char *getRegClassName(const TargetRegisterClass *Class) const { 707 return MCRegisterInfo::getRegClassName(Class->MC); 708 } 709 710 /// Find the largest common subclass of A and B. 711 /// Return NULL if there is no common subclass. 712 /// The common subclass should contain 713 /// simple value type SVT if it is not the Any type. 714 const TargetRegisterClass * 715 getCommonSubClass(const TargetRegisterClass *A, 716 const TargetRegisterClass *B, 717 const MVT::SimpleValueType SVT = 718 MVT::SimpleValueType::Any) const; 719 720 /// Returns a TargetRegisterClass used for pointer values. 721 /// If a target supports multiple different pointer register classes, 722 /// kind specifies which one is indicated. 723 virtual const TargetRegisterClass * 724 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const { 725 llvm_unreachable("Target didn't implement getPointerRegClass!"); 726 } 727 728 /// Returns a legal register class to copy a register in the specified class 729 /// to or from. If it is possible to copy the register directly without using 730 /// a cross register class copy, return the specified RC. Returns NULL if it 731 /// is not possible to copy between two registers of the specified class. 732 virtual const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass * RC)733 getCrossCopyRegClass(const TargetRegisterClass *RC) const { 734 return RC; 735 } 736 737 /// Returns the largest super class of RC that is legal to use in the current 738 /// sub-target and has the same spill size. 739 /// The returned register class can be used to create virtual registers which 740 /// means that all its registers can be copied and spilled. 741 virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass * RC,const MachineFunction &)742 getLargestLegalSuperClass(const TargetRegisterClass *RC, 743 const MachineFunction &) const { 744 /// The default implementation is very conservative and doesn't allow the 745 /// register allocator to inflate register classes. 746 return RC; 747 } 748 749 /// Return the register pressure "high water mark" for the specific register 750 /// class. The scheduler is in high register pressure mode (for the specific 751 /// register class) if it goes over the limit. 752 /// 753 /// Note: this is the old register pressure model that relies on a manually 754 /// specified representative register class per value type. getRegPressureLimit(const TargetRegisterClass * RC,MachineFunction & MF)755 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, 756 MachineFunction &MF) const { 757 return 0; 758 } 759 760 /// Return a heuristic for the machine scheduler to compare the profitability 761 /// of increasing one register pressure set versus another. The scheduler 762 /// will prefer increasing the register pressure of the set which returns 763 /// the largest value for this function. getRegPressureSetScore(const MachineFunction & MF,unsigned PSetID)764 virtual unsigned getRegPressureSetScore(const MachineFunction &MF, 765 unsigned PSetID) const { 766 return PSetID; 767 } 768 769 /// Get the weight in units of pressure for this register class. 770 virtual const RegClassWeight &getRegClassWeight( 771 const TargetRegisterClass *RC) const = 0; 772 773 /// Returns size in bits of a phys/virtual/generic register. 774 unsigned getRegSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI) const; 775 776 /// Get the weight in units of pressure for this register unit. 777 virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0; 778 779 /// Get the number of dimensions of register pressure. 780 virtual unsigned getNumRegPressureSets() const = 0; 781 782 /// Get the name of this register unit pressure set. 783 virtual const char *getRegPressureSetName(unsigned Idx) const = 0; 784 785 /// Get the register unit pressure limit for this dimension. 786 /// This limit must be adjusted dynamically for reserved registers. 787 virtual unsigned getRegPressureSetLimit(const MachineFunction &MF, 788 unsigned Idx) const = 0; 789 790 /// Get the dimensions of register pressure impacted by this register class. 791 /// Returns a -1 terminated array of pressure set IDs. 792 virtual const int *getRegClassPressureSets( 793 const TargetRegisterClass *RC) const = 0; 794 795 /// Get the dimensions of register pressure impacted by this register unit. 796 /// Returns a -1 terminated array of pressure set IDs. 797 virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0; 798 799 /// Get a list of 'hint' registers that the register allocator should try 800 /// first when allocating a physical register for the virtual register 801 /// VirtReg. These registers are effectively moved to the front of the 802 /// allocation order. If true is returned, regalloc will try to only use 803 /// hints to the greatest extent possible even if it means spilling. 804 /// 805 /// The Order argument is the allocation order for VirtReg's register class 806 /// as returned from RegisterClassInfo::getOrder(). The hint registers must 807 /// come from Order, and they must not be reserved. 808 /// 809 /// The default implementation of this function will only add target 810 /// independent register allocation hints. Targets that override this 811 /// function should typically call this default implementation as well and 812 /// expect to see generic copy hints added. 813 virtual bool getRegAllocationHints(unsigned VirtReg, 814 ArrayRef<MCPhysReg> Order, 815 SmallVectorImpl<MCPhysReg> &Hints, 816 const MachineFunction &MF, 817 const VirtRegMap *VRM = nullptr, 818 const LiveRegMatrix *Matrix = nullptr) 819 const; 820 821 /// A callback to allow target a chance to update register allocation hints 822 /// when a register is "changed" (e.g. coalesced) to another register. 823 /// e.g. On ARM, some virtual registers should target register pairs, 824 /// if one of pair is coalesced to another register, the allocation hint of 825 /// the other half of the pair should be changed to point to the new register. updateRegAllocHint(unsigned Reg,unsigned NewReg,MachineFunction & MF)826 virtual void updateRegAllocHint(unsigned Reg, unsigned NewReg, 827 MachineFunction &MF) const { 828 // Do nothing. 829 } 830 831 /// Allow the target to reverse allocation order of local live ranges. This 832 /// will generally allocate shorter local live ranges first. For targets with 833 /// many registers, this could reduce regalloc compile time by a large 834 /// factor. It is disabled by default for three reasons: 835 /// (1) Top-down allocation is simpler and easier to debug for targets that 836 /// don't benefit from reversing the order. 837 /// (2) Bottom-up allocation could result in poor evicition decisions on some 838 /// targets affecting the performance of compiled code. 839 /// (3) Bottom-up allocation is no longer guaranteed to optimally color. reverseLocalAssignment()840 virtual bool reverseLocalAssignment() const { return false; } 841 842 /// Allow the target to override the cost of using a callee-saved register for 843 /// the first time. Default value of 0 means we will use a callee-saved 844 /// register if it is available. getCSRFirstUseCost()845 virtual unsigned getCSRFirstUseCost() const { return 0; } 846 847 /// Returns true if the target requires (and can make use of) the register 848 /// scavenger. requiresRegisterScavenging(const MachineFunction & MF)849 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const { 850 return false; 851 } 852 853 /// Returns true if the target wants to use frame pointer based accesses to 854 /// spill to the scavenger emergency spill slot. useFPForScavengingIndex(const MachineFunction & MF)855 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const { 856 return true; 857 } 858 859 /// Returns true if the target requires post PEI scavenging of registers for 860 /// materializing frame index constants. requiresFrameIndexScavenging(const MachineFunction & MF)861 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const { 862 return false; 863 } 864 865 /// Returns true if the target requires using the RegScavenger directly for 866 /// frame elimination despite using requiresFrameIndexScavenging. requiresFrameIndexReplacementScavenging(const MachineFunction & MF)867 virtual bool requiresFrameIndexReplacementScavenging( 868 const MachineFunction &MF) const { 869 return false; 870 } 871 872 /// Returns true if the target wants the LocalStackAllocation pass to be run 873 /// and virtual base registers used for more efficient stack access. requiresVirtualBaseRegisters(const MachineFunction & MF)874 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const { 875 return false; 876 } 877 878 /// Return true if target has reserved a spill slot in the stack frame of 879 /// the given function for the specified register. e.g. On x86, if the frame 880 /// register is required, the first fixed stack object is reserved as its 881 /// spill slot. This tells PEI not to create a new stack frame 882 /// object for the given register. It should be called only after 883 /// determineCalleeSaves(). hasReservedSpillSlot(const MachineFunction & MF,unsigned Reg,int & FrameIdx)884 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 885 int &FrameIdx) const { 886 return false; 887 } 888 889 /// Returns true if the live-ins should be tracked after register allocation. trackLivenessAfterRegAlloc(const MachineFunction & MF)890 virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 891 return false; 892 } 893 894 /// True if the stack can be realigned for the target. 895 virtual bool canRealignStack(const MachineFunction &MF) const; 896 897 /// True if storage within the function requires the stack pointer to be 898 /// aligned more than the normal calling convention calls for. 899 /// This cannot be overriden by the target, but canRealignStack can be 900 /// overridden. 901 bool needsStackRealignment(const MachineFunction &MF) const; 902 903 /// Get the offset from the referenced frame index in the instruction, 904 /// if there is one. getFrameIndexInstrOffset(const MachineInstr * MI,int Idx)905 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI, 906 int Idx) const { 907 return 0; 908 } 909 910 /// Returns true if the instruction's frame index reference would be better 911 /// served by a base register other than FP or SP. 912 /// Used by LocalStackFrameAllocation to determine which frame index 913 /// references it should create new base registers for. needsFrameBaseReg(MachineInstr * MI,int64_t Offset)914 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 915 return false; 916 } 917 918 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx 919 /// before insertion point I. materializeFrameBaseRegister(MachineBasicBlock * MBB,unsigned BaseReg,int FrameIdx,int64_t Offset)920 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB, 921 unsigned BaseReg, int FrameIdx, 922 int64_t Offset) const { 923 llvm_unreachable("materializeFrameBaseRegister does not exist on this " 924 "target"); 925 } 926 927 /// Resolve a frame index operand of an instruction 928 /// to reference the indicated base register plus offset instead. resolveFrameIndex(MachineInstr & MI,unsigned BaseReg,int64_t Offset)929 virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 930 int64_t Offset) const { 931 llvm_unreachable("resolveFrameIndex does not exist on this target"); 932 } 933 934 /// Determine whether a given base register plus offset immediate is 935 /// encodable to resolve a frame index. isFrameOffsetLegal(const MachineInstr * MI,unsigned BaseReg,int64_t Offset)936 virtual bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, 937 int64_t Offset) const { 938 llvm_unreachable("isFrameOffsetLegal does not exist on this target"); 939 } 940 941 /// Spill the register so it can be used by the register scavenger. 942 /// Return true if the register was spilled, false otherwise. 943 /// If this function does not spill the register, the scavenger 944 /// will instead spill it to the emergency spill slot. saveScavengerRegister(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,MachineBasicBlock::iterator & UseMI,const TargetRegisterClass * RC,unsigned Reg)945 virtual bool saveScavengerRegister(MachineBasicBlock &MBB, 946 MachineBasicBlock::iterator I, 947 MachineBasicBlock::iterator &UseMI, 948 const TargetRegisterClass *RC, 949 unsigned Reg) const { 950 return false; 951 } 952 953 /// This method must be overriden to eliminate abstract frame indices from 954 /// instructions which may use them. The instruction referenced by the 955 /// iterator contains an MO_FrameIndex operand which must be eliminated by 956 /// this method. This method may modify or replace the specified instruction, 957 /// as long as it keeps the iterator pointing at the finished product. 958 /// SPAdj is the SP adjustment due to call frame setup instruction. 959 /// FIOperandNum is the FI operand number. 960 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, 961 int SPAdj, unsigned FIOperandNum, 962 RegScavenger *RS = nullptr) const = 0; 963 964 /// Return the assembly name for \p Reg. getRegAsmName(unsigned Reg)965 virtual StringRef getRegAsmName(unsigned Reg) const { 966 // FIXME: We are assuming that the assembly name is equal to the TableGen 967 // name converted to lower case 968 // 969 // The TableGen name is the name of the definition for this register in the 970 // target's tablegen files. For example, the TableGen name of 971 // def EAX : Register <...>; is "EAX" 972 return StringRef(getName(Reg)); 973 } 974 975 //===--------------------------------------------------------------------===// 976 /// Subtarget Hooks 977 978 /// SrcRC and DstRC will be morphed into NewRC if this returns true. shouldCoalesce(MachineInstr * MI,const TargetRegisterClass * SrcRC,unsigned SubReg,const TargetRegisterClass * DstRC,unsigned DstSubReg,const TargetRegisterClass * NewRC,LiveIntervals & LIS)979 virtual bool shouldCoalesce(MachineInstr *MI, 980 const TargetRegisterClass *SrcRC, 981 unsigned SubReg, 982 const TargetRegisterClass *DstRC, 983 unsigned DstSubReg, 984 const TargetRegisterClass *NewRC, 985 LiveIntervals &LIS) const 986 { return true; } 987 988 //===--------------------------------------------------------------------===// 989 /// Debug information queries. 990 991 /// getFrameRegister - This method should return the register used as a base 992 /// for values allocated in the current stack frame. 993 virtual Register getFrameRegister(const MachineFunction &MF) const = 0; 994 995 /// Mark a register and all its aliases as reserved in the given set. 996 void markSuperRegs(BitVector &RegisterSet, unsigned Reg) const; 997 998 /// Returns true if for every register in the set all super registers are part 999 /// of the set as well. 1000 bool checkAllSuperRegsMarked(const BitVector &RegisterSet, 1001 ArrayRef<MCPhysReg> Exceptions = ArrayRef<MCPhysReg>()) const; 1002 1003 virtual const TargetRegisterClass * getConstrainedRegClassForOperand(const MachineOperand & MO,const MachineRegisterInfo & MRI)1004 getConstrainedRegClassForOperand(const MachineOperand &MO, 1005 const MachineRegisterInfo &MRI) const { 1006 return nullptr; 1007 } 1008 }; 1009 1010 //===----------------------------------------------------------------------===// 1011 // SuperRegClassIterator 1012 //===----------------------------------------------------------------------===// 1013 // 1014 // Iterate over the possible super-registers for a given register class. The 1015 // iterator will visit a list of pairs (Idx, Mask) corresponding to the 1016 // possible classes of super-registers. 1017 // 1018 // Each bit mask will have at least one set bit, and each set bit in Mask 1019 // corresponds to a SuperRC such that: 1020 // 1021 // For all Reg in SuperRC: Reg:Idx is in RC. 1022 // 1023 // The iterator can include (O, RC->getSubClassMask()) as the first entry which 1024 // also satisfies the above requirement, assuming Reg:0 == Reg. 1025 // 1026 class SuperRegClassIterator { 1027 const unsigned RCMaskWords; 1028 unsigned SubReg = 0; 1029 const uint16_t *Idx; 1030 const uint32_t *Mask; 1031 1032 public: 1033 /// Create a SuperRegClassIterator that visits all the super-register classes 1034 /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry. 1035 SuperRegClassIterator(const TargetRegisterClass *RC, 1036 const TargetRegisterInfo *TRI, 1037 bool IncludeSelf = false) 1038 : RCMaskWords((TRI->getNumRegClasses() + 31) / 32), 1039 Idx(RC->getSuperRegIndices()), Mask(RC->getSubClassMask()) { 1040 if (!IncludeSelf) 1041 ++*this; 1042 } 1043 1044 /// Returns true if this iterator is still pointing at a valid entry. isValid()1045 bool isValid() const { return Idx; } 1046 1047 /// Returns the current sub-register index. getSubReg()1048 unsigned getSubReg() const { return SubReg; } 1049 1050 /// Returns the bit mask of register classes that getSubReg() projects into 1051 /// RC. 1052 /// See TargetRegisterClass::getSubClassMask() for how to use it. getMask()1053 const uint32_t *getMask() const { return Mask; } 1054 1055 /// Advance iterator to the next entry. 1056 void operator++() { 1057 assert(isValid() && "Cannot move iterator past end."); 1058 Mask += RCMaskWords; 1059 SubReg = *Idx++; 1060 if (!SubReg) 1061 Idx = nullptr; 1062 } 1063 }; 1064 1065 //===----------------------------------------------------------------------===// 1066 // BitMaskClassIterator 1067 //===----------------------------------------------------------------------===// 1068 /// This class encapuslates the logic to iterate over bitmask returned by 1069 /// the various RegClass related APIs. 1070 /// E.g., this class can be used to iterate over the subclasses provided by 1071 /// TargetRegisterClass::getSubClassMask or SuperRegClassIterator::getMask. 1072 class BitMaskClassIterator { 1073 /// Total number of register classes. 1074 const unsigned NumRegClasses; 1075 /// Base index of CurrentChunk. 1076 /// In other words, the number of bit we read to get at the 1077 /// beginning of that chunck. 1078 unsigned Base = 0; 1079 /// Adjust base index of CurrentChunk. 1080 /// Base index + how many bit we read within CurrentChunk. 1081 unsigned Idx = 0; 1082 /// Current register class ID. 1083 unsigned ID = 0; 1084 /// Mask we are iterating over. 1085 const uint32_t *Mask; 1086 /// Current chunk of the Mask we are traversing. 1087 uint32_t CurrentChunk; 1088 1089 /// Move ID to the next set bit. moveToNextID()1090 void moveToNextID() { 1091 // If the current chunk of memory is empty, move to the next one, 1092 // while making sure we do not go pass the number of register 1093 // classes. 1094 while (!CurrentChunk) { 1095 // Move to the next chunk. 1096 Base += 32; 1097 if (Base >= NumRegClasses) { 1098 ID = NumRegClasses; 1099 return; 1100 } 1101 CurrentChunk = *++Mask; 1102 Idx = Base; 1103 } 1104 // Otherwise look for the first bit set from the right 1105 // (representation of the class ID is big endian). 1106 // See getSubClassMask for more details on the representation. 1107 unsigned Offset = countTrailingZeros(CurrentChunk); 1108 // Add the Offset to the adjusted base number of this chunk: Idx. 1109 // This is the ID of the register class. 1110 ID = Idx + Offset; 1111 1112 // Consume the zeros, if any, and the bit we just read 1113 // so that we are at the right spot for the next call. 1114 // Do not do Offset + 1 because Offset may be 31 and 32 1115 // will be UB for the shift, though in that case we could 1116 // have make the chunk being equal to 0, but that would 1117 // have introduced a if statement. 1118 moveNBits(Offset); 1119 moveNBits(1); 1120 } 1121 1122 /// Move \p NumBits Bits forward in CurrentChunk. moveNBits(unsigned NumBits)1123 void moveNBits(unsigned NumBits) { 1124 assert(NumBits < 32 && "Undefined behavior spotted!"); 1125 // Consume the bit we read for the next call. 1126 CurrentChunk >>= NumBits; 1127 // Adjust the base for the chunk. 1128 Idx += NumBits; 1129 } 1130 1131 public: 1132 /// Create a BitMaskClassIterator that visits all the register classes 1133 /// represented by \p Mask. 1134 /// 1135 /// \pre \p Mask != nullptr BitMaskClassIterator(const uint32_t * Mask,const TargetRegisterInfo & TRI)1136 BitMaskClassIterator(const uint32_t *Mask, const TargetRegisterInfo &TRI) 1137 : NumRegClasses(TRI.getNumRegClasses()), Mask(Mask), CurrentChunk(*Mask) { 1138 // Move to the first ID. 1139 moveToNextID(); 1140 } 1141 1142 /// Returns true if this iterator is still pointing at a valid entry. isValid()1143 bool isValid() const { return getID() != NumRegClasses; } 1144 1145 /// Returns the current register class ID. getID()1146 unsigned getID() const { return ID; } 1147 1148 /// Advance iterator to the next entry. 1149 void operator++() { 1150 assert(isValid() && "Cannot move iterator past end."); 1151 moveToNextID(); 1152 } 1153 }; 1154 1155 // This is useful when building IndexedMaps keyed on virtual registers 1156 struct VirtReg2IndexFunctor { 1157 using argument_type = unsigned; operatorVirtReg2IndexFunctor1158 unsigned operator()(unsigned Reg) const { 1159 return TargetRegisterInfo::virtReg2Index(Reg); 1160 } 1161 }; 1162 1163 /// Prints virtual and physical registers with or without a TRI instance. 1164 /// 1165 /// The format is: 1166 /// %noreg - NoRegister 1167 /// %5 - a virtual register. 1168 /// %5:sub_8bit - a virtual register with sub-register index (with TRI). 1169 /// %eax - a physical register 1170 /// %physreg17 - a physical register when no TRI instance given. 1171 /// 1172 /// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n'; 1173 Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI = nullptr, 1174 unsigned SubIdx = 0, 1175 const MachineRegisterInfo *MRI = nullptr); 1176 1177 /// Create Printable object to print register units on a \ref raw_ostream. 1178 /// 1179 /// Register units are named after their root registers: 1180 /// 1181 /// al - Single root. 1182 /// fp0~st7 - Dual roots. 1183 /// 1184 /// Usage: OS << printRegUnit(Unit, TRI) << '\n'; 1185 Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI); 1186 1187 /// Create Printable object to print virtual registers and physical 1188 /// registers on a \ref raw_ostream. 1189 Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI); 1190 1191 /// Create Printable object to print register classes or register banks 1192 /// on a \ref raw_ostream. 1193 Printable printRegClassOrBank(unsigned Reg, const MachineRegisterInfo &RegInfo, 1194 const TargetRegisterInfo *TRI); 1195 1196 } // end namespace llvm 1197 1198 #endif // LLVM_CODEGEN_TARGETREGISTERINFO_H 1199