1 //===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Mips specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "MipsMCTargetDesc.h"
14 #include "MipsAsmBackend.h"
15 #include "MipsELFStreamer.h"
16 #include "MipsInstPrinter.h"
17 #include "MipsMCAsmInfo.h"
18 #include "MipsMCNaCl.h"
19 #include "MipsTargetStreamer.h"
20 #include "TargetInfo/MipsTargetInfo.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/MC/MCCodeEmitter.h"
23 #include "llvm/MC/MCELFStreamer.h"
24 #include "llvm/MC/MCInstrAnalysis.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCObjectWriter.h"
27 #include "llvm/MC/MCRegisterInfo.h"
28 #include "llvm/MC/MCSubtargetInfo.h"
29 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/MC/MachineLocation.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/FormattedStream.h"
33 #include "llvm/Support/TargetRegistry.h"
34
35 using namespace llvm;
36
37 #define GET_INSTRINFO_MC_DESC
38 #include "MipsGenInstrInfo.inc"
39
40 #define GET_SUBTARGETINFO_MC_DESC
41 #include "MipsGenSubtargetInfo.inc"
42
43 #define GET_REGINFO_MC_DESC
44 #include "MipsGenRegisterInfo.inc"
45
46 /// Select the Mips CPU for the given triple and cpu name.
47 /// FIXME: Merge with the copy in MipsSubtarget.cpp
selectMipsCPU(const Triple & TT,StringRef CPU)48 StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) {
49 if (CPU.empty() || CPU == "generic") {
50 if (TT.getSubArch() == llvm::Triple::MipsSubArch_r6) {
51 if (TT.isMIPS32())
52 CPU = "mips32r6";
53 else
54 CPU = "mips64r6";
55 } else {
56 if (TT.isMIPS32())
57 CPU = "mips32";
58 else
59 CPU = "mips64";
60 }
61 }
62 return CPU;
63 }
64
createMipsMCInstrInfo()65 static MCInstrInfo *createMipsMCInstrInfo() {
66 MCInstrInfo *X = new MCInstrInfo();
67 InitMipsMCInstrInfo(X);
68 return X;
69 }
70
createMipsMCRegisterInfo(const Triple & TT)71 static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) {
72 MCRegisterInfo *X = new MCRegisterInfo();
73 InitMipsMCRegisterInfo(X, Mips::RA);
74 return X;
75 }
76
createMipsMCSubtargetInfo(const Triple & TT,StringRef CPU,StringRef FS)77 static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
78 StringRef CPU, StringRef FS) {
79 CPU = MIPS_MC::selectMipsCPU(TT, CPU);
80 return createMipsMCSubtargetInfoImpl(TT, CPU, FS);
81 }
82
createMipsMCAsmInfo(const MCRegisterInfo & MRI,const Triple & TT)83 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
84 const Triple &TT) {
85 MCAsmInfo *MAI = new MipsMCAsmInfo(TT);
86
87 unsigned SP = MRI.getDwarfRegNum(Mips::SP, true);
88 MCCFIInstruction Inst = MCCFIInstruction::createDefCfaRegister(nullptr, SP);
89 MAI->addInitialFrameState(Inst);
90
91 return MAI;
92 }
93
createMipsMCInstPrinter(const Triple & T,unsigned SyntaxVariant,const MCAsmInfo & MAI,const MCInstrInfo & MII,const MCRegisterInfo & MRI)94 static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
95 unsigned SyntaxVariant,
96 const MCAsmInfo &MAI,
97 const MCInstrInfo &MII,
98 const MCRegisterInfo &MRI) {
99 return new MipsInstPrinter(MAI, MII, MRI);
100 }
101
createMCStreamer(const Triple & T,MCContext & Context,std::unique_ptr<MCAsmBackend> && MAB,std::unique_ptr<MCObjectWriter> && OW,std::unique_ptr<MCCodeEmitter> && Emitter,bool RelaxAll)102 static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
103 std::unique_ptr<MCAsmBackend> &&MAB,
104 std::unique_ptr<MCObjectWriter> &&OW,
105 std::unique_ptr<MCCodeEmitter> &&Emitter,
106 bool RelaxAll) {
107 MCStreamer *S;
108 if (!T.isOSNaCl())
109 S = createMipsELFStreamer(Context, std::move(MAB), std::move(OW),
110 std::move(Emitter), RelaxAll);
111 else
112 S = createMipsNaClELFStreamer(Context, std::move(MAB), std::move(OW),
113 std::move(Emitter), RelaxAll);
114 return S;
115 }
116
createMipsAsmTargetStreamer(MCStreamer & S,formatted_raw_ostream & OS,MCInstPrinter * InstPrint,bool isVerboseAsm)117 static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S,
118 formatted_raw_ostream &OS,
119 MCInstPrinter *InstPrint,
120 bool isVerboseAsm) {
121 return new MipsTargetAsmStreamer(S, OS);
122 }
123
createMipsNullTargetStreamer(MCStreamer & S)124 static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) {
125 return new MipsTargetStreamer(S);
126 }
127
128 static MCTargetStreamer *
createMipsObjectTargetStreamer(MCStreamer & S,const MCSubtargetInfo & STI)129 createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
130 return new MipsTargetELFStreamer(S, STI);
131 }
132
133 namespace {
134
135 class MipsMCInstrAnalysis : public MCInstrAnalysis {
136 public:
MipsMCInstrAnalysis(const MCInstrInfo * Info)137 MipsMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
138
evaluateBranch(const MCInst & Inst,uint64_t Addr,uint64_t Size,uint64_t & Target) const139 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
140 uint64_t &Target) const override {
141 unsigned NumOps = Inst.getNumOperands();
142 if (NumOps == 0)
143 return false;
144 switch (Info->get(Inst.getOpcode()).OpInfo[NumOps - 1].OperandType) {
145 case MCOI::OPERAND_UNKNOWN:
146 case MCOI::OPERAND_IMMEDIATE:
147 // jal, bal ...
148 Target = Inst.getOperand(NumOps - 1).getImm();
149 return true;
150 case MCOI::OPERAND_PCREL:
151 // b, j, beq ...
152 Target = Addr + Inst.getOperand(NumOps - 1).getImm();
153 return true;
154 default:
155 return false;
156 }
157 }
158 };
159 }
160
createMipsMCInstrAnalysis(const MCInstrInfo * Info)161 static MCInstrAnalysis *createMipsMCInstrAnalysis(const MCInstrInfo *Info) {
162 return new MipsMCInstrAnalysis(Info);
163 }
164
LLVMInitializeMipsTargetMC()165 extern "C" void LLVMInitializeMipsTargetMC() {
166 for (Target *T : {&getTheMipsTarget(), &getTheMipselTarget(),
167 &getTheMips64Target(), &getTheMips64elTarget()}) {
168 // Register the MC asm info.
169 RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo);
170
171 // Register the MC instruction info.
172 TargetRegistry::RegisterMCInstrInfo(*T, createMipsMCInstrInfo);
173
174 // Register the MC register info.
175 TargetRegistry::RegisterMCRegInfo(*T, createMipsMCRegisterInfo);
176
177 // Register the elf streamer.
178 TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
179
180 // Register the asm target streamer.
181 TargetRegistry::RegisterAsmTargetStreamer(*T, createMipsAsmTargetStreamer);
182
183 TargetRegistry::RegisterNullTargetStreamer(*T,
184 createMipsNullTargetStreamer);
185
186 // Register the MC subtarget info.
187 TargetRegistry::RegisterMCSubtargetInfo(*T, createMipsMCSubtargetInfo);
188
189 // Register the MC instruction analyzer.
190 TargetRegistry::RegisterMCInstrAnalysis(*T, createMipsMCInstrAnalysis);
191
192 // Register the MCInstPrinter.
193 TargetRegistry::RegisterMCInstPrinter(*T, createMipsMCInstPrinter);
194
195 TargetRegistry::RegisterObjectTargetStreamer(
196 *T, createMipsObjectTargetStreamer);
197
198 // Register the asm backend.
199 TargetRegistry::RegisterMCAsmBackend(*T, createMipsAsmBackend);
200 }
201
202 // Register the MC Code Emitter
203 for (Target *T : {&getTheMipsTarget(), &getTheMips64Target()})
204 TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEB);
205
206 for (Target *T : {&getTheMipselTarget(), &getTheMips64elTarget()})
207 TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL);
208 }
209