1;; Machine description for DEC Alpha for GNU C compiler 2;; Copyright (C) 1992-2013 Free Software Foundation, Inc. 3;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify 8;; it under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 3, or (at your option) 10;; any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, 13;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15;; GNU General Public License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 22 23;; Uses of UNSPEC in this file: 24 25(define_c_enum "unspec" [ 26 UNSPEC_ARG_HOME 27 UNSPEC_LDGP1 28 UNSPEC_INSXH 29 UNSPEC_MSKXH 30 UNSPEC_CVTQL 31 UNSPEC_CVTLQ 32 UNSPEC_LDGP2 33 UNSPEC_LITERAL 34 UNSPEC_LITUSE 35 UNSPEC_SIBCALL 36 UNSPEC_SYMBOL 37 38 ;; TLS Support 39 UNSPEC_TLSGD_CALL 40 UNSPEC_TLSLDM_CALL 41 UNSPEC_TLSGD 42 UNSPEC_TLSLDM 43 UNSPEC_DTPREL 44 UNSPEC_TPREL 45 UNSPEC_TP 46 47 ;; Builtins 48 UNSPEC_CMPBGE 49 UNSPEC_ZAP 50 UNSPEC_AMASK 51 UNSPEC_IMPLVER 52 UNSPEC_PERR 53 UNSPEC_COPYSIGN 54 55 ;; Atomic operations 56 UNSPEC_MB 57 UNSPEC_ATOMIC 58 UNSPEC_CMPXCHG 59 UNSPEC_XCHG 60]) 61 62;; UNSPEC_VOLATILE: 63 64(define_c_enum "unspecv" [ 65 UNSPECV_IMB 66 UNSPECV_BLOCKAGE 67 UNSPECV_SETJMPR ; builtin_setjmp_receiver 68 UNSPECV_LONGJMP ; builtin_longjmp 69 UNSPECV_TRAPB 70 UNSPECV_PSPL ; prologue_stack_probe_loop 71 UNSPECV_REALIGN 72 UNSPECV_EHR ; exception_receiver 73 UNSPECV_MCOUNT 74 UNSPECV_FORCE_MOV 75 UNSPECV_LDGP1 76 UNSPECV_PLDGP2 ; prologue ldgp 77 UNSPECV_SET_TP 78 UNSPECV_RPCC 79 UNSPECV_SETJMPR_ER ; builtin_setjmp_receiver fragment 80 UNSPECV_LL ; load-locked 81 UNSPECV_SC ; store-conditional 82 UNSPECV_CMPXCHG 83]) 84 85;; On non-BWX targets, CQImode must be handled the similarly to HImode 86;; when generating reloads. 87(define_mode_iterator RELOAD12 [QI HI CQI]) 88(define_mode_attr reloadmode [(QI "qi") (HI "hi") (CQI "hi")]) 89 90;; Other mode iterators 91(define_mode_iterator IMODE [QI HI SI DI]) 92(define_mode_iterator I12MODE [QI HI]) 93(define_mode_iterator I124MODE [QI HI SI]) 94(define_mode_iterator I24MODE [HI SI]) 95(define_mode_iterator I248MODE [HI SI DI]) 96(define_mode_iterator I48MODE [SI DI]) 97 98(define_mode_attr DWI [(SI "DI") (DI "TI")]) 99(define_mode_attr modesuffix [(QI "b") (HI "w") (SI "l") (DI "q") 100 (V8QI "b8") (V4HI "w4") 101 (SF "%,") (DF "%-")]) 102(define_mode_attr vecmodesuffix [(QI "b8") (HI "w4")]) 103 104(define_code_iterator any_maxmin [smax smin umax umin]) 105 106(define_code_attr maxmin [(smax "maxs") (smin "mins") 107 (umax "maxu") (umin "minu")]) 108 109;; Where necessary, the suffixes _le and _be are used to distinguish between 110;; little-endian and big-endian patterns. 111;; 112;; Note that the Unicos/Mk assembler does not support the following 113;; opcodes: mov, fmov, nop, fnop, unop. 114 115;; Processor type -- this attribute must exactly match the processor_type 116;; enumeration in alpha.h. 117 118(define_attr "tune" "ev4,ev5,ev6" 119 (const (symbol_ref "((enum attr_tune) alpha_tune)"))) 120 121;; Define an insn type attribute. This is used in function unit delay 122;; computations, among other purposes. For the most part, we use the names 123;; defined in the EV4 documentation, but add a few that we have to know about 124;; separately. 125 126(define_attr "type" 127 "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov, 128 icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,mb,ld_l,st_c, 129 multi,none" 130 (const_string "iadd")) 131 132;; Describe a user's asm statement. 133(define_asm_attributes 134 [(set_attr "type" "multi")]) 135 136;; Define the operand size an insn operates on. Used primarily by mul 137;; and div operations that have size dependent timings. 138 139(define_attr "opsize" "si,di,udi" 140 (const_string "di")) 141 142;; The TRAP attribute marks instructions that may generate traps 143;; (which are imprecise and may need a trapb if software completion 144;; is desired). 145 146(define_attr "trap" "no,yes" 147 (const_string "no")) 148 149;; The ROUND_SUFFIX attribute marks which instructions require a 150;; rounding-mode suffix. The value NONE indicates no suffix, 151;; the value NORMAL indicates a suffix controlled by alpha_fprm. 152 153(define_attr "round_suffix" "none,normal,c" 154 (const_string "none")) 155 156;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix: 157;; NONE no suffix 158;; SU accepts only /su (cmpt et al) 159;; SUI accepts only /sui (cvtqt and cvtqs) 160;; V_SV accepts /v and /sv (cvtql only) 161;; V_SV_SVI accepts /v, /sv and /svi (cvttq only) 162;; U_SU_SUI accepts /u, /su and /sui (most fp instructions) 163;; 164;; The actual suffix emitted is controlled by alpha_fptm. 165 166(define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui" 167 (const_string "none")) 168 169;; The length of an instruction sequence in bytes. 170 171(define_attr "length" "" 172 (const_int 4)) 173 174;; The USEGP attribute marks instructions that have relocations that use 175;; the GP. 176 177(define_attr "usegp" "no,yes" 178 (cond [(eq_attr "type" "ldsym,jsr") 179 (const_string "yes") 180 (eq_attr "type" "ild,fld,ist,fst") 181 (symbol_ref "((enum attr_usegp) alpha_find_lo_sum_using_gp (insn))") 182 ] 183 (const_string "no"))) 184 185;; The CANNOT_COPY attribute marks instructions with relocations that 186;; cannot easily be duplicated. This includes insns with gpdisp relocs 187;; since they have to stay in 1-1 correspondence with one another. This 188;; also includes jsr insns, since they must stay in correspondence with 189;; the immediately following gpdisp instructions. 190 191(define_attr "cannot_copy" "false,true" 192 (const_string "false")) 193 194;; Used to control the "enabled" attribute on a per-instruction basis. 195;; For convenience, conflate ABI issues re loading of addresses with 196;; an "isa". 197(define_attr "isa" "base,bwx,max,fix,cix,vms,ner,er" 198 (const_string "base")) 199 200(define_attr "enabled" "" 201 (cond [(eq_attr "isa" "bwx") (symbol_ref "TARGET_BWX") 202 (eq_attr "isa" "max") (symbol_ref "TARGET_MAX") 203 (eq_attr "isa" "fix") (symbol_ref "TARGET_FIX") 204 (eq_attr "isa" "cix") (symbol_ref "TARGET_CIX") 205 (eq_attr "isa" "vms") (symbol_ref "TARGET_ABI_OPEN_VMS") 206 (eq_attr "isa" "ner") (symbol_ref "!TARGET_EXPLICIT_RELOCS") 207 (eq_attr "isa" "er") (symbol_ref "TARGET_EXPLICIT_RELOCS") 208 ] 209 (const_int 1))) 210 211;; Include scheduling descriptions. 212 213(include "ev4.md") 214(include "ev5.md") 215(include "ev6.md") 216 217 218;; Operand and operator predicates and constraints 219 220(include "predicates.md") 221(include "constraints.md") 222 223 224;; First define the arithmetic insns. Note that the 32-bit forms also 225;; sign-extend. 226 227;; Handle 32-64 bit extension from memory to a floating point register 228;; specially, since this occurs frequently in int->double conversions. 229;; 230;; Note that while we must retain the =f case in the insn for reload's 231;; benefit, it should be eliminated after reload, so we should never emit 232;; code for that case. But we don't reject the possibility. 233 234(define_expand "extendsidi2" 235 [(set (match_operand:DI 0 "register_operand") 236 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]) 237 238(define_insn "*cvtlq" 239 [(set (match_operand:DI 0 "register_operand" "=f") 240 (unspec:DI [(match_operand:SF 1 "reg_or_0_operand" "fG")] 241 UNSPEC_CVTLQ))] 242 "" 243 "cvtlq %1,%0" 244 [(set_attr "type" "fadd")]) 245 246(define_insn "*extendsidi2_1" 247 [(set (match_operand:DI 0 "register_operand" "=r,r,!*f") 248 (sign_extend:DI 249 (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))] 250 "" 251 "@ 252 addl $31,%1,%0 253 ldl %0,%1 254 lds %0,%1\;cvtlq %0,%0" 255 [(set_attr "type" "iadd,ild,fld") 256 (set_attr "length" "*,*,8")]) 257 258(define_split 259 [(set (match_operand:DI 0 "hard_fp_register_operand") 260 (sign_extend:DI (match_operand:SI 1 "memory_operand")))] 261 "reload_completed" 262 [(set (match_dup 2) (match_dup 1)) 263 (set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))] 264{ 265 operands[1] = adjust_address (operands[1], SFmode, 0); 266 operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0])); 267}) 268 269;; Optimize sign-extension of SImode loads. This shows up in the wake of 270;; reload when converting fp->int. 271 272(define_peephole2 273 [(set (match_operand:SI 0 "hard_int_register_operand") 274 (match_operand:SI 1 "memory_operand")) 275 (set (match_operand:DI 2 "hard_int_register_operand") 276 (sign_extend:DI (match_dup 0)))] 277 "true_regnum (operands[0]) == true_regnum (operands[2]) 278 || peep2_reg_dead_p (2, operands[0])" 279 [(set (match_dup 2) 280 (sign_extend:DI (match_dup 1)))]) 281 282(define_insn "addsi3" 283 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") 284 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ") 285 (match_operand:SI 2 "add_operand" "rI,O,K,L")))] 286 "" 287 "@ 288 addl %r1,%2,%0 289 subl %r1,%n2,%0 290 lda %0,%2(%r1) 291 ldah %0,%h2(%r1)") 292 293(define_split 294 [(set (match_operand:SI 0 "register_operand") 295 (plus:SI (match_operand:SI 1 "register_operand") 296 (match_operand:SI 2 "const_int_operand")))] 297 "! add_operand (operands[2], SImode)" 298 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) 299 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] 300{ 301 HOST_WIDE_INT val = INTVAL (operands[2]); 302 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); 303 HOST_WIDE_INT rest = val - low; 304 305 operands[3] = GEN_INT (rest); 306 operands[4] = GEN_INT (low); 307}) 308 309(define_insn "*addsi_se" 310 [(set (match_operand:DI 0 "register_operand" "=r,r") 311 (sign_extend:DI 312 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") 313 (match_operand:SI 2 "sext_add_operand" "rI,O"))))] 314 "" 315 "@ 316 addl %r1,%2,%0 317 subl %r1,%n2,%0") 318 319(define_insn "*addsi_se2" 320 [(set (match_operand:DI 0 "register_operand" "=r,r") 321 (sign_extend:DI 322 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 323 (match_operand:DI 2 "sext_add_operand" "rI,O")) 324 0)))] 325 "" 326 "@ 327 addl %r1,%2,%0 328 subl %r1,%n2,%0") 329 330(define_split 331 [(set (match_operand:DI 0 "register_operand") 332 (sign_extend:DI 333 (plus:SI (match_operand:SI 1 "reg_not_elim_operand") 334 (match_operand:SI 2 "const_int_operand")))) 335 (clobber (match_operand:SI 3 "reg_not_elim_operand"))] 336 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0 337 && INTVAL (operands[2]) % 4 == 0" 338 [(set (match_dup 3) (match_dup 4)) 339 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3) 340 (match_dup 5)) 341 (match_dup 1))))] 342{ 343 HOST_WIDE_INT val = INTVAL (operands[2]) / 4; 344 int mult = 4; 345 346 if (val % 2 == 0) 347 val /= 2, mult = 8; 348 349 operands[4] = GEN_INT (val); 350 operands[5] = GEN_INT (mult); 351}) 352 353(define_split 354 [(set (match_operand:DI 0 "register_operand") 355 (sign_extend:DI 356 (plus:SI (match_operator:SI 1 "comparison_operator" 357 [(match_operand 2) 358 (match_operand 3)]) 359 (match_operand:SI 4 "add_operand")))) 360 (clobber (match_operand:DI 5 "register_operand"))] 361 "" 362 [(set (match_dup 5) (match_dup 6)) 363 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))] 364{ 365 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode, 366 operands[2], operands[3]); 367 operands[7] = gen_lowpart (SImode, operands[5]); 368}) 369 370(define_expand "adddi3" 371 [(set (match_operand:DI 0 "register_operand") 372 (plus:DI (match_operand:DI 1 "register_operand") 373 (match_operand:DI 2 "add_operand")))]) 374 375(define_insn "*adddi_er_lo16_dtp" 376 [(set (match_operand:DI 0 "register_operand" "=r") 377 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 378 (match_operand:DI 2 "dtp16_symbolic_operand")))] 379 "HAVE_AS_TLS" 380 "lda %0,%2(%1)\t\t!dtprel") 381 382(define_insn "*adddi_er_hi32_dtp" 383 [(set (match_operand:DI 0 "register_operand" "=r") 384 (plus:DI (match_operand:DI 1 "register_operand" "r") 385 (high:DI (match_operand:DI 2 "dtp32_symbolic_operand"))))] 386 "HAVE_AS_TLS" 387 "ldah %0,%2(%1)\t\t!dtprelhi") 388 389(define_insn "*adddi_er_lo32_dtp" 390 [(set (match_operand:DI 0 "register_operand" "=r") 391 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 392 (match_operand:DI 2 "dtp32_symbolic_operand")))] 393 "HAVE_AS_TLS" 394 "lda %0,%2(%1)\t\t!dtprello") 395 396(define_insn "*adddi_er_lo16_tp" 397 [(set (match_operand:DI 0 "register_operand" "=r") 398 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 399 (match_operand:DI 2 "tp16_symbolic_operand")))] 400 "HAVE_AS_TLS" 401 "lda %0,%2(%1)\t\t!tprel") 402 403(define_insn "*adddi_er_hi32_tp" 404 [(set (match_operand:DI 0 "register_operand" "=r") 405 (plus:DI (match_operand:DI 1 "register_operand" "r") 406 (high:DI (match_operand:DI 2 "tp32_symbolic_operand"))))] 407 "HAVE_AS_TLS" 408 "ldah %0,%2(%1)\t\t!tprelhi") 409 410(define_insn "*adddi_er_lo32_tp" 411 [(set (match_operand:DI 0 "register_operand" "=r") 412 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 413 (match_operand:DI 2 "tp32_symbolic_operand")))] 414 "HAVE_AS_TLS" 415 "lda %0,%2(%1)\t\t!tprello") 416 417(define_insn "*adddi_er_high_l" 418 [(set (match_operand:DI 0 "register_operand" "=r") 419 (plus:DI (match_operand:DI 1 "register_operand" "r") 420 (high:DI (match_operand:DI 2 "local_symbolic_operand"))))] 421 "TARGET_EXPLICIT_RELOCS && reload_completed" 422 "ldah %0,%2(%1)\t\t!gprelhigh" 423 [(set_attr "usegp" "yes")]) 424 425(define_split 426 [(set (match_operand:DI 0 "register_operand") 427 (high:DI (match_operand:DI 1 "local_symbolic_operand")))] 428 "TARGET_EXPLICIT_RELOCS && reload_completed" 429 [(set (match_dup 0) 430 (plus:DI (match_dup 2) (high:DI (match_dup 1))))] 431 "operands[2] = pic_offset_table_rtx;") 432 433;; We used to expend quite a lot of effort choosing addq/subq/lda. 434;; With complications like 435;; 436;; The NT stack unwind code can't handle a subq to adjust the stack 437;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3, 438;; the exception handling code will loop if a subq is used and an 439;; exception occurs. 440;; 441;; The 19980616 change to emit prologues as RTL also confused some 442;; versions of GDB, which also interprets prologues. This has been 443;; fixed as of GDB 4.18, but it does not harm to unconditionally 444;; use lda here. 445;; 446;; and the fact that the three insns schedule exactly the same, it's 447;; just not worth the effort. 448 449(define_insn "*adddi_internal" 450 [(set (match_operand:DI 0 "register_operand" "=r,r,r") 451 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r") 452 (match_operand:DI 2 "add_operand" "r,K,L")))] 453 "" 454 "@ 455 addq %1,%2,%0 456 lda %0,%2(%1) 457 ldah %0,%h2(%1)") 458 459;; ??? Allow large constants when basing off the frame pointer or some 460;; virtual register that may eliminate to the frame pointer. This is 461;; done because register elimination offsets will change the hi/lo split, 462;; and if we split before reload, we will require additional instructions. 463 464(define_insn "*adddi_fp_hack" 465 [(set (match_operand:DI 0 "register_operand" "=r,r,r") 466 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r,r,r") 467 (match_operand:DI 2 "const_int_operand" "K,L,n")))] 468 "NONSTRICT_REG_OK_FP_BASE_P (operands[1]) 469 && INTVAL (operands[2]) >= 0 470 /* This is the largest constant an lda+ldah pair can add, minus 471 an upper bound on the displacement between SP and AP during 472 register elimination. See INITIAL_ELIMINATION_OFFSET. */ 473 && INTVAL (operands[2]) 474 < (0x7fff8000 475 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD 476 - ALPHA_ROUND(crtl->outgoing_args_size) 477 - (ALPHA_ROUND (get_frame_size () 478 + max_reg_num () * UNITS_PER_WORD 479 + crtl->args.pretend_args_size) 480 - crtl->args.pretend_args_size))" 481 "@ 482 lda %0,%2(%1) 483 ldah %0,%h2(%1) 484 #") 485 486;; Don't do this if we are adjusting SP since we don't want to do it 487;; in two steps. Don't split FP sources for the reason listed above. 488(define_split 489 [(set (match_operand:DI 0 "register_operand") 490 (plus:DI (match_operand:DI 1 "register_operand") 491 (match_operand:DI 2 "const_int_operand")))] 492 "! add_operand (operands[2], DImode) 493 && operands[0] != stack_pointer_rtx 494 && operands[1] != frame_pointer_rtx 495 && operands[1] != arg_pointer_rtx" 496 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) 497 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] 498{ 499 HOST_WIDE_INT val = INTVAL (operands[2]); 500 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); 501 HOST_WIDE_INT rest = val - low; 502 rtx rest_rtx = GEN_INT (rest); 503 504 operands[4] = GEN_INT (low); 505 if (satisfies_constraint_L (rest_rtx)) 506 operands[3] = rest_rtx; 507 else if (can_create_pseudo_p ()) 508 { 509 operands[3] = gen_reg_rtx (DImode); 510 emit_move_insn (operands[3], operands[2]); 511 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); 512 DONE; 513 } 514 else 515 FAIL; 516}) 517 518(define_insn "*sadd<modesuffix>" 519 [(set (match_operand:I48MODE 0 "register_operand" "=r,r") 520 (plus:I48MODE 521 (mult:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r,r") 522 (match_operand:I48MODE 2 "const48_operand" "I,I")) 523 (match_operand:I48MODE 3 "sext_add_operand" "rI,O")))] 524 "" 525 "@ 526 s%2add<modesuffix> %1,%3,%0 527 s%2sub<modesuffix> %1,%n3,%0") 528 529(define_insn "*saddl_se" 530 [(set (match_operand:DI 0 "register_operand" "=r,r") 531 (sign_extend:DI 532 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r") 533 (match_operand:SI 2 "const48_operand" "I,I")) 534 (match_operand:SI 3 "sext_add_operand" "rI,O"))))] 535 "" 536 "@ 537 s%2addl %1,%3,%0 538 s%2subl %1,%n3,%0") 539 540(define_split 541 [(set (match_operand:DI 0 "register_operand") 542 (sign_extend:DI 543 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator" 544 [(match_operand 2) 545 (match_operand 3)]) 546 (match_operand:SI 4 "const48_operand")) 547 (match_operand:SI 5 "sext_add_operand")))) 548 (clobber (match_operand:DI 6 "reg_not_elim_operand"))] 549 "" 550 [(set (match_dup 6) (match_dup 7)) 551 (set (match_dup 0) 552 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4)) 553 (match_dup 5))))] 554{ 555 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode, 556 operands[2], operands[3]); 557 operands[8] = gen_lowpart (SImode, operands[6]); 558}) 559 560(define_insn "addv<mode>3" 561 [(set (match_operand:I48MODE 0 "register_operand" "=r,r") 562 (plus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ,rJ") 563 (match_operand:I48MODE 2 "sext_add_operand" "rI,O"))) 564 (trap_if (ne (plus:<DWI> (sign_extend:<DWI> (match_dup 1)) 565 (sign_extend:<DWI> (match_dup 2))) 566 (sign_extend:<DWI> (plus:I48MODE (match_dup 1) 567 (match_dup 2)))) 568 (const_int 0))] 569 "" 570 "@ 571 add<modesuffix>v %r1,%2,%0 572 sub<modesuffix>v %r1,%n2,%0") 573 574(define_insn "neg<mode>2" 575 [(set (match_operand:I48MODE 0 "register_operand" "=r") 576 (neg:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI")))] 577 "" 578 "sub<modesuffix> $31,%1,%0") 579 580(define_insn "*negsi_se" 581 [(set (match_operand:DI 0 "register_operand" "=r") 582 (sign_extend:DI (neg:SI 583 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))] 584 "" 585 "subl $31,%1,%0") 586 587(define_insn "negv<mode>2" 588 [(set (match_operand:I48MODE 0 "register_operand" "=r") 589 (neg:I48MODE (match_operand:I48MODE 1 "register_operand" "r"))) 590 (trap_if (ne (neg:<DWI> (sign_extend:<DWI> (match_dup 1))) 591 (sign_extend:<DWI> (neg:I48MODE (match_dup 1)))) 592 (const_int 0))] 593 "" 594 "sub<modesuffix>v $31,%1,%0") 595 596(define_insn "sub<mode>3" 597 [(set (match_operand:I48MODE 0 "register_operand" "=r") 598 (minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ") 599 (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))] 600 "" 601 "sub<modesuffix> %r1,%2,%0") 602 603(define_insn "*subsi_se" 604 [(set (match_operand:DI 0 "register_operand" "=r") 605 (sign_extend:DI 606 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") 607 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))] 608 "" 609 "subl %r1,%2,%0") 610 611(define_insn "*subsi_se2" 612 [(set (match_operand:DI 0 "register_operand" "=r") 613 (sign_extend:DI 614 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 615 (match_operand:DI 2 "reg_or_8bit_operand" "rI")) 616 0)))] 617 "" 618 "subl %r1,%2,%0") 619 620(define_insn "*ssub<modesuffix>" 621 [(set (match_operand:I48MODE 0 "register_operand" "=r") 622 (minus:I48MODE 623 (mult:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r") 624 (match_operand:I48MODE 2 "const48_operand" "I")) 625 (match_operand:I48MODE 3 "reg_or_8bit_operand" "rI")))] 626 "" 627 "s%2sub<modesuffix> %1,%3,%0") 628 629(define_insn "*ssubl_se" 630 [(set (match_operand:DI 0 "register_operand" "=r") 631 (sign_extend:DI 632 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r") 633 (match_operand:SI 2 "const48_operand" "I")) 634 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))] 635 "" 636 "s%2subl %1,%3,%0") 637 638(define_insn "subv<mode>3" 639 [(set (match_operand:I48MODE 0 "register_operand" "=r") 640 (minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ") 641 (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI"))) 642 (trap_if (ne (minus:<DWI> (sign_extend:<DWI> (match_dup 1)) 643 (sign_extend:<DWI> (match_dup 2))) 644 (sign_extend:<DWI> (minus:I48MODE (match_dup 1) 645 (match_dup 2)))) 646 (const_int 0))] 647 "" 648 "sub<modesuffix>v %r1,%2,%0") 649 650(define_insn "mul<mode>3" 651 [(set (match_operand:I48MODE 0 "register_operand" "=r") 652 (mult:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ") 653 (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))] 654 "" 655 "mul<modesuffix> %r1,%2,%0" 656 [(set_attr "type" "imul") 657 (set_attr "opsize" "<mode>")]) 658 659(define_insn "*mulsi_se" 660 [(set (match_operand:DI 0 "register_operand" "=r") 661 (sign_extend:DI 662 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") 663 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))] 664 "" 665 "mull %r1,%2,%0" 666 [(set_attr "type" "imul") 667 (set_attr "opsize" "si")]) 668 669(define_insn "mulv<mode>3" 670 [(set (match_operand:I48MODE 0 "register_operand" "=r") 671 (mult:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ") 672 (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI"))) 673 (trap_if (ne (mult:<DWI> (sign_extend:<DWI> (match_dup 1)) 674 (sign_extend:<DWI> (match_dup 2))) 675 (sign_extend:<DWI> (mult:I48MODE (match_dup 1) 676 (match_dup 2)))) 677 (const_int 0))] 678 "" 679 "mul<modesuffix>v %r1,%2,%0" 680 [(set_attr "type" "imul") 681 (set_attr "opsize" "<mode>")]) 682 683(define_expand "umuldi3_highpart" 684 [(set (match_operand:DI 0 "register_operand") 685 (truncate:DI 686 (lshiftrt:TI 687 (mult:TI (zero_extend:TI 688 (match_operand:DI 1 "register_operand")) 689 (match_operand:DI 2 "reg_or_8bit_operand")) 690 (const_int 64))))] 691 "" 692{ 693 if (REG_P (operands[2])) 694 operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]); 695}) 696 697(define_insn "*umuldi3_highpart_reg" 698 [(set (match_operand:DI 0 "register_operand" "=r") 699 (truncate:DI 700 (lshiftrt:TI 701 (mult:TI (zero_extend:TI 702 (match_operand:DI 1 "register_operand" "r")) 703 (zero_extend:TI 704 (match_operand:DI 2 "register_operand" "r"))) 705 (const_int 64))))] 706 "" 707 "umulh %1,%2,%0" 708 [(set_attr "type" "imul") 709 (set_attr "opsize" "udi")]) 710 711(define_insn "*umuldi3_highpart_const" 712 [(set (match_operand:DI 0 "register_operand" "=r") 713 (truncate:DI 714 (lshiftrt:TI 715 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r")) 716 (match_operand:TI 2 "cint8_operand" "I")) 717 (const_int 64))))] 718 "" 719 "umulh %1,%2,%0" 720 [(set_attr "type" "imul") 721 (set_attr "opsize" "udi")]) 722 723(define_expand "umulditi3" 724 [(set (match_operand:TI 0 "register_operand") 725 (mult:TI 726 (zero_extend:TI (match_operand:DI 1 "reg_no_subreg_operand")) 727 (zero_extend:TI (match_operand:DI 2 "reg_no_subreg_operand"))))] 728 "" 729{ 730 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode); 731 emit_insn (gen_muldi3 (l, operands[1], operands[2])); 732 emit_insn (gen_umuldi3_highpart (h, operands[1], operands[2])); 733 emit_move_insn (gen_lowpart (DImode, operands[0]), l); 734 emit_move_insn (gen_highpart (DImode, operands[0]), h); 735 DONE; 736}) 737 738;; The divide and remainder operations take their inputs from r24 and 739;; r25, put their output in r27, and clobber r23 and r28 on all systems. 740;; 741;; ??? Force sign-extension here because some versions of OSF/1 and 742;; Interix/NT don't do the right thing if the inputs are not properly 743;; sign-extended. But Linux, for instance, does not have this 744;; problem. Is it worth the complication here to eliminate the sign 745;; extension? 746 747(define_code_iterator any_divmod [div mod udiv umod]) 748 749(define_expand "<code>si3" 750 [(set (match_dup 3) 751 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"))) 752 (set (match_dup 4) 753 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand"))) 754 (parallel [(set (match_dup 5) 755 (sign_extend:DI 756 (any_divmod:SI (match_dup 3) (match_dup 4)))) 757 (clobber (reg:DI 23)) 758 (clobber (reg:DI 28))]) 759 (set (match_operand:SI 0 "nonimmediate_operand") 760 (subreg:SI (match_dup 5) 0))] 761 "TARGET_ABI_OSF" 762{ 763 operands[3] = gen_reg_rtx (DImode); 764 operands[4] = gen_reg_rtx (DImode); 765 operands[5] = gen_reg_rtx (DImode); 766}) 767 768(define_expand "<code>di3" 769 [(parallel [(set (match_operand:DI 0 "register_operand") 770 (any_divmod:DI 771 (match_operand:DI 1 "register_operand") 772 (match_operand:DI 2 "register_operand"))) 773 (clobber (reg:DI 23)) 774 (clobber (reg:DI 28))])] 775 "TARGET_ABI_OSF") 776 777;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as 778;; expanded by the assembler. 779 780(define_insn_and_split "*divmodsi_internal_er" 781 [(set (match_operand:DI 0 "register_operand" "=c") 782 (sign_extend:DI (match_operator:SI 3 "divmod_operator" 783 [(match_operand:DI 1 "register_operand" "a") 784 (match_operand:DI 2 "register_operand" "b")]))) 785 (clobber (reg:DI 23)) 786 (clobber (reg:DI 28))] 787 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 788 "#" 789 "&& reload_completed" 790 [(parallel [(set (match_dup 0) 791 (sign_extend:DI (match_dup 3))) 792 (use (match_dup 0)) 793 (use (match_dup 4)) 794 (clobber (reg:DI 23)) 795 (clobber (reg:DI 28))])] 796{ 797 const char *str; 798 switch (GET_CODE (operands[3])) 799 { 800 case DIV: 801 str = "__divl"; 802 break; 803 case UDIV: 804 str = "__divlu"; 805 break; 806 case MOD: 807 str = "__reml"; 808 break; 809 case UMOD: 810 str = "__remlu"; 811 break; 812 default: 813 gcc_unreachable (); 814 } 815 operands[4] = GEN_INT (alpha_next_sequence_number++); 816 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx, 817 gen_rtx_SYMBOL_REF (DImode, str), 818 operands[4])); 819} 820 [(set_attr "type" "jsr") 821 (set_attr "length" "8")]) 822 823(define_insn "*divmodsi_internal_er_1" 824 [(set (match_operand:DI 0 "register_operand" "=c") 825 (sign_extend:DI (match_operator:SI 3 "divmod_operator" 826 [(match_operand:DI 1 "register_operand" "a") 827 (match_operand:DI 2 "register_operand" "b")]))) 828 (use (match_operand:DI 4 "register_operand" "c")) 829 (use (match_operand 5 "const_int_operand")) 830 (clobber (reg:DI 23)) 831 (clobber (reg:DI 28))] 832 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 833 "jsr $23,($27),__%E3%j5" 834 [(set_attr "type" "jsr") 835 (set_attr "length" "4")]) 836 837(define_insn "*divmodsi_internal" 838 [(set (match_operand:DI 0 "register_operand" "=c") 839 (sign_extend:DI (match_operator:SI 3 "divmod_operator" 840 [(match_operand:DI 1 "register_operand" "a") 841 (match_operand:DI 2 "register_operand" "b")]))) 842 (clobber (reg:DI 23)) 843 (clobber (reg:DI 28))] 844 "TARGET_ABI_OSF" 845 "%E3 %1,%2,%0" 846 [(set_attr "type" "jsr") 847 (set_attr "length" "8")]) 848 849(define_insn_and_split "*divmoddi_internal_er" 850 [(set (match_operand:DI 0 "register_operand" "=c") 851 (match_operator:DI 3 "divmod_operator" 852 [(match_operand:DI 1 "register_operand" "a") 853 (match_operand:DI 2 "register_operand" "b")])) 854 (clobber (reg:DI 23)) 855 (clobber (reg:DI 28))] 856 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 857 "#" 858 "&& reload_completed" 859 [(parallel [(set (match_dup 0) (match_dup 3)) 860 (use (match_dup 0)) 861 (use (match_dup 4)) 862 (clobber (reg:DI 23)) 863 (clobber (reg:DI 28))])] 864{ 865 const char *str; 866 switch (GET_CODE (operands[3])) 867 { 868 case DIV: 869 str = "__divq"; 870 break; 871 case UDIV: 872 str = "__divqu"; 873 break; 874 case MOD: 875 str = "__remq"; 876 break; 877 case UMOD: 878 str = "__remqu"; 879 break; 880 default: 881 gcc_unreachable (); 882 } 883 operands[4] = GEN_INT (alpha_next_sequence_number++); 884 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx, 885 gen_rtx_SYMBOL_REF (DImode, str), 886 operands[4])); 887} 888 [(set_attr "type" "jsr") 889 (set_attr "length" "8")]) 890 891(define_insn "*divmoddi_internal_er_1" 892 [(set (match_operand:DI 0 "register_operand" "=c") 893 (match_operator:DI 3 "divmod_operator" 894 [(match_operand:DI 1 "register_operand" "a") 895 (match_operand:DI 2 "register_operand" "b")])) 896 (use (match_operand:DI 4 "register_operand" "c")) 897 (use (match_operand 5 "const_int_operand")) 898 (clobber (reg:DI 23)) 899 (clobber (reg:DI 28))] 900 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 901 "jsr $23,($27),__%E3%j5" 902 [(set_attr "type" "jsr") 903 (set_attr "length" "4")]) 904 905(define_insn "*divmoddi_internal" 906 [(set (match_operand:DI 0 "register_operand" "=c") 907 (match_operator:DI 3 "divmod_operator" 908 [(match_operand:DI 1 "register_operand" "a") 909 (match_operand:DI 2 "register_operand" "b")])) 910 (clobber (reg:DI 23)) 911 (clobber (reg:DI 28))] 912 "TARGET_ABI_OSF" 913 "%E3 %1,%2,%0" 914 [(set_attr "type" "jsr") 915 (set_attr "length" "8")]) 916 917;; Next are the basic logical operations. We only expose the DImode operations 918;; to the rtl expanders, but SImode versions exist for combine as well as for 919;; the atomic operation splitters. 920 921(define_insn "*andsi_internal" 922 [(set (match_operand:SI 0 "register_operand" "=r,r,r") 923 (and:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ") 924 (match_operand:SI 2 "and_operand" "rI,N,MH")))] 925 "" 926 "@ 927 and %r1,%2,%0 928 bic %r1,%N2,%0 929 zapnot %r1,%m2,%0" 930 [(set_attr "type" "ilog,ilog,shift")]) 931 932(define_insn "anddi3" 933 [(set (match_operand:DI 0 "register_operand" "=r,r,r") 934 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ") 935 (match_operand:DI 2 "and_operand" "rI,N,MH")))] 936 "" 937 "@ 938 and %r1,%2,%0 939 bic %r1,%N2,%0 940 zapnot %r1,%m2,%0" 941 [(set_attr "type" "ilog,ilog,shift")]) 942 943;; There are times when we can split an AND into two AND insns. This occurs 944;; when we can first clear any bytes and then clear anything else. For 945;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07". 946;; Only do this when running on 64-bit host since the computations are 947;; too messy otherwise. 948 949(define_split 950 [(set (match_operand:DI 0 "register_operand") 951 (and:DI (match_operand:DI 1 "register_operand") 952 (match_operand:DI 2 "const_int_operand")))] 953 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)" 954 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3))) 955 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))] 956{ 957 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]); 958 unsigned HOST_WIDE_INT mask2 = mask1; 959 int i; 960 961 /* For each byte that isn't all zeros, make it all ones. */ 962 for (i = 0; i < 64; i += 8) 963 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0) 964 mask1 |= (HOST_WIDE_INT) 0xff << i; 965 966 /* Now turn on any bits we've just turned off. */ 967 mask2 |= ~ mask1; 968 969 operands[3] = GEN_INT (mask1); 970 operands[4] = GEN_INT (mask2); 971}) 972 973(define_insn "zero_extendqi<mode>2" 974 [(set (match_operand:I248MODE 0 "register_operand" "=r,r") 975 (zero_extend:I248MODE 976 (match_operand:QI 1 "reg_or_bwx_memory_operand" "r,m")))] 977 "" 978 "@ 979 and %1,0xff,%0 980 ldbu %0,%1" 981 [(set_attr "type" "ilog,ild") 982 (set_attr "isa" "*,bwx")]) 983 984(define_insn "zero_extendhi<mode>2" 985 [(set (match_operand:I48MODE 0 "register_operand" "=r,r") 986 (zero_extend:I48MODE 987 (match_operand:HI 1 "reg_or_bwx_memory_operand" "r,m")))] 988 "" 989 "@ 990 zapnot %1,3,%0 991 ldwu %0,%1" 992 [(set_attr "type" "shift,ild") 993 (set_attr "isa" "*,bwx")]) 994 995(define_insn "zero_extendsidi2" 996 [(set (match_operand:DI 0 "register_operand" "=r") 997 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))] 998 "" 999 "zapnot %1,15,%0" 1000 [(set_attr "type" "shift")]) 1001 1002(define_insn "andnot<mode>3" 1003 [(set (match_operand:I48MODE 0 "register_operand" "=r") 1004 (and:I48MODE 1005 (not:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI")) 1006 (match_operand:I48MODE 2 "reg_or_0_operand" "rJ")))] 1007 "" 1008 "bic %r2,%1,%0" 1009 [(set_attr "type" "ilog")]) 1010 1011(define_insn "*iorsi_internal" 1012 [(set (match_operand:SI 0 "register_operand" "=r,r") 1013 (ior:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") 1014 (match_operand:SI 2 "or_operand" "rI,N")))] 1015 "" 1016 "@ 1017 bis %r1,%2,%0 1018 ornot %r1,%N2,%0" 1019 [(set_attr "type" "ilog")]) 1020 1021(define_insn "iordi3" 1022 [(set (match_operand:DI 0 "register_operand" "=r,r") 1023 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 1024 (match_operand:DI 2 "or_operand" "rI,N")))] 1025 "" 1026 "@ 1027 bis %r1,%2,%0 1028 ornot %r1,%N2,%0" 1029 [(set_attr "type" "ilog")]) 1030 1031(define_insn "*one_cmplsi_internal" 1032 [(set (match_operand:SI 0 "register_operand" "=r") 1033 (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))] 1034 "" 1035 "ornot $31,%1,%0" 1036 [(set_attr "type" "ilog")]) 1037 1038(define_insn "one_cmpldi2" 1039 [(set (match_operand:DI 0 "register_operand" "=r") 1040 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))] 1041 "" 1042 "ornot $31,%1,%0" 1043 [(set_attr "type" "ilog")]) 1044 1045(define_insn "*iornot<mode>3" 1046 [(set (match_operand:I48MODE 0 "register_operand" "=r") 1047 (ior:I48MODE 1048 (not:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI")) 1049 (match_operand:I48MODE 2 "reg_or_0_operand" "rJ")))] 1050 "" 1051 "ornot %r2,%1,%0" 1052 [(set_attr "type" "ilog")]) 1053 1054(define_insn "*xorsi_internal" 1055 [(set (match_operand:SI 0 "register_operand" "=r,r") 1056 (xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") 1057 (match_operand:SI 2 "or_operand" "rI,N")))] 1058 "" 1059 "@ 1060 xor %r1,%2,%0 1061 eqv %r1,%N2,%0" 1062 [(set_attr "type" "ilog")]) 1063 1064(define_insn "xordi3" 1065 [(set (match_operand:DI 0 "register_operand" "=r,r") 1066 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 1067 (match_operand:DI 2 "or_operand" "rI,N")))] 1068 "" 1069 "@ 1070 xor %r1,%2,%0 1071 eqv %r1,%N2,%0" 1072 [(set_attr "type" "ilog")]) 1073 1074(define_insn "*xornot<mode>3" 1075 [(set (match_operand:I48MODE 0 "register_operand" "=r") 1076 (not:I48MODE (xor:I48MODE 1077 (match_operand:I48MODE 1 "register_operand" "%rJ") 1078 (match_operand:I48MODE 2 "register_operand" "rI"))))] 1079 "" 1080 "eqv %r1,%2,%0" 1081 [(set_attr "type" "ilog")]) 1082 1083;; Handle FFS and related insns iff we support CIX. 1084 1085(define_expand "ffsdi2" 1086 [(set (match_dup 2) 1087 (ctz:DI (match_operand:DI 1 "register_operand"))) 1088 (set (match_dup 3) 1089 (plus:DI (match_dup 2) (const_int 1))) 1090 (set (match_operand:DI 0 "register_operand") 1091 (if_then_else:DI (eq (match_dup 1) (const_int 0)) 1092 (const_int 0) (match_dup 3)))] 1093 "TARGET_CIX" 1094{ 1095 operands[2] = gen_reg_rtx (DImode); 1096 operands[3] = gen_reg_rtx (DImode); 1097}) 1098 1099(define_insn "clzdi2" 1100 [(set (match_operand:DI 0 "register_operand" "=r") 1101 (clz:DI (match_operand:DI 1 "register_operand" "r")))] 1102 "TARGET_CIX" 1103 "ctlz %1,%0" 1104 [(set_attr "type" "mvi")]) 1105 1106(define_insn "ctzdi2" 1107 [(set (match_operand:DI 0 "register_operand" "=r") 1108 (ctz:DI (match_operand:DI 1 "register_operand" "r")))] 1109 "TARGET_CIX" 1110 "cttz %1,%0" 1111 [(set_attr "type" "mvi")]) 1112 1113(define_insn "popcountdi2" 1114 [(set (match_operand:DI 0 "register_operand" "=r") 1115 (popcount:DI (match_operand:DI 1 "register_operand" "r")))] 1116 "TARGET_CIX" 1117 "ctpop %1,%0" 1118 [(set_attr "type" "mvi")]) 1119 1120(define_expand "bswapsi2" 1121 [(set (match_operand:SI 0 "register_operand") 1122 (bswap:SI (match_operand:SI 1 "register_operand")))] 1123 "!optimize_size" 1124{ 1125 rtx t0, t1; 1126 1127 t0 = gen_reg_rtx (DImode); 1128 t1 = gen_reg_rtx (DImode); 1129 1130 emit_insn (gen_inslh (t0, gen_lowpart (DImode, operands[1]), GEN_INT (7))); 1131 emit_insn (gen_inswl_const (t1, gen_lowpart (HImode, operands[1]), 1132 GEN_INT (24))); 1133 emit_insn (gen_iordi3 (t1, t0, t1)); 1134 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16))); 1135 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x5))); 1136 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xa))); 1137 emit_insn (gen_addsi3 (operands[0], gen_lowpart (SImode, t0), 1138 gen_lowpart (SImode, t1))); 1139 DONE; 1140}) 1141 1142(define_expand "bswapdi2" 1143 [(set (match_operand:DI 0 "register_operand") 1144 (bswap:DI (match_operand:DI 1 "register_operand")))] 1145 "!optimize_size" 1146{ 1147 rtx t0, t1; 1148 1149 t0 = gen_reg_rtx (DImode); 1150 t1 = gen_reg_rtx (DImode); 1151 1152 /* This method of shifting and masking is not specific to Alpha, but 1153 is only profitable on Alpha because of our handy byte zap insn. */ 1154 1155 emit_insn (gen_lshrdi3 (t0, operands[1], GEN_INT (32))); 1156 emit_insn (gen_ashldi3 (t1, operands[1], GEN_INT (32))); 1157 emit_insn (gen_iordi3 (t1, t0, t1)); 1158 1159 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16))); 1160 emit_insn (gen_ashldi3 (t1, t1, GEN_INT (16))); 1161 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xcc))); 1162 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x33))); 1163 emit_insn (gen_iordi3 (t1, t0, t1)); 1164 1165 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (8))); 1166 emit_insn (gen_ashldi3 (t1, t1, GEN_INT (8))); 1167 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xaa))); 1168 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x55))); 1169 emit_insn (gen_iordi3 (operands[0], t0, t1)); 1170 DONE; 1171}) 1172 1173;; Next come the shifts and the various extract and insert operations. 1174 1175(define_insn "ashldi3" 1176 [(set (match_operand:DI 0 "register_operand" "=r,r") 1177 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ") 1178 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))] 1179 "" 1180{ 1181 switch (which_alternative) 1182 { 1183 case 0: 1184 if (operands[2] == const1_rtx) 1185 return "addq %r1,%r1,%0"; 1186 else 1187 return "s%P2addq %r1,0,%0"; 1188 case 1: 1189 return "sll %r1,%2,%0"; 1190 default: 1191 gcc_unreachable (); 1192 } 1193} 1194 [(set_attr "type" "iadd,shift")]) 1195 1196(define_insn "*ashldi_se" 1197 [(set (match_operand:DI 0 "register_operand" "=r") 1198 (sign_extend:DI 1199 (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1200 (match_operand:DI 2 "const_int_operand" "P")) 1201 0)))] 1202 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3" 1203{ 1204 if (operands[2] == const1_rtx) 1205 return "addl %r1,%r1,%0"; 1206 else 1207 return "s%P2addl %r1,0,%0"; 1208} 1209 [(set_attr "type" "iadd")]) 1210 1211(define_insn "lshrdi3" 1212 [(set (match_operand:DI 0 "register_operand" "=r") 1213 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1214 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))] 1215 "" 1216 "srl %r1,%2,%0" 1217 [(set_attr "type" "shift")]) 1218 1219(define_insn "ashrdi3" 1220 [(set (match_operand:DI 0 "register_operand" "=r") 1221 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1222 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))] 1223 "" 1224 "sra %r1,%2,%0" 1225 [(set_attr "type" "shift")]) 1226 1227(define_insn "extendqi<mode>2" 1228 [(set (match_operand:I24MODE 0 "register_operand" "=r") 1229 (sign_extend:I24MODE 1230 (match_operand:QI 1 "register_operand" "r")))] 1231 "TARGET_BWX" 1232 "sextb %1,%0" 1233 [(set_attr "type" "shift")]) 1234 1235(define_expand "extendqidi2" 1236 [(set (match_operand:DI 0 "register_operand") 1237 (sign_extend:DI (match_operand:QI 1 "some_operand")))] 1238 "" 1239{ 1240 if (TARGET_BWX) 1241 operands[1] = force_reg (QImode, operands[1]); 1242 else 1243 { 1244 rtx x, t1, t2, i56; 1245 1246 if (unaligned_memory_operand (operands[1], QImode)) 1247 { 1248 x = gen_unaligned_extendqidi (operands[0], XEXP (operands[1], 0)); 1249 alpha_set_memflags (x, operands[1]); 1250 emit_insn (x); 1251 DONE; 1252 } 1253 1254 t1 = gen_reg_rtx (DImode); 1255 t2 = gen_reg_rtx (DImode); 1256 i56 = GEN_INT (56); 1257 1258 x = gen_lowpart (DImode, force_reg (QImode, operands[1])); 1259 emit_move_insn (t1, x); 1260 emit_insn (gen_ashldi3 (t2, t1, i56)); 1261 emit_insn (gen_ashrdi3 (operands[0], t2, i56)); 1262 DONE; 1263 } 1264}) 1265 1266(define_insn "*extendqidi2_bwx" 1267 [(set (match_operand:DI 0 "register_operand" "=r") 1268 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))] 1269 "TARGET_BWX" 1270 "sextb %1,%0" 1271 [(set_attr "type" "shift")]) 1272 1273(define_insn "extendhisi2" 1274 [(set (match_operand:SI 0 "register_operand" "=r") 1275 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))] 1276 "TARGET_BWX" 1277 "sextw %1,%0" 1278 [(set_attr "type" "shift")]) 1279 1280(define_expand "extendhidi2" 1281 [(set (match_operand:DI 0 "register_operand") 1282 (sign_extend:DI (match_operand:HI 1 "some_operand")))] 1283 "" 1284{ 1285 if (TARGET_BWX) 1286 operands[1] = force_reg (HImode, operands[1]); 1287 else 1288 { 1289 rtx x, t1, t2, i48; 1290 1291 if (unaligned_memory_operand (operands[1], HImode)) 1292 { 1293 x = gen_unaligned_extendhidi (operands[0], XEXP (operands[1], 0)); 1294 alpha_set_memflags (x, operands[1]); 1295 emit_insn (x); 1296 DONE; 1297 } 1298 1299 t1 = gen_reg_rtx (DImode); 1300 t2 = gen_reg_rtx (DImode); 1301 i48 = GEN_INT (48); 1302 1303 x = gen_lowpart (DImode, force_reg (HImode, operands[1])); 1304 emit_move_insn (t1, x); 1305 emit_insn (gen_ashldi3 (t2, t1, i48)); 1306 emit_insn (gen_ashrdi3 (operands[0], t2, i48)); 1307 DONE; 1308 } 1309}) 1310 1311(define_insn "*extendhidi2_bwx" 1312 [(set (match_operand:DI 0 "register_operand" "=r") 1313 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))] 1314 "TARGET_BWX" 1315 "sextw %1,%0" 1316 [(set_attr "type" "shift")]) 1317 1318;; Here's how we sign extend an unaligned byte and halfword. Doing this 1319;; as a pattern saves one instruction. The code is similar to that for 1320;; the unaligned loads (see below). 1321;; 1322;; Operand 1 is the address, operand 0 is the result. 1323 1324(define_expand "unaligned_extendqidi" 1325 [(set (match_dup 3) 1326 (mem:DI (and:DI (match_operand:DI 1 "address_operand") (const_int -8)))) 1327 (set (match_dup 4) 1328 (ashift:DI (match_dup 3) 1329 (minus:DI (const_int 64) 1330 (ashift:DI 1331 (and:DI (match_dup 2) (const_int 7)) 1332 (const_int 3))))) 1333 (set (match_operand:QI 0 "register_operand") 1334 (ashiftrt:DI (match_dup 4) (const_int 56)))] 1335 "" 1336{ 1337 operands[0] = gen_lowpart (DImode, operands[0]); 1338 operands[2] = get_unaligned_offset (operands[1], 1); 1339 operands[3] = gen_reg_rtx (DImode); 1340 operands[4] = gen_reg_rtx (DImode); 1341}) 1342 1343(define_expand "unaligned_extendhidi" 1344 [(set (match_dup 3) 1345 (mem:DI (and:DI (match_operand:DI 1 "address_operand") (const_int -8)))) 1346 (set (match_dup 4) 1347 (ashift:DI (match_dup 3) 1348 (minus:DI (const_int 64) 1349 (ashift:DI 1350 (and:DI (match_dup 2) (const_int 7)) 1351 (const_int 3))))) 1352 (set (match_operand:HI 0 "register_operand") 1353 (ashiftrt:DI (match_dup 4) (const_int 48)))] 1354 "" 1355{ 1356 operands[0] = gen_lowpart (DImode, operands[0]); 1357 operands[2] = get_unaligned_offset (operands[1], 2); 1358 operands[3] = gen_reg_rtx (DImode); 1359 operands[4] = gen_reg_rtx (DImode); 1360}) 1361 1362(define_insn "*extxl_const" 1363 [(set (match_operand:DI 0 "register_operand" "=r") 1364 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1365 (match_operand:DI 2 "mode_width_operand" "n") 1366 (match_operand:DI 3 "mul8_operand" "I")))] 1367 "" 1368 "ext%M2l %r1,%s3,%0" 1369 [(set_attr "type" "shift")]) 1370 1371(define_insn "extxl" 1372 [(set (match_operand:DI 0 "register_operand" "=r") 1373 (zero_extract:DI 1374 (match_operand:DI 1 "reg_or_0_operand" "rJ") 1375 (match_operand:DI 2 "mode_width_operand" "n") 1376 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI") 1377 (const_int 3))))] 1378 "" 1379 "ext%M2l %r1,%3,%0" 1380 [(set_attr "type" "shift")]) 1381 1382;; Combine has some strange notion of preserving existing undefined behavior 1383;; in shifts larger than a word size. So capture these patterns that it 1384;; should have turned into zero_extracts. 1385 1386(define_insn "*extxl_1" 1387 [(set (match_operand:DI 0 "register_operand" "=r") 1388 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1389 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1390 (const_int 3))) 1391 (match_operand:DI 3 "mode_mask_operand" "n")))] 1392 "" 1393 "ext%U3l %1,%2,%0" 1394 [(set_attr "type" "shift")]) 1395 1396(define_insn "*extql_2" 1397 [(set (match_operand:DI 0 "register_operand" "=r") 1398 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1399 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1400 (const_int 3))))] 1401 "" 1402 "extql %1,%2,%0" 1403 [(set_attr "type" "shift")]) 1404 1405(define_insn "extqh" 1406 [(set (match_operand:DI 0 "register_operand" "=r") 1407 (ashift:DI 1408 (match_operand:DI 1 "reg_or_0_operand" "rJ") 1409 (minus:DI (const_int 64) 1410 (ashift:DI 1411 (and:DI 1412 (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1413 (const_int 7)) 1414 (const_int 3)))))] 1415 "" 1416 "extqh %r1,%2,%0" 1417 [(set_attr "type" "shift")]) 1418 1419(define_insn "extwh" 1420 [(set (match_operand:DI 0 "register_operand" "=r") 1421 (ashift:DI 1422 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1423 (const_int 65535)) 1424 (minus:DI (const_int 64) 1425 (ashift:DI 1426 (and:DI 1427 (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1428 (const_int 7)) 1429 (const_int 3)))))] 1430 "" 1431 "extwh %r1,%2,%0" 1432 [(set_attr "type" "shift")]) 1433 1434(define_insn "extlh" 1435 [(set (match_operand:DI 0 "register_operand" "=r") 1436 (ashift:DI 1437 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1438 (const_int 2147483647)) 1439 (minus:DI (const_int 64) 1440 (ashift:DI 1441 (and:DI 1442 (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1443 (const_int 7)) 1444 (const_int 3)))))] 1445 "" 1446 "extlh %r1,%2,%0" 1447 [(set_attr "type" "shift")]) 1448 1449;; This converts an extXl into an extXh with an appropriate adjustment 1450;; to the address calculation. 1451 1452;;(define_split 1453;; [(set (match_operand:DI 0 "register_operand") 1454;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand") 1455;; (match_operand:DI 2 "mode_width_operand") 1456;; (ashift:DI (match_operand:DI 3) 1457;; (const_int 3))) 1458;; (match_operand:DI 4 "const_int_operand"))) 1459;; (clobber (match_operand:DI 5 "register_operand"))] 1460;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])" 1461;; [(set (match_dup 5) (match_dup 6)) 1462;; (set (match_dup 0) 1463;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2) 1464;; (ashift:DI (plus:DI (match_dup 5) 1465;; (match_dup 7)) 1466;; (const_int 3))) 1467;; (match_dup 4)))] 1468;; " 1469;;{ 1470;; operands[6] = plus_constant (DImode, operands[3], 1471;; INTVAL (operands[2]) / BITS_PER_UNIT); 1472;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT); 1473;;}") 1474 1475(define_insn "ins<modesuffix>l_const" 1476 [(set (match_operand:DI 0 "register_operand" "=r") 1477 (ashift:DI (zero_extend:DI 1478 (match_operand:I124MODE 1 "register_operand" "r")) 1479 (match_operand:DI 2 "mul8_operand" "I")))] 1480 "" 1481 "ins<modesuffix>l %1,%s2,%0" 1482 [(set_attr "type" "shift")]) 1483 1484(define_insn "ins<modesuffix>l" 1485 [(set (match_operand:DI 0 "register_operand" "=r") 1486 (ashift:DI (zero_extend:DI 1487 (match_operand:I124MODE 1 "register_operand" "r")) 1488 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1489 (const_int 3))))] 1490 "" 1491 "ins<modesuffix>l %1,%2,%0" 1492 [(set_attr "type" "shift")]) 1493 1494(define_insn "insql" 1495 [(set (match_operand:DI 0 "register_operand" "=r") 1496 (ashift:DI (match_operand:DI 1 "register_operand" "r") 1497 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1498 (const_int 3))))] 1499 "" 1500 "insql %1,%2,%0" 1501 [(set_attr "type" "shift")]) 1502 1503;; Combine has this sometimes habit of moving the and outside of the 1504;; shift, making life more interesting. 1505 1506(define_insn "*insxl" 1507 [(set (match_operand:DI 0 "register_operand" "=r") 1508 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") 1509 (match_operand:DI 2 "mul8_operand" "I")) 1510 (match_operand:DI 3 "immediate_operand" "i")))] 1511 "HOST_BITS_PER_WIDE_INT == 64 1512 && CONST_INT_P (operands[3]) 1513 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2]) 1514 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1515 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2]) 1516 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1517 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2]) 1518 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))" 1519{ 1520#if HOST_BITS_PER_WIDE_INT == 64 1521 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2]) 1522 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1523 return "insbl %1,%s2,%0"; 1524 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2]) 1525 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1526 return "inswl %1,%s2,%0"; 1527 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2]) 1528 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1529 return "insll %1,%s2,%0"; 1530#endif 1531 gcc_unreachable (); 1532} 1533 [(set_attr "type" "shift")]) 1534 1535;; We do not include the insXh insns because they are complex to express 1536;; and it does not appear that we would ever want to generate them. 1537;; 1538;; Since we need them for block moves, though, cop out and use unspec. 1539 1540(define_insn "insxh" 1541 [(set (match_operand:DI 0 "register_operand" "=r") 1542 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 1543 (match_operand:DI 2 "mode_width_operand" "n") 1544 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 1545 UNSPEC_INSXH))] 1546 "" 1547 "ins%M2h %1,%3,%0" 1548 [(set_attr "type" "shift")]) 1549 1550(define_insn "mskxl" 1551 [(set (match_operand:DI 0 "register_operand" "=r") 1552 (and:DI (not:DI (ashift:DI 1553 (match_operand:DI 2 "mode_mask_operand" "n") 1554 (ashift:DI 1555 (match_operand:DI 3 "reg_or_8bit_operand" "rI") 1556 (const_int 3)))) 1557 (match_operand:DI 1 "reg_or_0_operand" "rJ")))] 1558 "" 1559 "msk%U2l %r1,%3,%0" 1560 [(set_attr "type" "shift")]) 1561 1562;; We do not include the mskXh insns because it does not appear we would 1563;; ever generate one. 1564;; 1565;; Again, we do for block moves and we use unspec again. 1566 1567(define_insn "mskxh" 1568 [(set (match_operand:DI 0 "register_operand" "=r") 1569 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 1570 (match_operand:DI 2 "mode_width_operand" "n") 1571 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 1572 UNSPEC_MSKXH))] 1573 "" 1574 "msk%M2h %1,%3,%0" 1575 [(set_attr "type" "shift")]) 1576 1577;; Prefer AND + NE over LSHIFTRT + AND. 1578 1579(define_insn_and_split "*ze_and_ne" 1580 [(set (match_operand:DI 0 "register_operand" "=r") 1581 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1582 (const_int 1) 1583 (match_operand 2 "const_int_operand" "I")))] 1584 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8" 1585 "#" 1586 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8" 1587 [(set (match_dup 0) 1588 (and:DI (match_dup 1) (match_dup 3))) 1589 (set (match_dup 0) 1590 (ne:DI (match_dup 0) (const_int 0)))] 1591 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));") 1592 1593;; Floating-point operations. All the double-precision insns can extend 1594;; from single, so indicate that. The exception are the ones that simply 1595;; play with the sign bits; it's not clear what to do there. 1596 1597(define_mode_iterator FMODE [SF DF]) 1598 1599(define_mode_attr opmode [(SF "si") (DF "di")]) 1600 1601(define_insn "abs<mode>2" 1602 [(set (match_operand:FMODE 0 "register_operand" "=f") 1603 (abs:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))] 1604 "TARGET_FP" 1605 "cpys $f31,%R1,%0" 1606 [(set_attr "type" "fcpys")]) 1607 1608(define_insn "*nabs<mode>2" 1609 [(set (match_operand:FMODE 0 "register_operand" "=f") 1610 (neg:FMODE 1611 (abs:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG"))))] 1612 "TARGET_FP" 1613 "cpysn $f31,%R1,%0" 1614 [(set_attr "type" "fadd")]) 1615 1616(define_expand "abstf2" 1617 [(parallel [(set (match_operand:TF 0 "register_operand") 1618 (abs:TF (match_operand:TF 1 "reg_or_0_operand"))) 1619 (use (match_dup 2))])] 1620 "TARGET_HAS_XFLOATING_LIBS" 1621{ 1622#if HOST_BITS_PER_WIDE_INT >= 64 1623 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63)); 1624#else 1625 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode)); 1626#endif 1627}) 1628 1629(define_insn_and_split "*abstf_internal" 1630 [(set (match_operand:TF 0 "register_operand" "=r") 1631 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG"))) 1632 (use (match_operand:DI 2 "register_operand" "r"))] 1633 "TARGET_HAS_XFLOATING_LIBS" 1634 "#" 1635 "&& reload_completed" 1636 [(const_int 0)] 1637 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;") 1638 1639(define_insn "neg<mode>2" 1640 [(set (match_operand:FMODE 0 "register_operand" "=f") 1641 (neg:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))] 1642 "TARGET_FP" 1643 "cpysn %R1,%R1,%0" 1644 [(set_attr "type" "fadd")]) 1645 1646(define_expand "negtf2" 1647 [(parallel [(set (match_operand:TF 0 "register_operand") 1648 (neg:TF (match_operand:TF 1 "reg_or_0_operand"))) 1649 (use (match_dup 2))])] 1650 "TARGET_HAS_XFLOATING_LIBS" 1651{ 1652#if HOST_BITS_PER_WIDE_INT >= 64 1653 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63)); 1654#else 1655 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode)); 1656#endif 1657}) 1658 1659(define_insn_and_split "*negtf_internal" 1660 [(set (match_operand:TF 0 "register_operand" "=r") 1661 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG"))) 1662 (use (match_operand:DI 2 "register_operand" "r"))] 1663 "TARGET_HAS_XFLOATING_LIBS" 1664 "#" 1665 "&& reload_completed" 1666 [(const_int 0)] 1667 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;") 1668 1669(define_insn "copysign<mode>3" 1670 [(set (match_operand:FMODE 0 "register_operand" "=f") 1671 (unspec:FMODE [(match_operand:FMODE 1 "reg_or_0_operand" "fG") 1672 (match_operand:FMODE 2 "reg_or_0_operand" "fG")] 1673 UNSPEC_COPYSIGN))] 1674 "TARGET_FP" 1675 "cpys %R2,%R1,%0" 1676 [(set_attr "type" "fadd")]) 1677 1678(define_insn "*ncopysign<mode>3" 1679 [(set (match_operand:FMODE 0 "register_operand" "=f") 1680 (neg:FMODE 1681 (unspec:FMODE [(match_operand:FMODE 1 "reg_or_0_operand" "fG") 1682 (match_operand:FMODE 2 "reg_or_0_operand" "fG")] 1683 UNSPEC_COPYSIGN)))] 1684 "TARGET_FP" 1685 "cpysn %R2,%R1,%0" 1686 [(set_attr "type" "fadd")]) 1687 1688(define_insn "*add<mode>3_ieee" 1689 [(set (match_operand:FMODE 0 "register_operand" "=&f") 1690 (plus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG") 1691 (match_operand:FMODE 2 "reg_or_0_operand" "fG")))] 1692 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 1693 "add<modesuffix>%/ %R1,%R2,%0" 1694 [(set_attr "type" "fadd") 1695 (set_attr "trap" "yes") 1696 (set_attr "round_suffix" "normal") 1697 (set_attr "trap_suffix" "u_su_sui")]) 1698 1699(define_insn "add<mode>3" 1700 [(set (match_operand:FMODE 0 "register_operand" "=f") 1701 (plus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG") 1702 (match_operand:FMODE 2 "reg_or_0_operand" "fG")))] 1703 "TARGET_FP" 1704 "add<modesuffix>%/ %R1,%R2,%0" 1705 [(set_attr "type" "fadd") 1706 (set_attr "trap" "yes") 1707 (set_attr "round_suffix" "normal") 1708 (set_attr "trap_suffix" "u_su_sui")]) 1709 1710(define_insn "*adddf_ext1" 1711 [(set (match_operand:DF 0 "register_operand" "=f") 1712 (plus:DF (float_extend:DF 1713 (match_operand:SF 1 "reg_or_0_operand" "fG")) 1714 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1715 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1716 "add%-%/ %R1,%R2,%0" 1717 [(set_attr "type" "fadd") 1718 (set_attr "trap" "yes") 1719 (set_attr "round_suffix" "normal") 1720 (set_attr "trap_suffix" "u_su_sui")]) 1721 1722(define_insn "*adddf_ext2" 1723 [(set (match_operand:DF 0 "register_operand" "=f") 1724 (plus:DF (float_extend:DF 1725 (match_operand:SF 1 "reg_or_0_operand" "%fG")) 1726 (float_extend:DF 1727 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1728 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1729 "add%-%/ %R1,%R2,%0" 1730 [(set_attr "type" "fadd") 1731 (set_attr "trap" "yes") 1732 (set_attr "round_suffix" "normal") 1733 (set_attr "trap_suffix" "u_su_sui")]) 1734 1735(define_expand "addtf3" 1736 [(use (match_operand:TF 0 "register_operand")) 1737 (use (match_operand:TF 1 "general_operand")) 1738 (use (match_operand:TF 2 "general_operand"))] 1739 "TARGET_HAS_XFLOATING_LIBS" 1740 "alpha_emit_xfloating_arith (PLUS, operands); DONE;") 1741 1742(define_insn "*sub<mode>3_ieee" 1743 [(set (match_operand:FMODE 0 "register_operand" "=&f") 1744 (minus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG") 1745 (match_operand:FMODE 2 "reg_or_0_operand" "fG")))] 1746 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 1747 "sub<modesuffix>%/ %R1,%R2,%0" 1748 [(set_attr "type" "fadd") 1749 (set_attr "trap" "yes") 1750 (set_attr "round_suffix" "normal") 1751 (set_attr "trap_suffix" "u_su_sui")]) 1752 1753(define_insn "sub<mode>3" 1754 [(set (match_operand:FMODE 0 "register_operand" "=f") 1755 (minus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG") 1756 (match_operand:FMODE 2 "reg_or_0_operand" "fG")))] 1757 "TARGET_FP" 1758 "sub<modesuffix>%/ %R1,%R2,%0" 1759 [(set_attr "type" "fadd") 1760 (set_attr "trap" "yes") 1761 (set_attr "round_suffix" "normal") 1762 (set_attr "trap_suffix" "u_su_sui")]) 1763 1764(define_insn "*subdf_ext1" 1765 [(set (match_operand:DF 0 "register_operand" "=f") 1766 (minus:DF (float_extend:DF 1767 (match_operand:SF 1 "reg_or_0_operand" "fG")) 1768 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1769 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1770 "sub%-%/ %R1,%R2,%0" 1771 [(set_attr "type" "fadd") 1772 (set_attr "trap" "yes") 1773 (set_attr "round_suffix" "normal") 1774 (set_attr "trap_suffix" "u_su_sui")]) 1775 1776(define_insn "*subdf_ext2" 1777 [(set (match_operand:DF 0 "register_operand" "=f") 1778 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG") 1779 (float_extend:DF 1780 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1781 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1782 "sub%-%/ %R1,%R2,%0" 1783 [(set_attr "type" "fadd") 1784 (set_attr "trap" "yes") 1785 (set_attr "round_suffix" "normal") 1786 (set_attr "trap_suffix" "u_su_sui")]) 1787 1788(define_insn "*subdf_ext3" 1789 [(set (match_operand:DF 0 "register_operand" "=f") 1790 (minus:DF (float_extend:DF 1791 (match_operand:SF 1 "reg_or_0_operand" "fG")) 1792 (float_extend:DF 1793 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1794 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1795 "sub%-%/ %R1,%R2,%0" 1796 [(set_attr "type" "fadd") 1797 (set_attr "trap" "yes") 1798 (set_attr "round_suffix" "normal") 1799 (set_attr "trap_suffix" "u_su_sui")]) 1800 1801(define_expand "subtf3" 1802 [(use (match_operand:TF 0 "register_operand")) 1803 (use (match_operand:TF 1 "general_operand")) 1804 (use (match_operand:TF 2 "general_operand"))] 1805 "TARGET_HAS_XFLOATING_LIBS" 1806 "alpha_emit_xfloating_arith (MINUS, operands); DONE;") 1807 1808(define_insn "*mul<mode>3_ieee" 1809 [(set (match_operand:FMODE 0 "register_operand" "=&f") 1810 (mult:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG") 1811 (match_operand:FMODE 2 "reg_or_0_operand" "fG")))] 1812 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 1813 "mul<modesuffix>%/ %R1,%R2,%0" 1814 [(set_attr "type" "fmul") 1815 (set_attr "trap" "yes") 1816 (set_attr "round_suffix" "normal") 1817 (set_attr "trap_suffix" "u_su_sui")]) 1818 1819(define_insn "mul<mode>3" 1820 [(set (match_operand:FMODE 0 "register_operand" "=f") 1821 (mult:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG") 1822 (match_operand:FMODE 2 "reg_or_0_operand" "fG")))] 1823 "TARGET_FP" 1824 "mul<modesuffix>%/ %R1,%R2,%0" 1825 [(set_attr "type" "fmul") 1826 (set_attr "trap" "yes") 1827 (set_attr "round_suffix" "normal") 1828 (set_attr "trap_suffix" "u_su_sui")]) 1829 1830(define_insn "*muldf_ext1" 1831 [(set (match_operand:DF 0 "register_operand" "=f") 1832 (mult:DF (float_extend:DF 1833 (match_operand:SF 1 "reg_or_0_operand" "fG")) 1834 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1835 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1836 "mul%-%/ %R1,%R2,%0" 1837 [(set_attr "type" "fmul") 1838 (set_attr "trap" "yes") 1839 (set_attr "round_suffix" "normal") 1840 (set_attr "trap_suffix" "u_su_sui")]) 1841 1842(define_insn "*muldf_ext2" 1843 [(set (match_operand:DF 0 "register_operand" "=f") 1844 (mult:DF (float_extend:DF 1845 (match_operand:SF 1 "reg_or_0_operand" "%fG")) 1846 (float_extend:DF 1847 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1848 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1849 "mul%-%/ %R1,%R2,%0" 1850 [(set_attr "type" "fmul") 1851 (set_attr "trap" "yes") 1852 (set_attr "round_suffix" "normal") 1853 (set_attr "trap_suffix" "u_su_sui")]) 1854 1855(define_expand "multf3" 1856 [(use (match_operand:TF 0 "register_operand")) 1857 (use (match_operand:TF 1 "general_operand")) 1858 (use (match_operand:TF 2 "general_operand"))] 1859 "TARGET_HAS_XFLOATING_LIBS" 1860 "alpha_emit_xfloating_arith (MULT, operands); DONE;") 1861 1862(define_insn "*div<mode>3_ieee" 1863 [(set (match_operand:FMODE 0 "register_operand" "=&f") 1864 (div:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG") 1865 (match_operand:FMODE 2 "reg_or_0_operand" "fG")))] 1866 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 1867 "div<modesuffix>%/ %R1,%R2,%0" 1868 [(set_attr "type" "fdiv") 1869 (set_attr "opsize" "<opmode>") 1870 (set_attr "trap" "yes") 1871 (set_attr "round_suffix" "normal") 1872 (set_attr "trap_suffix" "u_su_sui")]) 1873 1874(define_insn "div<mode>3" 1875 [(set (match_operand:FMODE 0 "register_operand" "=f") 1876 (div:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG") 1877 (match_operand:FMODE 2 "reg_or_0_operand" "fG")))] 1878 "TARGET_FP" 1879 "div<modesuffix>%/ %R1,%R2,%0" 1880 [(set_attr "type" "fdiv") 1881 (set_attr "opsize" "<opmode>") 1882 (set_attr "trap" "yes") 1883 (set_attr "round_suffix" "normal") 1884 (set_attr "trap_suffix" "u_su_sui")]) 1885 1886(define_insn "*divdf_ext1" 1887 [(set (match_operand:DF 0 "register_operand" "=f") 1888 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG")) 1889 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1890 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1891 "div%-%/ %R1,%R2,%0" 1892 [(set_attr "type" "fdiv") 1893 (set_attr "trap" "yes") 1894 (set_attr "round_suffix" "normal") 1895 (set_attr "trap_suffix" "u_su_sui")]) 1896 1897(define_insn "*divdf_ext2" 1898 [(set (match_operand:DF 0 "register_operand" "=f") 1899 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG") 1900 (float_extend:DF 1901 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1902 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1903 "div%-%/ %R1,%R2,%0" 1904 [(set_attr "type" "fdiv") 1905 (set_attr "trap" "yes") 1906 (set_attr "round_suffix" "normal") 1907 (set_attr "trap_suffix" "u_su_sui")]) 1908 1909(define_insn "*divdf_ext3" 1910 [(set (match_operand:DF 0 "register_operand" "=f") 1911 (div:DF (float_extend:DF 1912 (match_operand:SF 1 "reg_or_0_operand" "fG")) 1913 (float_extend:DF 1914 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1915 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1916 "div%-%/ %R1,%R2,%0" 1917 [(set_attr "type" "fdiv") 1918 (set_attr "trap" "yes") 1919 (set_attr "round_suffix" "normal") 1920 (set_attr "trap_suffix" "u_su_sui")]) 1921 1922(define_expand "divtf3" 1923 [(use (match_operand:TF 0 "register_operand")) 1924 (use (match_operand:TF 1 "general_operand")) 1925 (use (match_operand:TF 2 "general_operand"))] 1926 "TARGET_HAS_XFLOATING_LIBS" 1927 "alpha_emit_xfloating_arith (DIV, operands); DONE;") 1928 1929(define_insn "*sqrt<mode>2_ieee" 1930 [(set (match_operand:FMODE 0 "register_operand" "=&f") 1931 (sqrt:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))] 1932 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU" 1933 "sqrt<modesuffix>%/ %R1,%0" 1934 [(set_attr "type" "fsqrt") 1935 (set_attr "opsize" "<opmode>") 1936 (set_attr "trap" "yes") 1937 (set_attr "round_suffix" "normal") 1938 (set_attr "trap_suffix" "u_su_sui")]) 1939 1940(define_insn "sqrt<mode>2" 1941 [(set (match_operand:FMODE 0 "register_operand" "=f") 1942 (sqrt:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))] 1943 "TARGET_FP && TARGET_FIX" 1944 "sqrt<modesuffix>%/ %R1,%0" 1945 [(set_attr "type" "fsqrt") 1946 (set_attr "opsize" "<opmode>") 1947 (set_attr "trap" "yes") 1948 (set_attr "round_suffix" "normal") 1949 (set_attr "trap_suffix" "u_su_sui")]) 1950 1951;; Define conversion operators between DFmode and SImode, using the cvtql 1952;; instruction. To allow combine et al to do useful things, we keep the 1953;; operation as a unit until after reload, at which point we split the 1954;; instructions. 1955;; 1956;; Note that we (attempt to) only consider this optimization when the 1957;; ultimate destination is memory. If we will be doing further integer 1958;; processing, it is cheaper to do the truncation in the int regs. 1959 1960(define_insn "*cvtql" 1961 [(set (match_operand:SF 0 "register_operand" "=f") 1962 (unspec:SF [(match_operand:DI 1 "reg_or_0_operand" "fG")] 1963 UNSPEC_CVTQL))] 1964 "TARGET_FP" 1965 "cvtql%/ %R1,%0" 1966 [(set_attr "type" "fadd") 1967 (set_attr "trap" "yes") 1968 (set_attr "trap_suffix" "v_sv")]) 1969 1970(define_insn_and_split "*fix_truncdfsi_ieee" 1971 [(set (match_operand:SI 0 "memory_operand" "=m") 1972 (subreg:SI 1973 (match_operator:DI 4 "fix_operator" 1974 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0)) 1975 (clobber (match_scratch:DI 2 "=&f")) 1976 (clobber (match_scratch:SF 3 "=&f"))] 1977 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 1978 "#" 1979 "&& reload_completed" 1980 [(set (match_dup 2) (match_op_dup 4 [(match_dup 1)])) 1981 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 1982 (set (match_dup 5) (match_dup 3))] 1983{ 1984 operands[5] = adjust_address (operands[0], SFmode, 0); 1985} 1986 [(set_attr "type" "fadd") 1987 (set_attr "trap" "yes")]) 1988 1989(define_insn_and_split "*fix_truncdfsi_internal" 1990 [(set (match_operand:SI 0 "memory_operand" "=m") 1991 (subreg:SI 1992 (match_operator:DI 3 "fix_operator" 1993 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0)) 1994 (clobber (match_scratch:DI 2 "=f"))] 1995 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1996 "#" 1997 "&& reload_completed" 1998 [(set (match_dup 2) (match_op_dup 3 [(match_dup 1)])) 1999 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 2000 (set (match_dup 5) (match_dup 4))] 2001{ 2002 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2])); 2003 operands[5] = adjust_address (operands[0], SFmode, 0); 2004} 2005 [(set_attr "type" "fadd") 2006 (set_attr "trap" "yes")]) 2007 2008(define_insn "*fix_truncdfdi_ieee" 2009 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f") 2010 (match_operator:DI 2 "fix_operator" 2011 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))] 2012 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2013 "cvt%-q%/ %R1,%0" 2014 [(set_attr "type" "fadd") 2015 (set_attr "trap" "yes") 2016 (set_attr "round_suffix" "c") 2017 (set_attr "trap_suffix" "v_sv_svi")]) 2018 2019(define_insn "*fix_truncdfdi2" 2020 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f") 2021 (match_operator:DI 2 "fix_operator" 2022 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))] 2023 "TARGET_FP" 2024 "cvt%-q%/ %R1,%0" 2025 [(set_attr "type" "fadd") 2026 (set_attr "trap" "yes") 2027 (set_attr "round_suffix" "c") 2028 (set_attr "trap_suffix" "v_sv_svi")]) 2029 2030(define_expand "fix_truncdfdi2" 2031 [(set (match_operand:DI 0 "reg_no_subreg_operand") 2032 (fix:DI (match_operand:DF 1 "reg_or_0_operand")))] 2033 "TARGET_FP") 2034 2035(define_expand "fixuns_truncdfdi2" 2036 [(set (match_operand:DI 0 "reg_no_subreg_operand") 2037 (unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand")))] 2038 "TARGET_FP") 2039 2040;; Likewise between SFmode and SImode. 2041 2042(define_insn_and_split "*fix_truncsfsi_ieee" 2043 [(set (match_operand:SI 0 "memory_operand" "=m") 2044 (subreg:SI 2045 (match_operator:DI 4 "fix_operator" 2046 [(float_extend:DF 2047 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0)) 2048 (clobber (match_scratch:DI 2 "=&f")) 2049 (clobber (match_scratch:SF 3 "=&f"))] 2050 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2051 "#" 2052 "&& reload_completed" 2053 [(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))])) 2054 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 2055 (set (match_dup 5) (match_dup 3))] 2056 "operands[5] = adjust_address (operands[0], SFmode, 0);" 2057 [(set_attr "type" "fadd") 2058 (set_attr "trap" "yes")]) 2059 2060(define_insn_and_split "*fix_truncsfsi_internal" 2061 [(set (match_operand:SI 0 "memory_operand" "=m") 2062 (subreg:SI 2063 (match_operator:DI 3 "fix_operator" 2064 [(float_extend:DF 2065 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0)) 2066 (clobber (match_scratch:DI 2 "=f"))] 2067 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2068 "#" 2069 "&& reload_completed" 2070 [(set (match_dup 2) (match_op_dup 3 [(float_extend:DF (match_dup 1))])) 2071 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 2072 (set (match_dup 5) (match_dup 4))] 2073{ 2074 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2])); 2075 operands[5] = adjust_address (operands[0], SFmode, 0); 2076} 2077 [(set_attr "type" "fadd") 2078 (set_attr "trap" "yes")]) 2079 2080(define_insn "*fix_truncsfdi_ieee" 2081 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f") 2082 (match_operator:DI 2 "fix_operator" 2083 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))] 2084 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2085 "cvt%-q%/ %R1,%0" 2086 [(set_attr "type" "fadd") 2087 (set_attr "trap" "yes") 2088 (set_attr "round_suffix" "c") 2089 (set_attr "trap_suffix" "v_sv_svi")]) 2090 2091(define_insn "*fix_truncsfdi2" 2092 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f") 2093 (match_operator:DI 2 "fix_operator" 2094 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))] 2095 "TARGET_FP" 2096 "cvt%-q%/ %R1,%0" 2097 [(set_attr "type" "fadd") 2098 (set_attr "trap" "yes") 2099 (set_attr "round_suffix" "c") 2100 (set_attr "trap_suffix" "v_sv_svi")]) 2101 2102(define_expand "fix_truncsfdi2" 2103 [(set (match_operand:DI 0 "reg_no_subreg_operand") 2104 (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))))] 2105 "TARGET_FP") 2106 2107(define_expand "fixuns_truncsfdi2" 2108 [(set (match_operand:DI 0 "reg_no_subreg_operand") 2109 (unsigned_fix:DI 2110 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))))] 2111 "TARGET_FP") 2112 2113(define_expand "fix_trunctfdi2" 2114 [(use (match_operand:DI 0 "register_operand")) 2115 (use (match_operand:TF 1 "general_operand"))] 2116 "TARGET_HAS_XFLOATING_LIBS" 2117 "alpha_emit_xfloating_cvt (FIX, operands); DONE;") 2118 2119(define_expand "fixuns_trunctfdi2" 2120 [(use (match_operand:DI 0 "register_operand")) 2121 (use (match_operand:TF 1 "general_operand"))] 2122 "TARGET_HAS_XFLOATING_LIBS" 2123 "alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;") 2124 2125(define_insn "*floatdisf_ieee" 2126 [(set (match_operand:SF 0 "register_operand" "=&f") 2127 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))] 2128 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2129 "cvtq%,%/ %1,%0" 2130 [(set_attr "type" "fadd") 2131 (set_attr "trap" "yes") 2132 (set_attr "round_suffix" "normal") 2133 (set_attr "trap_suffix" "sui")]) 2134 2135(define_insn "floatdisf2" 2136 [(set (match_operand:SF 0 "register_operand" "=f") 2137 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))] 2138 "TARGET_FP" 2139 "cvtq%,%/ %1,%0" 2140 [(set_attr "type" "fadd") 2141 (set_attr "trap" "yes") 2142 (set_attr "round_suffix" "normal") 2143 (set_attr "trap_suffix" "sui")]) 2144 2145(define_insn_and_split "*floatsisf2_ieee" 2146 [(set (match_operand:SF 0 "register_operand" "=&f") 2147 (float:SF (match_operand:SI 1 "memory_operand" "m"))) 2148 (clobber (match_scratch:DI 2 "=&f")) 2149 (clobber (match_scratch:SF 3 "=&f"))] 2150 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2151 "#" 2152 "&& reload_completed" 2153 [(set (match_dup 3) (match_dup 1)) 2154 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) 2155 (set (match_dup 0) (float:SF (match_dup 2)))] 2156 "operands[1] = adjust_address (operands[1], SFmode, 0);") 2157 2158(define_insn_and_split "*floatsisf2" 2159 [(set (match_operand:SF 0 "register_operand" "=f") 2160 (float:SF (match_operand:SI 1 "memory_operand" "m")))] 2161 "TARGET_FP" 2162 "#" 2163 "&& reload_completed" 2164 [(set (match_dup 0) (match_dup 1)) 2165 (set (match_dup 2) (unspec:DI [(match_dup 0)] UNSPEC_CVTLQ)) 2166 (set (match_dup 0) (float:SF (match_dup 2)))] 2167{ 2168 operands[1] = adjust_address (operands[1], SFmode, 0); 2169 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0])); 2170}) 2171 2172(define_insn "*floatdidf_ieee" 2173 [(set (match_operand:DF 0 "register_operand" "=&f") 2174 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))] 2175 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2176 "cvtq%-%/ %1,%0" 2177 [(set_attr "type" "fadd") 2178 (set_attr "trap" "yes") 2179 (set_attr "round_suffix" "normal") 2180 (set_attr "trap_suffix" "sui")]) 2181 2182(define_insn "floatdidf2" 2183 [(set (match_operand:DF 0 "register_operand" "=f") 2184 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))] 2185 "TARGET_FP" 2186 "cvtq%-%/ %1,%0" 2187 [(set_attr "type" "fadd") 2188 (set_attr "trap" "yes") 2189 (set_attr "round_suffix" "normal") 2190 (set_attr "trap_suffix" "sui")]) 2191 2192(define_insn_and_split "*floatsidf2_ieee" 2193 [(set (match_operand:DF 0 "register_operand" "=&f") 2194 (float:DF (match_operand:SI 1 "memory_operand" "m"))) 2195 (clobber (match_scratch:DI 2 "=&f")) 2196 (clobber (match_scratch:SF 3 "=&f"))] 2197 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2198 "#" 2199 "&& reload_completed" 2200 [(set (match_dup 3) (match_dup 1)) 2201 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) 2202 (set (match_dup 0) (float:DF (match_dup 2)))] 2203 "operands[1] = adjust_address (operands[1], SFmode, 0);") 2204 2205(define_insn_and_split "*floatsidf2" 2206 [(set (match_operand:DF 0 "register_operand" "=f") 2207 (float:DF (match_operand:SI 1 "memory_operand" "m")))] 2208 "TARGET_FP" 2209 "#" 2210 "&& reload_completed" 2211 [(set (match_dup 3) (match_dup 1)) 2212 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) 2213 (set (match_dup 0) (float:DF (match_dup 2)))] 2214{ 2215 operands[1] = adjust_address (operands[1], SFmode, 0); 2216 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0])); 2217 operands[3] = gen_rtx_REG (SFmode, REGNO (operands[0])); 2218}) 2219 2220(define_expand "floatditf2" 2221 [(use (match_operand:TF 0 "register_operand")) 2222 (use (match_operand:DI 1 "general_operand"))] 2223 "TARGET_HAS_XFLOATING_LIBS" 2224 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;") 2225 2226(define_expand "floatunsdisf2" 2227 [(use (match_operand:SF 0 "register_operand")) 2228 (use (match_operand:DI 1 "register_operand"))] 2229 "TARGET_FP" 2230 "alpha_emit_floatuns (operands); DONE;") 2231 2232(define_expand "floatunsdidf2" 2233 [(use (match_operand:DF 0 "register_operand")) 2234 (use (match_operand:DI 1 "register_operand"))] 2235 "TARGET_FP" 2236 "alpha_emit_floatuns (operands); DONE;") 2237 2238(define_expand "floatunsditf2" 2239 [(use (match_operand:TF 0 "register_operand")) 2240 (use (match_operand:DI 1 "general_operand"))] 2241 "TARGET_HAS_XFLOATING_LIBS" 2242 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;") 2243 2244(define_expand "extendsfdf2" 2245 [(set (match_operand:DF 0 "register_operand") 2246 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand")))] 2247 "TARGET_FP" 2248{ 2249 if (alpha_fptm >= ALPHA_FPTM_SU) 2250 operands[1] = force_reg (SFmode, operands[1]); 2251}) 2252 2253;; The Unicos/Mk assembler doesn't support cvtst, but we've already 2254;; asserted that alpha_fptm == ALPHA_FPTM_N. 2255 2256(define_insn "*extendsfdf2_ieee" 2257 [(set (match_operand:DF 0 "register_operand" "=&f") 2258 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))] 2259 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2260 "cvtsts %1,%0" 2261 [(set_attr "type" "fadd") 2262 (set_attr "trap" "yes")]) 2263 2264(define_insn "*extendsfdf2_internal" 2265 [(set (match_operand:DF 0 "register_operand" "=f,f,m") 2266 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))] 2267 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2268 "@ 2269 cpys %1,%1,%0 2270 ld%, %0,%1 2271 st%- %1,%0" 2272 [(set_attr "type" "fcpys,fld,fst")]) 2273 2274;; Use register_operand for operand 1 to prevent compress_float_constant 2275;; from doing something silly. When optimizing we'll put things back 2276;; together anyway. 2277(define_expand "extendsftf2" 2278 [(use (match_operand:TF 0 "register_operand")) 2279 (use (match_operand:SF 1 "register_operand"))] 2280 "TARGET_HAS_XFLOATING_LIBS" 2281{ 2282 rtx tmp = gen_reg_rtx (DFmode); 2283 emit_insn (gen_extendsfdf2 (tmp, operands[1])); 2284 emit_insn (gen_extenddftf2 (operands[0], tmp)); 2285 DONE; 2286}) 2287 2288(define_expand "extenddftf2" 2289 [(use (match_operand:TF 0 "register_operand")) 2290 (use (match_operand:DF 1 "register_operand"))] 2291 "TARGET_HAS_XFLOATING_LIBS" 2292 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;") 2293 2294(define_insn "*truncdfsf2_ieee" 2295 [(set (match_operand:SF 0 "register_operand" "=&f") 2296 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))] 2297 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2298 "cvt%-%,%/ %R1,%0" 2299 [(set_attr "type" "fadd") 2300 (set_attr "trap" "yes") 2301 (set_attr "round_suffix" "normal") 2302 (set_attr "trap_suffix" "u_su_sui")]) 2303 2304(define_insn "truncdfsf2" 2305 [(set (match_operand:SF 0 "register_operand" "=f") 2306 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))] 2307 "TARGET_FP" 2308 "cvt%-%,%/ %R1,%0" 2309 [(set_attr "type" "fadd") 2310 (set_attr "trap" "yes") 2311 (set_attr "round_suffix" "normal") 2312 (set_attr "trap_suffix" "u_su_sui")]) 2313 2314(define_expand "trunctfdf2" 2315 [(use (match_operand:DF 0 "register_operand")) 2316 (use (match_operand:TF 1 "general_operand"))] 2317 "TARGET_HAS_XFLOATING_LIBS" 2318 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;") 2319 2320(define_expand "trunctfsf2" 2321 [(use (match_operand:SF 0 "register_operand")) 2322 (use (match_operand:TF 1 "general_operand"))] 2323 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS" 2324{ 2325 rtx tmpf, sticky, arg, lo, hi; 2326 2327 tmpf = gen_reg_rtx (DFmode); 2328 sticky = gen_reg_rtx (DImode); 2329 arg = copy_to_mode_reg (TFmode, operands[1]); 2330 lo = gen_lowpart (DImode, arg); 2331 hi = gen_highpart (DImode, arg); 2332 2333 /* Convert the low word of the TFmode value into a sticky rounding bit, 2334 then or it into the low bit of the high word. This leaves the sticky 2335 bit at bit 48 of the fraction, which is representable in DFmode, 2336 which prevents rounding error in the final conversion to SFmode. */ 2337 2338 emit_insn (gen_rtx_SET (VOIDmode, sticky, 2339 gen_rtx_NE (DImode, lo, const0_rtx))); 2340 emit_insn (gen_iordi3 (hi, hi, sticky)); 2341 emit_insn (gen_trunctfdf2 (tmpf, arg)); 2342 emit_insn (gen_truncdfsf2 (operands[0], tmpf)); 2343 DONE; 2344}) 2345 2346;; Next are all the integer comparisons, and conditional moves and branches 2347;; and some of the related define_expand's and define_split's. 2348 2349(define_insn "*setcc_internal" 2350 [(set (match_operand 0 "register_operand" "=r") 2351 (match_operator 1 "alpha_comparison_operator" 2352 [(match_operand:DI 2 "register_operand" "r") 2353 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))] 2354 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT 2355 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8 2356 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 2357 "cmp%C1 %2,%3,%0" 2358 [(set_attr "type" "icmp")]) 2359 2360;; Yes, we can technically support reg_or_8bit_operand in operand 2, 2361;; but that's non-canonical rtl and allowing that causes inefficiencies 2362;; from cse on. 2363(define_insn "*setcc_swapped_internal" 2364 [(set (match_operand 0 "register_operand" "=r") 2365 (match_operator 1 "alpha_swapped_comparison_operator" 2366 [(match_operand:DI 2 "register_operand" "r") 2367 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))] 2368 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT 2369 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8 2370 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 2371 "cmp%c1 %r3,%2,%0" 2372 [(set_attr "type" "icmp")]) 2373 2374;; Use match_operator rather than ne directly so that we can match 2375;; multiple integer modes. 2376(define_insn "*setne_internal" 2377 [(set (match_operand 0 "register_operand" "=r") 2378 (match_operator 1 "signed_comparison_operator" 2379 [(match_operand:DI 2 "register_operand" "r") 2380 (const_int 0)]))] 2381 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT 2382 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8 2383 && GET_CODE (operands[1]) == NE 2384 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 2385 "cmpult $31,%2,%0" 2386 [(set_attr "type" "icmp")]) 2387 2388;; The mode folding trick can't be used with const_int operands, since 2389;; reload needs to know the proper mode. 2390;; 2391;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand 2392;; in order to create more pairs of constants. As long as we're allowing 2393;; two constants at the same time, and will have to reload one of them... 2394 2395(define_insn "*mov<mode>cc_internal" 2396 [(set (match_operand:IMODE 0 "register_operand" "=r,r,r,r") 2397 (if_then_else:IMODE 2398 (match_operator 2 "signed_comparison_operator" 2399 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J") 2400 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")]) 2401 (match_operand:IMODE 1 "add_operand" "rI,0,rI,0") 2402 (match_operand:IMODE 5 "add_operand" "0,rI,0,rI")))] 2403 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)" 2404 "@ 2405 cmov%C2 %r3,%1,%0 2406 cmov%D2 %r3,%5,%0 2407 cmov%c2 %r4,%1,%0 2408 cmov%d2 %r4,%5,%0" 2409 [(set_attr "type" "icmov")]) 2410 2411(define_insn "*mov<mode>cc_lbc" 2412 [(set (match_operand:IMODE 0 "register_operand" "=r,r") 2413 (if_then_else:IMODE 2414 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") 2415 (const_int 1) 2416 (const_int 0)) 2417 (const_int 0)) 2418 (match_operand:IMODE 1 "reg_or_8bit_operand" "rI,0") 2419 (match_operand:IMODE 3 "reg_or_8bit_operand" "0,rI")))] 2420 "" 2421 "@ 2422 cmovlbc %r2,%1,%0 2423 cmovlbs %r2,%3,%0" 2424 [(set_attr "type" "icmov")]) 2425 2426(define_insn "*mov<mode>cc_lbs" 2427 [(set (match_operand:IMODE 0 "register_operand" "=r,r") 2428 (if_then_else:IMODE 2429 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") 2430 (const_int 1) 2431 (const_int 0)) 2432 (const_int 0)) 2433 (match_operand:IMODE 1 "reg_or_8bit_operand" "rI,0") 2434 (match_operand:IMODE 3 "reg_or_8bit_operand" "0,rI")))] 2435 "" 2436 "@ 2437 cmovlbs %r2,%1,%0 2438 cmovlbc %r2,%3,%0" 2439 [(set_attr "type" "icmov")]) 2440 2441;; For ABS, we have two choices, depending on whether the input and output 2442;; registers are the same or not. 2443(define_expand "absdi2" 2444 [(set (match_operand:DI 0 "register_operand") 2445 (abs:DI (match_operand:DI 1 "register_operand")))] 2446 "" 2447{ 2448 if (rtx_equal_p (operands[0], operands[1])) 2449 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode))); 2450 else 2451 emit_insn (gen_absdi2_diff (operands[0], operands[1])); 2452 DONE; 2453}) 2454 2455(define_expand "absdi2_same" 2456 [(set (match_operand:DI 1 "register_operand") 2457 (neg:DI (match_operand:DI 0 "register_operand"))) 2458 (set (match_dup 0) 2459 (if_then_else:DI (ge (match_dup 0) (const_int 0)) 2460 (match_dup 0) 2461 (match_dup 1)))]) 2462 2463(define_expand "absdi2_diff" 2464 [(set (match_operand:DI 0 "register_operand") 2465 (neg:DI (match_operand:DI 1 "register_operand"))) 2466 (set (match_dup 0) 2467 (if_then_else:DI (lt (match_dup 1) (const_int 0)) 2468 (match_dup 0) 2469 (match_dup 1)))]) 2470 2471(define_split 2472 [(set (match_operand:DI 0 "register_operand") 2473 (abs:DI (match_dup 0))) 2474 (clobber (match_operand:DI 1 "register_operand"))] 2475 "" 2476 [(set (match_dup 1) (neg:DI (match_dup 0))) 2477 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0)) 2478 (match_dup 0) (match_dup 1)))]) 2479 2480(define_split 2481 [(set (match_operand:DI 0 "register_operand") 2482 (abs:DI (match_operand:DI 1 "register_operand")))] 2483 "! rtx_equal_p (operands[0], operands[1])" 2484 [(set (match_dup 0) (neg:DI (match_dup 1))) 2485 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0)) 2486 (match_dup 0) (match_dup 1)))]) 2487 2488(define_split 2489 [(set (match_operand:DI 0 "register_operand") 2490 (neg:DI (abs:DI (match_dup 0)))) 2491 (clobber (match_operand:DI 1 "register_operand"))] 2492 "" 2493 [(set (match_dup 1) (neg:DI (match_dup 0))) 2494 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0)) 2495 (match_dup 0) (match_dup 1)))]) 2496 2497(define_split 2498 [(set (match_operand:DI 0 "register_operand") 2499 (neg:DI (abs:DI (match_operand:DI 1 "register_operand"))))] 2500 "! rtx_equal_p (operands[0], operands[1])" 2501 [(set (match_dup 0) (neg:DI (match_dup 1))) 2502 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0)) 2503 (match_dup 0) (match_dup 1)))]) 2504 2505(define_insn "<code><mode>3" 2506 [(set (match_operand:I12MODE 0 "register_operand" "=r") 2507 (any_maxmin:I12MODE 2508 (match_operand:I12MODE 1 "reg_or_0_operand" "%rJ") 2509 (match_operand:I12MODE 2 "reg_or_8bit_operand" "rI")))] 2510 "TARGET_MAX" 2511 "<maxmin><vecmodesuffix> %r1,%2,%0" 2512 [(set_attr "type" "mvi")]) 2513 2514(define_expand "smaxdi3" 2515 [(set (match_dup 3) 2516 (le:DI (match_operand:DI 1 "reg_or_0_operand") 2517 (match_operand:DI 2 "reg_or_8bit_operand"))) 2518 (set (match_operand:DI 0 "register_operand") 2519 (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2520 (match_dup 1) (match_dup 2)))] 2521 "" 2522 "operands[3] = gen_reg_rtx (DImode);") 2523 2524(define_split 2525 [(set (match_operand:DI 0 "register_operand") 2526 (smax:DI (match_operand:DI 1 "reg_or_0_operand") 2527 (match_operand:DI 2 "reg_or_8bit_operand"))) 2528 (clobber (match_operand:DI 3 "register_operand"))] 2529 "operands[2] != const0_rtx" 2530 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2))) 2531 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2532 (match_dup 1) (match_dup 2)))]) 2533 2534(define_insn "*smax_const0" 2535 [(set (match_operand:DI 0 "register_operand" "=r") 2536 (smax:DI (match_operand:DI 1 "register_operand" "0") 2537 (const_int 0)))] 2538 "" 2539 "cmovlt %0,0,%0" 2540 [(set_attr "type" "icmov")]) 2541 2542(define_expand "smindi3" 2543 [(set (match_dup 3) 2544 (lt:DI (match_operand:DI 1 "reg_or_0_operand") 2545 (match_operand:DI 2 "reg_or_8bit_operand"))) 2546 (set (match_operand:DI 0 "register_operand") 2547 (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2548 (match_dup 1) (match_dup 2)))] 2549 "" 2550 "operands[3] = gen_reg_rtx (DImode);") 2551 2552(define_split 2553 [(set (match_operand:DI 0 "register_operand") 2554 (smin:DI (match_operand:DI 1 "reg_or_0_operand") 2555 (match_operand:DI 2 "reg_or_8bit_operand"))) 2556 (clobber (match_operand:DI 3 "register_operand"))] 2557 "operands[2] != const0_rtx" 2558 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2))) 2559 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2560 (match_dup 1) (match_dup 2)))]) 2561 2562(define_insn "*smin_const0" 2563 [(set (match_operand:DI 0 "register_operand" "=r") 2564 (smin:DI (match_operand:DI 1 "register_operand" "0") 2565 (const_int 0)))] 2566 "" 2567 "cmovgt %0,0,%0" 2568 [(set_attr "type" "icmov")]) 2569 2570(define_expand "umaxdi3" 2571 [(set (match_dup 3) 2572 (leu:DI (match_operand:DI 1 "reg_or_0_operand") 2573 (match_operand:DI 2 "reg_or_8bit_operand"))) 2574 (set (match_operand:DI 0 "register_operand") 2575 (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2576 (match_dup 1) (match_dup 2)))] 2577 "" 2578 "operands[3] = gen_reg_rtx (DImode);") 2579 2580(define_split 2581 [(set (match_operand:DI 0 "register_operand") 2582 (umax:DI (match_operand:DI 1 "reg_or_0_operand") 2583 (match_operand:DI 2 "reg_or_8bit_operand"))) 2584 (clobber (match_operand:DI 3 "register_operand"))] 2585 "operands[2] != const0_rtx" 2586 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2))) 2587 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2588 (match_dup 1) (match_dup 2)))]) 2589 2590(define_expand "umindi3" 2591 [(set (match_dup 3) 2592 (ltu:DI (match_operand:DI 1 "reg_or_0_operand") 2593 (match_operand:DI 2 "reg_or_8bit_operand"))) 2594 (set (match_operand:DI 0 "register_operand") 2595 (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2596 (match_dup 1) (match_dup 2)))] 2597 "" 2598 "operands[3] = gen_reg_rtx (DImode);") 2599 2600(define_split 2601 [(set (match_operand:DI 0 "register_operand") 2602 (umin:DI (match_operand:DI 1 "reg_or_0_operand") 2603 (match_operand:DI 2 "reg_or_8bit_operand"))) 2604 (clobber (match_operand:DI 3 "register_operand"))] 2605 "operands[2] != const0_rtx" 2606 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2))) 2607 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2608 (match_dup 1) (match_dup 2)))]) 2609 2610(define_insn "*bcc_normal" 2611 [(set (pc) 2612 (if_then_else 2613 (match_operator 1 "signed_comparison_operator" 2614 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 2615 (const_int 0)]) 2616 (label_ref (match_operand 0)) 2617 (pc)))] 2618 "" 2619 "b%C1 %r2,%0" 2620 [(set_attr "type" "ibr")]) 2621 2622(define_insn "*bcc_reverse" 2623 [(set (pc) 2624 (if_then_else 2625 (match_operator 1 "signed_comparison_operator" 2626 [(match_operand:DI 2 "register_operand" "r") 2627 (const_int 0)]) 2628 2629 (pc) 2630 (label_ref (match_operand 0))))] 2631 "" 2632 "b%c1 %2,%0" 2633 [(set_attr "type" "ibr")]) 2634 2635(define_insn "*blbs_normal" 2636 [(set (pc) 2637 (if_then_else 2638 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 2639 (const_int 1) 2640 (const_int 0)) 2641 (const_int 0)) 2642 (label_ref (match_operand 0)) 2643 (pc)))] 2644 "" 2645 "blbs %r1,%0" 2646 [(set_attr "type" "ibr")]) 2647 2648(define_insn "*blbc_normal" 2649 [(set (pc) 2650 (if_then_else 2651 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 2652 (const_int 1) 2653 (const_int 0)) 2654 (const_int 0)) 2655 (label_ref (match_operand 0)) 2656 (pc)))] 2657 "" 2658 "blbc %r1,%0" 2659 [(set_attr "type" "ibr")]) 2660 2661(define_split 2662 [(parallel 2663 [(set (pc) 2664 (if_then_else 2665 (match_operator 1 "comparison_operator" 2666 [(zero_extract:DI (match_operand:DI 2 "register_operand") 2667 (const_int 1) 2668 (match_operand:DI 3 "const_int_operand")) 2669 (const_int 0)]) 2670 (label_ref (match_operand 0)) 2671 (pc))) 2672 (clobber (match_operand:DI 4 "register_operand"))])] 2673 "INTVAL (operands[3]) != 0" 2674 [(set (match_dup 4) 2675 (lshiftrt:DI (match_dup 2) (match_dup 3))) 2676 (set (pc) 2677 (if_then_else (match_op_dup 1 2678 [(zero_extract:DI (match_dup 4) 2679 (const_int 1) 2680 (const_int 0)) 2681 (const_int 0)]) 2682 (label_ref (match_dup 0)) 2683 (pc)))] 2684 ) 2685 2686;; The following are the corresponding floating-point insns. Recall 2687;; we need to have variants that expand the arguments from SFmode 2688;; to DFmode. 2689 2690(define_insn "*cmpdf_ieee" 2691 [(set (match_operand:DF 0 "register_operand" "=&f") 2692 (match_operator:DF 1 "alpha_fp_comparison_operator" 2693 [(match_operand:DF 2 "reg_or_0_operand" "fG") 2694 (match_operand:DF 3 "reg_or_0_operand" "fG")]))] 2695 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2696 "cmp%-%C1%/ %R2,%R3,%0" 2697 [(set_attr "type" "fadd") 2698 (set_attr "trap" "yes") 2699 (set_attr "trap_suffix" "su")]) 2700 2701(define_insn "*cmpdf_internal" 2702 [(set (match_operand:DF 0 "register_operand" "=f") 2703 (match_operator:DF 1 "alpha_fp_comparison_operator" 2704 [(match_operand:DF 2 "reg_or_0_operand" "fG") 2705 (match_operand:DF 3 "reg_or_0_operand" "fG")]))] 2706 "TARGET_FP" 2707 "cmp%-%C1%/ %R2,%R3,%0" 2708 [(set_attr "type" "fadd") 2709 (set_attr "trap" "yes") 2710 (set_attr "trap_suffix" "su")]) 2711 2712(define_insn "*cmpdf_ext1" 2713 [(set (match_operand:DF 0 "register_operand" "=f") 2714 (match_operator:DF 1 "alpha_fp_comparison_operator" 2715 [(float_extend:DF 2716 (match_operand:SF 2 "reg_or_0_operand" "fG")) 2717 (match_operand:DF 3 "reg_or_0_operand" "fG")]))] 2718 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2719 "cmp%-%C1%/ %R2,%R3,%0" 2720 [(set_attr "type" "fadd") 2721 (set_attr "trap" "yes") 2722 (set_attr "trap_suffix" "su")]) 2723 2724(define_insn "*cmpdf_ext2" 2725 [(set (match_operand:DF 0 "register_operand" "=f") 2726 (match_operator:DF 1 "alpha_fp_comparison_operator" 2727 [(match_operand:DF 2 "reg_or_0_operand" "fG") 2728 (float_extend:DF 2729 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))] 2730 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2731 "cmp%-%C1%/ %R2,%R3,%0" 2732 [(set_attr "type" "fadd") 2733 (set_attr "trap" "yes") 2734 (set_attr "trap_suffix" "su")]) 2735 2736(define_insn "*cmpdf_ext3" 2737 [(set (match_operand:DF 0 "register_operand" "=f") 2738 (match_operator:DF 1 "alpha_fp_comparison_operator" 2739 [(float_extend:DF 2740 (match_operand:SF 2 "reg_or_0_operand" "fG")) 2741 (float_extend:DF 2742 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))] 2743 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2744 "cmp%-%C1%/ %R2,%R3,%0" 2745 [(set_attr "type" "fadd") 2746 (set_attr "trap" "yes") 2747 (set_attr "trap_suffix" "su")]) 2748 2749(define_insn "*mov<mode>cc_internal" 2750 [(set (match_operand:FMODE 0 "register_operand" "=f,f") 2751 (if_then_else:FMODE 2752 (match_operator 3 "signed_comparison_operator" 2753 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG") 2754 (match_operand:DF 2 "const0_operand" "G,G")]) 2755 (match_operand:FMODE 1 "reg_or_0_operand" "fG,0") 2756 (match_operand:FMODE 5 "reg_or_0_operand" "0,fG")))] 2757 "TARGET_FP" 2758 "@ 2759 fcmov%C3 %R4,%R1,%0 2760 fcmov%D3 %R4,%R5,%0" 2761 [(set_attr "type" "fcmov")]) 2762 2763(define_insn "*movdfcc_ext1" 2764 [(set (match_operand:DF 0 "register_operand" "=f,f") 2765 (if_then_else:DF 2766 (match_operator 3 "signed_comparison_operator" 2767 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG") 2768 (match_operand:DF 2 "const0_operand" "G,G")]) 2769 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0")) 2770 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] 2771 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2772 "@ 2773 fcmov%C3 %R4,%R1,%0 2774 fcmov%D3 %R4,%R5,%0" 2775 [(set_attr "type" "fcmov")]) 2776 2777(define_insn "*movdfcc_ext2" 2778 [(set (match_operand:DF 0 "register_operand" "=f,f") 2779 (if_then_else:DF 2780 (match_operator 3 "signed_comparison_operator" 2781 [(float_extend:DF 2782 (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) 2783 (match_operand:DF 2 "const0_operand" "G,G")]) 2784 (match_operand:DF 1 "reg_or_0_operand" "fG,0") 2785 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] 2786 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2787 "@ 2788 fcmov%C3 %R4,%R1,%0 2789 fcmov%D3 %R4,%R5,%0" 2790 [(set_attr "type" "fcmov")]) 2791 2792(define_insn "*movdfcc_ext3" 2793 [(set (match_operand:SF 0 "register_operand" "=f,f") 2794 (if_then_else:SF 2795 (match_operator 3 "signed_comparison_operator" 2796 [(float_extend:DF 2797 (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) 2798 (match_operand:DF 2 "const0_operand" "G,G")]) 2799 (match_operand:SF 1 "reg_or_0_operand" "fG,0") 2800 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))] 2801 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2802 "@ 2803 fcmov%C3 %R4,%R1,%0 2804 fcmov%D3 %R4,%R5,%0" 2805 [(set_attr "type" "fcmov")]) 2806 2807(define_insn "*movdfcc_ext4" 2808 [(set (match_operand:DF 0 "register_operand" "=f,f") 2809 (if_then_else:DF 2810 (match_operator 3 "signed_comparison_operator" 2811 [(float_extend:DF 2812 (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) 2813 (match_operand:DF 2 "const0_operand" "G,G")]) 2814 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0")) 2815 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] 2816 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2817 "@ 2818 fcmov%C3 %R4,%R1,%0 2819 fcmov%D3 %R4,%R5,%0" 2820 [(set_attr "type" "fcmov")]) 2821 2822(define_expand "smaxdf3" 2823 [(set (match_dup 3) 2824 (le:DF (match_operand:DF 1 "reg_or_0_operand") 2825 (match_operand:DF 2 "reg_or_0_operand"))) 2826 (set (match_operand:DF 0 "register_operand") 2827 (if_then_else:DF (eq (match_dup 3) (match_dup 4)) 2828 (match_dup 1) (match_dup 2)))] 2829 "TARGET_FP" 2830{ 2831 operands[3] = gen_reg_rtx (DFmode); 2832 operands[4] = CONST0_RTX (DFmode); 2833}) 2834 2835(define_expand "smindf3" 2836 [(set (match_dup 3) 2837 (lt:DF (match_operand:DF 1 "reg_or_0_operand") 2838 (match_operand:DF 2 "reg_or_0_operand"))) 2839 (set (match_operand:DF 0 "register_operand") 2840 (if_then_else:DF (ne (match_dup 3) (match_dup 4)) 2841 (match_dup 1) (match_dup 2)))] 2842 "TARGET_FP" 2843{ 2844 operands[3] = gen_reg_rtx (DFmode); 2845 operands[4] = CONST0_RTX (DFmode); 2846}) 2847 2848(define_expand "smaxsf3" 2849 [(set (match_dup 3) 2850 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand")) 2851 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand")))) 2852 (set (match_operand:SF 0 "register_operand") 2853 (if_then_else:SF (eq (match_dup 3) (match_dup 4)) 2854 (match_dup 1) (match_dup 2)))] 2855 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2856{ 2857 operands[3] = gen_reg_rtx (DFmode); 2858 operands[4] = CONST0_RTX (DFmode); 2859}) 2860 2861(define_expand "sminsf3" 2862 [(set (match_dup 3) 2863 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand")) 2864 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand")))) 2865 (set (match_operand:SF 0 "register_operand") 2866 (if_then_else:SF (ne (match_dup 3) (match_dup 4)) 2867 (match_dup 1) (match_dup 2)))] 2868 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2869{ 2870 operands[3] = gen_reg_rtx (DFmode); 2871 operands[4] = CONST0_RTX (DFmode); 2872}) 2873 2874(define_insn "*fbcc_normal" 2875 [(set (pc) 2876 (if_then_else 2877 (match_operator 1 "signed_comparison_operator" 2878 [(match_operand:DF 2 "reg_or_0_operand" "fG") 2879 (match_operand:DF 3 "const0_operand" "G")]) 2880 (label_ref (match_operand 0)) 2881 (pc)))] 2882 "TARGET_FP" 2883 "fb%C1 %R2,%0" 2884 [(set_attr "type" "fbr")]) 2885 2886(define_insn "*fbcc_ext_normal" 2887 [(set (pc) 2888 (if_then_else 2889 (match_operator 1 "signed_comparison_operator" 2890 [(float_extend:DF 2891 (match_operand:SF 2 "reg_or_0_operand" "fG")) 2892 (match_operand:DF 3 "const0_operand" "G")]) 2893 (label_ref (match_operand 0)) 2894 (pc)))] 2895 "TARGET_FP" 2896 "fb%C1 %R2,%0" 2897 [(set_attr "type" "fbr")]) 2898 2899;; These are the main define_expand's used to make conditional branches 2900;; and compares. 2901 2902(define_expand "cbranchdf4" 2903 [(use (match_operator 0 "alpha_cbranch_operator" 2904 [(match_operand:DF 1 "reg_or_0_operand") 2905 (match_operand:DF 2 "reg_or_0_operand")])) 2906 (use (match_operand 3))] 2907 "TARGET_FP" 2908 "alpha_emit_conditional_branch (operands, DFmode); DONE;") 2909 2910(define_expand "cbranchtf4" 2911 [(use (match_operator 0 "alpha_cbranch_operator" 2912 [(match_operand:TF 1 "general_operand") 2913 (match_operand:TF 2 "general_operand")])) 2914 (use (match_operand 3))] 2915 "TARGET_HAS_XFLOATING_LIBS" 2916 "alpha_emit_conditional_branch (operands, TFmode); DONE;") 2917 2918(define_expand "cbranchdi4" 2919 [(use (match_operator 0 "alpha_cbranch_operator" 2920 [(match_operand:DI 1 "some_operand") 2921 (match_operand:DI 2 "some_operand")])) 2922 (use (match_operand 3))] 2923 "" 2924 "alpha_emit_conditional_branch (operands, DImode); DONE;") 2925 2926(define_expand "cstoredf4" 2927 [(use (match_operator:DI 1 "alpha_cbranch_operator" 2928 [(match_operand:DF 2 "reg_or_0_operand") 2929 (match_operand:DF 3 "reg_or_0_operand")])) 2930 (clobber (match_operand:DI 0 "register_operand"))] 2931 "TARGET_FP" 2932{ 2933 if (alpha_emit_setcc (operands, DFmode)) 2934 DONE; 2935 else 2936 FAIL; 2937}) 2938 2939(define_expand "cstoretf4" 2940 [(use (match_operator:DI 1 "alpha_cbranch_operator" 2941 [(match_operand:TF 2 "general_operand") 2942 (match_operand:TF 3 "general_operand")])) 2943 (clobber (match_operand:DI 0 "register_operand"))] 2944 "TARGET_HAS_XFLOATING_LIBS" 2945{ 2946 if (alpha_emit_setcc (operands, TFmode)) 2947 DONE; 2948 else 2949 FAIL; 2950}) 2951 2952(define_expand "cstoredi4" 2953 [(use (match_operator:DI 1 "alpha_cbranch_operator" 2954 [(match_operand:DI 2 "some_operand") 2955 (match_operand:DI 3 "some_operand")])) 2956 (clobber (match_operand:DI 0 "register_operand"))] 2957 "" 2958{ 2959 if (alpha_emit_setcc (operands, DImode)) 2960 DONE; 2961 else 2962 FAIL; 2963}) 2964 2965;; These are the main define_expand's used to make conditional moves. 2966 2967(define_expand "mov<mode>cc" 2968 [(set (match_operand:I48MODE 0 "register_operand") 2969 (if_then_else:I48MODE 2970 (match_operand 1 "comparison_operator") 2971 (match_operand:I48MODE 2 "reg_or_8bit_operand") 2972 (match_operand:I48MODE 3 "reg_or_8bit_operand")))] 2973 "" 2974{ 2975 operands[1] = alpha_emit_conditional_move (operands[1], <MODE>mode); 2976 if (operands[1] == 0) 2977 FAIL; 2978}) 2979 2980(define_expand "mov<mode>cc" 2981 [(set (match_operand:FMODE 0 "register_operand") 2982 (if_then_else:FMODE 2983 (match_operand 1 "comparison_operator") 2984 (match_operand:FMODE 2 "reg_or_8bit_operand") 2985 (match_operand:FMODE 3 "reg_or_8bit_operand")))] 2986 "" 2987{ 2988 operands[1] = alpha_emit_conditional_move (operands[1], <MODE>mode); 2989 if (operands[1] == 0) 2990 FAIL; 2991}) 2992 2993;; These define_split definitions are used in cases when comparisons have 2994;; not be stated in the correct way and we need to reverse the second 2995;; comparison. For example, x >= 7 has to be done as x < 6 with the 2996;; comparison that tests the result being reversed. We have one define_split 2997;; for each use of a comparison. They do not match valid insns and need 2998;; not generate valid insns. 2999;; 3000;; We can also handle equality comparisons (and inequality comparisons in 3001;; cases where the resulting add cannot overflow) by doing an add followed by 3002;; a comparison with zero. This is faster since the addition takes one 3003;; less cycle than a compare when feeding into a conditional move. 3004;; For this case, we also have an SImode pattern since we can merge the add 3005;; and sign extend and the order doesn't matter. 3006;; 3007;; We do not do this for floating-point, since it isn't clear how the "wrong" 3008;; operation could have been generated. 3009 3010(define_split 3011 [(set (match_operand:DI 0 "register_operand") 3012 (if_then_else:DI 3013 (match_operator 1 "comparison_operator" 3014 [(match_operand:DI 2 "reg_or_0_operand") 3015 (match_operand:DI 3 "reg_or_cint_operand")]) 3016 (match_operand:DI 4 "reg_or_cint_operand") 3017 (match_operand:DI 5 "reg_or_cint_operand"))) 3018 (clobber (match_operand:DI 6 "register_operand"))] 3019 "operands[3] != const0_rtx" 3020 [(set (match_dup 6) (match_dup 7)) 3021 (set (match_dup 0) 3022 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))] 3023{ 3024 enum rtx_code code = GET_CODE (operands[1]); 3025 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU); 3026 3027 /* If we are comparing for equality with a constant and that constant 3028 appears in the arm when the register equals the constant, use the 3029 register since that is more likely to match (and to produce better code 3030 if both would). */ 3031 3032 if (code == EQ && CONST_INT_P (operands[3]) 3033 && rtx_equal_p (operands[4], operands[3])) 3034 operands[4] = operands[2]; 3035 3036 else if (code == NE && CONST_INT_P (operands[3]) 3037 && rtx_equal_p (operands[5], operands[3])) 3038 operands[5] = operands[2]; 3039 3040 if (code == NE || code == EQ 3041 || (extended_count (operands[2], DImode, unsignedp) >= 1 3042 && extended_count (operands[3], DImode, unsignedp) >= 1)) 3043 { 3044 if (CONST_INT_P (operands[3])) 3045 operands[7] = gen_rtx_PLUS (DImode, operands[2], 3046 GEN_INT (- INTVAL (operands[3]))); 3047 else 3048 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]); 3049 3050 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx); 3051 } 3052 3053 else if (code == EQ || code == LE || code == LT 3054 || code == LEU || code == LTU) 3055 { 3056 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]); 3057 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx); 3058 } 3059 else 3060 { 3061 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode, 3062 operands[2], operands[3]); 3063 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx); 3064 } 3065}) 3066 3067(define_split 3068 [(set (match_operand:DI 0 "register_operand") 3069 (if_then_else:DI 3070 (match_operator 1 "comparison_operator" 3071 [(match_operand:SI 2 "reg_or_0_operand") 3072 (match_operand:SI 3 "reg_or_cint_operand")]) 3073 (match_operand:DI 4 "reg_or_8bit_operand") 3074 (match_operand:DI 5 "reg_or_8bit_operand"))) 3075 (clobber (match_operand:DI 6 "register_operand"))] 3076 "operands[3] != const0_rtx 3077 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)" 3078 [(set (match_dup 6) (match_dup 7)) 3079 (set (match_dup 0) 3080 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))] 3081{ 3082 enum rtx_code code = GET_CODE (operands[1]); 3083 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU); 3084 rtx tem; 3085 3086 if ((code != NE && code != EQ 3087 && ! (extended_count (operands[2], DImode, unsignedp) >= 1 3088 && extended_count (operands[3], DImode, unsignedp) >= 1))) 3089 FAIL; 3090 3091 if (CONST_INT_P (operands[3])) 3092 tem = gen_rtx_PLUS (SImode, operands[2], 3093 GEN_INT (- INTVAL (operands[3]))); 3094 else 3095 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]); 3096 3097 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem); 3098 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode, 3099 operands[6], const0_rtx); 3100}) 3101 3102;; Prefer to use cmp and arithmetic when possible instead of a cmove. 3103 3104(define_split 3105 [(set (match_operand 0 "register_operand") 3106 (if_then_else (match_operator 1 "signed_comparison_operator" 3107 [(match_operand:DI 2 "reg_or_0_operand") 3108 (const_int 0)]) 3109 (match_operand 3 "const_int_operand") 3110 (match_operand 4 "const_int_operand")))] 3111 "" 3112 [(const_int 0)] 3113{ 3114 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0], 3115 operands[2], operands[3], operands[4])) 3116 DONE; 3117 else 3118 FAIL; 3119}) 3120 3121;; ??? Why combine is allowed to create such non-canonical rtl, I don't know. 3122;; Oh well, we match it in movcc, so it must be partially our fault. 3123(define_split 3124 [(set (match_operand 0 "register_operand") 3125 (if_then_else (match_operator 1 "signed_comparison_operator" 3126 [(const_int 0) 3127 (match_operand:DI 2 "reg_or_0_operand")]) 3128 (match_operand 3 "const_int_operand") 3129 (match_operand 4 "const_int_operand")))] 3130 "" 3131 [(const_int 0)] 3132{ 3133 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])), 3134 operands[0], operands[2], operands[3], 3135 operands[4])) 3136 DONE; 3137 else 3138 FAIL; 3139}) 3140 3141(define_insn_and_split "*cmp_sadd_di" 3142 [(set (match_operand:DI 0 "register_operand" "=r") 3143 (plus:DI (if_then_else:DI 3144 (match_operator 1 "alpha_zero_comparison_operator" 3145 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3146 (const_int 0)]) 3147 (match_operand:DI 3 "const48_operand" "I") 3148 (const_int 0)) 3149 (match_operand:DI 4 "sext_add_operand" "rIO"))) 3150 (clobber (match_scratch:DI 5 "=r"))] 3151 "" 3152 "#" 3153 "" 3154 [(set (match_dup 5) 3155 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3156 (set (match_dup 0) 3157 (plus:DI (mult:DI (match_dup 5) (match_dup 3)) 3158 (match_dup 4)))] 3159{ 3160 if (can_create_pseudo_p ()) 3161 operands[5] = gen_reg_rtx (DImode); 3162 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3163 operands[5] = operands[0]; 3164}) 3165 3166(define_insn_and_split "*cmp_sadd_si" 3167 [(set (match_operand:SI 0 "register_operand" "=r") 3168 (plus:SI (if_then_else:SI 3169 (match_operator 1 "alpha_zero_comparison_operator" 3170 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3171 (const_int 0)]) 3172 (match_operand:SI 3 "const48_operand" "I") 3173 (const_int 0)) 3174 (match_operand:SI 4 "sext_add_operand" "rIO"))) 3175 (clobber (match_scratch:DI 5 "=r"))] 3176 "" 3177 "#" 3178 "" 3179 [(set (match_dup 5) 3180 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3181 (set (match_dup 0) 3182 (plus:SI (mult:SI (match_dup 6) (match_dup 3)) 3183 (match_dup 4)))] 3184{ 3185 if (can_create_pseudo_p ()) 3186 operands[5] = gen_reg_rtx (DImode); 3187 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3188 operands[5] = gen_lowpart (DImode, operands[0]); 3189 3190 operands[6] = gen_lowpart (SImode, operands[5]); 3191}) 3192 3193(define_insn_and_split "*cmp_sadd_sidi" 3194 [(set (match_operand:DI 0 "register_operand" "=r") 3195 (sign_extend:DI 3196 (plus:SI (if_then_else:SI 3197 (match_operator 1 "alpha_zero_comparison_operator" 3198 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3199 (const_int 0)]) 3200 (match_operand:SI 3 "const48_operand" "I") 3201 (const_int 0)) 3202 (match_operand:SI 4 "sext_add_operand" "rIO")))) 3203 (clobber (match_scratch:DI 5 "=r"))] 3204 "" 3205 "#" 3206 "" 3207 [(set (match_dup 5) 3208 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3209 (set (match_dup 0) 3210 (sign_extend:DI (plus:SI (mult:SI (match_dup 6) (match_dup 3)) 3211 (match_dup 4))))] 3212{ 3213 if (can_create_pseudo_p ()) 3214 operands[5] = gen_reg_rtx (DImode); 3215 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3216 operands[5] = operands[0]; 3217 3218 operands[6] = gen_lowpart (SImode, operands[5]); 3219}) 3220 3221(define_insn_and_split "*cmp_ssub_di" 3222 [(set (match_operand:DI 0 "register_operand" "=r") 3223 (minus:DI (if_then_else:DI 3224 (match_operator 1 "alpha_zero_comparison_operator" 3225 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3226 (const_int 0)]) 3227 (match_operand:DI 3 "const48_operand" "I") 3228 (const_int 0)) 3229 (match_operand:DI 4 "reg_or_8bit_operand" "rI"))) 3230 (clobber (match_scratch:DI 5 "=r"))] 3231 "" 3232 "#" 3233 "" 3234 [(set (match_dup 5) 3235 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3236 (set (match_dup 0) 3237 (minus:DI (mult:DI (match_dup 5) (match_dup 3)) 3238 (match_dup 4)))] 3239{ 3240 if (can_create_pseudo_p ()) 3241 operands[5] = gen_reg_rtx (DImode); 3242 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3243 operands[5] = operands[0]; 3244}) 3245 3246(define_insn_and_split "*cmp_ssub_si" 3247 [(set (match_operand:SI 0 "register_operand" "=r") 3248 (minus:SI (if_then_else:SI 3249 (match_operator 1 "alpha_zero_comparison_operator" 3250 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3251 (const_int 0)]) 3252 (match_operand:SI 3 "const48_operand" "I") 3253 (const_int 0)) 3254 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))) 3255 (clobber (match_scratch:DI 5 "=r"))] 3256 "" 3257 "#" 3258 "" 3259 [(set (match_dup 5) 3260 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3261 (set (match_dup 0) 3262 (minus:SI (mult:SI (match_dup 6) (match_dup 3)) 3263 (match_dup 4)))] 3264{ 3265 if (can_create_pseudo_p ()) 3266 operands[5] = gen_reg_rtx (DImode); 3267 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3268 operands[5] = gen_lowpart (DImode, operands[0]); 3269 3270 operands[6] = gen_lowpart (SImode, operands[5]); 3271}) 3272 3273(define_insn_and_split "*cmp_ssub_sidi" 3274 [(set (match_operand:DI 0 "register_operand" "=r") 3275 (sign_extend:DI 3276 (minus:SI (if_then_else:SI 3277 (match_operator 1 "alpha_zero_comparison_operator" 3278 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3279 (const_int 0)]) 3280 (match_operand:SI 3 "const48_operand" "I") 3281 (const_int 0)) 3282 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))) 3283 (clobber (match_scratch:DI 5 "=r"))] 3284 "" 3285 "#" 3286 "" 3287 [(set (match_dup 5) 3288 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3289 (set (match_dup 0) 3290 (sign_extend:DI (minus:SI (mult:SI (match_dup 6) (match_dup 3)) 3291 (match_dup 4))))] 3292{ 3293 if (can_create_pseudo_p ()) 3294 operands[5] = gen_reg_rtx (DImode); 3295 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3296 operands[5] = operands[0]; 3297 3298 operands[6] = gen_lowpart (SImode, operands[5]); 3299}) 3300 3301;; Here are the CALL and unconditional branch insns. Calls on NT and OSF 3302;; work differently, so we have different patterns for each. 3303 3304(define_expand "call" 3305 [(use (match_operand:DI 0)) 3306 (use (match_operand 1)) 3307 (use (match_operand 2)) 3308 (use (match_operand 3))] 3309 "" 3310{ 3311 if (TARGET_ABI_OPEN_VMS) 3312 emit_call_insn (gen_call_vms (operands[0], operands[2])); 3313 else 3314 emit_call_insn (gen_call_osf (operands[0], operands[1])); 3315 DONE; 3316}) 3317 3318(define_expand "sibcall" 3319 [(parallel [(call (mem:DI (match_operand 0)) 3320 (match_operand 1)) 3321 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])] 3322 "TARGET_ABI_OSF" 3323{ 3324 gcc_assert (MEM_P (operands[0])); 3325 operands[0] = XEXP (operands[0], 0); 3326}) 3327 3328(define_expand "call_osf" 3329 [(parallel [(call (mem:DI (match_operand 0)) 3330 (match_operand 1)) 3331 (use (reg:DI 29)) 3332 (clobber (reg:DI 26))])] 3333 "" 3334{ 3335 gcc_assert (MEM_P (operands[0])); 3336 3337 operands[0] = XEXP (operands[0], 0); 3338 if (! call_operand (operands[0], Pmode)) 3339 operands[0] = copy_to_mode_reg (Pmode, operands[0]); 3340}) 3341 3342;; 3343;; call openvms/alpha 3344;; op 0: symbol ref for called function 3345;; op 1: next_arg_reg (argument information value for R25) 3346;; 3347(define_expand "call_vms" 3348 [(parallel [(call (mem:DI (match_operand 0)) 3349 (match_operand 1)) 3350 (use (match_dup 2)) 3351 (use (reg:DI 25)) 3352 (use (reg:DI 26)) 3353 (clobber (reg:DI 27))])] 3354 "" 3355{ 3356 gcc_assert (MEM_P (operands[0])); 3357 3358 operands[0] = XEXP (operands[0], 0); 3359 3360 /* Always load AI with argument information, then handle symbolic and 3361 indirect call differently. Load RA and set operands[2] to PV in 3362 both cases. */ 3363 3364 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]); 3365 if (GET_CODE (operands[0]) == SYMBOL_REF) 3366 { 3367 operands[2] = const0_rtx; 3368 } 3369 else 3370 { 3371 emit_move_insn (gen_rtx_REG (Pmode, 26), 3372 gen_rtx_MEM (Pmode, plus_constant (Pmode, 3373 operands[0], 8))); 3374 operands[2] = operands[0]; 3375 } 3376}) 3377 3378(define_expand "call_value" 3379 [(use (match_operand 0)) 3380 (use (match_operand:DI 1)) 3381 (use (match_operand 2)) 3382 (use (match_operand 3)) 3383 (use (match_operand 4))] 3384 "" 3385{ 3386 if (TARGET_ABI_OPEN_VMS) 3387 emit_call_insn (gen_call_value_vms (operands[0], operands[1], 3388 operands[3])); 3389 else 3390 emit_call_insn (gen_call_value_osf (operands[0], operands[1], 3391 operands[2])); 3392 DONE; 3393}) 3394 3395(define_expand "sibcall_value" 3396 [(parallel [(set (match_operand 0) 3397 (call (mem:DI (match_operand 1)) 3398 (match_operand 2))) 3399 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])] 3400 "TARGET_ABI_OSF" 3401{ 3402 gcc_assert (MEM_P (operands[1])); 3403 operands[1] = XEXP (operands[1], 0); 3404}) 3405 3406(define_expand "call_value_osf" 3407 [(parallel [(set (match_operand 0) 3408 (call (mem:DI (match_operand 1)) 3409 (match_operand 2))) 3410 (use (reg:DI 29)) 3411 (clobber (reg:DI 26))])] 3412 "" 3413{ 3414 gcc_assert (MEM_P (operands[1])); 3415 3416 operands[1] = XEXP (operands[1], 0); 3417 if (! call_operand (operands[1], Pmode)) 3418 operands[1] = copy_to_mode_reg (Pmode, operands[1]); 3419}) 3420 3421(define_expand "call_value_vms" 3422 [(parallel [(set (match_operand 0) 3423 (call (mem:DI (match_operand:DI 1)) 3424 (match_operand 2))) 3425 (use (match_dup 3)) 3426 (use (reg:DI 25)) 3427 (use (reg:DI 26)) 3428 (clobber (reg:DI 27))])] 3429 "" 3430{ 3431 gcc_assert (MEM_P (operands[1])); 3432 3433 operands[1] = XEXP (operands[1], 0); 3434 3435 /* Always load AI with argument information, then handle symbolic and 3436 indirect call differently. Load RA and set operands[3] to PV in 3437 both cases. */ 3438 3439 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]); 3440 if (GET_CODE (operands[1]) == SYMBOL_REF) 3441 { 3442 operands[3] = const0_rtx; 3443 } 3444 else 3445 { 3446 emit_move_insn (gen_rtx_REG (Pmode, 26), 3447 gen_rtx_MEM (Pmode, plus_constant (Pmode, 3448 operands[1], 8))); 3449 operands[3] = operands[1]; 3450 } 3451}) 3452 3453(define_insn "*call_osf_1_er_noreturn" 3454 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3455 (match_operand 1)) 3456 (use (reg:DI 29)) 3457 (clobber (reg:DI 26))] 3458 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 3459 && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 3460 "@ 3461 jsr $26,($27),0 3462 bsr $26,%0\t\t!samegp 3463 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#" 3464 [(set_attr "type" "jsr") 3465 (set_attr "length" "*,*,8")]) 3466 3467(define_insn "*call_osf_1_er" 3468 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3469 (match_operand 1)) 3470 (use (reg:DI 29)) 3471 (clobber (reg:DI 26))] 3472 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3473 "@ 3474 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%* 3475 bsr $26,%0\t\t!samegp 3476 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*" 3477 [(set_attr "type" "jsr") 3478 (set_attr "length" "12,*,16")]) 3479 3480;; We must use peep2 instead of a split because we need accurate life 3481;; information for $gp. Consider the case of { bar(); while (1); }. 3482(define_peephole2 3483 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand")) 3484 (match_operand 1)) 3485 (use (reg:DI 29)) 3486 (clobber (reg:DI 26))])] 3487 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 3488 && ! samegp_function_operand (operands[0], Pmode) 3489 && (peep2_regno_dead_p (1, 29) 3490 || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 3491 [(parallel [(call (mem:DI (match_dup 2)) 3492 (match_dup 1)) 3493 (use (reg:DI 29)) 3494 (use (match_dup 0)) 3495 (use (match_dup 3)) 3496 (clobber (reg:DI 26))])] 3497{ 3498 if (CONSTANT_P (operands[0])) 3499 { 3500 operands[2] = gen_rtx_REG (Pmode, 27); 3501 operands[3] = GEN_INT (alpha_next_sequence_number++); 3502 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx, 3503 operands[0], operands[3])); 3504 } 3505 else 3506 { 3507 operands[2] = operands[0]; 3508 operands[0] = const0_rtx; 3509 operands[3] = const0_rtx; 3510 } 3511}) 3512 3513(define_peephole2 3514 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand")) 3515 (match_operand 1)) 3516 (use (reg:DI 29)) 3517 (clobber (reg:DI 26))])] 3518 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 3519 && ! samegp_function_operand (operands[0], Pmode) 3520 && ! (peep2_regno_dead_p (1, 29) 3521 || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 3522 [(parallel [(call (mem:DI (match_dup 2)) 3523 (match_dup 1)) 3524 (set (match_dup 5) 3525 (unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP1)) 3526 (use (match_dup 0)) 3527 (use (match_dup 4)) 3528 (clobber (reg:DI 26))]) 3529 (set (match_dup 5) 3530 (unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP2))] 3531{ 3532 if (CONSTANT_P (operands[0])) 3533 { 3534 operands[2] = gen_rtx_REG (Pmode, 27); 3535 operands[4] = GEN_INT (alpha_next_sequence_number++); 3536 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx, 3537 operands[0], operands[4])); 3538 } 3539 else 3540 { 3541 operands[2] = operands[0]; 3542 operands[0] = const0_rtx; 3543 operands[4] = const0_rtx; 3544 } 3545 operands[3] = GEN_INT (alpha_next_sequence_number++); 3546 operands[5] = pic_offset_table_rtx; 3547}) 3548 3549(define_insn "*call_osf_2_er_nogp" 3550 [(call (mem:DI (match_operand:DI 0 "register_operand" "c")) 3551 (match_operand 1)) 3552 (use (reg:DI 29)) 3553 (use (match_operand 2)) 3554 (use (match_operand 3 "const_int_operand")) 3555 (clobber (reg:DI 26))] 3556 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3557 "jsr $26,(%0),%2%J3" 3558 [(set_attr "type" "jsr")]) 3559 3560(define_insn "*call_osf_2_er" 3561 [(call (mem:DI (match_operand:DI 0 "register_operand" "c")) 3562 (match_operand 1)) 3563 (set (reg:DI 29) 3564 (unspec:DI [(reg:DI 29) (match_operand 4 "const_int_operand")] 3565 UNSPEC_LDGP1)) 3566 (use (match_operand 2)) 3567 (use (match_operand 3 "const_int_operand")) 3568 (clobber (reg:DI 26))] 3569 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3570 "jsr $26,(%0),%2%J3\;ldah $29,0($26)\t\t!gpdisp!%4" 3571 [(set_attr "type" "jsr") 3572 (set_attr "cannot_copy" "true") 3573 (set_attr "length" "8")]) 3574 3575(define_insn "*call_osf_1_noreturn" 3576 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3577 (match_operand 1)) 3578 (use (reg:DI 29)) 3579 (clobber (reg:DI 26))] 3580 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 3581 && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 3582 "@ 3583 jsr $26,($27),0 3584 bsr $26,$%0..ng 3585 jsr $26,%0" 3586 [(set_attr "type" "jsr") 3587 (set_attr "length" "*,*,8")]) 3588 3589(define_insn "*call_osf_1" 3590 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3591 (match_operand 1)) 3592 (use (reg:DI 29)) 3593 (clobber (reg:DI 26))] 3594 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3595 "@ 3596 jsr $26,($27),0\;ldgp $29,0($26) 3597 bsr $26,$%0..ng 3598 jsr $26,%0\;ldgp $29,0($26)" 3599 [(set_attr "type" "jsr") 3600 (set_attr "length" "12,*,16")]) 3601 3602(define_insn "*sibcall_osf_1_er" 3603 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s")) 3604 (match_operand 1)) 3605 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 3606 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3607 "@ 3608 br $31,%0\t\t!samegp 3609 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#" 3610 [(set_attr "type" "jsr") 3611 (set_attr "length" "*,8")]) 3612 3613;; Note that the DEC assembler expands "jmp foo" with $at, which 3614;; doesn't do what we want. 3615(define_insn "*sibcall_osf_1" 3616 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s")) 3617 (match_operand 1)) 3618 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 3619 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3620 "@ 3621 br $31,$%0..ng 3622 lda $27,%0\;jmp $31,($27),%0" 3623 [(set_attr "type" "jsr") 3624 (set_attr "length" "*,8")]) 3625 3626; GAS relies on the order and position of instructions output below in order 3627; to generate relocs for VMS link to potentially optimize the call. 3628; Please do not molest. 3629(define_insn "*call_vms_1" 3630 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s")) 3631 (match_operand 1)) 3632 (use (match_operand:DI 2 "nonmemory_operand" "r,n")) 3633 (use (reg:DI 25)) 3634 (use (reg:DI 26)) 3635 (clobber (reg:DI 27))] 3636 "TARGET_ABI_OPEN_VMS" 3637{ 3638 switch (which_alternative) 3639 { 3640 case 0: 3641 return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)"; 3642 case 1: 3643 operands [2] = alpha_use_linkage (operands [0], true, false); 3644 operands [3] = alpha_use_linkage (operands [0], false, false); 3645 return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"; 3646 default: 3647 gcc_unreachable (); 3648 } 3649} 3650 [(set_attr "type" "jsr") 3651 (set_attr "length" "12,16")]) 3652 3653;; Call subroutine returning any type. 3654 3655(define_expand "untyped_call" 3656 [(parallel [(call (match_operand 0) 3657 (const_int 0)) 3658 (match_operand 1) 3659 (match_operand 2)])] 3660 "" 3661{ 3662 int i; 3663 3664 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx)); 3665 3666 for (i = 0; i < XVECLEN (operands[2], 0); i++) 3667 { 3668 rtx set = XVECEXP (operands[2], 0, i); 3669 emit_move_insn (SET_DEST (set), SET_SRC (set)); 3670 } 3671 3672 /* The optimizer does not know that the call sets the function value 3673 registers we stored in the result block. We avoid problems by 3674 claiming that all hard registers are used and clobbered at this 3675 point. */ 3676 emit_insn (gen_blockage ()); 3677 3678 DONE; 3679}) 3680 3681;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 3682;; all of memory. This blocks insns from being moved across this point. 3683 3684(define_insn "blockage" 3685 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] 3686 "" 3687 "" 3688 [(set_attr "length" "0") 3689 (set_attr "type" "none")]) 3690 3691(define_insn "jump" 3692 [(set (pc) 3693 (label_ref (match_operand 0)))] 3694 "" 3695 "br $31,%l0" 3696 [(set_attr "type" "ibr")]) 3697 3698(define_expand "return" 3699 [(return)] 3700 "direct_return ()") 3701 3702(define_insn "*return_internal" 3703 [(return)] 3704 "reload_completed" 3705 "ret $31,($26),1" 3706 [(set_attr "type" "ibr")]) 3707 3708(define_insn "indirect_jump" 3709 [(set (pc) (match_operand:DI 0 "register_operand" "r"))] 3710 "" 3711 "jmp $31,(%0),0" 3712 [(set_attr "type" "ibr")]) 3713 3714(define_expand "tablejump" 3715 [(parallel [(set (pc) 3716 (match_operand 0 "register_operand")) 3717 (use (label_ref:DI (match_operand 1)))])] 3718 "" 3719{ 3720 if (TARGET_ABI_OSF) 3721 { 3722 rtx dest = gen_reg_rtx (DImode); 3723 emit_insn (gen_extendsidi2 (dest, operands[0])); 3724 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest)); 3725 operands[0] = dest; 3726 } 3727}) 3728 3729(define_insn "*tablejump_internal" 3730 [(set (pc) 3731 (match_operand:DI 0 "register_operand" "r")) 3732 (use (label_ref (match_operand 1)))] 3733 "" 3734 "jmp $31,(%0),0" 3735 [(set_attr "type" "ibr")]) 3736 3737;; Cache flush. Used by alpha_trampoline_init. 0x86 is PAL_imb, but we don't 3738;; want to have to include pal.h in our .s file. 3739(define_insn "imb" 3740 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)] 3741 "" 3742 "call_pal 0x86" 3743 [(set_attr "type" "callpal")]) 3744 3745(define_expand "clear_cache" 3746 [(match_operand:DI 0) ; region start 3747 (match_operand:DI 1)] ; region end 3748 "" 3749{ 3750 emit_insn (gen_imb ()); 3751 DONE; 3752}) 3753 3754;; BUGCHK is documented common to OSF/1 and VMS PALcode. 3755(define_insn "trap" 3756 [(trap_if (const_int 1) (const_int 0))] 3757 "" 3758 "call_pal 0x81" 3759 [(set_attr "type" "callpal")]) 3760 3761;; For userland, we load the thread pointer from the TCB. 3762;; For the kernel, we load the per-cpu private value. 3763 3764(define_insn "get_thread_pointerdi" 3765 [(set (match_operand:DI 0 "register_operand" "=v") 3766 (unspec:DI [(const_int 0)] UNSPEC_TP))] 3767 "TARGET_ABI_OSF" 3768{ 3769 if (TARGET_TLS_KERNEL) 3770 return "call_pal 0x32"; 3771 else 3772 return "call_pal 0x9e"; 3773} 3774 [(set_attr "type" "callpal")]) 3775 3776;; For completeness, and possibly a __builtin function, here's how to 3777;; set the thread pointer. Since we don't describe enough of this 3778;; quantity for CSE, we have to use a volatile unspec, and then there's 3779;; not much point in creating an R16_REG register class. 3780 3781(define_expand "set_thread_pointerdi" 3782 [(set (reg:DI 16) (match_operand:DI 0 "input_operand")) 3783 (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)] 3784 "TARGET_ABI_OSF") 3785 3786(define_insn "*set_tp" 3787 [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)] 3788 "TARGET_ABI_OSF" 3789{ 3790 if (TARGET_TLS_KERNEL) 3791 return "call_pal 0x31"; 3792 else 3793 return "call_pal 0x9f"; 3794} 3795 [(set_attr "type" "callpal")]) 3796 3797;; Special builtins for establishing and reverting VMS condition handlers. 3798 3799(define_expand "builtin_establish_vms_condition_handler" 3800 [(set (reg:DI 0) (match_operand:DI 0 "register_operand")) 3801 (use (match_operand:DI 1 "address_operand"))] 3802 "TARGET_ABI_OPEN_VMS" 3803{ 3804 alpha_expand_builtin_establish_vms_condition_handler (operands[0], 3805 operands[1]); 3806}) 3807 3808(define_expand "builtin_revert_vms_condition_handler" 3809 [(set (reg:DI 0) (match_operand:DI 0 "register_operand"))] 3810 "TARGET_ABI_OPEN_VMS" 3811 "alpha_expand_builtin_revert_vms_condition_handler (operands[0]);") 3812 3813;; Finally, we have the basic data motion insns. The byte and word insns 3814;; are done via define_expand. Start with the floating-point insns, since 3815;; they are simpler. 3816 3817(define_expand "movsf" 3818 [(set (match_operand:SF 0 "nonimmediate_operand") 3819 (match_operand:SF 1 "general_operand"))] 3820 "" 3821{ 3822 if (MEM_P (operands[0]) 3823 && ! reg_or_0_operand (operands[1], SFmode)) 3824 operands[1] = force_reg (SFmode, operands[1]); 3825}) 3826 3827(define_insn "*movsf" 3828 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r") 3829 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))] 3830 "register_operand (operands[0], SFmode) 3831 || reg_or_0_operand (operands[1], SFmode)" 3832 "@ 3833 cpys %R1,%R1,%0 3834 ld%, %0,%1 3835 bis $31,%r1,%0 3836 ldl %0,%1 3837 st%, %R1,%0 3838 stl %r1,%0 3839 itofs %1,%0 3840 ftois %1,%0" 3841 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi") 3842 (set_attr "isa" "*,*,*,*,*,*,fix,fix")]) 3843 3844(define_expand "movdf" 3845 [(set (match_operand:DF 0 "nonimmediate_operand") 3846 (match_operand:DF 1 "general_operand"))] 3847 "" 3848{ 3849 if (MEM_P (operands[0]) 3850 && ! reg_or_0_operand (operands[1], DFmode)) 3851 operands[1] = force_reg (DFmode, operands[1]); 3852}) 3853 3854(define_insn "*movdf" 3855 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r") 3856 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))] 3857 "register_operand (operands[0], DFmode) 3858 || reg_or_0_operand (operands[1], DFmode)" 3859 "@ 3860 cpys %R1,%R1,%0 3861 ld%- %0,%1 3862 bis $31,%r1,%0 3863 ldq %0,%1 3864 st%- %R1,%0 3865 stq %r1,%0 3866 itoft %1,%0 3867 ftoit %1,%0" 3868 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi") 3869 (set_attr "isa" "*,*,*,*,*,*,fix,fix")]) 3870 3871;; Subregs suck for register allocation. Pretend we can move TFmode 3872;; data between general registers until after reload. 3873;; ??? Is this still true now that we have the lower-subreg pass? 3874 3875(define_expand "movtf" 3876 [(set (match_operand:TF 0 "nonimmediate_operand") 3877 (match_operand:TF 1 "general_operand"))] 3878 "" 3879{ 3880 if (MEM_P (operands[0]) 3881 && ! reg_or_0_operand (operands[1], TFmode)) 3882 operands[1] = force_reg (TFmode, operands[1]); 3883}) 3884 3885(define_insn_and_split "*movtf" 3886 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o") 3887 (match_operand:TF 1 "input_operand" "roG,rG"))] 3888 "register_operand (operands[0], TFmode) 3889 || reg_or_0_operand (operands[1], TFmode)" 3890 "#" 3891 "reload_completed" 3892 [(set (match_dup 0) (match_dup 2)) 3893 (set (match_dup 1) (match_dup 3))] 3894 "alpha_split_tmode_pair (operands, TFmode, true);") 3895 3896;; We do two major things here: handle mem->mem and construct long 3897;; constants. 3898 3899(define_expand "movsi" 3900 [(set (match_operand:SI 0 "nonimmediate_operand") 3901 (match_operand:SI 1 "general_operand"))] 3902 "" 3903{ 3904 if (alpha_expand_mov (SImode, operands)) 3905 DONE; 3906}) 3907 3908(define_insn "*movsi" 3909 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,r") 3910 (match_operand:SI 1 "input_operand" "rJ,K,L,n,m,rJ,s"))] 3911 "register_operand (operands[0], SImode) 3912 || reg_or_0_operand (operands[1], SImode)" 3913 "@ 3914 bis $31,%r1,%0 3915 lda %0,%1($31) 3916 ldah %0,%h1($31) 3917 # 3918 ldl %0,%1 3919 stl %r1,%0 3920 lda %0,%1" 3921 [(set_attr "type" "ilog,iadd,iadd,multi,ild,ist,ldsym") 3922 (set_attr "isa" "*,*,*,*,*,*,vms")]) 3923 3924;; Split a load of a large constant into the appropriate two-insn 3925;; sequence. 3926 3927(define_split 3928 [(set (match_operand:SI 0 "register_operand") 3929 (match_operand:SI 1 "non_add_const_operand"))] 3930 "" 3931 [(const_int 0)] 3932{ 3933 if (alpha_split_const_mov (SImode, operands)) 3934 DONE; 3935 else 3936 FAIL; 3937}) 3938 3939(define_insn "*movdi_er_low_l" 3940 [(set (match_operand:DI 0 "register_operand" "=r") 3941 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 3942 (match_operand:DI 2 "local_symbolic_operand")))] 3943 "TARGET_EXPLICIT_RELOCS" 3944{ 3945 if (true_regnum (operands[1]) == 29) 3946 return "lda %0,%2(%1)\t\t!gprel"; 3947 else 3948 return "lda %0,%2(%1)\t\t!gprellow"; 3949} 3950 [(set_attr "usegp" "yes")]) 3951 3952(define_split 3953 [(set (match_operand:DI 0 "register_operand") 3954 (match_operand:DI 1 "small_symbolic_operand"))] 3955 "TARGET_EXPLICIT_RELOCS && reload_completed" 3956 [(set (match_dup 0) 3957 (lo_sum:DI (match_dup 2) (match_dup 1)))] 3958 "operands[2] = pic_offset_table_rtx;") 3959 3960(define_split 3961 [(set (match_operand:DI 0 "register_operand") 3962 (match_operand:DI 1 "local_symbolic_operand"))] 3963 "TARGET_EXPLICIT_RELOCS && reload_completed" 3964 [(set (match_dup 0) 3965 (plus:DI (match_dup 2) (high:DI (match_dup 1)))) 3966 (set (match_dup 0) 3967 (lo_sum:DI (match_dup 0) (match_dup 1)))] 3968 "operands[2] = pic_offset_table_rtx;") 3969 3970(define_split 3971 [(match_operand 0 "some_small_symbolic_operand")] 3972 "" 3973 [(match_dup 0)] 3974 "operands[0] = split_small_symbolic_operand (operands[0]);") 3975 3976;; Accepts any symbolic, not just global, since function calls that 3977;; don't go via bsr still use !literal in hopes of linker relaxation. 3978(define_insn "movdi_er_high_g" 3979 [(set (match_operand:DI 0 "register_operand" "=r") 3980 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 3981 (match_operand:DI 2 "symbolic_operand") 3982 (match_operand 3 "const_int_operand")] 3983 UNSPEC_LITERAL))] 3984 "TARGET_EXPLICIT_RELOCS" 3985{ 3986 if (INTVAL (operands[3]) == 0) 3987 return "ldq %0,%2(%1)\t\t!literal"; 3988 else 3989 return "ldq %0,%2(%1)\t\t!literal!%3"; 3990} 3991 [(set_attr "type" "ldsym")]) 3992 3993(define_split 3994 [(set (match_operand:DI 0 "register_operand") 3995 (match_operand:DI 1 "global_symbolic_operand"))] 3996 "TARGET_EXPLICIT_RELOCS && reload_completed" 3997 [(set (match_dup 0) 3998 (unspec:DI [(match_dup 2) 3999 (match_dup 1) 4000 (const_int 0)] UNSPEC_LITERAL))] 4001 "operands[2] = pic_offset_table_rtx;") 4002 4003(define_insn "movdi_er_tlsgd" 4004 [(set (match_operand:DI 0 "register_operand" "=r") 4005 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 4006 (match_operand:DI 2 "symbolic_operand") 4007 (match_operand 3 "const_int_operand")] 4008 UNSPEC_TLSGD))] 4009 "HAVE_AS_TLS" 4010{ 4011 if (INTVAL (operands[3]) == 0) 4012 return "lda %0,%2(%1)\t\t!tlsgd"; 4013 else 4014 return "lda %0,%2(%1)\t\t!tlsgd!%3"; 4015}) 4016 4017(define_insn "movdi_er_tlsldm" 4018 [(set (match_operand:DI 0 "register_operand" "=r") 4019 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 4020 (match_operand 2 "const_int_operand")] 4021 UNSPEC_TLSLDM))] 4022 "HAVE_AS_TLS" 4023{ 4024 if (INTVAL (operands[2]) == 0) 4025 return "lda %0,%&(%1)\t\t!tlsldm"; 4026 else 4027 return "lda %0,%&(%1)\t\t!tlsldm!%2"; 4028}) 4029 4030(define_insn "*movdi_er_gotdtp" 4031 [(set (match_operand:DI 0 "register_operand" "=r") 4032 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 4033 (match_operand:DI 2 "symbolic_operand")] 4034 UNSPEC_DTPREL))] 4035 "HAVE_AS_TLS" 4036 "ldq %0,%2(%1)\t\t!gotdtprel" 4037 [(set_attr "type" "ild") 4038 (set_attr "usegp" "yes")]) 4039 4040(define_split 4041 [(set (match_operand:DI 0 "register_operand") 4042 (match_operand:DI 1 "gotdtp_symbolic_operand"))] 4043 "HAVE_AS_TLS && reload_completed" 4044 [(set (match_dup 0) 4045 (unspec:DI [(match_dup 2) 4046 (match_dup 1)] UNSPEC_DTPREL))] 4047{ 4048 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0); 4049 operands[2] = pic_offset_table_rtx; 4050}) 4051 4052(define_insn "*movdi_er_gottp" 4053 [(set (match_operand:DI 0 "register_operand" "=r") 4054 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 4055 (match_operand:DI 2 "symbolic_operand")] 4056 UNSPEC_TPREL))] 4057 "HAVE_AS_TLS" 4058 "ldq %0,%2(%1)\t\t!gottprel" 4059 [(set_attr "type" "ild") 4060 (set_attr "usegp" "yes")]) 4061 4062(define_split 4063 [(set (match_operand:DI 0 "register_operand") 4064 (match_operand:DI 1 "gottp_symbolic_operand"))] 4065 "HAVE_AS_TLS && reload_completed" 4066 [(set (match_dup 0) 4067 (unspec:DI [(match_dup 2) 4068 (match_dup 1)] UNSPEC_TPREL))] 4069{ 4070 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0); 4071 operands[2] = pic_offset_table_rtx; 4072}) 4073 4074(define_insn "*movdi" 4075 [(set (match_operand:DI 0 "nonimmediate_operand" 4076 "=r,r,r,r,r,r,r,r, m, *f,*f, Q, r,*f") 4077 (match_operand:DI 1 "input_operand" 4078 "rJ,K,L,T,s,n,s,m,rJ,*fJ, Q,*f,*f, r"))] 4079 "register_operand (operands[0], DImode) 4080 || reg_or_0_operand (operands[1], DImode)" 4081 "@ 4082 mov %r1,%0 4083 lda %0,%1($31) 4084 ldah %0,%h1($31) 4085 # 4086 # 4087 # 4088 lda %0,%1 4089 ldq%A1 %0,%1 4090 stq%A0 %r1,%0 4091 fmov %R1,%0 4092 ldt %0,%1 4093 stt %R1,%0 4094 ftoit %1,%0 4095 itoft %1,%0" 4096 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof") 4097 (set_attr "isa" "*,*,*,er,er,*,ner,*,*,*,*,*,fix,fix") 4098 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*,*,*")]) 4099 4100;; VMS needs to set up "vms_base_regno" for unwinding. This move 4101;; often appears dead to the life analysis code, at which point we 4102;; die for emitting dead prologue instructions. Force this live. 4103 4104(define_insn "force_movdi" 4105 [(set (match_operand:DI 0 "register_operand" "=r") 4106 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")] 4107 UNSPECV_FORCE_MOV))] 4108 "" 4109 "mov %1,%0" 4110 [(set_attr "type" "ilog")]) 4111 4112;; We do three major things here: handle mem->mem, put 64-bit constants in 4113;; memory, and construct long 32-bit constants. 4114 4115(define_expand "movdi" 4116 [(set (match_operand:DI 0 "nonimmediate_operand") 4117 (match_operand:DI 1 "general_operand"))] 4118 "" 4119{ 4120 if (alpha_expand_mov (DImode, operands)) 4121 DONE; 4122}) 4123 4124;; Split a load of a large constant into the appropriate two-insn 4125;; sequence. 4126 4127(define_split 4128 [(set (match_operand:DI 0 "register_operand") 4129 (match_operand:DI 1 "non_add_const_operand"))] 4130 "" 4131 [(const_int 0)] 4132{ 4133 if (alpha_split_const_mov (DImode, operands)) 4134 DONE; 4135 else 4136 FAIL; 4137}) 4138 4139;; We need to prevent reload from splitting TImode moves, because it 4140;; might decide to overwrite a pointer with the value it points to. 4141;; In that case we have to do the loads in the appropriate order so 4142;; that the pointer is not destroyed too early. 4143 4144(define_insn_and_split "*movti_internal" 4145 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o") 4146 (match_operand:TI 1 "input_operand" "roJ,rJ"))] 4147 "(register_operand (operands[0], TImode) 4148 /* Prevent rematerialization of constants. */ 4149 && ! CONSTANT_P (operands[1])) 4150 || reg_or_0_operand (operands[1], TImode)" 4151 "#" 4152 "reload_completed" 4153 [(set (match_dup 0) (match_dup 2)) 4154 (set (match_dup 1) (match_dup 3))] 4155 "alpha_split_tmode_pair (operands, TImode, true);") 4156 4157(define_expand "movti" 4158 [(set (match_operand:TI 0 "nonimmediate_operand") 4159 (match_operand:TI 1 "general_operand"))] 4160 "" 4161{ 4162 if (MEM_P (operands[0]) 4163 && ! reg_or_0_operand (operands[1], TImode)) 4164 operands[1] = force_reg (TImode, operands[1]); 4165 4166 if (operands[1] == const0_rtx) 4167 ; 4168 /* We must put 64-bit constants in memory. We could keep the 4169 32-bit constants in TImode and rely on the splitter, but 4170 this doesn't seem to be worth the pain. */ 4171 else if (CONST_INT_P (operands[1]) 4172 || GET_CODE (operands[1]) == CONST_DOUBLE) 4173 { 4174 rtx in[2], out[2], target; 4175 4176 gcc_assert (can_create_pseudo_p ()); 4177 4178 split_double (operands[1], &in[0], &in[1]); 4179 4180 if (in[0] == const0_rtx) 4181 out[0] = const0_rtx; 4182 else 4183 { 4184 out[0] = gen_reg_rtx (DImode); 4185 emit_insn (gen_movdi (out[0], in[0])); 4186 } 4187 4188 if (in[1] == const0_rtx) 4189 out[1] = const0_rtx; 4190 else 4191 { 4192 out[1] = gen_reg_rtx (DImode); 4193 emit_insn (gen_movdi (out[1], in[1])); 4194 } 4195 4196 if (!REG_P (operands[0])) 4197 target = gen_reg_rtx (TImode); 4198 else 4199 target = operands[0]; 4200 4201 emit_insn (gen_movdi (operand_subword (target, 0, 0, TImode), out[0])); 4202 emit_insn (gen_movdi (operand_subword (target, 1, 0, TImode), out[1])); 4203 4204 if (target != operands[0]) 4205 emit_insn (gen_rtx_SET (VOIDmode, operands[0], target)); 4206 4207 DONE; 4208 } 4209}) 4210 4211;; These are the partial-word cases. 4212;; 4213;; First we have the code to load an aligned word. Operand 0 is the register 4214;; in which to place the result. It's mode is QImode or HImode. Operand 1 4215;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the 4216;; number of bits within the word that the value is. Operand 3 is an SImode 4217;; scratch register. If operand 0 is a hard register, operand 3 may be the 4218;; same register. It is allowed to conflict with operand 1 as well. 4219 4220(define_expand "aligned_loadqi" 4221 [(set (match_operand:SI 3 "register_operand") 4222 (match_operand:SI 1 "memory_operand")) 4223 (set (match_operand:DI 0 "register_operand") 4224 (zero_extract:DI (subreg:DI (match_dup 3) 0) 4225 (const_int 8) 4226 (match_operand:DI 2 "const_int_operand")))]) 4227 4228(define_expand "aligned_loadhi" 4229 [(set (match_operand:SI 3 "register_operand") 4230 (match_operand:SI 1 "memory_operand")) 4231 (set (match_operand:DI 0 "register_operand") 4232 (zero_extract:DI (subreg:DI (match_dup 3) 0) 4233 (const_int 16) 4234 (match_operand:DI 2 "const_int_operand")))]) 4235 4236;; Similar for unaligned loads, where we use the sequence from the 4237;; Alpha Architecture manual. We have to distinguish between little-endian 4238;; and big-endian systems as the sequences are different. 4239;; 4240;; Operand 1 is the address. Operands 2 and 3 are temporaries, where 4241;; operand 3 can overlap the input and output registers. 4242 4243(define_expand "unaligned_loadqi" 4244 [(set (match_operand:DI 2 "register_operand") 4245 (mem:DI (and:DI (match_operand:DI 1 "address_operand") 4246 (const_int -8)))) 4247 (set (match_operand:DI 3 "register_operand") 4248 (match_dup 1)) 4249 (set (match_operand:DI 0 "register_operand") 4250 (zero_extract:DI (match_dup 2) 4251 (const_int 8) 4252 (ashift:DI (match_dup 3) (const_int 3))))]) 4253 4254(define_expand "unaligned_loadhi" 4255 [(set (match_operand:DI 2 "register_operand") 4256 (mem:DI (and:DI (match_operand:DI 1 "address_operand") 4257 (const_int -8)))) 4258 (set (match_operand:DI 3 "register_operand") 4259 (match_dup 1)) 4260 (set (match_operand:DI 0 "register_operand") 4261 (zero_extract:DI (match_dup 2) 4262 (const_int 16) 4263 (ashift:DI (match_dup 3) (const_int 3))))]) 4264 4265;; Storing an aligned byte or word requires two temporaries. Operand 0 is the 4266;; aligned SImode MEM. Operand 1 is the register containing the 4267;; byte or word to store. Operand 2 is the number of bits within the word that 4268;; the value should be placed. Operands 3 and 4 are SImode temporaries. 4269 4270(define_expand "aligned_store" 4271 [(set (match_operand:SI 3 "register_operand") 4272 (match_operand:SI 0 "memory_operand")) 4273 (set (subreg:DI (match_dup 3) 0) 4274 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5))) 4275 (set (subreg:DI (match_operand:SI 4 "register_operand") 0) 4276 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand")) 4277 (match_operand:DI 2 "const_int_operand"))) 4278 (set (subreg:DI (match_dup 4) 0) 4279 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0))) 4280 (set (match_dup 0) (match_dup 4))] 4281 "" 4282{ 4283 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1])) 4284 << INTVAL (operands[2]))); 4285}) 4286 4287;; For the unaligned byte and halfword cases, we use code similar to that 4288;; in the ;; Architecture book, but reordered to lower the number of registers 4289;; required. Operand 0 is the address. Operand 1 is the data to store. 4290;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may 4291;; be the same temporary, if desired. If the address is in a register, 4292;; operand 2 can be that register. 4293 4294(define_expand "unaligned_store<mode>" 4295 [(set (match_operand:DI 3 "register_operand") 4296 (mem:DI (and:DI (match_operand:DI 0 "address_operand") 4297 (const_int -8)))) 4298 (set (match_operand:DI 2 "register_operand") 4299 (match_dup 0)) 4300 (set (match_dup 3) 4301 (and:DI (not:DI (ashift:DI (match_dup 5) 4302 (ashift:DI (match_dup 2) (const_int 3)))) 4303 (match_dup 3))) 4304 (set (match_operand:DI 4 "register_operand") 4305 (ashift:DI (zero_extend:DI 4306 (match_operand:I12MODE 1 "register_operand")) 4307 (ashift:DI (match_dup 2) (const_int 3)))) 4308 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3))) 4309 (set (mem:DI (and:DI (match_dup 0) (const_int -8))) 4310 (match_dup 4))] 4311 "" 4312 "operands[5] = GEN_INT (GET_MODE_MASK (<MODE>mode));") 4313 4314;; Here are the define_expand's for QI and HI moves that use the above 4315;; patterns. We have the normal sets, plus the ones that need scratch 4316;; registers for reload. 4317 4318(define_expand "mov<mode>" 4319 [(set (match_operand:I12MODE 0 "nonimmediate_operand") 4320 (match_operand:I12MODE 1 "general_operand"))] 4321 "" 4322{ 4323 if (TARGET_BWX 4324 ? alpha_expand_mov (<MODE>mode, operands) 4325 : alpha_expand_mov_nobwx (<MODE>mode, operands)) 4326 DONE; 4327}) 4328 4329(define_insn "*movqi" 4330 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m") 4331 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))] 4332 "register_operand (operands[0], QImode) 4333 || reg_or_0_operand (operands[1], QImode)" 4334 "@ 4335 bis $31,%r1,%0 4336 lda %0,%L1($31) 4337 ldbu %0,%1 4338 stb %r1,%0" 4339 [(set_attr "type" "ilog,iadd,ild,ist") 4340 (set_attr "isa" "*,*,bwx,bwx")]) 4341 4342(define_insn "*movhi" 4343 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m") 4344 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))] 4345 "register_operand (operands[0], HImode) 4346 || reg_or_0_operand (operands[1], HImode)" 4347 "@ 4348 bis $31,%r1,%0 4349 lda %0,%L1($31) 4350 ldwu %0,%1 4351 stw %r1,%0" 4352 [(set_attr "type" "ilog,iadd,ild,ist") 4353 (set_attr "isa" "*,*,bwx,bwx")]) 4354 4355;; We need to hook into the extra support that we have for HImode 4356;; reloads when BWX insns are not available. 4357(define_expand "movcqi" 4358 [(set (match_operand:CQI 0 "nonimmediate_operand") 4359 (match_operand:CQI 1 "general_operand"))] 4360 "!TARGET_BWX" 4361{ 4362 if (GET_CODE (operands[0]) == CONCAT || GET_CODE (operands[1]) == CONCAT) 4363 ; 4364 else if (!any_memory_operand (operands[0], CQImode)) 4365 { 4366 if (!any_memory_operand (operands[1], CQImode)) 4367 { 4368 emit_move_insn (gen_lowpart (HImode, operands[0]), 4369 gen_lowpart (HImode, operands[1])); 4370 DONE; 4371 } 4372 if (aligned_memory_operand (operands[1], CQImode)) 4373 { 4374 bool done; 4375 do_aligned1: 4376 operands[1] = gen_lowpart (HImode, operands[1]); 4377 do_aligned2: 4378 operands[0] = gen_lowpart (HImode, operands[0]); 4379 done = alpha_expand_mov_nobwx (HImode, operands); 4380 gcc_assert (done); 4381 DONE; 4382 } 4383 } 4384 else if (aligned_memory_operand (operands[0], CQImode)) 4385 { 4386 if (MEM_P (operands[1])) 4387 { 4388 rtx x = gen_reg_rtx (HImode); 4389 emit_move_insn (gen_lowpart (CQImode, x), operands[1]); 4390 operands[1] = x; 4391 goto do_aligned2; 4392 } 4393 goto do_aligned1; 4394 } 4395 4396 gcc_assert (!reload_in_progress); 4397 emit_move_complex_parts (operands[0], operands[1]); 4398 DONE; 4399}) 4400 4401;; Here are the versions for reload. 4402;; 4403;; The aligned input case is recognized early in alpha_secondary_reload 4404;; in order to avoid allocating an unnecessary scratch register. 4405;; 4406;; Note that in the unaligned cases we know that the operand must not be 4407;; a pseudo-register because stack slots are always aligned references. 4408 4409(define_expand "reload_in<mode>" 4410 [(parallel [(match_operand:RELOAD12 0 "register_operand" "=r") 4411 (match_operand:RELOAD12 1 "any_memory_operand" "m") 4412 (match_operand:TI 2 "register_operand" "=&r")])] 4413 "!TARGET_BWX" 4414{ 4415 rtx scratch, seq, addr; 4416 unsigned regno = REGNO (operands[2]); 4417 4418 /* It is possible that one of the registers we got for operands[2] 4419 might coincide with that of operands[0] (which is why we made 4420 it TImode). Pick the other one to use as our scratch. */ 4421 if (regno == REGNO (operands[0])) 4422 regno++; 4423 scratch = gen_rtx_REG (DImode, regno); 4424 4425 addr = get_unaligned_address (operands[1]); 4426 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0])); 4427 seq = gen_unaligned_load<reloadmode> (operands[0], addr, 4428 scratch, operands[0]); 4429 alpha_set_memflags (seq, operands[1]); 4430 4431 emit_insn (seq); 4432 DONE; 4433}) 4434 4435(define_expand "reload_out<mode>" 4436 [(parallel [(match_operand:RELOAD12 0 "any_memory_operand" "=m") 4437 (match_operand:RELOAD12 1 "register_operand" "r") 4438 (match_operand:TI 2 "register_operand" "=&r")])] 4439 "!TARGET_BWX" 4440{ 4441 unsigned regno = REGNO (operands[2]); 4442 4443 if (<MODE>mode == CQImode) 4444 { 4445 operands[0] = gen_lowpart (HImode, operands[0]); 4446 operands[1] = gen_lowpart (HImode, operands[1]); 4447 } 4448 4449 if (aligned_memory_operand (operands[0], <MODE>mode)) 4450 { 4451 emit_insn (gen_reload_out<reloadmode>_aligned 4452 (operands[0], operands[1], 4453 gen_rtx_REG (SImode, regno), 4454 gen_rtx_REG (SImode, regno + 1))); 4455 } 4456 else 4457 { 4458 rtx addr = get_unaligned_address (operands[0]); 4459 rtx scratch1 = gen_rtx_REG (DImode, regno); 4460 rtx scratch2 = gen_rtx_REG (DImode, regno + 1); 4461 rtx scratch3 = scratch1; 4462 rtx seq; 4463 4464 if (REG_P (addr)) 4465 scratch1 = addr; 4466 4467 seq = gen_unaligned_store<reloadmode> (addr, operands[1], scratch1, 4468 scratch2, scratch3); 4469 alpha_set_memflags (seq, operands[0]); 4470 emit_insn (seq); 4471 } 4472 DONE; 4473}) 4474 4475;; Helpers for the above. The way reload is structured, we can't 4476;; always get a proper address for a stack slot during reload_foo 4477;; expansion, so we must delay our address manipulations until after. 4478 4479(define_insn_and_split "reload_in<mode>_aligned" 4480 [(set (match_operand:I12MODE 0 "register_operand" "=r") 4481 (match_operand:I12MODE 1 "memory_operand" "m"))] 4482 "!TARGET_BWX && (reload_in_progress || reload_completed)" 4483 "#" 4484 "!TARGET_BWX && reload_completed" 4485 [(const_int 0)] 4486{ 4487 rtx aligned_mem, bitnum; 4488 get_aligned_mem (operands[1], &aligned_mem, &bitnum); 4489 emit_insn (gen_aligned_load<reloadmode> 4490 (gen_lowpart (DImode, operands[0]), aligned_mem, bitnum, 4491 gen_rtx_REG (SImode, REGNO (operands[0])))); 4492 DONE; 4493}) 4494 4495(define_insn_and_split "reload_out<mode>_aligned" 4496 [(set (match_operand:I12MODE 0 "memory_operand" "=m") 4497 (match_operand:I12MODE 1 "register_operand" "r")) 4498 (clobber (match_operand:SI 2 "register_operand" "=r")) 4499 (clobber (match_operand:SI 3 "register_operand" "=r"))] 4500 "!TARGET_BWX && (reload_in_progress || reload_completed)" 4501 "#" 4502 "!TARGET_BWX && reload_completed" 4503 [(const_int 0)] 4504{ 4505 rtx aligned_mem, bitnum; 4506 get_aligned_mem (operands[0], &aligned_mem, &bitnum); 4507 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum, 4508 operands[2], operands[3])); 4509 DONE; 4510}) 4511 4512;; Vector operations 4513 4514(define_mode_iterator VEC [V8QI V4HI V2SI]) 4515(define_mode_iterator VEC12 [V8QI V4HI]) 4516 4517(define_expand "mov<mode>" 4518 [(set (match_operand:VEC 0 "nonimmediate_operand") 4519 (match_operand:VEC 1 "general_operand"))] 4520 "" 4521{ 4522 if (alpha_expand_mov (<MODE>mode, operands)) 4523 DONE; 4524}) 4525 4526(define_split 4527 [(set (match_operand:VEC 0 "register_operand") 4528 (match_operand:VEC 1 "non_zero_const_operand"))] 4529 "" 4530 [(const_int 0)] 4531{ 4532 if (alpha_split_const_mov (<MODE>mode, operands)) 4533 DONE; 4534 else 4535 FAIL; 4536}) 4537 4538 4539(define_expand "movmisalign<mode>" 4540 [(set (match_operand:VEC 0 "nonimmediate_operand") 4541 (match_operand:VEC 1 "general_operand"))] 4542 "" 4543{ 4544 alpha_expand_movmisalign (<MODE>mode, operands); 4545 DONE; 4546}) 4547 4548(define_insn "*mov<mode>_fix" 4549 [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m,r,*f") 4550 (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f,*f,r"))] 4551 "register_operand (operands[0], <MODE>mode) 4552 || reg_or_0_operand (operands[1], <MODE>mode)" 4553 "@ 4554 bis $31,%r1,%0 4555 # 4556 ldq %0,%1 4557 stq %r1,%0 4558 cpys %R1,%R1,%0 4559 ldt %0,%1 4560 stt %R1,%0 4561 ftoit %1,%0 4562 itoft %1,%0" 4563 [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof") 4564 (set_attr "isa" "*,*,*,*,*,*,*,fix,fix")]) 4565 4566(define_insn "<code><mode>3" 4567 [(set (match_operand:VEC12 0 "register_operand" "=r") 4568 (any_maxmin:VEC12 4569 (match_operand:VEC12 1 "reg_or_0_operand" "rW") 4570 (match_operand:VEC12 2 "reg_or_0_operand" "rW")))] 4571 "TARGET_MAX" 4572 "<maxmin><modesuffix> %r1,%r2,%0" 4573 [(set_attr "type" "mvi")]) 4574 4575(define_insn "one_cmpl<mode>2" 4576 [(set (match_operand:VEC 0 "register_operand" "=r") 4577 (not:VEC (match_operand:VEC 1 "register_operand" "r")))] 4578 "" 4579 "ornot $31,%1,%0" 4580 [(set_attr "type" "ilog")]) 4581 4582(define_insn "and<mode>3" 4583 [(set (match_operand:VEC 0 "register_operand" "=r") 4584 (and:VEC (match_operand:VEC 1 "register_operand" "r") 4585 (match_operand:VEC 2 "register_operand" "r")))] 4586 "" 4587 "and %1,%2,%0" 4588 [(set_attr "type" "ilog")]) 4589 4590(define_insn "*andnot<mode>3" 4591 [(set (match_operand:VEC 0 "register_operand" "=r") 4592 (and:VEC (not:VEC (match_operand:VEC 1 "register_operand" "r")) 4593 (match_operand:VEC 2 "register_operand" "r")))] 4594 "" 4595 "bic %2,%1,%0" 4596 [(set_attr "type" "ilog")]) 4597 4598(define_insn "ior<mode>3" 4599 [(set (match_operand:VEC 0 "register_operand" "=r") 4600 (ior:VEC (match_operand:VEC 1 "register_operand" "r") 4601 (match_operand:VEC 2 "register_operand" "r")))] 4602 "" 4603 "bis %1,%2,%0" 4604 [(set_attr "type" "ilog")]) 4605 4606(define_insn "*iornot<mode>3" 4607 [(set (match_operand:VEC 0 "register_operand" "=r") 4608 (ior:VEC (not:DI (match_operand:VEC 1 "register_operand" "r")) 4609 (match_operand:VEC 2 "register_operand" "r")))] 4610 "" 4611 "ornot %2,%1,%0" 4612 [(set_attr "type" "ilog")]) 4613 4614(define_insn "xor<mode>3" 4615 [(set (match_operand:VEC 0 "register_operand" "=r") 4616 (xor:VEC (match_operand:VEC 1 "register_operand" "r") 4617 (match_operand:VEC 2 "register_operand" "r")))] 4618 "" 4619 "xor %1,%2,%0" 4620 [(set_attr "type" "ilog")]) 4621 4622(define_insn "*xornot<mode>3" 4623 [(set (match_operand:VEC 0 "register_operand" "=r") 4624 (not:VEC (xor:VEC (match_operand:VEC 1 "register_operand" "r") 4625 (match_operand:VEC 2 "register_operand" "r"))))] 4626 "" 4627 "eqv %1,%2,%0" 4628 [(set_attr "type" "ilog")]) 4629 4630(define_expand "vec_shl_<mode>" 4631 [(set (match_operand:VEC 0 "register_operand") 4632 (ashift:DI (match_operand:VEC 1 "register_operand") 4633 (match_operand:DI 2 "reg_or_6bit_operand")))] 4634 "" 4635{ 4636 operands[0] = gen_lowpart (DImode, operands[0]); 4637 operands[1] = gen_lowpart (DImode, operands[1]); 4638}) 4639 4640(define_expand "vec_shr_<mode>" 4641 [(set (match_operand:VEC 0 "register_operand") 4642 (lshiftrt:DI (match_operand:VEC 1 "register_operand") 4643 (match_operand:DI 2 "reg_or_6bit_operand")))] 4644 "" 4645{ 4646 operands[0] = gen_lowpart (DImode, operands[0]); 4647 operands[1] = gen_lowpart (DImode, operands[1]); 4648}) 4649 4650;; Bit field extract patterns which use ext[wlq][lh] 4651 4652(define_expand "extvmisaligndi" 4653 [(set (match_operand:DI 0 "register_operand") 4654 (sign_extract:DI (match_operand:BLK 1 "memory_operand") 4655 (match_operand:DI 2 "const_int_operand") 4656 (match_operand:DI 3 "const_int_operand")))] 4657 "" 4658{ 4659 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */ 4660 if (INTVAL (operands[3]) % 8 != 0 4661 || (INTVAL (operands[2]) != 16 4662 && INTVAL (operands[2]) != 32 4663 && INTVAL (operands[2]) != 64)) 4664 FAIL; 4665 4666 alpha_expand_unaligned_load (operands[0], operands[1], 4667 INTVAL (operands[2]) / 8, 4668 INTVAL (operands[3]) / 8, 1); 4669 DONE; 4670}) 4671 4672(define_expand "extzvdi" 4673 [(set (match_operand:DI 0 "register_operand") 4674 (zero_extract:DI (match_operand:DI 1 "register_operand") 4675 (match_operand:DI 2 "const_int_operand") 4676 (match_operand:DI 3 "const_int_operand")))] 4677 "" 4678{ 4679 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */ 4680 if (INTVAL (operands[3]) % 8 != 0 4681 || (INTVAL (operands[2]) != 8 4682 && INTVAL (operands[2]) != 16 4683 && INTVAL (operands[2]) != 32 4684 && INTVAL (operands[2]) != 64)) 4685 FAIL; 4686}) 4687 4688(define_expand "extzvmisaligndi" 4689 [(set (match_operand:DI 0 "register_operand") 4690 (zero_extract:DI (match_operand:BLK 1 "memory_operand") 4691 (match_operand:DI 2 "const_int_operand") 4692 (match_operand:DI 3 "const_int_operand")))] 4693 "" 4694{ 4695 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. 4696 We fail 8-bit fields, falling back on a simple byte load. */ 4697 if (INTVAL (operands[3]) % 8 != 0 4698 || (INTVAL (operands[2]) != 16 4699 && INTVAL (operands[2]) != 32 4700 && INTVAL (operands[2]) != 64)) 4701 FAIL; 4702 4703 alpha_expand_unaligned_load (operands[0], operands[1], 4704 INTVAL (operands[2]) / 8, 4705 INTVAL (operands[3]) / 8, 0); 4706 DONE; 4707}) 4708 4709(define_expand "insvmisaligndi" 4710 [(set (zero_extract:DI (match_operand:BLK 0 "memory_operand") 4711 (match_operand:DI 1 "const_int_operand") 4712 (match_operand:DI 2 "const_int_operand")) 4713 (match_operand:DI 3 "register_operand"))] 4714 "" 4715{ 4716 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */ 4717 if (INTVAL (operands[2]) % 8 != 0 4718 || (INTVAL (operands[1]) != 16 4719 && INTVAL (operands[1]) != 32 4720 && INTVAL (operands[1]) != 64)) 4721 FAIL; 4722 4723 alpha_expand_unaligned_store (operands[0], operands[3], 4724 INTVAL (operands[1]) / 8, 4725 INTVAL (operands[2]) / 8); 4726 DONE; 4727}) 4728 4729;; Block move/clear, see alpha.c for more details. 4730;; Argument 0 is the destination 4731;; Argument 1 is the source 4732;; Argument 2 is the length 4733;; Argument 3 is the alignment 4734 4735(define_expand "movmemqi" 4736 [(parallel [(set (match_operand:BLK 0 "memory_operand") 4737 (match_operand:BLK 1 "memory_operand")) 4738 (use (match_operand:DI 2 "immediate_operand")) 4739 (use (match_operand:DI 3 "immediate_operand"))])] 4740 "" 4741{ 4742 if (alpha_expand_block_move (operands)) 4743 DONE; 4744 else 4745 FAIL; 4746}) 4747 4748(define_expand "movmemdi" 4749 [(parallel [(set (match_operand:BLK 0 "memory_operand") 4750 (match_operand:BLK 1 "memory_operand")) 4751 (use (match_operand:DI 2 "immediate_operand")) 4752 (use (match_operand:DI 3 "immediate_operand")) 4753 (use (match_dup 4)) 4754 (clobber (reg:DI 25)) 4755 (clobber (reg:DI 16)) 4756 (clobber (reg:DI 17)) 4757 (clobber (reg:DI 18)) 4758 (clobber (reg:DI 19)) 4759 (clobber (reg:DI 20)) 4760 (clobber (reg:DI 26)) 4761 (clobber (reg:DI 27))])] 4762 "TARGET_ABI_OPEN_VMS" 4763 "operands[4] = gen_rtx_SYMBOL_REF (Pmode, \"OTS$MOVE\");") 4764 4765(define_insn "*movmemdi_1" 4766 [(set (match_operand:BLK 0 "memory_operand" "=m,=m") 4767 (match_operand:BLK 1 "memory_operand" "m,m")) 4768 (use (match_operand:DI 2 "nonmemory_operand" "r,i")) 4769 (use (match_operand:DI 3 "immediate_operand")) 4770 (use (match_operand:DI 4 "call_operand" "i,i")) 4771 (clobber (reg:DI 25)) 4772 (clobber (reg:DI 16)) 4773 (clobber (reg:DI 17)) 4774 (clobber (reg:DI 18)) 4775 (clobber (reg:DI 19)) 4776 (clobber (reg:DI 20)) 4777 (clobber (reg:DI 26)) 4778 (clobber (reg:DI 27))] 4779 "TARGET_ABI_OPEN_VMS" 4780{ 4781 operands [5] = alpha_use_linkage (operands [4], false, true); 4782 switch (which_alternative) 4783 { 4784 case 0: 4785 return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)"; 4786 case 1: 4787 return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)"; 4788 default: 4789 gcc_unreachable (); 4790 } 4791} 4792 [(set_attr "type" "multi") 4793 (set_attr "length" "28")]) 4794 4795(define_expand "setmemqi" 4796 [(parallel [(set (match_operand:BLK 0 "memory_operand") 4797 (match_operand 2 "const_int_operand")) 4798 (use (match_operand:DI 1 "immediate_operand")) 4799 (use (match_operand:DI 3 "immediate_operand"))])] 4800 "" 4801{ 4802 /* If value to set is not zero, use the library routine. */ 4803 if (operands[2] != const0_rtx) 4804 FAIL; 4805 4806 if (alpha_expand_block_clear (operands)) 4807 DONE; 4808 else 4809 FAIL; 4810}) 4811 4812(define_expand "setmemdi" 4813 [(parallel [(set (match_operand:BLK 0 "memory_operand") 4814 (match_operand 2 "const_int_operand")) 4815 (use (match_operand:DI 1 "immediate_operand")) 4816 (use (match_operand:DI 3 "immediate_operand")) 4817 (use (match_dup 4)) 4818 (clobber (reg:DI 25)) 4819 (clobber (reg:DI 16)) 4820 (clobber (reg:DI 17)) 4821 (clobber (reg:DI 26)) 4822 (clobber (reg:DI 27))])] 4823 "TARGET_ABI_OPEN_VMS" 4824{ 4825 /* If value to set is not zero, use the library routine. */ 4826 if (operands[2] != const0_rtx) 4827 FAIL; 4828 4829 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO"); 4830}) 4831 4832(define_insn "*clrmemdi_1" 4833 [(set (match_operand:BLK 0 "memory_operand" "=m,=m") 4834 (const_int 0)) 4835 (use (match_operand:DI 1 "nonmemory_operand" "r,i")) 4836 (use (match_operand:DI 2 "immediate_operand")) 4837 (use (match_operand:DI 3 "call_operand" "i,i")) 4838 (clobber (reg:DI 25)) 4839 (clobber (reg:DI 16)) 4840 (clobber (reg:DI 17)) 4841 (clobber (reg:DI 26)) 4842 (clobber (reg:DI 27))] 4843 "TARGET_ABI_OPEN_VMS" 4844{ 4845 operands [4] = alpha_use_linkage (operands [3], false, true); 4846 switch (which_alternative) 4847 { 4848 case 0: 4849 return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)"; 4850 case 1: 4851 return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)"; 4852 default: 4853 gcc_unreachable (); 4854 } 4855} 4856 [(set_attr "type" "multi") 4857 (set_attr "length" "24")]) 4858 4859 4860;; Subroutine of stack space allocation. Perform a stack probe. 4861(define_expand "probe_stack" 4862 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand"))] 4863 "" 4864{ 4865 operands[1] = gen_rtx_MEM (DImode, plus_constant (Pmode, stack_pointer_rtx, 4866 INTVAL (operands[0]))); 4867 MEM_VOLATILE_P (operands[1]) = 1; 4868 4869 operands[0] = const0_rtx; 4870}) 4871 4872;; This is how we allocate stack space. If we are allocating a 4873;; constant amount of space and we know it is less than 4096 4874;; bytes, we need do nothing. 4875;; 4876;; If it is more than 4096 bytes, we need to probe the stack 4877;; periodically. 4878(define_expand "allocate_stack" 4879 [(set (reg:DI 30) 4880 (plus:DI (reg:DI 30) 4881 (match_operand:DI 1 "reg_or_cint_operand"))) 4882 (set (match_operand:DI 0 "register_operand" "=r") 4883 (match_dup 2))] 4884 "" 4885{ 4886 if (CONST_INT_P (operands[1]) 4887 && INTVAL (operands[1]) < 32768) 4888 { 4889 if (INTVAL (operands[1]) >= 4096) 4890 { 4891 /* We do this the same way as in the prologue and generate explicit 4892 probes. Then we update the stack by the constant. */ 4893 4894 int probed = 4096; 4895 4896 emit_insn (gen_probe_stack (GEN_INT (- probed))); 4897 while (probed + 8192 < INTVAL (operands[1])) 4898 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192)))); 4899 4900 if (probed + 4096 < INTVAL (operands[1])) 4901 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1])))); 4902 } 4903 4904 operands[1] = GEN_INT (- INTVAL (operands[1])); 4905 operands[2] = virtual_stack_dynamic_rtx; 4906 } 4907 else 4908 { 4909 rtx out_label = 0; 4910 rtx loop_label = gen_label_rtx (); 4911 rtx want = gen_reg_rtx (Pmode); 4912 rtx tmp = gen_reg_rtx (Pmode); 4913 rtx memref, test; 4914 4915 emit_insn (gen_subdi3 (want, stack_pointer_rtx, 4916 force_reg (Pmode, operands[1]))); 4917 4918 if (!CONST_INT_P (operands[1])) 4919 { 4920 rtx limit = GEN_INT (4096); 4921 out_label = gen_label_rtx (); 4922 test = gen_rtx_LTU (VOIDmode, operands[1], limit); 4923 emit_jump_insn 4924 (gen_cbranchdi4 (test, operands[1], limit, out_label)); 4925 } 4926 4927 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096))); 4928 emit_label (loop_label); 4929 memref = gen_rtx_MEM (DImode, tmp); 4930 MEM_VOLATILE_P (memref) = 1; 4931 emit_move_insn (memref, const0_rtx); 4932 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192))); 4933 test = gen_rtx_GTU (VOIDmode, tmp, want); 4934 emit_jump_insn (gen_cbranchdi4 (test, tmp, want, loop_label)); 4935 4936 memref = gen_rtx_MEM (DImode, want); 4937 MEM_VOLATILE_P (memref) = 1; 4938 emit_move_insn (memref, const0_rtx); 4939 4940 if (out_label) 4941 emit_label (out_label); 4942 4943 emit_move_insn (stack_pointer_rtx, want); 4944 emit_move_insn (operands[0], virtual_stack_dynamic_rtx); 4945 DONE; 4946 } 4947}) 4948 4949;; This is used by alpha_expand_prolog to do the same thing as above, 4950;; except we cannot at that time generate new basic blocks, so we hide 4951;; the loop in this one insn. 4952 4953(define_insn "prologue_stack_probe_loop" 4954 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r") 4955 (match_operand:DI 1 "register_operand" "r")] 4956 UNSPECV_PSPL)] 4957 "" 4958{ 4959 operands[2] = gen_label_rtx (); 4960 (*targetm.asm_out.internal_label) (asm_out_file, "L", 4961 CODE_LABEL_NUMBER (operands[2])); 4962 4963 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2"; 4964} 4965 [(set_attr "length" "16") 4966 (set_attr "type" "multi")]) 4967 4968(define_expand "prologue" 4969 [(const_int 0)] 4970 "" 4971{ 4972 alpha_expand_prologue (); 4973 DONE; 4974}) 4975 4976;; These take care of emitting the ldgp insn in the prologue. This will be 4977;; an lda/ldah pair and we want to align them properly. So we have two 4978;; unspec_volatile insns, the first of which emits the ldgp assembler macro 4979;; and the second of which emits nothing. However, both are marked as type 4980;; IADD (the default) so the alignment code in alpha.c does the right thing 4981;; with them. 4982 4983(define_expand "prologue_ldgp" 4984 [(set (match_dup 0) 4985 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1)) 4986 (set (match_dup 0) 4987 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))] 4988 "" 4989{ 4990 operands[0] = pic_offset_table_rtx; 4991 operands[1] = gen_rtx_REG (Pmode, 27); 4992 operands[2] = (TARGET_EXPLICIT_RELOCS 4993 ? GEN_INT (alpha_next_sequence_number++) 4994 : const0_rtx); 4995}) 4996 4997(define_insn "*ldgp_er_1" 4998 [(set (match_operand:DI 0 "register_operand" "=r") 4999 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 5000 (match_operand 2 "const_int_operand")] 5001 UNSPECV_LDGP1))] 5002 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5003 "ldah %0,0(%1)\t\t!gpdisp!%2" 5004 [(set_attr "cannot_copy" "true")]) 5005 5006(define_insn "*ldgp_er_2" 5007 [(set (match_operand:DI 0 "register_operand" "=r") 5008 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 5009 (match_operand 2 "const_int_operand")] 5010 UNSPEC_LDGP2))] 5011 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5012 "lda %0,0(%1)\t\t!gpdisp!%2" 5013 [(set_attr "cannot_copy" "true")]) 5014 5015(define_insn "*prologue_ldgp_er_2" 5016 [(set (match_operand:DI 0 "register_operand" "=r") 5017 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 5018 (match_operand 2 "const_int_operand")] 5019 UNSPECV_PLDGP2))] 5020 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5021 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:" 5022 [(set_attr "cannot_copy" "true")]) 5023 5024(define_insn "*prologue_ldgp_1" 5025 [(set (match_operand:DI 0 "register_operand" "=r") 5026 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 5027 (match_operand 2 "const_int_operand")] 5028 UNSPECV_LDGP1))] 5029 "" 5030 "ldgp %0,0(%1)\n$%~..ng:" 5031 [(set_attr "cannot_copy" "true")]) 5032 5033(define_insn "*prologue_ldgp_2" 5034 [(set (match_operand:DI 0 "register_operand" "=r") 5035 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 5036 (match_operand 2 "const_int_operand")] 5037 UNSPECV_PLDGP2))] 5038 "" 5039 ) 5040 5041;; The _mcount profiling hook has special calling conventions, and 5042;; does not clobber all the registers that a normal call would. So 5043;; hide the fact this is a call at all. 5044 5045(define_insn "prologue_mcount" 5046 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)] 5047 "" 5048{ 5049 if (TARGET_EXPLICIT_RELOCS) 5050 /* Note that we cannot use a lituse_jsr reloc, since _mcount 5051 cannot be called via the PLT. */ 5052 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount"; 5053 else 5054 return "lda $28,_mcount\;jsr $28,($28),_mcount"; 5055} 5056 [(set_attr "type" "multi") 5057 (set_attr "length" "8")]) 5058 5059(define_insn "init_fp" 5060 [(set (match_operand:DI 0 "register_operand" "=r") 5061 (match_operand:DI 1 "register_operand" "r")) 5062 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))] 5063 "" 5064 "bis $31,%1,%0") 5065 5066(define_expand "epilogue" 5067 [(return)] 5068 "" 5069 "alpha_expand_epilogue ();") 5070 5071(define_expand "sibcall_epilogue" 5072 [(return)] 5073 "TARGET_ABI_OSF" 5074{ 5075 alpha_expand_epilogue (); 5076 DONE; 5077}) 5078 5079(define_expand "builtin_longjmp" 5080 [(use (match_operand:DI 0 "register_operand" "r"))] 5081 "TARGET_ABI_OSF" 5082{ 5083 /* The elements of the buffer are, in order: */ 5084 rtx fp = gen_rtx_MEM (Pmode, operands[0]); 5085 rtx lab = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 8)); 5086 rtx stack = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 16)); 5087 rtx pv = gen_rtx_REG (Pmode, 27); 5088 5089 /* This bit is the same as expand_builtin_longjmp. */ 5090 emit_move_insn (hard_frame_pointer_rtx, fp); 5091 emit_move_insn (pv, lab); 5092 emit_stack_restore (SAVE_NONLOCAL, stack); 5093 emit_use (hard_frame_pointer_rtx); 5094 emit_use (stack_pointer_rtx); 5095 5096 /* Load the label we are jumping through into $27 so that we know 5097 where to look for it when we get back to setjmp's function for 5098 restoring the gp. */ 5099 emit_jump_insn (gen_builtin_longjmp_internal (pv)); 5100 emit_barrier (); 5101 DONE; 5102}) 5103 5104;; This is effectively a copy of indirect_jump, but constrained such 5105;; that register renaming cannot foil our cunning plan with $27. 5106(define_insn "builtin_longjmp_internal" 5107 [(set (pc) 5108 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")] 5109 UNSPECV_LONGJMP))] 5110 "" 5111 "jmp $31,(%0),0" 5112 [(set_attr "type" "ibr")]) 5113 5114(define_expand "builtin_setjmp_receiver" 5115 [(unspec_volatile [(label_ref (match_operand 0))] UNSPECV_SETJMPR)] 5116 "TARGET_ABI_OSF") 5117 5118(define_insn_and_split "*builtin_setjmp_receiver_1" 5119 [(unspec_volatile [(match_operand 0)] UNSPECV_SETJMPR)] 5120 "TARGET_ABI_OSF" 5121{ 5122 if (TARGET_EXPLICIT_RELOCS) 5123 return "#"; 5124 else 5125 return "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)"; 5126} 5127 "&& TARGET_EXPLICIT_RELOCS && reload_completed" 5128 [(set (match_dup 1) 5129 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1)) 5130 (set (match_dup 1) 5131 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))] 5132{ 5133 if (prev_nonnote_insn (curr_insn) != XEXP (operands[0], 0)) 5134 emit_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, operands[0]), 5135 UNSPECV_SETJMPR_ER)); 5136 operands[1] = pic_offset_table_rtx; 5137 operands[2] = gen_rtx_REG (Pmode, 27); 5138 operands[3] = GEN_INT (alpha_next_sequence_number++); 5139} 5140 [(set_attr "length" "12") 5141 (set_attr "type" "multi")]) 5142 5143(define_insn "*builtin_setjmp_receiver_er_sl_1" 5144 [(unspec_volatile [(match_operand 0)] UNSPECV_SETJMPR_ER)] 5145 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS" 5146 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:") 5147 5148;; When flag_reorder_blocks_and_partition is in effect, compiler puts 5149;; exception landing pads in a cold section. To prevent inter-section offset 5150;; calculation, a jump to original landing pad is emitted in the place of the 5151;; original landing pad. Since landing pad is moved, RA-relative GP 5152;; calculation in the prologue of landing pad breaks. To solve this problem, 5153;; we use alternative GP load approach. 5154 5155(define_expand "exception_receiver" 5156 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)] 5157 "TARGET_ABI_OSF" 5158{ 5159 if (flag_reorder_blocks_and_partition) 5160 operands[0] = alpha_gp_save_rtx (); 5161 else 5162 operands[0] = const0_rtx; 5163}) 5164 5165(define_insn "*exception_receiver_2" 5166 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)] 5167 "TARGET_ABI_OSF && flag_reorder_blocks_and_partition" 5168 "ldq $29,%0" 5169 [(set_attr "type" "ild")]) 5170 5171(define_insn_and_split "*exception_receiver_1" 5172 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)] 5173 "TARGET_ABI_OSF" 5174{ 5175 if (TARGET_EXPLICIT_RELOCS) 5176 return "ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"; 5177 else 5178 return "ldgp $29,0($26)"; 5179} 5180 "&& TARGET_EXPLICIT_RELOCS && reload_completed" 5181 [(set (match_dup 0) 5182 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1)) 5183 (set (match_dup 0) 5184 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))] 5185{ 5186 operands[0] = pic_offset_table_rtx; 5187 operands[1] = gen_rtx_REG (Pmode, 26); 5188 operands[2] = GEN_INT (alpha_next_sequence_number++); 5189} 5190 [(set_attr "length" "8") 5191 (set_attr "type" "multi")]) 5192 5193(define_expand "nonlocal_goto_receiver" 5194 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE) 5195 (set (reg:DI 27) (mem:DI (reg:DI 29))) 5196 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE) 5197 (use (reg:DI 27))] 5198 "TARGET_ABI_OPEN_VMS") 5199 5200(define_insn "arg_home" 5201 [(unspec [(const_int 0)] UNSPEC_ARG_HOME) 5202 (use (reg:DI 1)) 5203 (use (reg:DI 25)) 5204 (use (reg:DI 16)) 5205 (use (reg:DI 17)) 5206 (use (reg:DI 18)) 5207 (use (reg:DI 19)) 5208 (use (reg:DI 20)) 5209 (use (reg:DI 21)) 5210 (use (reg:DI 48)) 5211 (use (reg:DI 49)) 5212 (use (reg:DI 50)) 5213 (use (reg:DI 51)) 5214 (use (reg:DI 52)) 5215 (use (reg:DI 53)) 5216 (clobber (mem:BLK (const_int 0))) 5217 (clobber (reg:DI 24)) 5218 (clobber (reg:DI 25)) 5219 (clobber (reg:DI 0))] 5220 "TARGET_ABI_OPEN_VMS" 5221 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS" 5222 [(set_attr "length" "16") 5223 (set_attr "type" "multi")]) 5224 5225;; Prefetch data. 5226;; 5227;; On EV4, these instructions are nops -- no load occurs. 5228;; 5229;; On EV5, these instructions act as a normal load, and thus can trap 5230;; if the address is invalid. The OS may (or may not) handle this in 5231;; the entMM fault handler and suppress the fault. If so, then this 5232;; has the effect of a read prefetch instruction. 5233;; 5234;; On EV6, these become official prefetch instructions. 5235 5236(define_insn "prefetch" 5237 [(prefetch (match_operand:DI 0 "address_operand" "p") 5238 (match_operand:DI 1 "const_int_operand" "n") 5239 (match_operand:DI 2 "const_int_operand" "n"))] 5240 "TARGET_FIXUP_EV5_PREFETCH || alpha_cpu == PROCESSOR_EV6" 5241{ 5242 /* Interpret "no temporal locality" as this data should be evicted once 5243 it is used. The "evict next" alternatives load the data into the cache 5244 and leave the LRU eviction counter pointing to that block. */ 5245 static const char * const alt[2][2] = { 5246 { 5247 "ldq $31,%a0", /* read, evict next */ 5248 "ldl $31,%a0", /* read, evict last */ 5249 }, 5250 { 5251 "ldt $f31,%a0", /* write, evict next */ 5252 "lds $f31,%a0", /* write, evict last */ 5253 } 5254 }; 5255 5256 bool write = INTVAL (operands[1]) != 0; 5257 bool lru = INTVAL (operands[2]) != 0; 5258 5259 return alt[write][lru]; 5260} 5261 [(set_attr "type" "ild")]) 5262 5263;; Close the trap shadow of preceding instructions. This is generated 5264;; by alpha_reorg. 5265 5266(define_insn "trapb" 5267 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)] 5268 "" 5269 "trapb" 5270 [(set_attr "type" "misc")]) 5271 5272;; No-op instructions used by machine-dependent reorg to preserve 5273;; alignment for instruction issue. 5274;; The Unicos/Mk assembler does not support these opcodes. 5275 5276(define_insn "nop" 5277 [(const_int 0)] 5278 "" 5279 "bis $31,$31,$31" 5280 [(set_attr "type" "ilog")]) 5281 5282(define_insn "fnop" 5283 [(const_int 1)] 5284 "TARGET_FP" 5285 "cpys $f31,$f31,$f31" 5286 [(set_attr "type" "fcpys")]) 5287 5288(define_insn "unop" 5289 [(const_int 2)] 5290 "" 5291 "ldq_u $31,0($30)") 5292 5293(define_insn "realign" 5294 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")] 5295 UNSPECV_REALIGN)] 5296 "" 5297 ".align %0 #realign") 5298 5299;; Instructions to be emitted from __builtins. 5300 5301(define_insn "builtin_cmpbge" 5302 [(set (match_operand:DI 0 "register_operand" "=r") 5303 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ") 5304 (match_operand:DI 2 "reg_or_8bit_operand" "rI")] 5305 UNSPEC_CMPBGE))] 5306 "" 5307 "cmpbge %r1,%2,%0" 5308 ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't 5309 ;; actually differentiate between ILOG and ICMP in the schedule. 5310 [(set_attr "type" "icmp")]) 5311 5312(define_expand "extbl" 5313 [(match_operand:DI 0 "register_operand") 5314 (match_operand:DI 1 "reg_or_0_operand") 5315 (match_operand:DI 2 "reg_or_8bit_operand")] 5316 "" 5317{ 5318 emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (8), operands[2])); 5319 DONE; 5320}) 5321 5322(define_expand "extwl" 5323 [(match_operand:DI 0 "register_operand") 5324 (match_operand:DI 1 "reg_or_0_operand") 5325 (match_operand:DI 2 "reg_or_8bit_operand")] 5326 "" 5327{ 5328 emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (16), operands[2])); 5329 DONE; 5330}) 5331 5332(define_expand "extll" 5333 [(match_operand:DI 0 "register_operand") 5334 (match_operand:DI 1 "reg_or_0_operand") 5335 (match_operand:DI 2 "reg_or_8bit_operand")] 5336 "" 5337{ 5338 emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (32), operands[2])); 5339 DONE; 5340}) 5341 5342(define_expand "extql" 5343 [(match_operand:DI 0 "register_operand") 5344 (match_operand:DI 1 "reg_or_0_operand") 5345 (match_operand:DI 2 "reg_or_8bit_operand")] 5346 "" 5347{ 5348 emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (64), operands[2])); 5349 DONE; 5350}) 5351 5352(define_expand "builtin_insbl" 5353 [(match_operand:DI 0 "register_operand") 5354 (match_operand:DI 1 "register_operand") 5355 (match_operand:DI 2 "reg_or_8bit_operand")] 5356 "" 5357{ 5358 operands[1] = gen_lowpart (QImode, operands[1]); 5359 emit_insn (gen_insbl (operands[0], operands[1], operands[2])); 5360 DONE; 5361}) 5362 5363(define_expand "builtin_inswl" 5364 [(match_operand:DI 0 "register_operand") 5365 (match_operand:DI 1 "register_operand") 5366 (match_operand:DI 2 "reg_or_8bit_operand")] 5367 "" 5368{ 5369 operands[1] = gen_lowpart (HImode, operands[1]); 5370 emit_insn (gen_inswl (operands[0], operands[1], operands[2])); 5371 DONE; 5372}) 5373 5374(define_expand "builtin_insll" 5375 [(match_operand:DI 0 "register_operand") 5376 (match_operand:DI 1 "register_operand") 5377 (match_operand:DI 2 "reg_or_8bit_operand")] 5378 "" 5379{ 5380 operands[1] = gen_lowpart (SImode, operands[1]); 5381 emit_insn (gen_insll (operands[0], operands[1], operands[2])); 5382 DONE; 5383}) 5384 5385(define_expand "inswh" 5386 [(match_operand:DI 0 "register_operand") 5387 (match_operand:DI 1 "register_operand") 5388 (match_operand:DI 2 "reg_or_8bit_operand")] 5389 "" 5390{ 5391 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2])); 5392 DONE; 5393}) 5394 5395(define_expand "inslh" 5396 [(match_operand:DI 0 "register_operand") 5397 (match_operand:DI 1 "register_operand") 5398 (match_operand:DI 2 "reg_or_8bit_operand")] 5399 "" 5400{ 5401 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2])); 5402 DONE; 5403}) 5404 5405(define_expand "insqh" 5406 [(match_operand:DI 0 "register_operand") 5407 (match_operand:DI 1 "register_operand") 5408 (match_operand:DI 2 "reg_or_8bit_operand")] 5409 "" 5410{ 5411 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2])); 5412 DONE; 5413}) 5414 5415(define_expand "mskbl" 5416 [(match_operand:DI 0 "register_operand") 5417 (match_operand:DI 1 "reg_or_0_operand") 5418 (match_operand:DI 2 "reg_or_8bit_operand")] 5419 "" 5420{ 5421 rtx mask = GEN_INT (0xff); 5422 emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5423 DONE; 5424}) 5425 5426(define_expand "mskwl" 5427 [(match_operand:DI 0 "register_operand") 5428 (match_operand:DI 1 "reg_or_0_operand") 5429 (match_operand:DI 2 "reg_or_8bit_operand")] 5430 "" 5431{ 5432 rtx mask = GEN_INT (0xffff); 5433 emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5434 DONE; 5435}) 5436 5437(define_expand "mskll" 5438 [(match_operand:DI 0 "register_operand") 5439 (match_operand:DI 1 "reg_or_0_operand") 5440 (match_operand:DI 2 "reg_or_8bit_operand")] 5441 "" 5442{ 5443 rtx mask = immed_double_const (0xffffffff, 0, DImode); 5444 emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5445 DONE; 5446}) 5447 5448(define_expand "mskql" 5449 [(match_operand:DI 0 "register_operand") 5450 (match_operand:DI 1 "reg_or_0_operand") 5451 (match_operand:DI 2 "reg_or_8bit_operand")] 5452 "" 5453{ 5454 rtx mask = constm1_rtx; 5455 emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5456 DONE; 5457}) 5458 5459(define_expand "mskwh" 5460 [(match_operand:DI 0 "register_operand") 5461 (match_operand:DI 1 "register_operand") 5462 (match_operand:DI 2 "reg_or_8bit_operand")] 5463 "" 5464{ 5465 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2])); 5466 DONE; 5467}) 5468 5469(define_expand "msklh" 5470 [(match_operand:DI 0 "register_operand") 5471 (match_operand:DI 1 "register_operand") 5472 (match_operand:DI 2 "reg_or_8bit_operand")] 5473 "" 5474{ 5475 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2])); 5476 DONE; 5477}) 5478 5479(define_expand "mskqh" 5480 [(match_operand:DI 0 "register_operand") 5481 (match_operand:DI 1 "register_operand") 5482 (match_operand:DI 2 "reg_or_8bit_operand")] 5483 "" 5484{ 5485 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2])); 5486 DONE; 5487}) 5488 5489(define_expand "builtin_zap" 5490 [(set (match_operand:DI 0 "register_operand") 5491 (and:DI (unspec:DI 5492 [(match_operand:DI 2 "reg_or_cint_operand")] 5493 UNSPEC_ZAP) 5494 (match_operand:DI 1 "reg_or_cint_operand")))] 5495 "" 5496{ 5497 if (CONST_INT_P (operands[2])) 5498 { 5499 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2])); 5500 5501 if (mask == const0_rtx) 5502 { 5503 emit_move_insn (operands[0], const0_rtx); 5504 DONE; 5505 } 5506 if (mask == constm1_rtx) 5507 { 5508 emit_move_insn (operands[0], operands[1]); 5509 DONE; 5510 } 5511 5512 operands[1] = force_reg (DImode, operands[1]); 5513 emit_insn (gen_anddi3 (operands[0], operands[1], mask)); 5514 DONE; 5515 } 5516 5517 operands[1] = force_reg (DImode, operands[1]); 5518 operands[2] = gen_lowpart (QImode, operands[2]); 5519}) 5520 5521(define_insn "*builtin_zap_1" 5522 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r") 5523 (and:DI (unspec:DI 5524 [(match_operand:QI 2 "reg_or_cint_operand" "n,n,r,r")] 5525 UNSPEC_ZAP) 5526 (match_operand:DI 1 "reg_or_cint_operand" "n,r,J,r")))] 5527 "" 5528 "@ 5529 # 5530 # 5531 bis $31,$31,%0 5532 zap %r1,%2,%0" 5533 [(set_attr "type" "shift,shift,ilog,shift")]) 5534 5535(define_split 5536 [(set (match_operand:DI 0 "register_operand") 5537 (and:DI (unspec:DI 5538 [(match_operand:QI 2 "const_int_operand")] 5539 UNSPEC_ZAP) 5540 (match_operand:DI 1 "const_int_operand")))] 5541 "" 5542 [(const_int 0)] 5543{ 5544 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2])); 5545 if (HOST_BITS_PER_WIDE_INT >= 64 || CONST_INT_P (mask)) 5546 operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode); 5547 else 5548 { 5549 HOST_WIDE_INT c_lo = INTVAL (operands[1]); 5550 HOST_WIDE_INT c_hi = (c_lo < 0 ? -1 : 0); 5551 operands[1] = immed_double_const (c_lo & CONST_DOUBLE_LOW (mask), 5552 c_hi & CONST_DOUBLE_HIGH (mask), 5553 DImode); 5554 } 5555 emit_move_insn (operands[0], operands[1]); 5556 DONE; 5557}) 5558 5559(define_split 5560 [(set (match_operand:DI 0 "register_operand") 5561 (and:DI (unspec:DI 5562 [(match_operand:QI 2 "const_int_operand")] 5563 UNSPEC_ZAP) 5564 (match_operand:DI 1 "register_operand")))] 5565 "" 5566 [(set (match_dup 0) 5567 (and:DI (match_dup 1) (match_dup 2)))] 5568{ 5569 operands[2] = alpha_expand_zap_mask (INTVAL (operands[2])); 5570 if (operands[2] == const0_rtx) 5571 { 5572 emit_move_insn (operands[0], const0_rtx); 5573 DONE; 5574 } 5575 if (operands[2] == constm1_rtx) 5576 { 5577 emit_move_insn (operands[0], operands[1]); 5578 DONE; 5579 } 5580}) 5581 5582(define_expand "builtin_zapnot" 5583 [(set (match_operand:DI 0 "register_operand") 5584 (and:DI (unspec:DI 5585 [(not:QI (match_operand:DI 2 "reg_or_cint_operand"))] 5586 UNSPEC_ZAP) 5587 (match_operand:DI 1 "reg_or_cint_operand")))] 5588 "" 5589{ 5590 if (CONST_INT_P (operands[2])) 5591 { 5592 rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2])); 5593 5594 if (mask == const0_rtx) 5595 { 5596 emit_move_insn (operands[0], const0_rtx); 5597 DONE; 5598 } 5599 if (mask == constm1_rtx) 5600 { 5601 emit_move_insn (operands[0], operands[1]); 5602 DONE; 5603 } 5604 5605 operands[1] = force_reg (DImode, operands[1]); 5606 emit_insn (gen_anddi3 (operands[0], operands[1], mask)); 5607 DONE; 5608 } 5609 5610 operands[1] = force_reg (DImode, operands[1]); 5611 operands[2] = gen_lowpart (QImode, operands[2]); 5612}) 5613 5614(define_insn "*builtin_zapnot_1" 5615 [(set (match_operand:DI 0 "register_operand" "=r") 5616 (and:DI (unspec:DI 5617 [(not:QI (match_operand:QI 2 "register_operand" "r"))] 5618 UNSPEC_ZAP) 5619 (match_operand:DI 1 "reg_or_0_operand" "rJ")))] 5620 "" 5621 "zapnot %r1,%2,%0" 5622 [(set_attr "type" "shift")]) 5623 5624(define_insn "builtin_amask" 5625 [(set (match_operand:DI 0 "register_operand" "=r") 5626 (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")] 5627 UNSPEC_AMASK))] 5628 "" 5629 "amask %1,%0" 5630 [(set_attr "type" "ilog")]) 5631 5632(define_insn "builtin_implver" 5633 [(set (match_operand:DI 0 "register_operand" "=r") 5634 (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))] 5635 "" 5636 "implver %0" 5637 [(set_attr "type" "ilog")]) 5638 5639(define_insn "builtin_rpcc" 5640 [(set (match_operand:DI 0 "register_operand" "=r") 5641 (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))] 5642 "" 5643 "rpcc %0" 5644 [(set_attr "type" "ilog")]) 5645 5646(define_expand "builtin_minub8" 5647 [(match_operand:DI 0 "register_operand") 5648 (match_operand:DI 1 "reg_or_0_operand") 5649 (match_operand:DI 2 "reg_or_0_operand")] 5650 "TARGET_MAX" 5651{ 5652 alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0], 5653 operands[1], operands[2]); 5654 DONE; 5655}) 5656 5657(define_expand "builtin_minsb8" 5658 [(match_operand:DI 0 "register_operand") 5659 (match_operand:DI 1 "reg_or_0_operand") 5660 (match_operand:DI 2 "reg_or_0_operand")] 5661 "TARGET_MAX" 5662{ 5663 alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0], 5664 operands[1], operands[2]); 5665 DONE; 5666}) 5667 5668(define_expand "builtin_minuw4" 5669 [(match_operand:DI 0 "register_operand") 5670 (match_operand:DI 1 "reg_or_0_operand") 5671 (match_operand:DI 2 "reg_or_0_operand")] 5672 "TARGET_MAX" 5673{ 5674 alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0], 5675 operands[1], operands[2]); 5676 DONE; 5677}) 5678 5679(define_expand "builtin_minsw4" 5680 [(match_operand:DI 0 "register_operand") 5681 (match_operand:DI 1 "reg_or_0_operand") 5682 (match_operand:DI 2 "reg_or_0_operand")] 5683 "TARGET_MAX" 5684{ 5685 alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0], 5686 operands[1], operands[2]); 5687 DONE; 5688}) 5689 5690(define_expand "builtin_maxub8" 5691 [(match_operand:DI 0 "register_operand") 5692 (match_operand:DI 1 "reg_or_0_operand") 5693 (match_operand:DI 2 "reg_or_0_operand")] 5694 "TARGET_MAX" 5695{ 5696 alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0], 5697 operands[1], operands[2]); 5698 DONE; 5699}) 5700 5701(define_expand "builtin_maxsb8" 5702 [(match_operand:DI 0 "register_operand") 5703 (match_operand:DI 1 "reg_or_0_operand") 5704 (match_operand:DI 2 "reg_or_0_operand")] 5705 "TARGET_MAX" 5706{ 5707 alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0], 5708 operands[1], operands[2]); 5709 DONE; 5710}) 5711 5712(define_expand "builtin_maxuw4" 5713 [(match_operand:DI 0 "register_operand") 5714 (match_operand:DI 1 "reg_or_0_operand") 5715 (match_operand:DI 2 "reg_or_0_operand")] 5716 "TARGET_MAX" 5717{ 5718 alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0], 5719 operands[1], operands[2]); 5720 DONE; 5721}) 5722 5723(define_expand "builtin_maxsw4" 5724 [(match_operand:DI 0 "register_operand") 5725 (match_operand:DI 1 "reg_or_0_operand") 5726 (match_operand:DI 2 "reg_or_0_operand")] 5727 "TARGET_MAX" 5728{ 5729 alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0], 5730 operands[1], operands[2]); 5731 DONE; 5732}) 5733 5734(define_insn "builtin_perr" 5735 [(set (match_operand:DI 0 "register_operand" "=r") 5736 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ") 5737 (match_operand:DI 2 "reg_or_8bit_operand" "rJ")] 5738 UNSPEC_PERR))] 5739 "TARGET_MAX" 5740 "perr %r1,%r2,%0" 5741 [(set_attr "type" "mvi")]) 5742 5743(define_expand "builtin_pklb" 5744 [(set (match_operand:DI 0 "register_operand") 5745 (vec_concat:V8QI 5746 (vec_concat:V4QI 5747 (truncate:V2QI (match_operand:DI 1 "register_operand")) 5748 (match_dup 2)) 5749 (match_dup 3)))] 5750 "TARGET_MAX" 5751{ 5752 operands[0] = gen_lowpart (V8QImode, operands[0]); 5753 operands[1] = gen_lowpart (V2SImode, operands[1]); 5754 operands[2] = CONST0_RTX (V2QImode); 5755 operands[3] = CONST0_RTX (V4QImode); 5756}) 5757 5758(define_insn "*pklb" 5759 [(set (match_operand:V8QI 0 "register_operand" "=r") 5760 (vec_concat:V8QI 5761 (vec_concat:V4QI 5762 (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r")) 5763 (match_operand:V2QI 2 "const0_operand")) 5764 (match_operand:V4QI 3 "const0_operand")))] 5765 "TARGET_MAX" 5766 "pklb %r1,%0" 5767 [(set_attr "type" "mvi")]) 5768 5769(define_expand "builtin_pkwb" 5770 [(set (match_operand:DI 0 "register_operand") 5771 (vec_concat:V8QI 5772 (truncate:V4QI (match_operand:DI 1 "register_operand")) 5773 (match_dup 2)))] 5774 "TARGET_MAX" 5775{ 5776 operands[0] = gen_lowpart (V8QImode, operands[0]); 5777 operands[1] = gen_lowpart (V4HImode, operands[1]); 5778 operands[2] = CONST0_RTX (V4QImode); 5779}) 5780 5781(define_insn "*pkwb" 5782 [(set (match_operand:V8QI 0 "register_operand" "=r") 5783 (vec_concat:V8QI 5784 (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r")) 5785 (match_operand:V4QI 2 "const0_operand")))] 5786 "TARGET_MAX" 5787 "pkwb %r1,%0" 5788 [(set_attr "type" "mvi")]) 5789 5790(define_expand "builtin_unpkbl" 5791 [(set (match_operand:DI 0 "register_operand") 5792 (zero_extend:V2SI 5793 (vec_select:V2QI (match_operand:DI 1 "register_operand") 5794 (parallel [(const_int 0) (const_int 1)]))))] 5795 "TARGET_MAX" 5796{ 5797 operands[0] = gen_lowpart (V2SImode, operands[0]); 5798 operands[1] = gen_lowpart (V8QImode, operands[1]); 5799}) 5800 5801(define_insn "*unpkbl" 5802 [(set (match_operand:V2SI 0 "register_operand" "=r") 5803 (zero_extend:V2SI 5804 (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") 5805 (parallel [(const_int 0) (const_int 1)]))))] 5806 "TARGET_MAX" 5807 "unpkbl %r1,%0" 5808 [(set_attr "type" "mvi")]) 5809 5810(define_expand "builtin_unpkbw" 5811 [(set (match_operand:DI 0 "register_operand") 5812 (zero_extend:V4HI 5813 (vec_select:V4QI (match_operand:DI 1 "register_operand") 5814 (parallel [(const_int 0) 5815 (const_int 1) 5816 (const_int 2) 5817 (const_int 3)]))))] 5818 "TARGET_MAX" 5819{ 5820 operands[0] = gen_lowpart (V4HImode, operands[0]); 5821 operands[1] = gen_lowpart (V8QImode, operands[1]); 5822}) 5823 5824(define_insn "*unpkbw" 5825 [(set (match_operand:V4HI 0 "register_operand" "=r") 5826 (zero_extend:V4HI 5827 (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") 5828 (parallel [(const_int 0) 5829 (const_int 1) 5830 (const_int 2) 5831 (const_int 3)]))))] 5832 "TARGET_MAX" 5833 "unpkbw %r1,%0" 5834 [(set_attr "type" "mvi")]) 5835 5836(include "sync.md") 5837 5838;; The call patterns are at the end of the file because their 5839;; wildcard operand0 interferes with nice recognition. 5840 5841(define_insn "*call_value_osf_1_er_noreturn" 5842 [(set (match_operand 0) 5843 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 5844 (match_operand 2))) 5845 (use (reg:DI 29)) 5846 (clobber (reg:DI 26))] 5847 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 5848 && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 5849 "@ 5850 jsr $26,($27),0 5851 bsr $26,%1\t\t!samegp 5852 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),%1\t\t!lituse_jsr!%#" 5853 [(set_attr "type" "jsr") 5854 (set_attr "length" "*,*,8")]) 5855 5856(define_insn "*call_value_osf_1_er" 5857 [(set (match_operand 0) 5858 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 5859 (match_operand 2))) 5860 (use (reg:DI 29)) 5861 (clobber (reg:DI 26))] 5862 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5863 "@ 5864 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%* 5865 bsr $26,%1\t\t!samegp 5866 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*" 5867 [(set_attr "type" "jsr") 5868 (set_attr "length" "12,*,16")]) 5869 5870;; We must use peep2 instead of a split because we need accurate life 5871;; information for $gp. Consider the case of { bar(); while (1); }. 5872(define_peephole2 5873 [(parallel [(set (match_operand 0) 5874 (call (mem:DI (match_operand:DI 1 "call_operand")) 5875 (match_operand 2))) 5876 (use (reg:DI 29)) 5877 (clobber (reg:DI 26))])] 5878 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 5879 && ! samegp_function_operand (operands[1], Pmode) 5880 && (peep2_regno_dead_p (1, 29) 5881 || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 5882 [(parallel [(set (match_dup 0) 5883 (call (mem:DI (match_dup 3)) 5884 (match_dup 2))) 5885 (use (reg:DI 29)) 5886 (use (match_dup 1)) 5887 (use (match_dup 4)) 5888 (clobber (reg:DI 26))])] 5889{ 5890 if (CONSTANT_P (operands[1])) 5891 { 5892 operands[3] = gen_rtx_REG (Pmode, 27); 5893 operands[4] = GEN_INT (alpha_next_sequence_number++); 5894 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx, 5895 operands[1], operands[4])); 5896 } 5897 else 5898 { 5899 operands[3] = operands[1]; 5900 operands[1] = const0_rtx; 5901 operands[4] = const0_rtx; 5902 } 5903}) 5904 5905(define_peephole2 5906 [(parallel [(set (match_operand 0) 5907 (call (mem:DI (match_operand:DI 1 "call_operand")) 5908 (match_operand 2))) 5909 (use (reg:DI 29)) 5910 (clobber (reg:DI 26))])] 5911 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 5912 && ! samegp_function_operand (operands[1], Pmode) 5913 && ! (peep2_regno_dead_p (1, 29) 5914 || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 5915 [(parallel [(set (match_dup 0) 5916 (call (mem:DI (match_dup 3)) 5917 (match_dup 2))) 5918 (set (match_dup 6) 5919 (unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP1)) 5920 (use (match_dup 1)) 5921 (use (match_dup 5)) 5922 (clobber (reg:DI 26))]) 5923 (set (match_dup 6) 5924 (unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP2))] 5925{ 5926 if (CONSTANT_P (operands[1])) 5927 { 5928 operands[3] = gen_rtx_REG (Pmode, 27); 5929 operands[5] = GEN_INT (alpha_next_sequence_number++); 5930 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx, 5931 operands[1], operands[5])); 5932 } 5933 else 5934 { 5935 operands[3] = operands[1]; 5936 operands[1] = const0_rtx; 5937 operands[5] = const0_rtx; 5938 } 5939 operands[4] = GEN_INT (alpha_next_sequence_number++); 5940 operands[6] = pic_offset_table_rtx; 5941}) 5942 5943(define_insn "*call_value_osf_2_er_nogp" 5944 [(set (match_operand 0) 5945 (call (mem:DI (match_operand:DI 1 "register_operand" "c")) 5946 (match_operand 2))) 5947 (use (reg:DI 29)) 5948 (use (match_operand 3)) 5949 (use (match_operand 4)) 5950 (clobber (reg:DI 26))] 5951 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5952 "jsr $26,(%1),%3%J4" 5953 [(set_attr "type" "jsr")]) 5954 5955(define_insn "*call_value_osf_2_er" 5956 [(set (match_operand 0) 5957 (call (mem:DI (match_operand:DI 1 "register_operand" "c")) 5958 (match_operand 2))) 5959 (set (reg:DI 29) 5960 (unspec:DI [(reg:DI 29) (match_operand 5 "const_int_operand")] 5961 UNSPEC_LDGP1)) 5962 (use (match_operand 3)) 5963 (use (match_operand 4)) 5964 (clobber (reg:DI 26))] 5965 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5966 "jsr $26,(%1),%3%J4\;ldah $29,0($26)\t\t!gpdisp!%5" 5967 [(set_attr "type" "jsr") 5968 (set_attr "cannot_copy" "true") 5969 (set_attr "length" "8")]) 5970 5971(define_insn "*call_value_osf_1_noreturn" 5972 [(set (match_operand 0) 5973 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 5974 (match_operand 2))) 5975 (use (reg:DI 29)) 5976 (clobber (reg:DI 26))] 5977 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 5978 && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 5979 "@ 5980 jsr $26,($27),0 5981 bsr $26,$%1..ng 5982 jsr $26,%1" 5983 [(set_attr "type" "jsr") 5984 (set_attr "length" "*,*,8")]) 5985 5986(define_insn_and_split "call_value_osf_tlsgd" 5987 [(set (match_operand 0) 5988 (call (mem:DI (match_operand:DI 1 "symbolic_operand")) 5989 (const_int 0))) 5990 (unspec [(match_operand:DI 2 "const_int_operand")] UNSPEC_TLSGD_CALL) 5991 (use (reg:DI 29)) 5992 (clobber (reg:DI 26))] 5993 "HAVE_AS_TLS" 5994 "#" 5995 "&& reload_completed" 5996 [(set (match_dup 3) 5997 (unspec:DI [(match_dup 5) 5998 (match_dup 1) 5999 (match_dup 2)] UNSPEC_LITERAL)) 6000 (parallel [(set (match_dup 0) 6001 (call (mem:DI (match_dup 3)) 6002 (const_int 0))) 6003 (set (match_dup 5) 6004 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1)) 6005 (use (match_dup 1)) 6006 (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL)) 6007 (clobber (reg:DI 26))]) 6008 (set (match_dup 5) 6009 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))] 6010{ 6011 operands[3] = gen_rtx_REG (Pmode, 27); 6012 operands[4] = GEN_INT (alpha_next_sequence_number++); 6013 operands[5] = pic_offset_table_rtx; 6014} 6015 [(set_attr "type" "multi")]) 6016 6017(define_insn_and_split "call_value_osf_tlsldm" 6018 [(set (match_operand 0) 6019 (call (mem:DI (match_operand:DI 1 "symbolic_operand")) 6020 (const_int 0))) 6021 (unspec [(match_operand:DI 2 "const_int_operand")] UNSPEC_TLSLDM_CALL) 6022 (use (reg:DI 29)) 6023 (clobber (reg:DI 26))] 6024 "HAVE_AS_TLS" 6025 "#" 6026 "&& reload_completed" 6027 [(set (match_dup 3) 6028 (unspec:DI [(match_dup 5) 6029 (match_dup 1) 6030 (match_dup 2)] UNSPEC_LITERAL)) 6031 (parallel [(set (match_dup 0) 6032 (call (mem:DI (match_dup 3)) 6033 (const_int 0))) 6034 (set (match_dup 5) 6035 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1)) 6036 (use (match_dup 1)) 6037 (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL)) 6038 (clobber (reg:DI 26))]) 6039 (set (match_dup 5) 6040 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))] 6041{ 6042 operands[3] = gen_rtx_REG (Pmode, 27); 6043 operands[4] = GEN_INT (alpha_next_sequence_number++); 6044 operands[5] = pic_offset_table_rtx; 6045} 6046 [(set_attr "type" "multi")]) 6047 6048(define_insn "*call_value_osf_1" 6049 [(set (match_operand 0) 6050 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 6051 (match_operand 2))) 6052 (use (reg:DI 29)) 6053 (clobber (reg:DI 26))] 6054 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 6055 "@ 6056 jsr $26,($27),0\;ldgp $29,0($26) 6057 bsr $26,$%1..ng 6058 jsr $26,%1\;ldgp $29,0($26)" 6059 [(set_attr "type" "jsr") 6060 (set_attr "length" "12,*,16")]) 6061 6062(define_insn "*sibcall_value_osf_1_er" 6063 [(set (match_operand 0) 6064 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s")) 6065 (match_operand 2))) 6066 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 6067 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 6068 "@ 6069 br $31,%1\t\t!samegp 6070 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#" 6071 [(set_attr "type" "jsr") 6072 (set_attr "length" "*,8")]) 6073 6074(define_insn "*sibcall_value_osf_1" 6075 [(set (match_operand 0) 6076 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s")) 6077 (match_operand 2))) 6078 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 6079 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 6080 "@ 6081 br $31,$%1..ng 6082 lda $27,%1\;jmp $31,($27),%1" 6083 [(set_attr "type" "jsr") 6084 (set_attr "length" "*,8")]) 6085 6086; GAS relies on the order and position of instructions output below in order 6087; to generate relocs for VMS link to potentially optimize the call. 6088; Please do not molest. 6089(define_insn "*call_value_vms_1" 6090 [(set (match_operand 0) 6091 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s")) 6092 (match_operand 2))) 6093 (use (match_operand:DI 3 "nonmemory_operand" "r,n")) 6094 (use (reg:DI 25)) 6095 (use (reg:DI 26)) 6096 (clobber (reg:DI 27))] 6097 "TARGET_ABI_OPEN_VMS" 6098{ 6099 switch (which_alternative) 6100 { 6101 case 0: 6102 return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)"; 6103 case 1: 6104 operands [3] = alpha_use_linkage (operands [1], true, false); 6105 operands [4] = alpha_use_linkage (operands [1], false, false); 6106 return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"; 6107 default: 6108 gcc_unreachable (); 6109 } 6110} 6111 [(set_attr "type" "jsr") 6112 (set_attr "length" "12,16")]) 6113