1 /*
2 * hil_2wDma.c
3 *
4 * <FILEBRIEF>
5 *
6 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 *
13 * Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 *
16 * Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the
19 * distribution.
20 *
21 * Neither the name of Texas Instruments Incorporated nor the names of
22 * its contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 //! \ingroup MODULHIL
39 //! \file hil_2wDma.c
40 //! \brief
41 //!
42
43 #include "hw_compiler_specific.h"
44 #include "arch.h"
45 #include "hilDelays.h"
46 #include "JTAG_defs.h"
47
48 #ifdef MSP_FET
49 #include "hilFpgaAccess.h"
50 #endif
51
52 static struct jtag _Jtag = {0};
53 unsigned char tdo_bitDma = 0;
54
55 #ifdef MSP_FET
56 unsigned short protocol_id = 0;
57 #endif
58
59 #define SBW_DELAY { _NOP();_NOP();_NOP();/*_NOP();_NOP();_NOP();*/}
60
61 extern void testVpp(unsigned char mode);
62 extern void setVpp(long voltage);
63 extern void TCLKset1();
64 extern void TCLKset0();
65 unsigned long _hil_2w_SetReg_XBits32_Dma(unsigned long data);
66
67 //#pragma inline=forced
68 #pragma optimize = low
TMSH_DMA()69 void TMSH_DMA()
70 {
71 /*_DINT();*/ (*_Jtag.Out) |= _Jtag.RST; (*_Jtag.Out) &= ~_Jtag.TST; SBW_DELAY; (*_Jtag.Out) |= _Jtag.TST; /*_EINT();*/ // TMS = 1
72 }
73
74 #pragma optimize = low
TMSL_DMA()75 void TMSL_DMA()
76 {
77 /*_DINT();*/ (*_Jtag.Out) &= ~_Jtag.RST;(*_Jtag.Out) &= ~_Jtag.TST; SBW_DELAY; (*_Jtag.Out) |= _Jtag.TST; /*_EINT();*/ // TMS = 0
78 }
79
80 #pragma optimize = low
TMSLDH_DMA()81 void TMSLDH_DMA()
82 {
83 /*_DINT();*/ (*_Jtag.Out) &= ~_Jtag.RST;(*_Jtag.Out) &= ~_Jtag.TST; SBW_DELAY; (*_Jtag.Out) |= _Jtag.RST; (*_Jtag.Out) |= _Jtag.TST; /*_EINT();*/ // TMS = 0, then TCLK immediately = 1
84 }
85
86 #pragma optimize = low
TDIH_DMA()87 void TDIH_DMA()
88 {
89 /*_DINT();*/ (*_Jtag.Out) |= _Jtag.RST; (*_Jtag.Out) &= ~_Jtag.TST; SBW_DELAY; (*_Jtag.Out) |= _Jtag.TST; /*_EINT();*/ // TDI = 1
90 }
91
92 #pragma optimize = low
TDIL_DMA()93 void TDIL_DMA()
94 {
95 /*_DINT();*/ (*_Jtag.Out) &= ~_Jtag.RST; (*_Jtag.Out) &= ~_Jtag.TST; SBW_DELAY; (*_Jtag.Out) |= _Jtag.TST; /*_EINT();*/
96 }
97
98 #pragma inline=forced
TDOsbwDma()99 void TDOsbwDma()
100 {
101 _DINT_FET(); (*_Jtag.DIRECTION) &= ~_Jtag.RST; (*_Jtag.Out) &= ~_Jtag.TST; SBW_DELAY; (*_Jtag.Out) |= _Jtag.TST; SBW_DELAY;SBW_DELAY;(*_Jtag.DIRECTION) |= _Jtag.RST;_EINT_FET();// TDO cycle without reading TDO
102 }
103 #pragma inline=forced
TDOsbwFuse()104 void TDOsbwFuse()
105 {
106 (*_Jtag.DIRECTION) &= ~_Jtag.RST; (*_Jtag.Out) &= ~_Jtag.TST; SBW_DELAY; (*_Jtag.Out) |= _Jtag.TST; SBW_DELAY;SBW_DELAY;SBW_DELAY;(*_Jtag.DIRECTION) |= _Jtag.RST;// TDO cycle without reading TDO
107 }
108 #pragma inline=forced
TDO_RD_FUSE()109 void TDO_RD_FUSE()
110 {
111 (*_Jtag.DIRECTION) &= ~_Jtag.RST; (*_Jtag.Out) &= ~_Jtag.TST; SBW_DELAY; tdo_bitDma = (*_Jtag.In); SBW_DELAY;SBW_DELAY;SBW_DELAY;(*_Jtag.Out) |= _Jtag.TST; ; (*_Jtag.DIRECTION) |= _Jtag.RST; // TDO cycle with TDO read
112 }
113 #pragma inline=forced
TDO_RD_DMA()114 void TDO_RD_DMA()
115 {
116 _DINT_FET(); (*_Jtag.DIRECTION) &= ~_Jtag.RST; (*_Jtag.Out) &= ~_Jtag.TST; SBW_DELAY; tdo_bitDma = (*_Jtag.In); SBW_DELAY;SBW_DELAY;(*_Jtag.Out) |= _Jtag.TST; ; (*_Jtag.DIRECTION) |= _Jtag.RST; _EINT_FET(); // TDO cycle with TDO read
117 }
118
119 unsigned char DMA_TMSH_TDIH[84] = {0};
120
121 unsigned char DMA_TMSH_TDIL[84] = {0};
122
123 unsigned char DMA_TMSL_TDIH[84] = {0};
124
125 unsigned char DMA_TMSL_TDIL[84] = {0};
126
127 unsigned char TCLK_savedDma;
128 unsigned char current_Instr;
129 unsigned char prevInstruction;
130 void _hil_2w_ConfigureSpeed_Dma(unsigned short speed);
131
132
initJtagSbw2Dma(struct jtag tmp)133 void initJtagSbw2Dma(struct jtag tmp)
134 {
135 _Jtag = tmp;
136 TCLK_savedDma =0;
137 current_Instr = 0;
138 prevInstruction = 0;
139
140 #ifdef MSP_FET
141 protocol_id = 0;
142 #endif
143 }
144
145 #ifdef MSP_FET
setProtocolSbw2Dma(unsigned short id)146 void setProtocolSbw2Dma(unsigned short id)
147 {
148 protocol_id = id;
149 }
150 #endif
151
_hil_2w_GetPrevInstruction_Dma()152 unsigned char _hil_2w_GetPrevInstruction_Dma()
153 {
154 return prevInstruction;
155 }
156
157 #pragma inline=forced
DMA1sbw(void)158 void DMA1sbw(void)
159 {
160 DMA1CTL |= DMAEN;
161 DMA1CTL |= DMAREQ; // DMA1 FIRE!!!
162 TDOsbwDma();
163 }
164
165 #pragma inline=forced
DMA2sbw(void)166 void DMA2sbw(void)
167 {
168 DMA2CTL |= DMAEN;
169 DMA2CTL |= DMAREQ; // DMA2 FIRE!!!
170 TDOsbwDma();
171 }
172
173 #pragma inline=forced
restoreTCLK(void)174 void restoreTCLK(void)
175 {
176 if (TCLK_savedDma & _Jtag.RST)
177 {
178 DMA1SA = (unsigned char*)DMA_TMSH_TDIH;
179 DMA1sbw();
180 DMA1SA = (unsigned char*) DMA_TMSL_TDIH;
181 DMA1sbw();
182 }
183 else
184 {
185 DMA1SA = (unsigned char*)DMA_TMSH_TDIL;
186 DMA1sbw();
187 // TMSL_TDIL is preloaded;
188 DMA2sbw();
189 }
190 }
191
192 #pragma inline=forced
sbw_ShiftDma(unsigned long long Data,unsigned short Bits)193 unsigned long long sbw_ShiftDma(unsigned long long Data, unsigned short Bits)
194 {
195 unsigned long long TDOvalue = 0x0000000000000000;
196 unsigned long long MSB = 0x0000000000000000;
197
198 switch(Bits)
199 {
200 case F_BYTE: MSB = 0x00000080;
201 break;
202 case F_WORD: MSB = 0x00008000;
203 break;
204 case F_ADDR: MSB = 0x00080000;
205 break;
206 case F_LONG: MSB = 0x80000000;
207 break;
208 case F_LONG_LONG: MSB = 0x8000000000000000;
209 break;
210 default: // this is an unsupported format, function will just return 0
211 return TDOvalue;
212 }
213 do
214 {
215 if (MSB & 1) // Last bit requires TMS=1
216 {
217 if(Data & MSB)
218 {
219 DMA1SA = (unsigned char*)DMA_TMSH_TDIH;
220 }
221 else
222 {
223 DMA1SA = (unsigned char*)DMA_TMSH_TDIL;
224 }
225 DMA1CTL |= DMAEN;
226 DMA1CTL |= DMAREQ; // DMA1 FIRE!!!
227 }
228 else
229 {
230 if(Data & MSB)
231 {
232 // TMSL_TDIH is preloaded;
233 DMA1CTL |= DMAEN;
234 DMA1CTL |= DMAREQ; // DMA1 FIRE!!!
235 }
236 else
237 {
238 // TMSL_TDIL is preloaded;
239 DMA2CTL |= DMAEN;
240 DMA2CTL |= DMAREQ; // DMA2 FIRE!!!
241 }
242 }
243 TDO_RD_DMA();
244 TDOvalue <<= 1; // TDO could be any port pin
245 TDOvalue |= (tdo_bitDma & _Jtag.RST) > 0;
246 }
247 while(MSB >>= 1);
248 restoreTCLK();
249 return(TDOvalue);
250 }
251
252 // -----------------------------------------------------------------------------
_hil_2w_TapReset_Dma(void)253 short _hil_2w_TapReset_Dma(void)
254 {
255 unsigned short i;
256
257 DMA1SA = (unsigned char*)DMA_TMSH_TDIH;
258
259 #ifdef MSP_FET
260 if (protocol_id != SPYBIWIRE_SUBMCU)
261 {
262 hil_fpga_enable_bypass();
263 }
264 #endif
265
266 // Reset JTAG FSM
267 for (i = 0; i < 6; i++) // 6 is nominal
268 {
269 // TMSH_TDIH is preloaded
270 DMA1sbw();
271 }
272 DMA1SA = (unsigned char*)DMA_TMSL_TDIH;
273 DMA1sbw();
274
275 #ifdef MSP_FET
276 if (protocol_id != SPYBIWIRE_SUBMCU)
277 {
278 hil_fpga_disable_bypass();
279 }
280 #endif
281 return 0;
282 }
283
284 // -----------------------------------------------------------------------------
_hil_2w_CheckJtagFuse_Dma(void)285 short _hil_2w_CheckJtagFuse_Dma(void)
286 {
287 unsigned short * dma2_tmp = DMA2SA;
288
289 DMA1SA = (unsigned char*)DMA_TMSH_TDIH;
290 DMA2SA = (unsigned char*)DMA_TMSL_TDIH;
291
292 #ifdef MSP_FET
293 if (protocol_id != SPYBIWIRE_SUBMCU)
294 {
295 hil_fpga_enable_bypass();
296 }
297 #endif
298
299 // TMSL_TDIH is preloaded // now in Run/Test Idle
300 DMA2sbw();
301 // Fuse check
302 // TMSH_TDIH is preloaded
303 DMA1sbw();
304 // TMSL_TDIH is preloaded
305 DMA2sbw();
306 // TMSH_TDIH is preloaded
307 DMA1sbw();
308 // TMSL_TDIH is preloaded
309 DMA2sbw();
310 // TMSH_TDIH is preloaded
311 DMA1sbw();
312 // In every TDI slot a TCK for the JTAG machine is generated.
313 // Thus we need to get TAP in Run/Test Idle state back again.
314 // TMSH_TDIH is preloaded
315 DMA1sbw();
316 // TMSL_TDIH is preloaded
317 DMA2sbw();
318
319 DMA2SA = dma2_tmp;
320
321 #ifdef MSP_FET
322 if (protocol_id != SPYBIWIRE_SUBMCU)
323 {
324 hil_fpga_disable_bypass();
325 }
326 #endif
327
328 return 0;
329 }
330
331 // -----------------------------------------------------------------------------
_hil_2w_Instr_Dma(unsigned char Instruction)332 unsigned char _hil_2w_Instr_Dma(unsigned char Instruction)
333 {
334 prevInstruction = Instruction;
335
336 // JTAG FSM state = Run-Test/Idle
337 if (TCLK_savedDma & _Jtag.RST) //PrepTCLK
338 {
339 DMA1SA = (unsigned char*)DMA_TMSH_TDIH;
340 DMA1sbw();
341 }
342 else
343 {
344 DMA1SA = (unsigned char*)DMA_TMSH_TDIL;
345 DMA1sbw();
346 DMA1SA = (unsigned char*)DMA_TMSH_TDIH;
347 }
348
349 // JTAG FSM state = Select DR-Scan
350 // TMSH_TDIH loaded in previous if/else
351 DMA1sbw();
352 // JTAG FSM state = Select IR-Scan
353 DMA1SA = (unsigned char*)DMA_TMSL_TDIH;
354 DMA1sbw();
355 // JTAG FSM state = Capture-IR
356 DMA1sbw();
357 // JTAG FSM state = Shift-IR, Shiftin TDI (8 bit)
358 return sbw_ShiftDma(Instruction,F_BYTE); // JTAG FSM state = Run-Test/Idle
359 }
360
361
362 #pragma inline=forced
hil_2w_SetReg_XBits8_64_Entry_DMA()363 void hil_2w_SetReg_XBits8_64_Entry_DMA()
364 {
365 // JTAG FSM state = Run-Test/Idle
366 if (TCLK_savedDma & _Jtag.RST) //PrepTCLK
367 {
368 DMA1SA = (unsigned char*)DMA_TMSH_TDIH;
369 }
370 else
371 {
372 DMA1SA = (unsigned char*)DMA_TMSH_TDIL;
373 }
374 DMA1sbw();
375
376 DMA1SA = (unsigned char*)DMA_TMSL_TDIH;
377 // JTAG FSM state = Select DR-Scan
378 DMA1sbw();
379 // JTAG FSM state = Capture-DR
380 DMA1sbw();
381 }
382
383 #pragma inline=forced
hil_2w_SetReg_XBits8_64_Exit_DMA()384 void hil_2w_SetReg_XBits8_64_Exit_DMA()
385 {
386 // TMS & TDI slot
387 DMA1SA = (unsigned char*)DMA_TMSH_TDIH;
388 DMA1sbw();
389 restoreTCLK();
390 }
391
392 //! \brief This function executes an SBW2 64BIT Data SHIFT (DR-SHIFT) in the case,
393 //! that the first 8 bits show a valid data capture from the JSTATE register. In case
394 //! of no valid capture the shift is ended after the first 8 bits.
395 //! \param[in] Data to be shifted into target device
396 //! \param[out] Data State - shows state of shifted out data
397 //! \return Value shifted out of target device JTAG module
398 #pragma inline=forced
hil_2w_SetReg_XBits8_64_Run_Dma(unsigned long long Data,unsigned char * DataState,unsigned short JStateVersion)399 unsigned long long hil_2w_SetReg_XBits8_64_Run_Dma(unsigned long long Data, unsigned char * DataState, unsigned short JStateVersion)
400 {
401 unsigned long long TDOvalue = 0x00000000;
402 unsigned long long MSB = 0x8000000000000000;
403 unsigned char currentDeviceState = 0;
404
405 hil_2w_SetReg_XBits8_64_Entry_DMA();
406
407 do
408 {
409 if (MSB & 1) // Last bit requires TMS=1
410 {
411 if(Data & MSB)
412 {
413 DMA1SA = (unsigned char*)DMA_TMSH_TDIH;
414 }
415 else
416 {
417 DMA1SA = (unsigned char*)DMA_TMSH_TDIL;
418 }
419 DMA1CTL |= DMAEN;
420 DMA1CTL |= DMAREQ; // DMA1 FIRE!!!
421 }
422 else
423 {
424 if(Data & MSB)
425 {
426 // TMSL_TDIH is preloaded;
427 DMA1CTL |= DMAEN;
428 DMA1CTL |= DMAREQ; // DMA1 FIRE!!!
429 }
430 else
431 {
432 // TMSL_TDIL is preloaded;
433 DMA2CTL |= DMAEN;
434 DMA2CTL |= DMAREQ; // DMA2 FIRE!!!
435 }
436 }
437 TDO_RD_DMA();
438 TDOvalue <<= 1; // TDO could be any port pin
439 TDOvalue |= (tdo_bitDma & _Jtag.RST) > 0;
440
441 // first 8 bits have been shifted out now go and evaluate it
442 if(MSB & EIGHT_JSTATE_BITS)
443 {
444 // Mask out all not needed bits for device state detection
445 currentDeviceState = TDOvalue & JSTATE_FLOW_CONTROL_BITS;
446
447 // check, if BIT[63, 62, 61, 60, 59 58, 57, 56, ] & 0x4 (BP_HIT) == TRUE
448 if(currentDeviceState & JSTATE_BP_HIT)
449 {
450 // exit DR shift state
451 hil_2w_SetReg_XBits8_64_Exit_DMA();
452 // reload Jstate IR
453 _hil_2w_Instr_Dma(IR_JSTATE_ID);
454
455 *DataState = VALID_DATA;
456 // retrun BP_HIT BIT
457 return(TDOvalue << 56);
458 }
459
460 // check, if BIT[63, 62, 61, 60, 59 58, 57, 56] (AM Sync. ongoing) == 0x83
461 else if(currentDeviceState == JSTATE_SYNC_ONGOING)
462 {
463 // exit DR shift state
464 hil_2w_SetReg_XBits8_64_Exit_DMA();
465
466 *DataState = SYNC_ONGOING;
467 return 0;
468 }
469 //check, if BIT[63, 62, 61, 60, 59 58, 57, 56] & 0x40 (Locked State) == 0x40
470 else if((currentDeviceState & JSTATE_LOCKED_STATE) == JSTATE_LOCKED_STATE &&
471 (currentDeviceState & JSTATE_LPM_X_FIVE) != JSTATE_LPM_X_FIVE)
472 {
473 // exit DR shift state
474 hil_2w_SetReg_XBits8_64_Exit_DMA();
475 *DataState = JTAG_LOCKED;
476 return(TDOvalue << 56);
477 }
478
479 //check, if BIT[63, 62, 61, 60, 59 58, 57, 56] ( Invalid LPM) == 0x81)
480 else if(currentDeviceState == JSTATE_INVALID_STATE)
481 {
482 // exit DR shift state
483 hil_2w_SetReg_XBits8_64_Exit_DMA();
484 // reload Jstate IR
485 _hil_2w_Instr_Dma(IR_JSTATE_ID);
486
487 *DataState = INVALID_DATA;
488 return 0;
489 }
490 /*PG2.0 && PG2.1 frozen Sync detection*/
491 else if (((currentDeviceState & JSTATE_SYNC_BROKEN_MASK) == JSTATE_SYNC_BROKEN_MCLK)
492 ||((currentDeviceState & JSTATE_SYNC_BROKEN_MASK) == JSTATE_SYNC_BROKEN_MCLK_PGACT)
493 ||((currentDeviceState & JSTATE_SYNC_BROKEN_MASK) == JSTATE_SYNC_BROKEN_PGACT))
494 {
495 hil_2w_SetReg_XBits8_64_Exit_DMA();
496
497 if(JStateVersion >= 0x21)
498 {
499 *DataState = SYNC_BROKEN;
500 return(0);
501 }
502 else // PG2.0
503 {
504 *DataState = VALID_DATA;
505 return(TDOvalue << 56);
506 }
507 }
508 // device is not in LPMx or AC read out mode just restart the shift but do not reload the JState IR
509 else if(currentDeviceState != JSTATE_VALID_CAPTURE
510 && (currentDeviceState != JSTATE_LPM_ONE_TWO)
511 && (currentDeviceState != JSTATE_LPM_THREE_FOUR)
512 && ((currentDeviceState & JSTATE_LPM_X_FIVE) != JSTATE_LPM_X_FIVE))
513 {
514 // exit DR shift state
515 hil_2w_SetReg_XBits8_64_Exit_DMA();
516 *DataState = INVALID_DATA;
517 return 0;
518 }
519 /*
520 else
521 {
522 do not break, continue shift of valid data
523 }
524 */
525 }
526
527 }
528 while(MSB >>= 1);
529 restoreTCLK();
530
531 if( currentDeviceState == JSTATE_LPM_ONE_TWO
532 || currentDeviceState == JSTATE_LPM_THREE_FOUR
533 || currentDeviceState == 0x00
534 || currentDeviceState == 0x02)
535 {
536 // reload Jstate IR
537 _hil_2w_Instr_Dma(IR_JSTATE_ID);
538 }
539
540 *DataState = VALID_DATA;
541 return(TDOvalue);
542 }
543
544 //! \brief This function executes an SBW2 64BIT Data SHIFT (DR-SHIFT) in the case,
545 //! that the first 8 bits show a valid data capture from the JSTATE register. In case
546 //! of no valid capture the shift is ended after the first 8 bits. Timeout could be
547 //! used to set the function run count.
548 //! \param[in] Data to be shifted into target device
549 //! \return Value shifted out of target device JTAG module
_hil_2w_SetReg_XBits8_64_Dma(unsigned long long Data,unsigned short loopCount,unsigned short JStateVersion)550 unsigned long long _hil_2w_SetReg_XBits8_64_Dma(unsigned long long Data, unsigned short loopCount, unsigned short JStateVersion)
551 {
552 unsigned long long TDOvalue = 0x00000000;
553 unsigned short timeout = loopCount, syncBorkenCount = loopCount/2;
554 unsigned char DataState = 0;
555 do
556 {
557 TDOvalue = hil_2w_SetReg_XBits8_64_Run_Dma(Data, &DataState, JStateVersion);
558 if(!timeout)
559 {
560 return TDOvalue;
561 }
562 timeout--;
563
564 if(DataState == SYNC_BROKEN && syncBorkenCount > 0)
565 {
566 syncBorkenCount--;
567 if(JStateVersion >= 0x21)
568 { // Only working for PG2.1, do not harm if executed on PG2.0 � but will not create any effect only consume time
569 unsigned long current3VtestReg = 0;
570
571 // read current 3VtestReg value
572 _hil_2w_Instr_Dma(IR_TEST_REG);
573 current3VtestReg = _hil_2w_SetReg_XBits32_Dma(0);
574 // set bit 25 high to rest sync
575 current3VtestReg |= 0x2000000;
576 _hil_2w_SetReg_XBits32_Dma(current3VtestReg);
577 // set bit 25 low reset sync done
578 current3VtestReg &= ~0x2000000;
579 _hil_2w_SetReg_XBits32_Dma(current3VtestReg);
580 _hil_2w_Instr_Dma(IR_JSTATE_ID);
581
582 }
583 else
584 {
585 return(TDOvalue);
586 }
587 }
588 }
589 while(DataState == INVALID_DATA || DataState == SYNC_ONGOING);
590 return(TDOvalue);
591 }
592
_hil_2w_SetReg_XBits08_Dma(unsigned char data)593 unsigned char _hil_2w_SetReg_XBits08_Dma(unsigned char data)
594 {
595 // JTAG FSM state = Run-Test/Idle
596 if (TCLK_savedDma & _Jtag.RST) //PrepTCLK
597 {
598 DMA1SA = (unsigned char*)DMA_TMSH_TDIH;
599 }
600 else
601 {
602 DMA1SA = (unsigned char*)DMA_TMSH_TDIL;
603 }
604 DMA1sbw();
605
606 DMA1SA = (unsigned char*)DMA_TMSL_TDIH;
607 // JTAG FSM state = Select DR-Scan
608 DMA1sbw();
609 // JTAG FSM state = Capture-DR
610 DMA1sbw();
611 // JTAG FSM state = Shift-DR, Shiftin TDI (16 bit)
612 return (sbw_ShiftDma(data,F_BYTE));
613 // JTAG FSM state = Run-Test/Idle
614 }
615
616
617
_hil_2w_SetReg_XBits16_Dma(unsigned short data)618 unsigned short _hil_2w_SetReg_XBits16_Dma(unsigned short data)
619 {
620 // JTAG FSM state = Run-Test/Idle
621 if (TCLK_savedDma & _Jtag.RST) //PrepTCLK
622 {
623 DMA1SA = (unsigned char*)DMA_TMSH_TDIH;
624 }
625 else
626 {
627 DMA1SA = (unsigned char*)DMA_TMSH_TDIL;
628 }
629 DMA1sbw();
630
631 DMA1SA = (unsigned char*)DMA_TMSL_TDIH;
632 // JTAG FSM state = Select DR-Scan
633 DMA1sbw();
634 // JTAG FSM state = Capture-DR
635 DMA1sbw();
636 // JTAG FSM state = Shift-DR, Shiftin TDI (16 bit)
637 return (sbw_ShiftDma(data,F_WORD));
638 // JTAG FSM state = Run-Test/Idle
639 }
640
641
642
_hil_2w_SetReg_XBits20_Dma(unsigned long data)643 unsigned long _hil_2w_SetReg_XBits20_Dma(unsigned long data)
644 {
645 unsigned long tmp;
646
647 // JTAG FSM state = Run-Test/Idle
648 if (TCLK_savedDma & _Jtag.RST) //PrepTCLK
649 {
650 DMA1SA = (unsigned char*)DMA_TMSH_TDIH;
651 }
652 else
653 {
654 DMA1SA = (unsigned char*)DMA_TMSH_TDIL;
655 }
656 DMA1sbw();
657
658 DMA1SA = (unsigned char*)DMA_TMSL_TDIH;
659 // JTAG FSM state = Select DR-Scan
660 DMA1sbw();
661 // JTAG FSM state = Capture-DR
662 DMA1sbw();
663 // JTAG FSM state = Shift-DR, Shiftin TDI (16 bit)
664 // de-scramble upper 4 bits if it was a 20bit shift
665 tmp = sbw_ShiftDma(data, F_ADDR);
666 tmp = ((tmp >> 4) | (tmp << 16)) & 0x000FFFFF;
667 return (tmp);
668 // JTAG FSM state = Run-Test/Idle
669 }
670
671
672
_hil_2w_SetReg_XBits32_Dma(unsigned long data)673 unsigned long _hil_2w_SetReg_XBits32_Dma(unsigned long data)
674 {
675 // JTAG FSM state = Run-Test/Idle
676 if (TCLK_savedDma & _Jtag.RST) //PrepTCLK
677 {
678 DMA1SA = (unsigned char*)DMA_TMSH_TDIH;
679 }
680 else
681 {
682 DMA1SA = (unsigned char*)DMA_TMSH_TDIL;
683 }
684 DMA1sbw();
685
686 DMA1SA = (unsigned char*)DMA_TMSL_TDIH;
687 // JTAG FSM state = Select DR-Scan
688 DMA1sbw();
689 // JTAG FSM state = Capture-DR
690 DMA1sbw();
691 // JTAG FSM state = Shift-DR, Shiftin TDI (32 bit)
692 return (sbw_ShiftDma(data, F_LONG));
693 // JTAG FSM state = Run-Test/Idle
694 }
695
696
_hil_2w_SetReg_XBits64_Dma(unsigned long long data)697 unsigned long long _hil_2w_SetReg_XBits64_Dma(unsigned long long data)
698 {
699 // JTAG FSM state = Run-Test/Idle
700 if (TCLK_savedDma & _Jtag.RST) //PrepTCLK
701 {
702 DMA1SA = (unsigned char*)DMA_TMSH_TDIH;
703 }
704 else
705 {
706 DMA1SA = (unsigned char*)DMA_TMSH_TDIL;
707 }
708 DMA1sbw();
709
710 DMA1SA = (unsigned char*)DMA_TMSL_TDIH;
711 // JTAG FSM state = Select DR-Scan
712 DMA1sbw();
713 // JTAG FSM state = Capture-DR
714 DMA1sbw();
715 // JTAG FSM state = Shift-DR, Shiftin TDI 64 bit)
716 return (sbw_ShiftDma(data, F_LONG_LONG));
717 // JTAG FSM state = Run-Test/Idle
718 }
719
720
721 //#pragma optimize = low
722 // -----------------------------------------------------------------------------
_hil_2w_Tclk_Dma(unsigned char state)723 void _hil_2w_Tclk_Dma(unsigned char state)
724 {
725 _DINT_FET();
726 if (TCLK_savedDma & _Jtag.RST) //PrepTCLK
727 {
728 TMSLDH_DMA();
729 }
730 else
731 {
732 TMSL_DMA();
733 }
734
735 if(state)
736 {
737 (*_Jtag.Out) |= _Jtag.RST;
738 TDIH_DMA(); TDOsbwDma(); // ExitTCLK
739 TCLK_savedDma = _Jtag.RST;
740 }
741 else
742 {
743 (*_Jtag.Out) &= ~_Jtag.RST;// original
744 TDIL_DMA(); TDOsbwDma(); // ExitTCLK
745 TCLK_savedDma = ~_Jtag.RST;
746 }
747 _EINT_FET();
748 }
749
750 // -----------------------------------------------------------------------------
_hil_2w_StepPsa_Dma_Xv2(unsigned long length)751 void _hil_2w_StepPsa_Dma_Xv2(unsigned long length)
752 {
753 unsigned short * dma2_tmp = DMA2SA;
754
755 DMA1SA = (unsigned char*)DMA_TMSH_TDIL;
756 DMA2SA = (unsigned char*)DMA_TMSL_TDIL;
757
758 #ifdef MSP_FET
759 if (protocol_id != SPYBIWIRE_SUBMCU)
760 {
761 hil_fpga_enable_bypass();
762 }
763 #endif
764
765 while(length--)
766 {
767 _hil_2w_Tclk_Dma(0);
768 // TMSH_TDIL preloaded
769 DMA1sbw();
770 // TMSL_TDIL preloaded
771 DMA2sbw();
772 // TMSL_TDIL preloaded
773 DMA2sbw();
774 // TMSH_TDIL preloaded
775 DMA1sbw();
776 // TMSH_TDIL preloaded
777 DMA1sbw();
778 // TMSL_TDIL preloaded
779 DMA2sbw();
780 _hil_2w_Tclk_Dma(1);
781 }
782
783 // Restore the prvious DMA2SA value
784 DMA2SA = dma2_tmp;
785
786 #ifdef MSP_FET
787 if (protocol_id != SPYBIWIRE_SUBMCU)
788 {
789 hil_fpga_disable_bypass();
790 }
791 #endif
792 }
793
794 // -----------------------------------------------------------------------------
_hil_2w_StepPsa_Dma(unsigned long length)795 void _hil_2w_StepPsa_Dma(unsigned long length)
796 {
797 unsigned short * dma2_tmp = DMA2SA;
798
799 DMA1SA = (unsigned char*)DMA_TMSH_TDIL;
800 DMA2SA = (unsigned char*)DMA_TMSL_TDIL;
801
802 #ifdef MSP_FET
803 if (protocol_id != SPYBIWIRE_SUBMCU)
804 {
805 hil_fpga_enable_bypass();
806 }
807 #endif
808 while(length--)
809 {
810 _hil_2w_Tclk_Dma(1);
811 _hil_2w_Tclk_Dma(0);
812 // TMSH_TDIH preloaded
813 DMA1sbw();
814 // TMSL_TDIH preloaded
815 DMA2sbw();
816 // TMSL_TDIH preloaded
817 DMA2sbw();
818 // TMSH_TDIH preloaded
819 DMA1sbw();
820 // TMSH_TDIH preloaded
821 DMA1sbw();
822 // TMSL_TDIH preloaded
823 DMA2sbw();
824 }
825 // Restore the prvious DMA2SA value
826 DMA2SA = dma2_tmp;
827
828 #ifdef MSP_FET
829 if (protocol_id != SPYBIWIRE_SUBMCU)
830 {
831 hil_fpga_disable_bypass();
832 }
833 #endif
834 }
835
836 // -----------------------------------------------------------------------------
_hil_2w_StepPsaTclkHigh_Dma(unsigned long length)837 void _hil_2w_StepPsaTclkHigh_Dma(unsigned long length)
838 {
839 unsigned short * dma2_tmp = DMA2SA;
840
841 DMA1SA = (unsigned char*)DMA_TMSH_TDIH;
842 DMA2SA = (unsigned char*)DMA_TMSL_TDIH;
843
844 #ifdef MSP_FET
845 if (protocol_id != SPYBIWIRE_SUBMCU)
846 {
847 hil_fpga_enable_bypass();
848 }
849 #endif
850
851 while(length--)
852 {
853 _hil_2w_Tclk_Dma(1);
854 // TMSH_TDIH preloaded
855 DMA1sbw();
856 // TMSL_TDIH preloaded
857 DMA2sbw();
858 // TMSL_TDIH preloaded
859 DMA2sbw();
860 // TMSH_TDIH preloaded
861 DMA1sbw();
862 // TMSH_TDIH preloaded
863 DMA1sbw();
864 // TMSL_TDIH preloaded
865 DMA2sbw();
866 _hil_2w_Tclk_Dma(0);
867 }
868
869 // Restore the prvious DMA2SA value
870 DMA2SA = dma2_tmp;
871
872 #ifdef MSP_FET
873 if (protocol_id != SPYBIWIRE_SUBMCU)
874 {
875 hil_fpga_disable_bypass();
876 }
877 #endif
878 }
879
_hil_2w_ConfigureSpeed_Dma(unsigned short speed)880 void _hil_2w_ConfigureSpeed_Dma(unsigned short speed)
881 {
882 switch(speed)
883 { //----------------------------------------------------------------------
884 case SBW600KHz: // fastes SBW2 speed
885 {
886 DMA1SZ = 8; // load DMA1 with size
887 DMA2SZ = 8; // load DMA1 with size
888 DMA_TMSH_TDIH[0] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
889 DMA_TMSH_TDIH[1] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
890 DMA_TMSH_TDIH[2] = /*TMS Slot*/ _Jtag.RST;
891 DMA_TMSH_TDIH[3] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
892
893 DMA_TMSH_TDIH[4] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
894 DMA_TMSH_TDIH[5] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
895 DMA_TMSH_TDIH[6] = /*TDI Slot*/ _Jtag.RST;
896 DMA_TMSH_TDIH[7] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
897
898 DMA_TMSH_TDIL[0] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
899 DMA_TMSH_TDIL[1] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
900 DMA_TMSH_TDIL[2] = /*TMS Slot*/ _Jtag.RST;
901 DMA_TMSH_TDIL[3] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
902
903 DMA_TMSH_TDIL[4] = /*TDI Slot*/ _Jtag.TST;
904 DMA_TMSH_TDIL[5] = /*TDI Slot*/ _Jtag.TST;
905 DMA_TMSH_TDIL[6] = /*TDI Slot*/ 0;
906 DMA_TMSH_TDIL[7] = /*TDI Slot*/ _Jtag.TST;
907
908 DMA_TMSL_TDIH[0] = /*TMS Slot*/ _Jtag.TST;
909 DMA_TMSL_TDIH[1] = /*TMS Slot*/ _Jtag.TST;
910 DMA_TMSL_TDIH[2] = /*TMS Slot*/ 0;
911 DMA_TMSL_TDIH[3] = /*TMS Slot*/ _Jtag.TST;
912
913 DMA_TMSL_TDIH[4] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
914 DMA_TMSL_TDIH[5] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
915 DMA_TMSL_TDIH[6] = /*TDI SLot*/ _Jtag.RST;
916 DMA_TMSL_TDIH[7] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
917
918 DMA_TMSL_TDIL[0] = /*TMS Slot*/ _Jtag.TST;
919 DMA_TMSL_TDIL[1] = /*TMS Slot*/ _Jtag.TST;
920 DMA_TMSL_TDIL[2] = /*TMS Slot*/ 0;
921 DMA_TMSL_TDIL[3] = /*TMS Slot*/ _Jtag.TST;
922
923 DMA_TMSL_TDIL[4] = /*TDI Slot*/ _Jtag.TST;
924 DMA_TMSL_TDIL[5] = /*TDI Slot*/ _Jtag.TST;
925 DMA_TMSL_TDIL[6] = /*TDI Slot*/ 0;
926 DMA_TMSL_TDIL[7] = /*TDI Slot*/ _Jtag.TST;
927 break;
928 }//---------------------------------------------------------------------
929 case SBW400KHz: // fastes SBW2 speed
930 {
931 DMA1SZ = 24; // load DMA1 with size
932 DMA2SZ = 24; // load DMA1 with size
933
934 DMA_TMSH_TDIH[0] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
935 DMA_TMSH_TDIH[1] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
936 DMA_TMSH_TDIH[2] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
937 DMA_TMSH_TDIH[3] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
938 DMA_TMSH_TDIH[4] = /*TMS Slot*/ _Jtag.RST;
939 DMA_TMSH_TDIH[5] = /*TMS Slot*/ _Jtag.RST;
940 DMA_TMSH_TDIH[6] = /*TMS Slot*/ _Jtag.RST;
941 DMA_TMSH_TDIH[7] = /*TMS Slot*/ _Jtag.RST;
942 DMA_TMSH_TDIH[8] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
943 DMA_TMSH_TDIH[9] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
944 DMA_TMSH_TDIH[10] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
945 DMA_TMSH_TDIH[11] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
946
947 DMA_TMSH_TDIH[12] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
948 DMA_TMSH_TDIH[13] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
949 DMA_TMSH_TDIH[14] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
950 DMA_TMSH_TDIH[15] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
951 DMA_TMSH_TDIH[16] = /*TDI Slot*/ _Jtag.RST;
952 DMA_TMSH_TDIH[17] = /*TDI Slot*/ _Jtag.RST;
953 DMA_TMSH_TDIH[18] = /*TDI Slot*/ _Jtag.RST;
954 DMA_TMSH_TDIH[19] = /*TDI Slot*/ _Jtag.RST;
955 DMA_TMSH_TDIH[20] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
956 DMA_TMSH_TDIH[21] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
957 DMA_TMSH_TDIH[22] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
958 DMA_TMSH_TDIH[23] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
959
960 DMA_TMSH_TDIL[0] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
961 DMA_TMSH_TDIL[1] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
962 DMA_TMSH_TDIL[2] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
963 DMA_TMSH_TDIL[3] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
964 DMA_TMSH_TDIL[4] = /*TMS Slot*/ _Jtag.RST;
965 DMA_TMSH_TDIL[5] = /*TMS Slot*/ _Jtag.RST;
966 DMA_TMSH_TDIL[6] = /*TMS Slot*/ _Jtag.RST;
967 DMA_TMSH_TDIL[7] = /*TMS Slot*/ _Jtag.RST;
968 DMA_TMSH_TDIL[8] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
969 DMA_TMSH_TDIL[9] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
970 DMA_TMSH_TDIL[10] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
971 DMA_TMSH_TDIL[11] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
972
973 DMA_TMSH_TDIL[12] = /*TDI Slot*/ _Jtag.TST;
974 DMA_TMSH_TDIL[13] = /*TDI Slot*/ _Jtag.TST;
975 DMA_TMSH_TDIL[14] = /*TDI Slot*/ _Jtag.TST;
976 DMA_TMSH_TDIL[15] = /*TDI Slot*/ _Jtag.TST;
977 DMA_TMSH_TDIL[16] = /*TDI Slot*/ 0;
978 DMA_TMSH_TDIL[17] = /*TDI Slot*/ 0;
979 DMA_TMSH_TDIL[18] = /*TDI Slot*/ 0;
980 DMA_TMSH_TDIL[19] = /*TDI Slot*/ 0;
981 DMA_TMSH_TDIL[20] = /*TDI Slot*/ _Jtag.TST;
982 DMA_TMSH_TDIL[21] = /*TDI Slot*/ _Jtag.TST;
983 DMA_TMSH_TDIL[22] = /*TDI Slot*/ _Jtag.TST;
984 DMA_TMSH_TDIL[23] = /*TDI Slot*/ _Jtag.TST;
985
986 DMA_TMSL_TDIH[0] = /*TMS Slot*/ _Jtag.TST;
987 DMA_TMSL_TDIH[1] = /*TMS Slot*/ _Jtag.TST;
988 DMA_TMSL_TDIH[2] = /*TMS Slot*/ _Jtag.TST;
989 DMA_TMSL_TDIH[3] = /*TMS Slot*/ _Jtag.TST;
990 DMA_TMSL_TDIH[4] = /*TMS Slot*/ 0;
991 DMA_TMSL_TDIH[5] = /*TMS Slot*/ 0;
992 DMA_TMSL_TDIH[6] = /*TMS Slot*/ 0;
993 DMA_TMSL_TDIH[7] = /*TMS Slot*/ 0;
994 DMA_TMSL_TDIH[8] = /*TMS Slot*/ _Jtag.TST;
995 DMA_TMSL_TDIH[9] = /*TMS Slot*/ _Jtag.TST;
996 DMA_TMSL_TDIH[10] = /*TMS Slot*/ _Jtag.TST;
997 DMA_TMSL_TDIH[11] = /*TMS Slot*/ _Jtag.TST;
998
999 DMA_TMSL_TDIH[12] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1000 DMA_TMSL_TDIH[13] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1001 DMA_TMSL_TDIH[14] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1002 DMA_TMSL_TDIH[15] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1003 DMA_TMSL_TDIH[16] = /*TDI SLot*/ _Jtag.RST;
1004 DMA_TMSL_TDIH[17] = /*TDI SLot*/ _Jtag.RST;
1005 DMA_TMSL_TDIH[18] = /*TDI SLot*/ _Jtag.RST;
1006 DMA_TMSL_TDIH[19] = /*TDI SLot*/ _Jtag.RST;
1007 DMA_TMSL_TDIH[20] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1008 DMA_TMSL_TDIH[21] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1009 DMA_TMSL_TDIH[22] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1010 DMA_TMSL_TDIH[23] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1011
1012 DMA_TMSL_TDIL[0] = /*TMS Slot*/ _Jtag.TST;
1013 DMA_TMSL_TDIL[1] = /*TMS Slot*/ _Jtag.TST;
1014 DMA_TMSL_TDIL[2] = /*TMS Slot*/ _Jtag.TST;
1015 DMA_TMSL_TDIL[3] = /*TMS Slot*/ _Jtag.TST;
1016 DMA_TMSL_TDIL[4] = /*TMS Slot*/ 0;
1017 DMA_TMSL_TDIL[5] = /*TMS Slot*/ 0;
1018 DMA_TMSL_TDIL[6] = /*TMS Slot*/ 0;
1019 DMA_TMSL_TDIL[7] = /*TMS Slot*/ 0;
1020 DMA_TMSL_TDIL[8] = /*TMS Slot*/ _Jtag.TST;
1021 DMA_TMSL_TDIL[9] = /*TMS Slot*/ _Jtag.TST;
1022 DMA_TMSL_TDIL[10] = /*TMS Slot*/ _Jtag.TST;
1023 DMA_TMSL_TDIL[11] = /*TMS Slot*/ _Jtag.TST;
1024
1025 DMA_TMSL_TDIL[12] = /*TDI Slot*/ _Jtag.TST;
1026 DMA_TMSL_TDIL[13] = /*TDI Slot*/ _Jtag.TST;
1027 DMA_TMSL_TDIL[14] = /*TDI Slot*/ _Jtag.TST;
1028 DMA_TMSL_TDIL[15] = /*TDI Slot*/ _Jtag.TST;
1029 DMA_TMSL_TDIL[16] = /*TDI Slot*/ 0;
1030 DMA_TMSL_TDIL[17] = /*TDI Slot*/ 0;
1031 DMA_TMSL_TDIL[18] = /*TDI Slot*/ 0;
1032 DMA_TMSL_TDIL[19] = /*TDI Slot*/ 0;
1033 DMA_TMSL_TDIL[20] = /*TDI Slot*/ _Jtag.TST;
1034 DMA_TMSL_TDIL[21] = /*TDI Slot*/ _Jtag.TST;
1035 DMA_TMSL_TDIL[22] = /*TDI Slot*/ _Jtag.TST;
1036 DMA_TMSL_TDIL[23] = /*TDI Slot*/ _Jtag.TST;
1037 break;
1038 }//---------------------------------------------------------------------
1039 case SBW200KHz: // fastes SBW2 speed
1040 {//---------------------------------------------------------------------
1041 DMA1SZ = 48; // load DMA1 with size
1042 DMA2SZ = 48; // load DMA1 with size
1043
1044 DMA_TMSH_TDIH[0] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1045 DMA_TMSH_TDIH[1] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1046 DMA_TMSH_TDIH[2] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1047 DMA_TMSH_TDIH[3] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1048 DMA_TMSH_TDIH[4] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1049 DMA_TMSH_TDIH[5] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1050 DMA_TMSH_TDIH[6] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1051 DMA_TMSH_TDIH[7] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1052 DMA_TMSH_TDIH[8] = /*TMS Slot*/ _Jtag.RST;
1053 DMA_TMSH_TDIH[9] = /*TMS Slot*/ _Jtag.RST;
1054 DMA_TMSH_TDIH[10] = /*TMS Slot*/ _Jtag.RST;
1055 DMA_TMSH_TDIH[11] = /*TMS Slot*/ _Jtag.RST;
1056 DMA_TMSH_TDIH[12] = /*TMS Slot*/ _Jtag.RST;
1057 DMA_TMSH_TDIH[13] = /*TMS Slot*/ _Jtag.RST;
1058 DMA_TMSH_TDIH[14] = /*TMS Slot*/ _Jtag.RST;
1059 DMA_TMSH_TDIH[15] = /*TMS Slot*/ _Jtag.RST;
1060 DMA_TMSH_TDIH[16] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1061 DMA_TMSH_TDIH[17] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1062 DMA_TMSH_TDIH[18] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1063 DMA_TMSH_TDIH[19] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1064 DMA_TMSH_TDIH[20] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1065 DMA_TMSH_TDIH[21] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1066 DMA_TMSH_TDIH[22] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1067 DMA_TMSH_TDIH[23] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1068
1069 DMA_TMSH_TDIH[24] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1070 DMA_TMSH_TDIH[25] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1071 DMA_TMSH_TDIH[26] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1072 DMA_TMSH_TDIH[27] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1073 DMA_TMSH_TDIH[28] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1074 DMA_TMSH_TDIH[29] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1075 DMA_TMSH_TDIH[30] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1076 DMA_TMSH_TDIH[31] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1077 DMA_TMSH_TDIH[32] = /*TDI Slot*/ _Jtag.RST;
1078 DMA_TMSH_TDIH[33] = /*TDI Slot*/ _Jtag.RST;
1079 DMA_TMSH_TDIH[34] = /*TDI Slot*/ _Jtag.RST;
1080 DMA_TMSH_TDIH[35] = /*TDI Slot*/ _Jtag.RST;
1081 DMA_TMSH_TDIH[36] = /*TDI Slot*/ _Jtag.RST;
1082 DMA_TMSH_TDIH[37] = /*TDI Slot*/ _Jtag.RST;
1083 DMA_TMSH_TDIH[38] = /*TDI Slot*/ _Jtag.RST;
1084 DMA_TMSH_TDIH[39] = /*TDI Slot*/ _Jtag.RST;
1085 DMA_TMSH_TDIH[40] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1086 DMA_TMSH_TDIH[41] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1087 DMA_TMSH_TDIH[42] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1088 DMA_TMSH_TDIH[43] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1089 DMA_TMSH_TDIH[44] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1090 DMA_TMSH_TDIH[45] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1091 DMA_TMSH_TDIH[46] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1092 DMA_TMSH_TDIH[47] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1093
1094 DMA_TMSH_TDIL[0] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1095 DMA_TMSH_TDIL[1] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1096 DMA_TMSH_TDIL[2] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1097 DMA_TMSH_TDIL[3] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1098 DMA_TMSH_TDIL[4] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1099 DMA_TMSH_TDIL[5] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1100 DMA_TMSH_TDIL[6] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1101 DMA_TMSH_TDIL[7] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1102 DMA_TMSH_TDIL[8] = /*TMS Slot*/ _Jtag.RST;
1103 DMA_TMSH_TDIL[9] = /*TMS Slot*/ _Jtag.RST;
1104 DMA_TMSH_TDIL[10] = /*TMS Slot*/ _Jtag.RST;
1105 DMA_TMSH_TDIL[11] = /*TMS Slot*/ _Jtag.RST;
1106 DMA_TMSH_TDIL[12] = /*TMS Slot*/ _Jtag.RST;
1107 DMA_TMSH_TDIL[13] = /*TMS Slot*/ _Jtag.RST;
1108 DMA_TMSH_TDIL[14] = /*TMS Slot*/ _Jtag.RST;
1109 DMA_TMSH_TDIL[15] = /*TMS Slot*/ _Jtag.RST;
1110 DMA_TMSH_TDIL[16] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1111 DMA_TMSH_TDIL[17] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1112 DMA_TMSH_TDIL[18] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1113 DMA_TMSH_TDIL[19] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1114 DMA_TMSH_TDIL[20] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1115 DMA_TMSH_TDIL[21] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1116 DMA_TMSH_TDIL[22] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1117 DMA_TMSH_TDIL[23] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1118
1119 DMA_TMSH_TDIL[24] = /*TDI Slot*/ _Jtag.TST;
1120 DMA_TMSH_TDIL[25] = /*TDI Slot*/ _Jtag.TST;
1121 DMA_TMSH_TDIL[26] = /*TDI Slot*/ _Jtag.TST;
1122 DMA_TMSH_TDIL[27] = /*TDI Slot*/ _Jtag.TST;
1123 DMA_TMSH_TDIL[28] = /*TDI Slot*/ _Jtag.TST;
1124 DMA_TMSH_TDIL[29] = /*TDI Slot*/ _Jtag.TST;
1125 DMA_TMSH_TDIL[30] = /*TDI Slot*/ _Jtag.TST;
1126 DMA_TMSH_TDIL[31] = /*TDI Slot*/ _Jtag.TST;
1127 DMA_TMSH_TDIL[32] = /*TDI Slot*/ 0;
1128 DMA_TMSH_TDIL[33] = /*TDI Slot*/ 0;
1129 DMA_TMSH_TDIL[34] = /*TDI Slot*/ 0;
1130 DMA_TMSH_TDIL[35] = /*TDI Slot*/ 0;
1131 DMA_TMSH_TDIL[36] = /*TDI Slot*/ 0;
1132 DMA_TMSH_TDIL[37] = /*TDI Slot*/ 0;
1133 DMA_TMSH_TDIL[38] = /*TDI Slot*/ 0;
1134 DMA_TMSH_TDIL[39] = /*TDI Slot*/ 0;
1135 DMA_TMSH_TDIL[40] = /*TDI Slot*/ _Jtag.TST;
1136 DMA_TMSH_TDIL[41] = /*TDI Slot*/ _Jtag.TST;
1137 DMA_TMSH_TDIL[42] = /*TDI Slot*/ _Jtag.TST;
1138 DMA_TMSH_TDIL[43] = /*TDI Slot*/ _Jtag.TST;
1139 DMA_TMSH_TDIL[44] = /*TDI Slot*/ _Jtag.TST;
1140 DMA_TMSH_TDIL[45] = /*TDI Slot*/ _Jtag.TST;
1141 DMA_TMSH_TDIL[46] = /*TDI Slot*/ _Jtag.TST;
1142 DMA_TMSH_TDIL[47] = /*TDI Slot*/ _Jtag.TST;
1143
1144 DMA_TMSL_TDIH[0] = /*TMS Slot*/ _Jtag.TST;
1145 DMA_TMSL_TDIH[1] = /*TMS Slot*/ _Jtag.TST;
1146 DMA_TMSL_TDIH[2] = /*TMS Slot*/ _Jtag.TST;
1147 DMA_TMSL_TDIH[3] = /*TMS Slot*/ _Jtag.TST;
1148 DMA_TMSL_TDIH[4] = /*TMS Slot*/ _Jtag.TST;
1149 DMA_TMSL_TDIH[5] = /*TMS Slot*/ _Jtag.TST;
1150 DMA_TMSL_TDIH[6] = /*TMS Slot*/ _Jtag.TST;
1151 DMA_TMSL_TDIH[7] = /*TMS Slot*/ _Jtag.TST;
1152 DMA_TMSL_TDIH[8] = /*TMS Slot*/ 0;
1153 DMA_TMSL_TDIH[9] = /*TMS Slot*/ 0;
1154 DMA_TMSL_TDIH[10] = /*TMS Slot*/ 0;
1155 DMA_TMSL_TDIH[11] = /*TMS Slot*/ 0;
1156 DMA_TMSL_TDIH[12] = /*TMS Slot*/ 0;
1157 DMA_TMSL_TDIH[13] = /*TMS Slot*/ 0;
1158 DMA_TMSL_TDIH[14] = /*TMS Slot*/ 0;
1159 DMA_TMSL_TDIH[15] = /*TMS Slot*/ 0;
1160 DMA_TMSL_TDIH[16] = /*TMS Slot*/ _Jtag.TST;
1161 DMA_TMSL_TDIH[17] = /*TMS Slot*/ _Jtag.TST;
1162 DMA_TMSL_TDIH[18] = /*TMS Slot*/ _Jtag.TST;
1163 DMA_TMSL_TDIH[19] = /*TMS Slot*/ _Jtag.TST;
1164 DMA_TMSL_TDIH[20] = /*TMS Slot*/ _Jtag.TST;
1165 DMA_TMSL_TDIH[21] = /*TMS Slot*/ _Jtag.TST;
1166 DMA_TMSL_TDIH[22] = /*TMS Slot*/ _Jtag.TST;
1167 DMA_TMSL_TDIH[23] = /*TMS Slot*/ _Jtag.TST;
1168
1169 DMA_TMSL_TDIH[24] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1170 DMA_TMSL_TDIH[25] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1171 DMA_TMSL_TDIH[26] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1172 DMA_TMSL_TDIH[27] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1173 DMA_TMSL_TDIH[28] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1174 DMA_TMSL_TDIH[29] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1175 DMA_TMSL_TDIH[30] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1176 DMA_TMSL_TDIH[31] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1177 DMA_TMSL_TDIH[32] = /*TDI SLot*/ _Jtag.RST;
1178 DMA_TMSL_TDIH[33] = /*TDI SLot*/ _Jtag.RST;
1179 DMA_TMSL_TDIH[34] = /*TDI SLot*/ _Jtag.RST;
1180 DMA_TMSL_TDIH[35] = /*TDI SLot*/ _Jtag.RST;
1181 DMA_TMSL_TDIH[36] = /*TDI SLot*/ _Jtag.RST;
1182 DMA_TMSL_TDIH[37] = /*TDI SLot*/ _Jtag.RST;
1183 DMA_TMSL_TDIH[38] = /*TDI SLot*/ _Jtag.RST;
1184 DMA_TMSL_TDIH[39] = /*TDI SLot*/ _Jtag.RST;
1185 DMA_TMSL_TDIH[40] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1186 DMA_TMSL_TDIH[41] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1187 DMA_TMSL_TDIH[42] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1188 DMA_TMSL_TDIH[43] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1189 DMA_TMSL_TDIH[44] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1190 DMA_TMSL_TDIH[45] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1191 DMA_TMSL_TDIH[46] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1192 DMA_TMSL_TDIH[47] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1193
1194 DMA_TMSL_TDIL[0] = /*TMS Slot*/ _Jtag.TST;
1195 DMA_TMSL_TDIL[1] = /*TMS Slot*/ _Jtag.TST;
1196 DMA_TMSL_TDIL[2] = /*TMS Slot*/ _Jtag.TST;
1197 DMA_TMSL_TDIL[3] = /*TMS Slot*/ _Jtag.TST;
1198 DMA_TMSL_TDIL[4] = /*TMS Slot*/ _Jtag.TST;
1199 DMA_TMSL_TDIL[5] = /*TMS Slot*/ _Jtag.TST;
1200 DMA_TMSL_TDIL[6] = /*TMS Slot*/ _Jtag.TST;
1201 DMA_TMSL_TDIL[7] = /*TMS Slot*/ _Jtag.TST;
1202 DMA_TMSL_TDIL[8] = /*TMS Slot*/ 0;
1203 DMA_TMSL_TDIL[9] = /*TMS Slot*/ 0;
1204 DMA_TMSL_TDIL[10] = /*TMS Slot*/ 0;
1205 DMA_TMSL_TDIL[11] = /*TMS Slot*/ 0;
1206 DMA_TMSL_TDIL[12] = /*TMS Slot*/ 0;
1207 DMA_TMSL_TDIL[13] = /*TMS Slot*/ 0;
1208 DMA_TMSL_TDIL[14] = /*TMS Slot*/ 0;
1209 DMA_TMSL_TDIL[15] = /*TMS Slot*/ 0;
1210 DMA_TMSL_TDIL[16] = /*TMS Slot*/ _Jtag.TST;
1211 DMA_TMSL_TDIL[17] = /*TMS Slot*/ _Jtag.TST;
1212 DMA_TMSL_TDIL[18]= /*TMS Slot*/ _Jtag.TST;
1213 DMA_TMSL_TDIL[19] = /*TMS Slot*/ _Jtag.TST;
1214 DMA_TMSL_TDIL[20] = /*TMS Slot*/ _Jtag.TST;
1215 DMA_TMSL_TDIL[21] = /*TMS Slot*/ _Jtag.TST;
1216 DMA_TMSL_TDIL[22] = /*TMS Slot*/ _Jtag.TST;
1217 DMA_TMSL_TDIL[23] = /*TMS Slot*/ _Jtag.TST;
1218
1219 DMA_TMSL_TDIL[24] = /*TDI Slot*/ _Jtag.TST;
1220 DMA_TMSL_TDIL[25] = /*TDI Slot*/ _Jtag.TST;
1221 DMA_TMSL_TDIL[26] = /*TDI Slot*/ _Jtag.TST;
1222 DMA_TMSL_TDIL[27] = /*TDI Slot*/ _Jtag.TST;
1223 DMA_TMSL_TDIL[28] = /*TDI Slot*/ _Jtag.TST;
1224 DMA_TMSL_TDIL[29] = /*TDI Slot*/ _Jtag.TST;
1225 DMA_TMSL_TDIL[30] = /*TDI Slot*/ _Jtag.TST;
1226 DMA_TMSL_TDIL[31] = /*TDI Slot*/ _Jtag.TST;
1227 DMA_TMSL_TDIL[32] = /*TDI Slot*/ 0;
1228 DMA_TMSL_TDIL[33] = /*TDI Slot*/ 0;
1229 DMA_TMSL_TDIL[34] = /*TDI Slot*/ 0;
1230 DMA_TMSL_TDIL[35] = /*TDI Slot*/ 0;
1231 DMA_TMSL_TDIL[36] = /*TDI Slot*/ 0;
1232 DMA_TMSL_TDIL[37] = /*TDI Slot*/ 0;
1233 DMA_TMSL_TDIL[38] = /*TDI Slot*/ 0;
1234 DMA_TMSL_TDIL[39] = /*TDI Slot*/ 0;
1235 DMA_TMSL_TDIL[40] = /*TDI Slot*/ _Jtag.TST;
1236 DMA_TMSL_TDIL[41] = /*TDI Slot*/ _Jtag.TST;
1237 DMA_TMSL_TDIL[42] = /*TDI Slot*/ _Jtag.TST;
1238 DMA_TMSL_TDIL[43] = /*TDI Slot*/ _Jtag.TST;
1239 DMA_TMSL_TDIL[44] = /*TDI Slot*/ _Jtag.TST;
1240 DMA_TMSL_TDIL[45] = /*TDI Slot*/ _Jtag.TST;
1241 DMA_TMSL_TDIL[46] = /*TDI Slot*/ _Jtag.TST;
1242 DMA_TMSL_TDIL[47] = /*TDI Slot*/ _Jtag.TST;
1243 break;
1244 }//---------------------------------------------------------------------
1245 case SBW100KHz: // fastes SBW2 speed
1246 {//---------------------------------------------------------------------
1247 DMA1SZ = 84; // load DMA1 with size
1248 DMA2SZ = 84; // load DMA1 with size
1249
1250 DMA_TMSH_TDIH[0] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1251 DMA_TMSH_TDIH[1] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1252 DMA_TMSH_TDIH[2] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1253 DMA_TMSH_TDIH[3] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1254 DMA_TMSH_TDIH[4] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1255 DMA_TMSH_TDIH[5] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1256 DMA_TMSH_TDIH[6] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1257 DMA_TMSH_TDIH[7] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1258 DMA_TMSH_TDIH[8] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1259 DMA_TMSH_TDIH[9] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1260 DMA_TMSH_TDIH[10] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1261 DMA_TMSH_TDIH[11] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1262 DMA_TMSH_TDIH[12] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1263 DMA_TMSH_TDIH[13] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1264 DMA_TMSH_TDIH[14] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1265 DMA_TMSH_TDIH[15] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1266 DMA_TMSH_TDIH[16] = /*TMS Slot*/ _Jtag.RST;
1267 DMA_TMSH_TDIH[17] = /*TMS Slot*/ _Jtag.RST;
1268 DMA_TMSH_TDIH[18] = /*TMS Slot*/ _Jtag.RST;
1269 DMA_TMSH_TDIH[19] = /*TMS Slot*/ _Jtag.RST;
1270 DMA_TMSH_TDIH[20] = /*TMS Slot*/ _Jtag.RST;
1271 DMA_TMSH_TDIH[21] = /*TMS Slot*/ _Jtag.RST;
1272 DMA_TMSH_TDIH[22] = /*TMS Slot*/ _Jtag.RST;
1273 DMA_TMSH_TDIH[23] = /*TMS Slot*/ _Jtag.RST;
1274 DMA_TMSH_TDIH[24] = /*TMS Slot*/ _Jtag.RST;
1275 DMA_TMSH_TDIH[25] = /*TMS Slot*/ _Jtag.RST;
1276 DMA_TMSH_TDIH[26] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1277 DMA_TMSH_TDIH[27] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1278 DMA_TMSH_TDIH[28] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1279 DMA_TMSH_TDIH[29] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1280 DMA_TMSH_TDIH[30] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1281 DMA_TMSH_TDIH[31] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1282 DMA_TMSH_TDIH[32] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1283 DMA_TMSH_TDIH[33] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1284 DMA_TMSH_TDIH[34] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1285 DMA_TMSH_TDIH[35] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1286 DMA_TMSH_TDIH[36] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1287 DMA_TMSH_TDIH[37] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1288 DMA_TMSH_TDIH[38] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1289 DMA_TMSH_TDIH[39] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1290 DMA_TMSH_TDIH[40] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1291 DMA_TMSH_TDIH[41] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1292
1293 DMA_TMSH_TDIH[42] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1294 DMA_TMSH_TDIH[43] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1295 DMA_TMSH_TDIH[44] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1296 DMA_TMSH_TDIH[45] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1297 DMA_TMSH_TDIH[46] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1298 DMA_TMSH_TDIH[47] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1299 DMA_TMSH_TDIH[48] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1300 DMA_TMSH_TDIH[49] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1301 DMA_TMSH_TDIH[50] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1302 DMA_TMSH_TDIH[51] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1303 DMA_TMSH_TDIH[52] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1304 DMA_TMSH_TDIH[53] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1305 DMA_TMSH_TDIH[54] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1306 DMA_TMSH_TDIH[55] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1307 DMA_TMSH_TDIH[56] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1308 DMA_TMSH_TDIH[57] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1309 DMA_TMSH_TDIH[58] = /*TDI Slot*/ _Jtag.RST;
1310 DMA_TMSH_TDIH[59] = /*TDI Slot*/ _Jtag.RST;
1311 DMA_TMSH_TDIH[60] = /*TDI Slot*/ _Jtag.RST;
1312 DMA_TMSH_TDIH[61] = /*TDI Slot*/ _Jtag.RST;
1313 DMA_TMSH_TDIH[62] = /*TDI Slot*/ _Jtag.RST;
1314 DMA_TMSH_TDIH[63] = /*TDI Slot*/ _Jtag.RST;
1315 DMA_TMSH_TDIH[64] = /*TDI Slot*/ _Jtag.RST;
1316 DMA_TMSH_TDIH[65] = /*TDI Slot*/ _Jtag.RST;
1317 DMA_TMSH_TDIH[66] = /*TDI Slot*/ _Jtag.RST;
1318 DMA_TMSH_TDIH[67] = /*TDI Slot*/ _Jtag.RST;
1319 DMA_TMSH_TDIH[68] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1320 DMA_TMSH_TDIH[69] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1321 DMA_TMSH_TDIH[70] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1322 DMA_TMSH_TDIH[71] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1323 DMA_TMSH_TDIH[72] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1324 DMA_TMSH_TDIH[73] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1325 DMA_TMSH_TDIH[74] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1326 DMA_TMSH_TDIH[75] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1327 DMA_TMSH_TDIH[76] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1328 DMA_TMSH_TDIH[77] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1329 DMA_TMSH_TDIH[78] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1330 DMA_TMSH_TDIH[79] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1331 DMA_TMSH_TDIH[80] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1332 DMA_TMSH_TDIH[81] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1333 DMA_TMSH_TDIH[82] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1334 DMA_TMSH_TDIH[83] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1335
1336 DMA_TMSH_TDIL[0] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1337 DMA_TMSH_TDIL[1] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1338 DMA_TMSH_TDIL[2] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1339 DMA_TMSH_TDIL[3] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1340 DMA_TMSH_TDIL[4] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1341 DMA_TMSH_TDIL[5] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1342 DMA_TMSH_TDIL[6] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1343 DMA_TMSH_TDIL[7] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1344 DMA_TMSH_TDIL[8] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1345 DMA_TMSH_TDIL[9] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1346 DMA_TMSH_TDIL[10] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1347 DMA_TMSH_TDIL[11] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1348 DMA_TMSH_TDIL[12] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1349 DMA_TMSH_TDIL[13] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1350 DMA_TMSH_TDIL[14] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1351 DMA_TMSH_TDIL[15] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1352 DMA_TMSH_TDIL[16] = /*TMS Slot*/ _Jtag.RST;
1353 DMA_TMSH_TDIL[17] = /*TMS Slot*/ _Jtag.RST;
1354 DMA_TMSH_TDIL[18] = /*TMS Slot*/ _Jtag.RST;
1355 DMA_TMSH_TDIL[19] = /*TMS Slot*/ _Jtag.RST;
1356 DMA_TMSH_TDIL[20] = /*TMS Slot*/ _Jtag.RST;
1357 DMA_TMSH_TDIL[21] = /*TMS Slot*/ _Jtag.RST;
1358 DMA_TMSH_TDIL[22] = /*TMS Slot*/ _Jtag.RST;
1359 DMA_TMSH_TDIL[23] = /*TMS Slot*/ _Jtag.RST;
1360 DMA_TMSH_TDIL[24] = /*TMS Slot*/ _Jtag.RST;
1361 DMA_TMSH_TDIL[25] = /*TMS Slot*/ _Jtag.RST;
1362 DMA_TMSH_TDIL[26] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1363 DMA_TMSH_TDIL[27] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1364 DMA_TMSH_TDIL[28] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1365 DMA_TMSH_TDIL[29] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1366 DMA_TMSH_TDIL[30] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1367 DMA_TMSH_TDIL[31] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1368 DMA_TMSH_TDIL[32] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1369 DMA_TMSH_TDIL[33] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1370 DMA_TMSH_TDIL[34] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1371 DMA_TMSH_TDIL[35] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1372 DMA_TMSH_TDIL[36] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1373 DMA_TMSH_TDIL[37] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1374 DMA_TMSH_TDIL[38] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1375 DMA_TMSH_TDIL[39] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1376 DMA_TMSH_TDIL[40] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1377 DMA_TMSH_TDIL[41] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1378
1379 DMA_TMSH_TDIL[42] = /*TDI Slot*/ _Jtag.TST;
1380 DMA_TMSH_TDIL[43] = /*TDI Slot*/ _Jtag.TST;
1381 DMA_TMSH_TDIL[44] = /*TDI Slot*/ _Jtag.TST;
1382 DMA_TMSH_TDIL[45] = /*TDI Slot*/ _Jtag.TST;
1383 DMA_TMSH_TDIL[46] = /*TDI Slot*/ _Jtag.TST;
1384 DMA_TMSH_TDIL[47] = /*TDI Slot*/ _Jtag.TST;
1385 DMA_TMSH_TDIL[48] = /*TDI Slot*/ _Jtag.TST;
1386 DMA_TMSH_TDIL[49] = /*TDI Slot*/ _Jtag.TST;
1387 DMA_TMSH_TDIL[50] = /*TDI Slot*/ _Jtag.TST;
1388 DMA_TMSH_TDIL[51] = /*TDI Slot*/ _Jtag.TST;
1389 DMA_TMSH_TDIL[52] = /*TDI Slot*/ _Jtag.TST;
1390 DMA_TMSH_TDIL[53] = /*TDI Slot*/ _Jtag.TST;
1391 DMA_TMSH_TDIL[54] = /*TDI Slot*/ _Jtag.TST;
1392 DMA_TMSH_TDIL[55] = /*TDI Slot*/ _Jtag.TST;
1393 DMA_TMSH_TDIL[56] = /*TDI Slot*/ _Jtag.TST;
1394 DMA_TMSH_TDIL[57] = /*TDI Slot*/ _Jtag.TST;
1395 DMA_TMSH_TDIL[58] = /*TDI Slot*/ 0;
1396 DMA_TMSH_TDIL[59] = /*TDI Slot*/ 0;
1397 DMA_TMSH_TDIL[60] = /*TDI Slot*/ 0;
1398 DMA_TMSH_TDIL[61] = /*TDI Slot*/ 0;
1399 DMA_TMSH_TDIL[62] = /*TDI Slot*/ 0;
1400 DMA_TMSH_TDIL[63] = /*TDI Slot*/ 0;
1401 DMA_TMSH_TDIL[64] = /*TDI Slot*/ 0;
1402 DMA_TMSH_TDIL[65] = /*TDI Slot*/ 0;
1403 DMA_TMSH_TDIL[66] = /*TDI Slot*/ 0;
1404 DMA_TMSH_TDIL[67] = /*TDI Slot*/ 0;
1405 DMA_TMSH_TDIL[68] = /*TDI Slot*/ _Jtag.TST;
1406 DMA_TMSH_TDIL[69] = /*TDI Slot*/ _Jtag.TST;
1407 DMA_TMSH_TDIL[70] = /*TDI Slot*/ _Jtag.TST;
1408 DMA_TMSH_TDIL[71] = /*TDI Slot*/ _Jtag.TST;
1409 DMA_TMSH_TDIL[72] = /*TDI Slot*/ _Jtag.TST;
1410 DMA_TMSH_TDIL[73] = /*TDI Slot*/ _Jtag.TST;
1411 DMA_TMSH_TDIL[74] = /*TDI Slot*/ _Jtag.TST;
1412 DMA_TMSH_TDIL[75] = /*TDI Slot*/ _Jtag.TST;
1413 DMA_TMSH_TDIL[76] = /*TDI Slot*/ _Jtag.TST;
1414 DMA_TMSH_TDIL[77] = /*TDI Slot*/ _Jtag.TST;
1415 DMA_TMSH_TDIL[78] = /*TDI Slot*/ _Jtag.TST;
1416 DMA_TMSH_TDIL[79] = /*TDI Slot*/ _Jtag.TST;
1417 DMA_TMSH_TDIL[80] = /*TDI Slot*/ _Jtag.TST;
1418 DMA_TMSH_TDIL[81] = /*TDI Slot*/ _Jtag.TST;
1419 DMA_TMSH_TDIL[82] = /*TDI Slot*/ _Jtag.TST;
1420 DMA_TMSH_TDIL[83] = /*TDI Slot*/ _Jtag.TST;
1421
1422 DMA_TMSL_TDIH[0] = /*TMS Slot*/ _Jtag.TST;
1423 DMA_TMSL_TDIH[1] = /*TMS Slot*/ _Jtag.TST;
1424 DMA_TMSL_TDIH[2] = /*TMS Slot*/ _Jtag.TST;
1425 DMA_TMSL_TDIH[3] = /*TMS Slot*/ _Jtag.TST;
1426 DMA_TMSL_TDIH[4] = /*TMS Slot*/ _Jtag.TST;
1427 DMA_TMSL_TDIH[5] = /*TMS Slot*/ _Jtag.TST;
1428 DMA_TMSL_TDIH[6] = /*TMS Slot*/ _Jtag.TST;
1429 DMA_TMSL_TDIH[7] = /*TMS Slot*/ _Jtag.TST;
1430 DMA_TMSL_TDIH[8] = /*TMS Slot*/ _Jtag.TST;
1431 DMA_TMSL_TDIH[9] = /*TMS Slot*/ _Jtag.TST;
1432 DMA_TMSL_TDIH[10] = /*TMS Slot*/ _Jtag.TST;
1433 DMA_TMSL_TDIH[11] = /*TMS Slot*/ _Jtag.TST;
1434 DMA_TMSL_TDIH[12] = /*TMS Slot*/ _Jtag.TST;
1435 DMA_TMSL_TDIH[13] = /*TMS Slot*/ _Jtag.TST;
1436 DMA_TMSL_TDIH[14] = /*TMS Slot*/ _Jtag.TST;
1437 DMA_TMSL_TDIH[15] = /*TMS Slot*/ _Jtag.TST;
1438 DMA_TMSL_TDIH[16] = /*TMS Slot*/ 0;
1439 DMA_TMSL_TDIH[17] = /*TMS Slot*/ 0;
1440 DMA_TMSL_TDIH[18] = /*TMS Slot*/ 0;
1441 DMA_TMSL_TDIH[19] = /*TMS Slot*/ 0;
1442 DMA_TMSL_TDIH[20] = /*TMS Slot*/ 0;
1443 DMA_TMSL_TDIH[21] = /*TMS Slot*/ 0;
1444 DMA_TMSL_TDIH[22] = /*TMS Slot*/ 0;
1445 DMA_TMSL_TDIH[23] = /*TMS Slot*/ 0;
1446 DMA_TMSL_TDIH[24] = /*TMS Slot*/ 0;
1447 DMA_TMSL_TDIH[25] = /*TMS Slot*/ 0;
1448 DMA_TMSL_TDIH[26] = /*TMS Slot*/ _Jtag.TST;
1449 DMA_TMSL_TDIH[27] = /*TMS Slot*/ _Jtag.TST;
1450 DMA_TMSL_TDIH[28] = /*TMS Slot*/ _Jtag.TST;
1451 DMA_TMSL_TDIH[29] = /*TMS Slot*/ _Jtag.TST;
1452 DMA_TMSL_TDIH[30] = /*TMS Slot*/ _Jtag.TST;
1453 DMA_TMSL_TDIH[31] = /*TMS Slot*/ _Jtag.TST;
1454 DMA_TMSL_TDIH[32] = /*TMS Slot*/ _Jtag.TST;
1455 DMA_TMSL_TDIH[33] = /*TMS Slot*/ _Jtag.TST;
1456 DMA_TMSL_TDIH[34] = /*TMS Slot*/ _Jtag.TST;
1457 DMA_TMSL_TDIH[35] = /*TMS Slot*/ _Jtag.TST;
1458 DMA_TMSL_TDIH[36] = /*TMS Slot*/ _Jtag.TST;
1459 DMA_TMSL_TDIH[37] = /*TMS Slot*/ _Jtag.TST;
1460 DMA_TMSL_TDIH[38] = /*TMS Slot*/ _Jtag.TST;
1461 DMA_TMSL_TDIH[39] = /*TMS Slot*/ _Jtag.TST;
1462 DMA_TMSL_TDIH[40] = /*TMS Slot*/ _Jtag.TST;
1463 DMA_TMSL_TDIH[41] = /*TMS Slot*/ _Jtag.TST;
1464
1465 DMA_TMSL_TDIH[42] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1466 DMA_TMSL_TDIH[43] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1467 DMA_TMSL_TDIH[44] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1468 DMA_TMSL_TDIH[45] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1469 DMA_TMSL_TDIH[46] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1470 DMA_TMSL_TDIH[47] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1471 DMA_TMSL_TDIH[48] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1472 DMA_TMSL_TDIH[49] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1473 DMA_TMSL_TDIH[50] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1474 DMA_TMSL_TDIH[51] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1475 DMA_TMSL_TDIH[52] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1476 DMA_TMSL_TDIH[53] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1477 DMA_TMSL_TDIH[54] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1478 DMA_TMSL_TDIH[55] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1479 DMA_TMSL_TDIH[56] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1480 DMA_TMSL_TDIH[57] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1481 DMA_TMSL_TDIH[58] = /*TDI SLot*/ _Jtag.RST;
1482 DMA_TMSL_TDIH[59] = /*TDI SLot*/ _Jtag.RST;
1483 DMA_TMSL_TDIH[60] = /*TDI SLot*/ _Jtag.RST;
1484 DMA_TMSL_TDIH[61] = /*TDI SLot*/ _Jtag.RST;
1485 DMA_TMSL_TDIH[62] = /*TDI SLot*/ _Jtag.RST;
1486 DMA_TMSL_TDIH[63] = /*TDI SLot*/ _Jtag.RST;
1487 DMA_TMSL_TDIH[64] = /*TDI SLot*/ _Jtag.RST;
1488 DMA_TMSL_TDIH[65] = /*TDI SLot*/ _Jtag.RST;
1489 DMA_TMSL_TDIH[66] = /*TDI SLot*/ _Jtag.RST;
1490 DMA_TMSL_TDIH[67] = /*TDI SLot*/ _Jtag.RST;
1491 DMA_TMSL_TDIH[68] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1492 DMA_TMSL_TDIH[69] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1493 DMA_TMSL_TDIH[70] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1494 DMA_TMSL_TDIH[71] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1495 DMA_TMSL_TDIH[72] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1496 DMA_TMSL_TDIH[73] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1497 DMA_TMSL_TDIH[74] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1498 DMA_TMSL_TDIH[75] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1499 DMA_TMSL_TDIH[76] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1500 DMA_TMSL_TDIH[77] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1501 DMA_TMSL_TDIH[78] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1502 DMA_TMSL_TDIH[79] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1503 DMA_TMSL_TDIH[80] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1504 DMA_TMSL_TDIH[81] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1505 DMA_TMSL_TDIH[82] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1506 DMA_TMSL_TDIH[83] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1507
1508 DMA_TMSL_TDIL[0] = /*TMS Slot*/ _Jtag.TST;
1509 DMA_TMSL_TDIL[1] = /*TMS Slot*/ _Jtag.TST;
1510 DMA_TMSL_TDIL[2] = /*TMS Slot*/ _Jtag.TST;
1511 DMA_TMSL_TDIL[3] = /*TMS Slot*/ _Jtag.TST;
1512 DMA_TMSL_TDIL[4] = /*TMS Slot*/ _Jtag.TST;
1513 DMA_TMSL_TDIL[5] = /*TMS Slot*/ _Jtag.TST;
1514 DMA_TMSL_TDIL[6] = /*TMS Slot*/ _Jtag.TST;
1515 DMA_TMSL_TDIL[7] = /*TMS Slot*/ _Jtag.TST;
1516 DMA_TMSL_TDIL[8] = /*TMS Slot*/ _Jtag.TST;
1517 DMA_TMSL_TDIL[9] = /*TMS Slot*/ _Jtag.TST;
1518 DMA_TMSL_TDIL[10] = /*TMS Slot*/ _Jtag.TST;
1519 DMA_TMSL_TDIL[11] = /*TMS Slot*/ _Jtag.TST;
1520 DMA_TMSL_TDIL[12] = /*TMS Slot*/ _Jtag.TST;
1521 DMA_TMSL_TDIL[13] = /*TMS Slot*/ _Jtag.TST;
1522 DMA_TMSL_TDIL[14] = /*TMS Slot*/ _Jtag.TST;
1523 DMA_TMSL_TDIL[15] = /*TMS Slot*/ _Jtag.TST;
1524 DMA_TMSL_TDIL[16] = /*TMS Slot*/ 0;
1525 DMA_TMSL_TDIL[17] = /*TMS Slot*/ 0;
1526 DMA_TMSL_TDIL[18] = /*TMS Slot*/ 0;
1527 DMA_TMSL_TDIL[19] = /*TMS Slot*/ 0;
1528 DMA_TMSL_TDIL[20] = /*TMS Slot*/ 0;
1529 DMA_TMSL_TDIL[21] = /*TMS Slot*/ 0;
1530 DMA_TMSL_TDIL[22] = /*TMS Slot*/ 0;
1531 DMA_TMSL_TDIL[23] = /*TMS Slot*/ 0;
1532 DMA_TMSL_TDIL[24] = /*TMS Slot*/ 0;
1533 DMA_TMSL_TDIL[25] = /*TMS Slot*/ 0;
1534 DMA_TMSL_TDIL[26] = /*TMS Slot*/ _Jtag.TST;
1535 DMA_TMSL_TDIL[27] = /*TMS Slot*/ _Jtag.TST;
1536 DMA_TMSL_TDIL[28]= /*TMS Slot*/ _Jtag.TST;
1537 DMA_TMSL_TDIL[29] = /*TMS Slot*/ _Jtag.TST;
1538 DMA_TMSL_TDIL[30] = /*TMS Slot*/ _Jtag.TST;
1539 DMA_TMSL_TDIL[31] = /*TMS Slot*/ _Jtag.TST;
1540 DMA_TMSL_TDIL[32] = /*TMS Slot*/ _Jtag.TST;
1541 DMA_TMSL_TDIL[33] = /*TMS Slot*/ _Jtag.TST;
1542 DMA_TMSL_TDIL[34] = /*TMS Slot*/ _Jtag.TST;
1543 DMA_TMSL_TDIL[35] = /*TMS Slot*/ _Jtag.TST;
1544 DMA_TMSL_TDIL[36]= /*TMS Slot*/ _Jtag.TST;
1545 DMA_TMSL_TDIL[37] = /*TMS Slot*/ _Jtag.TST;
1546 DMA_TMSL_TDIL[38] = /*TMS Slot*/ _Jtag.TST;
1547 DMA_TMSL_TDIL[39] = /*TMS Slot*/ _Jtag.TST;
1548 DMA_TMSL_TDIL[40] = /*TMS Slot*/ _Jtag.TST;
1549 DMA_TMSL_TDIL[41] = /*TMS Slot*/ _Jtag.TST;
1550
1551 DMA_TMSL_TDIL[42] = /*TDI Slot*/ _Jtag.TST;
1552 DMA_TMSL_TDIL[43] = /*TDI Slot*/ _Jtag.TST;
1553 DMA_TMSL_TDIL[44] = /*TDI Slot*/ _Jtag.TST;
1554 DMA_TMSL_TDIL[45] = /*TDI Slot*/ _Jtag.TST;
1555 DMA_TMSL_TDIL[46] = /*TDI Slot*/ _Jtag.TST;
1556 DMA_TMSL_TDIL[47] = /*TDI Slot*/ _Jtag.TST;
1557 DMA_TMSL_TDIL[48] = /*TDI Slot*/ _Jtag.TST;
1558 DMA_TMSL_TDIL[49] = /*TDI Slot*/ _Jtag.TST;
1559 DMA_TMSL_TDIL[50] = /*TDI Slot*/ _Jtag.TST;
1560 DMA_TMSL_TDIL[51] = /*TDI Slot*/ _Jtag.TST;
1561 DMA_TMSL_TDIL[52] = /*TDI Slot*/ _Jtag.TST;
1562 DMA_TMSL_TDIL[53] = /*TDI Slot*/ _Jtag.TST;
1563 DMA_TMSL_TDIL[54] = /*TDI Slot*/ _Jtag.TST;
1564 DMA_TMSL_TDIL[55] = /*TDI Slot*/ _Jtag.TST;
1565 DMA_TMSL_TDIL[56] = /*TDI Slot*/ _Jtag.TST;
1566 DMA_TMSL_TDIL[57] = /*TDI Slot*/ _Jtag.TST;
1567 DMA_TMSL_TDIL[58] = /*TDI Slot*/ 0;
1568 DMA_TMSL_TDIL[59] = /*TDI Slot*/ 0;
1569 DMA_TMSL_TDIL[60] = /*TDI Slot*/ 0;
1570 DMA_TMSL_TDIL[61] = /*TDI Slot*/ 0;
1571 DMA_TMSL_TDIL[62] = /*TDI Slot*/ 0;
1572 DMA_TMSL_TDIL[63] = /*TDI Slot*/ 0;
1573 DMA_TMSL_TDIL[64] = /*TDI Slot*/ 0;
1574 DMA_TMSL_TDIL[65] = /*TDI Slot*/ 0;
1575 DMA_TMSL_TDIL[66] = /*TDI Slot*/ 0;
1576 DMA_TMSL_TDIL[67] = /*TDI Slot*/ 0;
1577 DMA_TMSL_TDIL[68] = /*TDI Slot*/ _Jtag.TST;
1578 DMA_TMSL_TDIL[69] = /*TDI Slot*/ _Jtag.TST;
1579 DMA_TMSL_TDIL[70] = /*TDI Slot*/ _Jtag.TST;
1580 DMA_TMSL_TDIL[71] = /*TDI Slot*/ _Jtag.TST;
1581 DMA_TMSL_TDIL[72] = /*TDI Slot*/ _Jtag.TST;
1582 DMA_TMSL_TDIL[73] = /*TDI Slot*/ _Jtag.TST;
1583 DMA_TMSL_TDIL[74] = /*TDI Slot*/ _Jtag.TST;
1584 DMA_TMSL_TDIL[75] = /*TDI Slot*/ _Jtag.TST;
1585 DMA_TMSL_TDIL[76] = /*TDI Slot*/ _Jtag.TST;
1586 DMA_TMSL_TDIL[77] = /*TDI Slot*/ _Jtag.TST;
1587 DMA_TMSL_TDIL[78] = /*TDI Slot*/ _Jtag.TST;
1588 DMA_TMSL_TDIL[79] = /*TDI Slot*/ _Jtag.TST;
1589 DMA_TMSL_TDIL[80] = /*TDI Slot*/ _Jtag.TST;
1590 DMA_TMSL_TDIL[81] = /*TDI Slot*/ _Jtag.TST;
1591 DMA_TMSL_TDIL[82] = /*TDI Slot*/ _Jtag.TST;
1592 DMA_TMSL_TDIL[83] = /*TDI Slot*/ _Jtag.TST;
1593 break;
1594 }//---------------------------------------------------------------------
1595 default:// fastes SBW2 speed
1596 {
1597 DMA1SZ = 8; // load DMA1 with size
1598 DMA2SZ = 8; // load DMA1 with size
1599 DMA_TMSH_TDIH[0] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1600 DMA_TMSH_TDIH[1] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1601 DMA_TMSH_TDIH[2] = /*TMS Slot*/ _Jtag.RST;
1602 DMA_TMSH_TDIH[3] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1603
1604 DMA_TMSH_TDIH[4] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1605 DMA_TMSH_TDIH[5] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1606 DMA_TMSH_TDIH[6] = /*TDI Slot*/ _Jtag.RST;
1607 DMA_TMSH_TDIH[7] = /*TDI Slot*/ _Jtag.RST|_Jtag.TST;
1608
1609 DMA_TMSH_TDIL[0] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1610 DMA_TMSH_TDIL[1] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1611 DMA_TMSH_TDIL[2] = /*TMS Slot*/ _Jtag.RST;
1612 DMA_TMSH_TDIL[3] = /*TMS Slot*/ _Jtag.RST|_Jtag.TST;
1613
1614 DMA_TMSH_TDIL[4] = /*TDI Slot*/ _Jtag.TST;
1615 DMA_TMSH_TDIL[5] = /*TDI Slot*/ _Jtag.TST;
1616 DMA_TMSH_TDIL[6] = /*TDI Slot*/ 0;
1617 DMA_TMSH_TDIL[7] = /*TDI Slot*/ _Jtag.TST;
1618
1619 DMA_TMSL_TDIH[0] = /*TMS Slot*/ _Jtag.TST;
1620 DMA_TMSL_TDIH[1] = /*TMS Slot*/ _Jtag.TST;
1621 DMA_TMSL_TDIH[2] = /*TMS Slot*/ 0;
1622 DMA_TMSL_TDIH[3] = /*TMS Slot*/ _Jtag.TST;
1623
1624 DMA_TMSL_TDIH[4] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1625 DMA_TMSL_TDIH[5] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1626 DMA_TMSL_TDIH[6] = /*TDI SLot*/ _Jtag.RST;
1627 DMA_TMSL_TDIH[7] = /*TDI SLot*/ _Jtag.RST|_Jtag.TST;
1628
1629 DMA_TMSL_TDIL[0] = /*TMS Slot*/ _Jtag.TST;
1630 DMA_TMSL_TDIL[1] = /*TMS Slot*/ _Jtag.TST;
1631 DMA_TMSL_TDIL[2] = /*TMS Slot*/ 0;
1632 DMA_TMSL_TDIL[3] = /*TMS Slot*/ _Jtag.TST;
1633
1634 DMA_TMSL_TDIL[4] = /*TDI Slot*/ _Jtag.TST;
1635 DMA_TMSL_TDIL[5] = /*TDI Slot*/ _Jtag.TST;
1636 DMA_TMSL_TDIL[6] = /*TDI Slot*/ 0;
1637 DMA_TMSL_TDIL[7] = /*TDI Slot*/ _Jtag.TST;
1638 break;
1639 }//---------------------------------------------------------------------
1640 }
1641 }
1642
1643 #ifdef MSP_FET
1644 extern unsigned char _hil_generic_Instr(unsigned char Instruction);
1645 extern unsigned char _hil_generic_SetReg_XBits08(unsigned char Data);
1646 extern unsigned short _hil_generic_SetReg_XBits16(unsigned short Data);
1647 extern unsigned long _hil_generic_SetReg_XBits20(unsigned long Data);
1648 extern unsigned long _hil_generic_SetReg_XBits32(unsigned long Data);
1649
1650 extern unsigned char lastTestState;
1651 extern unsigned char lastResetState;
1652 extern short _hil_SetVcc(unsigned short Vcc);
1653
1654 #endif
1655
1656 #pragma optimize = medium
1657 // -----------------------------------------------------------------------------
_hil_2w_BlowFuse_Dma(unsigned char targetHasTestVpp)1658 short _hil_2w_BlowFuse_Dma(unsigned char targetHasTestVpp)
1659 {
1660 #ifdef MSP_FET
1661 if (protocol_id != SPYBIWIRE_SUBMCU)
1662 {
1663 unsigned char MSB = 0x80;;
1664 unsigned char Data = IR_EX_BLOW, i = 0;
1665
1666 //_hil_SetVcc(2500);
1667 _hil_generic_Instr(IR_PREPARE_BLOW);
1668
1669 _DINT_FET();
1670 lastResetState = 1;
1671 lastTestState = 1;
1672 hil_fpga_enable_bypass();
1673
1674 // JTAG FSM state = Run-Test/Idle
1675 TMSH_DMA(); TDIH_DMA(); TDOsbwFuse();
1676
1677 // JTAG FSM state = Select DR-Scan
1678 TMSH_DMA(); TDIH_DMA(); TDOsbwFuse();
1679
1680 // JTAG FSM state = Select IR-Scan
1681 TMSL_DMA(); TDIH_DMA(); TDOsbwFuse();
1682
1683 // JTAG FSM state = Capture-IR
1684 TMSL_DMA(); TDIH_DMA(); TDOsbwFuse();
1685
1686 for (i = 8; i > 1; i--)
1687 {
1688 if((Data & MSB) == 0)
1689 {
1690 TMSL_DMA(); TDIL_DMA(); TDO_RD_FUSE();
1691 }
1692 else
1693 {
1694 TMSL_DMA(); TDIH_DMA(); TDO_RD_FUSE();
1695 }
1696 Data <<= 1;
1697 }
1698 // last bit requires TMS=1; TDO one bit before TDI
1699 if((Data & MSB) == 0)
1700 {
1701 TMSH_DMA(); TDIL_DMA(); TDO_RD_FUSE();
1702 }
1703 else
1704 {
1705 TMSH_DMA(); TDIH_DMA(); TDO_RD_FUSE();
1706 }
1707 // SBWTDIO must be low on exit!
1708 TMSH_DMA(); TDIL_DMA(); TDOsbwFuse();
1709
1710 TMSL_DMA(); TDIL_DMA(); TDOsbwFuse();
1711 // instruction shift done!
1712
1713 // After the IR_EX_BLOW instruction is shifted in via SBW, one more TMS_SLOT must be performed
1714 // create TMSL slot
1715
1716 (*_Jtag.Out) &= ~_Jtag.RST;
1717 SBW_DELAY; SBW_DELAY;
1718 SBW_DELAY; SBW_DELAY;
1719
1720 (*_Jtag.Out) &= ~_Jtag.TST;
1721 SBW_DELAY; SBW_DELAY;
1722 SBW_DELAY; SBW_DELAY;
1723
1724 (*_Jtag.Out) |= _Jtag.TST;
1725 _hil_Delay_1ms(1);
1726
1727 // Apply fuse blow voltage
1728 setVpp(1);
1729
1730 // Taking SBWTDIO high as soon as Vpp has been settled blows the fuse
1731 (*_Jtag.Out) |= _Jtag.RST;
1732
1733 _hil_Delay_1ms(1);
1734
1735 setVpp(0); // switch VPP off
1736
1737 hil_fpga_disable_bypass();
1738
1739 // now perform a BOR via JTAG - we loose control of the device then...
1740 _hil_generic_Instr(IR_TEST_REG);
1741 _hil_generic_SetReg_XBits32(0x00000200);
1742
1743 _EINT_FET();
1744 }
1745 #endif
1746 // not suppored by eZ-FET
1747 return 0;
1748 }
1749 /* EOF */
1750