1 /* 2 * Copyright (C) 2007 - 2014 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the 15 * distribution. 16 * 17 * Neither the name of Texas Instruments Incorporated nor the names of 18 * its contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include "msp430.h" 35 #define uController_uif 36 37 #ifndef _FPGA_ARCH_H_ 38 #define _FPGA_ARCH_H_ 39 // ------------------------------------------------------------------------------ 40 // FPGA 41 42 // RESET 43 #define FPGA_RESET_BIT ( BIT1 ) 44 #define FPGA_RESET_PORT_DIR ( P5DIR ) 45 #define FPGA_RESET_PORT_OUT ( P5OUT ) 46 #define FPGA_RESET_ASSERT { FPGA_RESET_PORT_OUT &= ~FPGA_RESET_BIT; } 47 #define FPGA_RESET_DEASSERT { FPGA_RESET_PORT_OUT |= FPGA_RESET_BIT; } 48 49 #define TRIGGER_LA { P6OUT |= BIT7; __delay_cycles(10); P6OUT &= ~BIT7; } 50 #define TRIGGER_ONCE { P6OUT ^= BIT7; } 51 52 // DCDC output to target VCC 53 #define DCDC_VCC_BIT ( BIT7 ) 54 #define DCDC_VCC_PORT_OUT ( P8OUT ) 55 #define DCDC_VCC_ENABLE { DCDC_VCC_PORT_OUT |= DCDC_VCC_BIT; } 56 #define DCDC_VCC_DISABLE { DCDC_VCC_PORT_OUT &= ~DCDC_VCC_BIT; } 57 58 // DT voltage to target VCC 59 #define DT_VCC_BIT ( BIT6 ) 60 #define DT_VCC_PORT_OUT ( P9OUT ) 61 #define DT_VCC_ENABLE { DT_VCC_PORT_OUT |= DT_VCC_BIT; } 62 #define DT_VCC_DISABLE { DT_VCC_PORT_OUT &= ~DT_VCC_BIT; } 63 64 // DT voltage to level shifters 65 #define DT_SIGNALS_BIT ( BIT0 ) 66 #define DT_SIGNALS_PORT_OUT ( P8OUT ) 67 #define DT_SIGNALS_ENABLE { DT_SIGNALS_PORT_OUT |= DT_SIGNALS_BIT; } 68 #define DT_SIGNALS_DISABLE { DT_SIGNALS_PORT_OUT &= ~DT_SIGNALS_BIT; } 69 70 // SYS_CLK 71 #define FPGA_SYS_CLK_BIT ( BIT7 ) 72 #define FPGA_SYS_CLK_PORT_DIR ( P2DIR ) 73 #define FPGA_SYS_CLK_PORT_SEL ( P2SEL ) 74 #define FPGA_SYS_CLK_START { FPGA_SYS_CLK_PORT_SEL |= FPGA_SYS_CLK_BIT; } 75 #define FPGA_SYS_CLK_STOP { FPGA_SYS_CLK_PORT_SEL &= ~FPGA_SYS_CLK_BIT; } 76 77 // WR_TRIG 78 #define FPGA_WR_TRIG_BIT ( BIT6 ) 79 #define FPGA_WR_TRIG_PORT_DIR ( P2DIR ) 80 #define FPGA_WR_TRIG_PORT_OUT ( P2OUT ) 81 82 // RD_TRIG 83 #define FPGA_RD_TRIG_BIT ( BIT6 ) 84 #define FPGA_RD_TRIG_PORT_DIR ( P5DIR ) 85 #define FPGA_RD_TRIG_PORT_IN ( P5IN ) 86 #define FPGA_RD_TRIG_IS_ASSERTED ( FPGA_RD_TRIG_PORT_IN & FPGA_RD_TRIG_BIT ) 87 88 // CMD 89 #define FPGA_CMD_BITS ( BIT2 + BIT3 + BIT4 + BIT5 ) 90 #define FPGA_CMD_PORT_DIR ( P2DIR ) 91 #define FPGA_CMD_PORT_OUT ( P2OUT ) 92 93 // DATA0 94 #define FPGA_DATA0_BITS ( 0xFF ) 95 #define FPGA_DATA0_PORT_DIR ( P1DIR ) 96 #define FPGA_DATA0_PORT_IN ( P1IN ) 97 #define FPGA_DATA0_PORT_OUT ( P1OUT ) 98 99 // CMD, DATA0, WR_TRIG 100 #define FPGA_CMD_DATA0_PORT_OUT ( PAOUT ) 101 102 // DATA1 103 #define FPGA_DATA1_BITS ( 0xFFFF ) 104 #define FPGA_DATA1_PORT_DIR ( PBDIR ) 105 #define FPGA_DATA1_PORT_IN ( PBIN ) 106 #define FPGA_DATA1_PORT_OUT ( PBOUT ) 107 108 // IO_DIR 109 #define FPGA_IO_DIR_BIT ( BIT1 ) 110 #define FPGA_IO_DIR_PORT_DIR ( P8SEL ) 111 #define FPGA_IO_DIR_PORT_OUT ( P8OUT ) 112 113 // UART_TXD / UART_TXD (MSP-FET RXD input, JTAG.12) 114 #define FPGA_UART_TXD_BIT ( BIT3 ) 115 #define FPGA_UART_TXD_PORT_SEL ( P8SEL ) 116 117 // UART_RXD / UART_RXD (MSP-FET TXD output, JTAG.14) 118 #define FPGA_UART_RXD_BIT ( BIT2 ) 119 #define FPGA_UART_RXD_PORT_SEL ( P8SEL ) 120 #define FPGA_UART_RXD_PORT_OUT ( P8OUT ) 121 #define FPGA_UART_RXD_HIGH { FPGA_UART_RXD_PORT_OUT |= FPGA_UART_RXD_BIT; } 122 #define FPGA_UART_RXD_LOW { FPGA_UART_RXD_PORT_OUT &= ~FPGA_UART_RXD_BIT; } 123 124 // UART_CTS / UART_CTS (MSP-FET "clear to send" output, JTAG.10) 125 #define FPGA_UART_CTS_BIT ( BIT5 ) 126 #define FPGA_UART_CTS_PORT_DIR ( P9DIR ) 127 #define FPGA_UART_CTS_PORT_OUT ( P9OUT ) 128 #define FPGA_UART_CTS_HIGH { FPGA_UART_CTS_PORT_OUT |= FPGA_UART_CTS_BIT; } 129 #define FPGA_UART_CTS_LOW { FPGA_UART_CTS_PORT_OUT &= ~FPGA_UART_CTS_BIT; } 130 131 // UART_RTR / UART_RTR (MSP-FET "ready to receive" input, JTAG.13) 132 #define FPGA_UART_RTR_BIT ( BIT1 ) 133 #define FPGA_UART_RTR_PORT_DIR ( P2DIR ) 134 #define FPGA_UART_RTR_PORT_IN ( P2IN ) 135 #define FPGA_UART_RTR_IS_HIGH ( FPGA_UART_RTR_PORT_IN & FPGA_UART_RTR_BIT ) 136 137 // JTAG signals in bypass mode 138 #define FPGA_BYPASS_DIR_CTRL_TEST_BIT ( BIT5 ) 139 #define FPGA_BYPASS_DIR_CTRL_RST_BIT ( BIT4 ) 140 #define FPGA_BYPASS_DIR_CTRL_TDO_BIT ( BIT3 ) 141 #define FPGA_BYPASS_DIR_CTRL_TDI_BIT ( BIT2 ) 142 #define FPGA_BYPASS_DIR_CTRL_TMS_BIT ( BIT1 ) 143 #define FPGA_BYPASS_DIR_CTRL_TCK_BIT ( BIT0 ) 144 #define FPGA_BYPASS_DIR_CTRL_PORT_DIR ( P4DIR ) 145 #define FPGA_BYPASS_DIR_CTRL_PORT_OUT ( P4OUT ) 146 #define FPGA_BYPASS_DIR_CTRL_PORT_IN ( P4IN ) 147 148 #define FPGA_BYPASS_TEST_BIT ( BIT5 ) 149 #define FPGA_BYPASS_RST_BIT ( BIT4 ) 150 #define FPGA_BYPASS_TDO_BIT ( BIT3 ) 151 #define FPGA_BYPASS_TDI_BIT ( BIT2 ) 152 #define FPGA_BYPASS_TMS_BIT ( BIT1 ) 153 #define FPGA_BYPASS_TCK_BIT ( BIT0 ) 154 #define FPGA_BYPASS_JTAG_PORT_DIR ( P3DIR ) 155 #define FPGA_BYPASS_JTAG_PORT_OUT ( P3OUT ) 156 #define FPGA_BYPASS_JTAG_PORT_IN ( P3IN ) 157 158 #define FPGA_BYPASS_TEST_HIGH { FPGA_BYPASS_JTAG_SBW_PORT_OUT |= FPGA_BYPASS_TEST_BIT; } 159 #define FPGA_BYPASS_TEST_LOW { FPGA_BYPASS_JTAG_SBW_PORT_OUT &= ~FPGA_BYPASS_TEST_BIT; } 160 #define FPGA_BYPASS_RST_HIGH { FPGA_BYPASS_JTAG_SBW_PORT_OUT |= FPGA_BYPASS_RST_BIT; } 161 #define FPGA_BYPASS_RST_LOW { FPGA_BYPASS_JTAG_SBW_PORT_OUT &= ~FPGA_BYPASS_RST_BIT; } 162 #define FPGA_BYPASS_TDI_HIGH { FPGA_BYPASS_JTAG_SBW_PORT_OUT |= FPGA_BYPASS_TDI_BIT; } 163 #define FPGA_BYPASS_TDI_LOW { FPGA_BYPASS_JTAG_SBW_PORT_OUT &= ~FPGA_BYPASS_TDI_BIT; } 164 #define FPGA_BYPASS_TMS_HIGH { FPGA_BYPASS_JTAG_SBW_PORT_OUT |= FPGA_BYPASS_TMS_BIT; } 165 #define FPGA_BYPASS_TMS_LOW { FPGA_BYPASS_JTAG_SBW_PORT_OUT &= ~FPGA_BYPASS_TMS_BIT; } 166 #define FPGA_BYPASS_TCK_HIGH { FPGA_BYPASS_JTAG_SBW_PORT_OUT |= FPGA_BYPASS_TCK_BIT; } 167 #define FPGA_BYPASS_TCK_LOW { FPGA_BYPASS_JTAG_SBW_PORT_OUT &= ~FPGA_BYPASS_TCK_BIT; } 168 #define FPGA_BYPASS_TDO_IS_ASSERTED ( FPGA_BYPASS_JTAG_SBW_PORT_IN & FPGA_BYPASS_TDO_BIT ) 169 170 // UART direction signals in bypass mode 171 #define FPGA_BYPASS_DIR_CTRL_UART_RTR_BIT ( BIT7 ) 172 #define FPGA_BYPASS_DIR_CTRL_UART_CTS_BIT ( BIT6 ) 173 #define FPGA_BYPASS_DIR_CTRL_UART_RXD_BIT ( BIT5 ) 174 #define FPGA_BYPASS_DIR_CTRL_UART_TXD_BIT ( BIT4 ) 175 //#define FPGA_BYPASS_DIR_CTRL_PORT_OUT ( P1OUT ) 176 177 // UART data signals in bypass mode 178 #define FPGA_BYPASS_UART_RTR_BIT ( BIT1 ) 179 #define FPGA_BYPASS_UART_RTR_PORT_DIR ( P2DIR) 180 #define FPGA_BYPASS_UART_RTR_PORT_OUT ( P2OUT ) 181 #define FPGA_BYPASS_UART_CTS_BIT ( BIT5 ) 182 #define FPGA_BYPASS_UART_CTS_PORT_DIR ( P9DIR ) 183 #define FPGA_BYPASS_UART_CTS_PORT_OUT ( P9OUT ) 184 #define FPGA_BYPASS_UART_RXD_BIT ( BIT2 ) 185 #define FPGA_BYPASS_UART_RXD_PORT_DIR ( P8DIR ) 186 #define FPGA_BYPASS_UART_RXD_PORT_OUT ( P8OUT ) 187 #define FPGA_BYPASS_UART_TXD_BIT ( BIT3 ) 188 #define FPGA_BYPASS_UART_TXD_PORT_DIR ( P8DIR ) 189 #define FPGA_BYPASS_UART_TXD_PORT_OUT ( P8OUT ) 190 191 // FPGA commands 192 #define FPGA_CMD_CFG 0x00 193 #define FPGA_CMD_IR8_RD 0x01 194 #define FPGA_CMD_IR8 0x02 195 #define FPGA_CMD_IR4_RD 0x03 196 #define FPGA_CMD_IR4 0x04 197 #define FPGA_CMD_DR8_RD 0x05 198 #define FPGA_CMD_DR8 0x06 199 #define FPGA_CMD_DRX_RD 0x07 200 #define FPGA_CMD_DRX 0x08 201 #define FPGA_CMD_DRX0_RD 0x09 202 #define FPGA_CMD_BYPASS 0x0A 203 #define FPGA_CMD_RESET 0x0B 204 #define FPGA_CMD_ABORT 0x0C 205 #define FPGA_CMD_VERSION 0x0D 206 #define FPGA_CMD_CJTAG 0x0E 207 208 // FPGA cJTAG commands 209 #define FPGA_CJTAG_ZBS 0x00 210 #define FPGA_CJTAG_TCKIDLE 0x01 211 212 // Config Parameters 213 //FPGA registers 214 #define REG_RESPONSE_HANDSHAKE_OFF 0x00 215 #define REG_PROTOCOL 0x01 216 #define REG_IRSCAN_PREAMBLE 0x02 217 #define REG_IRSCAN_POSTAMBLE 0x03 218 #define REG_DRSCAN_PREAMBLE 0x04 219 #define REG_DRSCAN_POSTAMBLE 0x05 220 #define REG_TEST_CLK_FREQUENCY 0x06 221 #define REG_TARGET_IO_CONFIGURATION 0x07 222 #define REG_TCLKset0 0x08 223 #define REG_TCLKset1 0x09 224 #define REG_TCLK_CLK_FREQUENCY 0x0a 225 #define REG_START_FIFO 0x0b 226 #define REG_STOP_FIFO 0x0c 227 #define REG_JTAG_4_WIRE_FPGA_432 0x0D 228 229 #define JTAG_4_WIRE_FPGA 0 230 #define SBW_2_MSP_FET_FPGA 2 231 #define SBW_2_BACK_FPGA 1 232 #define TDI_TO_TDO_FPGA 3 233 #define TRI_STATE_FPGA_JTAG 4 234 #define TRI_STATE_FPGA_SBW 5 235 236 237 // PORTA bits 238 typedef union 239 { 240 // Bit control 241 struct 242 { 243 unsigned char DATA0 : 8; 244 unsigned char UCA0TXD : 1; 245 unsigned char UCA0RXD : 1; 246 unsigned char CMD : 4; 247 unsigned char WR_TRIG : 1; 248 unsigned char RESERVED1 : 1; 249 } bit; 250 251 // Bypass control 252 struct 253 { 254 unsigned char IO_GPIO0 : 1; 255 unsigned char IO_GPIO1 : 1; 256 unsigned char RESERVED0 : 2; 257 unsigned char DIR_CTRL_GPIO0 : 1; 258 unsigned char DIR_CTRL_GPIO1 : 1; 259 unsigned char DIR_CTRL_GPIO2 : 1; 260 unsigned char DIR_CTRL_GPIO3 : 1; 261 unsigned char IO_GPIO2 : 1; 262 unsigned char IO_GPIO3 : 1; 263 unsigned char RESERVED1 : 6; 264 } byp; 265 266 // 16-bit access 267 unsigned int all; 268 269 } s_FPGA_PA; 270 271 // PORTB bits 272 typedef union 273 { 274 // Bypass control 275 struct 276 { 277 unsigned char IO_TCK : 1; 278 unsigned char IO_TMS : 1; 279 unsigned char IO_TDI : 1; 280 unsigned char IO_TDO : 1; 281 unsigned char IO_RST : 1; 282 unsigned char IO_TEST : 1; 283 unsigned char RESERVED0 : 2; 284 unsigned char DIR_CTRL_TCK : 1; 285 unsigned char DIR_CTRL_TMS : 1; 286 unsigned char DIR_CTRL_TDI : 1; 287 unsigned char DIR_CTRL_TDO : 1; 288 unsigned char DIR_CTRL_RST : 1; 289 unsigned char DIR_CTRL_TEST : 1; 290 unsigned char RESERVED1 : 2; 291 } byp; 292 293 // 16-bit access 294 unsigned int all; 295 296 } s_FPGA_PB; 297 298 #endif 299