1`default_nettype none 2 3module wtf( 4 input clk_12, 5 output fast 6); 7 8wire clk_216; 9 10ice40_pll_12_216 pll( 11 .clock_in(clk_12), 12 .clock_out(clk_216) 13); 14 15assign fast = clk_216; 16 17endmodule 18