1#
2# script for Nordic nRF51 series, a Cortex-M0 chip
3#
4
5source [find target/swj-dp.tcl]
6
7if { [info exists CHIPNAME] } {
8   set _CHIPNAME $CHIPNAME
9} else {
10   set _CHIPNAME nrf51
11}
12
13if { [info exists ENDIAN] } {
14   set _ENDIAN $ENDIAN
15} else {
16   set _ENDIAN little
17}
18
19# Work-area is a space in RAM used for flash programming
20# By default use 16kB
21if { [info exists WORKAREASIZE] } {
22   set _WORKAREASIZE $WORKAREASIZE
23} else {
24   set _WORKAREASIZE 0x4000
25}
26
27if { [info exists CPUTAPID] } {
28   set _CPUTAPID $CPUTAPID
29} else {
30   set _CPUTAPID 0x0bb11477
31}
32
33swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
34dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
35
36set _TARGETNAME $_CHIPNAME.cpu
37target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
38
39$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
40
41if {![using_hla]} {
42   # The chip supports standard ARM/Cortex-M0 SYSRESETREQ signal
43   cortex_m reset_config sysresetreq
44}
45
46flash bank $_CHIPNAME.flash nrf51 0x00000000 0 1 1 $_TARGETNAME
47flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME
48
49#
50#  The chip should start up from internal 16Mhz RC, so setting adapter
51#  clock to 1Mhz should be OK
52#
53adapter speed 1000
54
55proc enable_all_ram {} {
56	# nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks
57	# are reliably enabled after reset on some revisions (contrary to spec.) So after
58	# resetting we enable all banks via the RAMON register
59	mww 0x40000524 0xF
60}
61$_TARGETNAME configure -event reset-end {  enable_all_ram }
62