1 /**
2 ******************************************************************************
3 * @file stm32l1xx_ll_dac.h
4 * @author MCD Application Team
5 * @version V1.2.0
6 * @date 01-July-2016
7 * @brief Header file of DAC LL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32L1xx_LL_DAC_H
40 #define __STM32L1xx_LL_DAC_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32l1xx.h"
48
49 /** @addtogroup STM32L1xx_LL_Driver
50 * @{
51 */
52
53 #if defined (DAC1)
54
55 /** @defgroup DAC_LL DAC
56 * @{
57 */
58
59 /* Private types -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61
62 /* Private constants ---------------------------------------------------------*/
63 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
64 * @{
65 */
66
67 /* Internal masks for DAC channels definition */
68 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
69 /* - channel bits position into register CR */
70 /* - channel bits position into register SWTRIG */
71 /* - channel register offset of data holding register DHRx */
72 /* - channel register offset of data output register DORx */
73 #define DAC_CR_CH1_BITOFFSET ((uint32_t) 0U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
74 #define DAC_CR_CH2_BITOFFSET ((uint32_t)16U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
75 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
76
77 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
78 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
79 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
80
81 #define DAC_REG_DHR12R1_REGOFFSET ((uint32_t)0x00000000U) /* Register DHR12Rx channel 1 taken as reference */
82 #define DAC_REG_DHR12L1_REGOFFSET ((uint32_t)0x00100000U) /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
83 #define DAC_REG_DHR8R1_REGOFFSET ((uint32_t)0x02000000U) /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
84 #define DAC_REG_DHR12R2_REGOFFSET ((uint32_t)0x00030000U) /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
85 #define DAC_REG_DHR12L2_REGOFFSET ((uint32_t)0x00400000U) /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
86 #define DAC_REG_DHR8R2_REGOFFSET ((uint32_t)0x05000000U) /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
87 #define DAC_REG_DHR12RX_REGOFFSET_MASK ((uint32_t)0x000F0000U)
88 #define DAC_REG_DHR12LX_REGOFFSET_MASK ((uint32_t)0x00F00000U)
89 #define DAC_REG_DHR8RX_REGOFFSET_MASK ((uint32_t)0x0F000000U)
90 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
91
92 #define DAC_REG_DOR1_REGOFFSET ((uint32_t)0x00000000U) /* Register DORx channel 1 taken as reference */
93 #define DAC_REG_DOR2_REGOFFSET ((uint32_t)0x10000000U)/* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
94 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
95
96 /* DAC registers bits positions */
97 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
98 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
99 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
100
101 /* Miscellaneous data */
102 #define DAC_DIGITAL_SCALE_12BITS ((uint32_t)4095U) /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
103
104 /**
105 * @}
106 */
107
108
109 /* Private macros ------------------------------------------------------------*/
110 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
111 * @{
112 */
113
114 /**
115 * @brief Driver macro reserved for internal use: isolate bits with the
116 * selected mask and shift them to the register LSB
117 * (shift mask on register position bit 0).
118 * @param __BITS__ Bits in register 32 bits
119 * @param __MASK__ Mask in register 32 bits
120 * @retval Bits in register 32 bits
121 */
122 #define __DAC_MASK_SHIFT(__BITS__, __MASK__) \
123 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
124
125 /**
126 * @brief Driver macro reserved for internal use: set a pointer to
127 * a register from a register basis from which an offset
128 * is applied.
129 * @param __REG__ Register basis from which the offset is applied.
130 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
131 * @retval Pointer to register address
132 */
133 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
134 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
135
136 /**
137 * @}
138 */
139
140
141 /* Exported types ------------------------------------------------------------*/
142 #if defined(USE_FULL_LL_DRIVER)
143 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
144 * @{
145 */
146
147 /**
148 * @brief Structure definition of some features of DAC instance.
149 */
150 typedef struct
151 {
152 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
153 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
154
155 This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
156
157 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
158 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
159
160 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
161
162 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
163 If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
164 If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
165 @note If waveform automatic generation mode is disabled, this parameter is discarded.
166
167 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
168
169 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
170 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
171
172 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
173
174 } LL_DAC_InitTypeDef;
175
176 /**
177 * @}
178 */
179 #endif /* USE_FULL_LL_DRIVER */
180
181 /* Exported constants --------------------------------------------------------*/
182 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
183 * @{
184 */
185
186 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
187 * @brief Flags defines which can be used with LL_DAC_ReadReg function
188 * @{
189 */
190 /* DAC channel 1 flags */
191 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
192
193 /* DAC channel 2 flags */
194 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
195 /**
196 * @}
197 */
198
199 /** @defgroup DAC_LL_EC_IT DAC interruptions
200 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
201 * @{
202 */
203 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
204 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
205 /**
206 * @}
207 */
208
209 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
210 * @{
211 */
212 #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
213 #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
214 /**
215 * @}
216 */
217
218 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
219 * @{
220 */
221 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
222 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
223 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
224 #define LL_DAC_TRIG_EXT_TIM6_TRGO ((uint32_t)0x00000000U) /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
225 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
226 #define LL_DAC_TRIG_EXT_TIM9_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */
227 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
228 /**
229 * @}
230 */
231
232 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
233 * @{
234 */
235 #define LL_DAC_WAVE_AUTO_GENERATION_NONE ((uint32_t)0x00000000U) /*!< DAC channel wave auto generation mode disabled. */
236 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
237 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
238 /**
239 * @}
240 */
241
242 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
243 * @{
244 */
245 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 ((uint32_t)0x00000000U) /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
246 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
247 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
248 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
249 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
250 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
251 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
252 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
253 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
254 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
255 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
256 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
257 /**
258 * @}
259 */
260
261 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
262 * @{
263 */
264 #define LL_DAC_TRIANGLE_AMPLITUDE_1 ((uint32_t)0x00000000U) /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
265 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
266 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
267 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
268 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
269 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
270 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
271 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
272 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
273 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
274 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
275 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
276 /**
277 * @}
278 */
279
280 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
281 * @{
282 */
283 #define LL_DAC_OUTPUT_BUFFER_ENABLE ((uint32_t)0x00000000U) /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
284 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
285 /**
286 * @}
287 */
288
289
290 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
291 * @{
292 */
293 #define LL_DAC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< DAC channel resolution 12 bits */
294 #define LL_DAC_RESOLUTION_8B ((uint32_t)0x00000002U) /*!< DAC channel resolution 8 bits */
295 /**
296 * @}
297 */
298
299 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
300 * @{
301 */
302 /* List of DAC registers intended to be used (most commonly) with */
303 /* DMA transfer. */
304 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
305 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
306 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
307 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */
308 /**
309 * @}
310 */
311
312 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
313 * @note Only DAC IP HW delays are defined in DAC LL driver driver,
314 * not timeout values.
315 * For details on delays values, refer to descriptions in source code
316 * above each literal definition.
317 * @{
318 */
319
320 /* Delay for DAC channel voltage settling time from DAC channel startup */
321 /* (transition from disable to enable). */
322 /* Note: DAC channel startup time depends on board application environment: */
323 /* impedance connected to DAC channel output. */
324 /* The delay below is specified under conditions: */
325 /* - voltage maximum transition (lowest to highest value) */
326 /* - until voltage reaches final value +-1LSB */
327 /* - DAC channel output buffer enabled */
328 /* - load impedance of 5kOhm (min), 50pF (max) */
329 /* Literal set to maximum value (refer to device datasheet, */
330 /* parameter "tWAKEUP"). */
331 /* Unit: us */
332 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US ((uint32_t) 15U) /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
333
334 /* Delay for DAC channel voltage settling time. */
335 /* Note: DAC channel startup time depends on board application environment: */
336 /* impedance connected to DAC channel output. */
337 /* The delay below is specified under conditions: */
338 /* - voltage maximum transition (lowest to highest value) */
339 /* - until voltage reaches final value +-1LSB */
340 /* - DAC channel output buffer enabled */
341 /* - load impedance of 5kOhm min, 50pF max */
342 /* Literal set to maximum value (refer to device datasheet, */
343 /* parameter "tSETTLING"). */
344 /* Unit: us */
345 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US ((uint32_t) 12U) /*!< Delay for DAC channel voltage settling time */
346 /**
347 * @}
348 */
349
350 /**
351 * @}
352 */
353
354 /* Exported macro ------------------------------------------------------------*/
355 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
356 * @{
357 */
358
359 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
360 * @{
361 */
362
363 /**
364 * @brief Write a value in DAC register
365 * @param __INSTANCE__ DAC Instance
366 * @param __REG__ Register to be written
367 * @param __VALUE__ Value to be written in the register
368 * @retval None
369 */
370 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
371
372 /**
373 * @brief Read a value in DAC register
374 * @param __INSTANCE__ DAC Instance
375 * @param __REG__ Register to be read
376 * @retval Register value
377 */
378 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
379
380 /**
381 * @}
382 */
383
384 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
385 * @{
386 */
387
388 /**
389 * @brief Helper macro to get DAC channel number in decimal format
390 * from literals LL_DAC_CHANNEL_x.
391 * Example:
392 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
393 * will return decimal number "1".
394 * @note The input can be a value from functions where a channel
395 * number is returned.
396 * @param __CHANNEL__ This parameter can be one of the following values:
397 * @arg @ref LL_DAC_CHANNEL_1
398 * @arg @ref LL_DAC_CHANNEL_2
399 * @retval 1...2
400 */
401 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
402 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
403
404 /**
405 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
406 * from number in decimal format.
407 * Example:
408 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
409 * will return a data equivalent to "LL_DAC_CHANNEL_1".
410 * @note If the input parameter does not correspond to a DAC channel,
411 * this macro returns value '0'.
412 * @param __DECIMAL_NB__ 1...2
413 * @retval Returned value can be one of the following values:
414 * @arg @ref LL_DAC_CHANNEL_1
415 * @arg @ref LL_DAC_CHANNEL_2
416 */
417 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
418 (((__DECIMAL_NB__) == 1U) \
419 ? ( \
420 LL_DAC_CHANNEL_1 \
421 ) \
422 : \
423 (((__DECIMAL_NB__) == 2U) \
424 ? ( \
425 LL_DAC_CHANNEL_2 \
426 ) \
427 : \
428 ( \
429 0 \
430 ) \
431 ) \
432 )
433
434 /**
435 * @brief Helper macro to define the DAC conversion data full-scale digital
436 * value corresponding to the selected DAC resolution.
437 * @note DAC conversion data full-scale corresponds to voltage range
438 * determined by analog voltage references Vref+ and Vref-
439 * (refer to reference manual).
440 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
441 * @arg @ref LL_DAC_RESOLUTION_12B
442 * @arg @ref LL_DAC_RESOLUTION_8B
443 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
444 */
445 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
446 (((uint32_t)0xFFFU) >> ((__DAC_RESOLUTION__) << 1U))
447
448 /**
449 * @brief Helper macro to calculate the DAC conversion data (unit: digital
450 * value) corresponding to a voltage (unit: mVolt).
451 * @note This helper macro is intended to provide input data in voltage
452 * rather than digital value,
453 * to be used with LL DAC functions such as
454 * @ref LL_DAC_ConvertData12RightAligned().
455 * @note Analog reference voltage (Vref+) must be either known from
456 * user board environment or can be calculated using ADC measurement
457 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
458 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
459 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
460 * (unit: mVolt).
461 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
462 * @arg @ref LL_DAC_RESOLUTION_12B
463 * @arg @ref LL_DAC_RESOLUTION_8B
464 * @retval DAC conversion data (unit: digital value)
465 */
466 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
467 __DAC_VOLTAGE__,\
468 __DAC_RESOLUTION__) \
469 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
470 / (__VREFANALOG_VOLTAGE__) \
471 )
472
473 /**
474 * @}
475 */
476
477 /**
478 * @}
479 */
480
481
482 /* Exported functions --------------------------------------------------------*/
483 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
484 * @{
485 */
486 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
487 * @{
488 */
489
490 /**
491 * @brief Set the conversion trigger source for the selected DAC channel.
492 * @note For conversion trigger source to be effective, DAC trigger
493 * must be enabled using function @ref LL_DAC_EnableTrigger().
494 * @note To set conversion trigger source, DAC channel must be disabled.
495 * Otherwise, the setting is discarded.
496 * @note Availability of parameters of trigger sources from timer
497 * depends on timers availability on the selected device.
498 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
499 * CR TSEL2 LL_DAC_SetTriggerSource
500 * @param DACx DAC instance
501 * @param DAC_Channel This parameter can be one of the following values:
502 * @arg @ref LL_DAC_CHANNEL_1
503 * @arg @ref LL_DAC_CHANNEL_2
504 * @param TriggerSource This parameter can be one of the following values:
505 * @arg @ref LL_DAC_TRIG_SOFTWARE
506 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
507 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
508 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
509 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
510 * @arg @ref LL_DAC_TRIG_EXT_TIM9_TRGO
511 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
512 * @retval None
513 */
LL_DAC_SetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriggerSource)514 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
515 {
516 MODIFY_REG(DACx->CR,
517 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
518 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
519 }
520
521 /**
522 * @brief Get the conversion trigger source for the selected DAC channel.
523 * @note For conversion trigger source to be effective, DAC trigger
524 * must be enabled using function @ref LL_DAC_EnableTrigger().
525 * @note Availability of parameters of trigger sources from timer
526 * depends on timers availability on the selected device.
527 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
528 * CR TSEL2 LL_DAC_GetTriggerSource
529 * @param DACx DAC instance
530 * @param DAC_Channel This parameter can be one of the following values:
531 * @arg @ref LL_DAC_CHANNEL_1
532 * @arg @ref LL_DAC_CHANNEL_2
533 * @retval Returned value can be one of the following values:
534 * @arg @ref LL_DAC_TRIG_SOFTWARE
535 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
536 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
537 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
538 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
539 * @arg @ref LL_DAC_TRIG_EXT_TIM9_TRGO
540 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
541 */
LL_DAC_GetTriggerSource(DAC_TypeDef * DACx,uint32_t DAC_Channel)542 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
543 {
544 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
545 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
546 );
547 }
548
549 /**
550 * @brief Set the waveform automatic generation mode
551 * for the selected DAC channel.
552 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
553 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
554 * @param DACx DAC instance
555 * @param DAC_Channel This parameter can be one of the following values:
556 * @arg @ref LL_DAC_CHANNEL_1
557 * @arg @ref LL_DAC_CHANNEL_2
558 * @param WaveAutoGeneration This parameter can be one of the following values:
559 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
560 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
561 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
562 * @retval None
563 */
LL_DAC_SetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t WaveAutoGeneration)564 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
565 {
566 MODIFY_REG(DACx->CR,
567 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
568 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
569 }
570
571 /**
572 * @brief Get the waveform automatic generation mode
573 * for the selected DAC channel.
574 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
575 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
576 * @param DACx DAC instance
577 * @param DAC_Channel This parameter can be one of the following values:
578 * @arg @ref LL_DAC_CHANNEL_1
579 * @arg @ref LL_DAC_CHANNEL_2
580 * @retval Returned value can be one of the following values:
581 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
582 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
583 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
584 */
LL_DAC_GetWaveAutoGeneration(DAC_TypeDef * DACx,uint32_t DAC_Channel)585 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
586 {
587 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
588 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
589 );
590 }
591
592 /**
593 * @brief Set the noise waveform generation for the selected DAC channel:
594 * Noise mode and parameters LFSR (linear feedback shift register).
595 * @note For wave generation to be effective, DAC channel
596 * wave generation mode must be enabled using
597 * function @ref LL_DAC_SetWaveAutoGeneration().
598 * @note This setting can be set when the selected DAC channel is disabled
599 * (otherwise, the setting operation is ignored).
600 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
601 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
602 * @param DACx DAC instance
603 * @param DAC_Channel This parameter can be one of the following values:
604 * @arg @ref LL_DAC_CHANNEL_1
605 * @arg @ref LL_DAC_CHANNEL_2
606 * @param NoiseLFSRMask This parameter can be one of the following values:
607 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
608 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
609 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
610 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
611 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
612 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
613 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
614 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
615 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
616 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
617 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
618 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
619 * @retval None
620 */
LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t NoiseLFSRMask)621 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
622 {
623 MODIFY_REG(DACx->CR,
624 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
625 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
626 }
627
628 /**
629 * @brief Set the noise waveform generation for the selected DAC channel:
630 * Noise mode and parameters LFSR (linear feedback shift register).
631 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
632 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
633 * @param DACx DAC instance
634 * @param DAC_Channel This parameter can be one of the following values:
635 * @arg @ref LL_DAC_CHANNEL_1
636 * @arg @ref LL_DAC_CHANNEL_2
637 * @retval Returned value can be one of the following values:
638 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
639 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
640 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
641 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
642 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
643 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
644 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
645 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
646 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
647 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
648 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
649 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
650 */
LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef * DACx,uint32_t DAC_Channel)651 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
652 {
653 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
654 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
655 );
656 }
657
658 /**
659 * @brief Set the triangle waveform generation for the selected DAC channel:
660 * triangle mode and amplitude.
661 * @note For wave generation to be effective, DAC channel
662 * wave generation mode must be enabled using
663 * function @ref LL_DAC_SetWaveAutoGeneration().
664 * @note This setting can be set when the selected DAC channel is disabled
665 * (otherwise, the setting operation is ignored).
666 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
667 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
668 * @param DACx DAC instance
669 * @param DAC_Channel This parameter can be one of the following values:
670 * @arg @ref LL_DAC_CHANNEL_1
671 * @arg @ref LL_DAC_CHANNEL_2
672 * @param TriangleAmplitude This parameter can be one of the following values:
673 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
674 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
675 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
676 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
677 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
678 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
679 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
680 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
681 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
682 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
683 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
684 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
685 * @retval None
686 */
LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t TriangleAmplitude)687 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
688 {
689 MODIFY_REG(DACx->CR,
690 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
691 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
692 }
693
694 /**
695 * @brief Set the triangle waveform generation for the selected DAC channel:
696 * triangle mode and amplitude.
697 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
698 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
699 * @param DACx DAC instance
700 * @param DAC_Channel This parameter can be one of the following values:
701 * @arg @ref LL_DAC_CHANNEL_1
702 * @arg @ref LL_DAC_CHANNEL_2
703 * @retval Returned value can be one of the following values:
704 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
705 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
706 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
707 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
708 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
709 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
710 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
711 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
712 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
713 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
714 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
715 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
716 */
LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef * DACx,uint32_t DAC_Channel)717 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
718 {
719 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
720 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
721 );
722 }
723
724 /**
725 * @brief Set the output buffer for the selected DAC channel.
726 * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
727 * CR BOFF2 LL_DAC_SetOutputBuffer
728 * @param DACx DAC instance
729 * @param DAC_Channel This parameter can be one of the following values:
730 * @arg @ref LL_DAC_CHANNEL_1
731 * @arg @ref LL_DAC_CHANNEL_2
732 * @param OutputBuffer This parameter can be one of the following values:
733 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
734 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
735 * @retval None
736 */
LL_DAC_SetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t OutputBuffer)737 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
738 {
739 MODIFY_REG(DACx->CR,
740 DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
741 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
742 }
743
744 /**
745 * @brief Get the output buffer state for the selected DAC channel.
746 * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
747 * CR BOFF2 LL_DAC_GetOutputBuffer
748 * @param DACx DAC instance
749 * @param DAC_Channel This parameter can be one of the following values:
750 * @arg @ref LL_DAC_CHANNEL_1
751 * @arg @ref LL_DAC_CHANNEL_2
752 * @retval Returned value can be one of the following values:
753 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
754 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
755 */
LL_DAC_GetOutputBuffer(DAC_TypeDef * DACx,uint32_t DAC_Channel)756 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
757 {
758 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
759 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
760 );
761 }
762
763 /**
764 * @}
765 */
766
767 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
768 * @{
769 */
770
771 /**
772 * @brief Enable DAC DMA transfer request of the selected channel.
773 * @note To configure DMA source address (peripheral address),
774 * use function @ref LL_DAC_DMA_GetRegAddr().
775 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
776 * CR DMAEN2 LL_DAC_EnableDMAReq
777 * @param DACx DAC instance
778 * @param DAC_Channel This parameter can be one of the following values:
779 * @arg @ref LL_DAC_CHANNEL_1
780 * @arg @ref LL_DAC_CHANNEL_2
781 * @retval None
782 */
LL_DAC_EnableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)783 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
784 {
785 SET_BIT(DACx->CR,
786 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
787 }
788
789 /**
790 * @brief Disable DAC DMA transfer request of the selected channel.
791 * @note To configure DMA source address (peripheral address),
792 * use function @ref LL_DAC_DMA_GetRegAddr().
793 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
794 * CR DMAEN2 LL_DAC_DisableDMAReq
795 * @param DACx DAC instance
796 * @param DAC_Channel This parameter can be one of the following values:
797 * @arg @ref LL_DAC_CHANNEL_1
798 * @arg @ref LL_DAC_CHANNEL_2
799 * @retval None
800 */
LL_DAC_DisableDMAReq(DAC_TypeDef * DACx,uint32_t DAC_Channel)801 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
802 {
803 CLEAR_BIT(DACx->CR,
804 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
805 }
806
807 /**
808 * @brief Get DAC DMA transfer request state of the selected channel.
809 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
810 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
811 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
812 * @param DACx DAC instance
813 * @param DAC_Channel This parameter can be one of the following values:
814 * @arg @ref LL_DAC_CHANNEL_1
815 * @arg @ref LL_DAC_CHANNEL_2
816 * @retval State of bit (1 or 0).
817 */
LL_DAC_IsDMAReqEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)818 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
819 {
820 return (READ_BIT(DACx->CR,
821 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
822 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
823 }
824
825 /**
826 * @brief Function to help to configure DMA transfer to DAC: retrieve the
827 * DAC register address from DAC instance and a list of DAC registers
828 * intended to be used (most commonly) with DMA transfer.
829 * @note These DAC registers are data holding registers:
830 * when DAC conversion is requested, DAC generates a DMA transfer
831 * request to have data available in DAC data holding registers.
832 * @note This macro is intended to be used with LL DMA driver, refer to
833 * function "LL_DMA_ConfigAddresses()".
834 * Example:
835 * LL_DMA_ConfigAddresses(DMA1,
836 * LL_DMA_CHANNEL_1,
837 * (uint32_t)&< array or variable >,
838 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
839 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
840 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
841 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
842 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
843 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
844 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
845 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
846 * @param DACx DAC instance
847 * @param DAC_Channel This parameter can be one of the following values:
848 * @arg @ref LL_DAC_CHANNEL_1
849 * @arg @ref LL_DAC_CHANNEL_2
850 * @param Register This parameter can be one of the following values:
851 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
852 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
853 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
854 * @retval DAC register address
855 */
LL_DAC_DMA_GetRegAddr(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Register)856 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
857 {
858 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
859 /* DAC channel selected. */
860 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
861 }
862 /**
863 * @}
864 */
865
866 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
867 * @{
868 */
869
870 /**
871 * @brief Enable DAC selected channel.
872 * @rmtoll CR EN1 LL_DAC_Enable\n
873 * CR EN2 LL_DAC_Enable
874 * @note After enable from off state, DAC channel requires a delay
875 * for output voltage to reach accuracy +/- 1 LSB.
876 * Refer to device datasheet, parameter "tWAKEUP".
877 * @param DACx DAC instance
878 * @param DAC_Channel This parameter can be one of the following values:
879 * @arg @ref LL_DAC_CHANNEL_1
880 * @arg @ref LL_DAC_CHANNEL_2
881 * @retval None
882 */
LL_DAC_Enable(DAC_TypeDef * DACx,uint32_t DAC_Channel)883 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
884 {
885 SET_BIT(DACx->CR,
886 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
887 }
888
889 /**
890 * @brief Disable DAC selected channel.
891 * @rmtoll CR EN1 LL_DAC_Disable\n
892 * CR EN2 LL_DAC_Disable
893 * @param DACx DAC instance
894 * @param DAC_Channel This parameter can be one of the following values:
895 * @arg @ref LL_DAC_CHANNEL_1
896 * @arg @ref LL_DAC_CHANNEL_2
897 * @retval None
898 */
LL_DAC_Disable(DAC_TypeDef * DACx,uint32_t DAC_Channel)899 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
900 {
901 CLEAR_BIT(DACx->CR,
902 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
903 }
904
905 /**
906 * @brief Get DAC enable state of the selected channel.
907 * (0: DAC channel is disabled, 1: DAC channel is enabled)
908 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
909 * CR EN2 LL_DAC_IsEnabled
910 * @param DACx DAC instance
911 * @param DAC_Channel This parameter can be one of the following values:
912 * @arg @ref LL_DAC_CHANNEL_1
913 * @arg @ref LL_DAC_CHANNEL_2
914 * @retval State of bit (1 or 0).
915 */
LL_DAC_IsEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)916 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
917 {
918 return (READ_BIT(DACx->CR,
919 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
920 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
921 }
922
923 /**
924 * @brief Enable DAC trigger of the selected channel.
925 * @note - If DAC trigger is disabled, DAC conversion is performed
926 * automatically once the data holding register is updated,
927 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
928 * @ref LL_DAC_ConvertData12RightAligned(), ...
929 * - If DAC trigger is enabled, DAC conversion is performed
930 * only when a hardware of software trigger event is occurring.
931 * Select trigger source using
932 * function @ref LL_DAC_SetTriggerSource().
933 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
934 * CR TEN2 LL_DAC_EnableTrigger
935 * @param DACx DAC instance
936 * @param DAC_Channel This parameter can be one of the following values:
937 * @arg @ref LL_DAC_CHANNEL_1
938 * @arg @ref LL_DAC_CHANNEL_2
939 * @retval None
940 */
LL_DAC_EnableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)941 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
942 {
943 SET_BIT(DACx->CR,
944 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
945 }
946
947 /**
948 * @brief Disable DAC trigger of the selected channel.
949 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
950 * CR TEN2 LL_DAC_DisableTrigger
951 * @param DACx DAC instance
952 * @param DAC_Channel This parameter can be one of the following values:
953 * @arg @ref LL_DAC_CHANNEL_1
954 * @arg @ref LL_DAC_CHANNEL_2
955 * @retval None
956 */
LL_DAC_DisableTrigger(DAC_TypeDef * DACx,uint32_t DAC_Channel)957 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
958 {
959 CLEAR_BIT(DACx->CR,
960 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
961 }
962
963 /**
964 * @brief Get DAC trigger state of the selected channel.
965 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
966 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
967 * CR TEN2 LL_DAC_IsTriggerEnabled
968 * @param DACx DAC instance
969 * @param DAC_Channel This parameter can be one of the following values:
970 * @arg @ref LL_DAC_CHANNEL_1
971 * @arg @ref LL_DAC_CHANNEL_2
972 * @retval State of bit (1 or 0).
973 */
LL_DAC_IsTriggerEnabled(DAC_TypeDef * DACx,uint32_t DAC_Channel)974 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
975 {
976 return (READ_BIT(DACx->CR,
977 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
978 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
979 }
980
981 /**
982 * @brief Trig DAC conversion by software for the selected DAC channel.
983 * @note Preliminarily, DAC trigger must be set to software trigger
984 * using function @ref LL_DAC_SetTriggerSource()
985 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
986 * and DAC trigger must be enabled using
987 * function @ref LL_DAC_EnableTrigger().
988 * @note For devices featuring DAC with 2 channels: this function
989 * can perform a SW start of both DAC channels simultaneously.
990 * Two channels can be selected as parameter.
991 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
992 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
993 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
994 * @param DACx DAC instance
995 * @param DAC_Channel This parameter can a combination of the following values:
996 * @arg @ref LL_DAC_CHANNEL_1
997 * @arg @ref LL_DAC_CHANNEL_2
998 * @retval None
999 */
LL_DAC_TrigSWConversion(DAC_TypeDef * DACx,uint32_t DAC_Channel)1000 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1001 {
1002 SET_BIT(DACx->SWTRIGR,
1003 (DAC_Channel & DAC_SWTR_CHX_MASK));
1004 }
1005
1006 /**
1007 * @brief Set the data to be loaded in the data holding register
1008 * in format 12 bits left alignment (LSB aligned on bit 0),
1009 * for the selected DAC channel.
1010 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
1011 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
1012 * @param DACx DAC instance
1013 * @param DAC_Channel This parameter can be one of the following values:
1014 * @arg @ref LL_DAC_CHANNEL_1
1015 * @arg @ref LL_DAC_CHANNEL_2
1016 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1017 * @retval None
1018 */
LL_DAC_ConvertData12RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1019 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1020 {
1021 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
1022
1023 MODIFY_REG(*preg,
1024 DAC_DHR12R1_DACC1DHR,
1025 Data);
1026 }
1027
1028 /**
1029 * @brief Set the data to be loaded in the data holding register
1030 * in format 12 bits left alignment (MSB aligned on bit 15),
1031 * for the selected DAC channel.
1032 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
1033 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
1034 * @param DACx DAC instance
1035 * @param DAC_Channel This parameter can be one of the following values:
1036 * @arg @ref LL_DAC_CHANNEL_1
1037 * @arg @ref LL_DAC_CHANNEL_2
1038 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
1039 * @retval None
1040 */
LL_DAC_ConvertData12LeftAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1041 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1042 {
1043 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
1044
1045 MODIFY_REG(*preg,
1046 DAC_DHR12L1_DACC1DHR,
1047 Data);
1048 }
1049
1050 /**
1051 * @brief Set the data to be loaded in the data holding register
1052 * in format 8 bits left alignment (LSB aligned on bit 0),
1053 * for the selected DAC channel.
1054 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
1055 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
1056 * @param DACx DAC instance
1057 * @param DAC_Channel This parameter can be one of the following values:
1058 * @arg @ref LL_DAC_CHANNEL_1
1059 * @arg @ref LL_DAC_CHANNEL_2
1060 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1061 * @retval None
1062 */
LL_DAC_ConvertData8RightAligned(DAC_TypeDef * DACx,uint32_t DAC_Channel,uint32_t Data)1063 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1064 {
1065 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
1066
1067 MODIFY_REG(*preg,
1068 DAC_DHR8R1_DACC1DHR,
1069 Data);
1070 }
1071
1072 /**
1073 * @brief Set the data to be loaded in the data holding register
1074 * in format 12 bits left alignment (LSB aligned on bit 0),
1075 * for both DAC channels.
1076 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
1077 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
1078 * @param DACx DAC instance
1079 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1080 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1081 * @retval None
1082 */
LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1083 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1084 {
1085 MODIFY_REG(DACx->DHR12RD,
1086 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1087 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1088 }
1089
1090 /**
1091 * @brief Set the data to be loaded in the data holding register
1092 * in format 12 bits left alignment (MSB aligned on bit 15),
1093 * for both DAC channels.
1094 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
1095 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
1096 * @param DACx DAC instance
1097 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
1098 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
1099 * @retval None
1100 */
LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1101 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1102 {
1103 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1104 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1105 /* the 4 LSB must be taken into account for the shift value. */
1106 MODIFY_REG(DACx->DHR12LD,
1107 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1108 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1109 }
1110
1111 /**
1112 * @brief Set the data to be loaded in the data holding register
1113 * in format 8 bits left alignment (LSB aligned on bit 0),
1114 * for both DAC channels.
1115 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
1116 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
1117 * @param DACx DAC instance
1118 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
1119 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
1120 * @retval None
1121 */
LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef * DACx,uint32_t DataChannel1,uint32_t DataChannel2)1122 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
1123 {
1124 MODIFY_REG(DACx->DHR8RD,
1125 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1126 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1127 }
1128
1129 /**
1130 * @brief Retrieve output data currently generated for the selected DAC channel.
1131 * @note Whatever alignment and resolution settings
1132 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
1133 * @ref LL_DAC_ConvertData12RightAligned(), ...),
1134 * output data format is 12 bits right aligned (LSB aligned on bit 0).
1135 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
1136 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
1137 * @param DACx DAC instance
1138 * @param DAC_Channel This parameter can be one of the following values:
1139 * @arg @ref LL_DAC_CHANNEL_1
1140 * @arg @ref LL_DAC_CHANNEL_2
1141 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1142 */
LL_DAC_RetrieveOutputData(DAC_TypeDef * DACx,uint32_t DAC_Channel)1143 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1144 {
1145 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
1146
1147 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1148 }
1149
1150 /**
1151 * @}
1152 */
1153
1154 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
1155 * @{
1156 */
1157 /**
1158 * @brief Get DAC underrun flag for DAC channel 1
1159 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
1160 * @param DACx DAC instance
1161 * @retval State of bit (1 or 0).
1162 */
LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef * DACx)1163 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
1164 {
1165 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
1166 }
1167
1168 /**
1169 * @brief Get DAC underrun flag for DAC channel 2
1170 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
1171 * @param DACx DAC instance
1172 * @retval State of bit (1 or 0).
1173 */
LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef * DACx)1174 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
1175 {
1176 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
1177 }
1178
1179 /**
1180 * @brief Clear DAC underrun flag for DAC channel 1
1181 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
1182 * @param DACx DAC instance
1183 * @retval None
1184 */
LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef * DACx)1185 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1186 {
1187 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1188 }
1189
1190 /**
1191 * @brief Clear DAC underrun flag for DAC channel 2
1192 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
1193 * @param DACx DAC instance
1194 * @retval None
1195 */
LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef * DACx)1196 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1197 {
1198 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1199 }
1200
1201 /**
1202 * @}
1203 */
1204
1205 /** @defgroup DAC_LL_EF_IT_Management IT management
1206 * @{
1207 */
1208
1209 /**
1210 * @brief Enable DMA underrun interrupt for DAC channel 1
1211 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
1212 * @param DACx DAC instance
1213 * @retval None
1214 */
LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef * DACx)1215 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1216 {
1217 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1218 }
1219
1220 /**
1221 * @brief Enable DMA underrun interrupt for DAC channel 2
1222 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
1223 * @param DACx DAC instance
1224 * @retval None
1225 */
LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef * DACx)1226 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1227 {
1228 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1229 }
1230
1231 /**
1232 * @brief Disable DMA underrun interrupt for DAC channel 1
1233 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
1234 * @param DACx DAC instance
1235 * @retval None
1236 */
LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef * DACx)1237 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1238 {
1239 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1240 }
1241
1242 /**
1243 * @brief Disable DMA underrun interrupt for DAC channel 2
1244 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
1245 * @param DACx DAC instance
1246 * @retval None
1247 */
LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef * DACx)1248 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1249 {
1250 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1251 }
1252
1253 /**
1254 * @brief Get DMA underrun interrupt for DAC channel 1
1255 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
1256 * @param DACx DAC instance
1257 * @retval State of bit (1 or 0).
1258 */
LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef * DACx)1259 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
1260 {
1261 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
1262 }
1263
1264 /**
1265 * @brief Get DMA underrun interrupt for DAC channel 2
1266 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
1267 * @param DACx DAC instance
1268 * @retval State of bit (1 or 0).
1269 */
LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef * DACx)1270 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
1271 {
1272 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
1273 }
1274
1275 /**
1276 * @}
1277 */
1278
1279 #if defined(USE_FULL_LL_DRIVER)
1280 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
1281 * @{
1282 */
1283
1284 ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
1285 ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
1286 void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
1287
1288 /**
1289 * @}
1290 */
1291 #endif /* USE_FULL_LL_DRIVER */
1292
1293 /**
1294 * @}
1295 */
1296
1297 /**
1298 * @}
1299 */
1300
1301 #endif /* DAC1 */
1302
1303 /**
1304 * @}
1305 */
1306
1307 #ifdef __cplusplus
1308 }
1309 #endif
1310
1311 #endif /* __STM32L1xx_LL_DAC_H */
1312
1313 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1314