1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Target Instruction Enum Values *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10#ifdef GET_INSTRINFO_ENUM 11#undef GET_INSTRINFO_ENUM 12namespace llvm { 13 14namespace ARM { 15 enum { 16 PHI = 0, 17 INLINEASM = 1, 18 CFI_INSTRUCTION = 2, 19 EH_LABEL = 3, 20 GC_LABEL = 4, 21 KILL = 5, 22 EXTRACT_SUBREG = 6, 23 INSERT_SUBREG = 7, 24 IMPLICIT_DEF = 8, 25 SUBREG_TO_REG = 9, 26 COPY_TO_REGCLASS = 10, 27 DBG_VALUE = 11, 28 REG_SEQUENCE = 12, 29 COPY = 13, 30 BUNDLE = 14, 31 LIFETIME_START = 15, 32 LIFETIME_END = 16, 33 STACKMAP = 17, 34 PATCHPOINT = 18, 35 LOAD_STACK_GUARD = 19, 36 STATEPOINT = 20, 37 LOCAL_ESCAPE = 21, 38 FAULTING_LOAD_OP = 22, 39 G_ADD = 23, 40 ABS = 24, 41 ADCri = 25, 42 ADCrr = 26, 43 ADCrsi = 27, 44 ADCrsr = 28, 45 ADDSri = 29, 46 ADDSrr = 30, 47 ADDSrsi = 31, 48 ADDSrsr = 32, 49 ADDri = 33, 50 ADDrr = 34, 51 ADDrsi = 35, 52 ADDrsr = 36, 53 ADJCALLSTACKDOWN = 37, 54 ADJCALLSTACKUP = 38, 55 ADR = 39, 56 AESD = 40, 57 AESE = 41, 58 AESIMC = 42, 59 AESMC = 43, 60 ANDri = 44, 61 ANDrr = 45, 62 ANDrsi = 46, 63 ANDrsr = 47, 64 ASRi = 48, 65 ASRr = 49, 66 B = 50, 67 BCCZi64 = 51, 68 BCCi64 = 52, 69 BFC = 53, 70 BFI = 54, 71 BICri = 55, 72 BICrr = 56, 73 BICrsi = 57, 74 BICrsr = 58, 75 BKPT = 59, 76 BL = 60, 77 BLX = 61, 78 BLX_pred = 62, 79 BLXi = 63, 80 BL_pred = 64, 81 BMOVPCB_CALL = 65, 82 BMOVPCRX_CALL = 66, 83 BR_JTadd = 67, 84 BR_JTm = 68, 85 BR_JTr = 69, 86 BX = 70, 87 BXJ = 71, 88 BX_CALL = 72, 89 BX_RET = 73, 90 BX_pred = 74, 91 Bcc = 75, 92 CDP = 76, 93 CDP2 = 77, 94 CLREX = 78, 95 CLZ = 79, 96 CMNri = 80, 97 CMNzrr = 81, 98 CMNzrsi = 82, 99 CMNzrsr = 83, 100 CMPri = 84, 101 CMPrr = 85, 102 CMPrsi = 86, 103 CMPrsr = 87, 104 CONSTPOOL_ENTRY = 88, 105 COPY_STRUCT_BYVAL_I32 = 89, 106 CPS1p = 90, 107 CPS2p = 91, 108 CPS3p = 92, 109 CRC32B = 93, 110 CRC32CB = 94, 111 CRC32CH = 95, 112 CRC32CW = 96, 113 CRC32H = 97, 114 CRC32W = 98, 115 DBG = 99, 116 DMB = 100, 117 DSB = 101, 118 EORri = 102, 119 EORrr = 103, 120 EORrsi = 104, 121 EORrsr = 105, 122 ERET = 106, 123 FCONSTD = 107, 124 FCONSTH = 108, 125 FCONSTS = 109, 126 FLDMXDB_UPD = 110, 127 FLDMXIA = 111, 128 FLDMXIA_UPD = 112, 129 FMSTAT = 113, 130 FSTMXDB_UPD = 114, 131 FSTMXIA = 115, 132 FSTMXIA_UPD = 116, 133 HINT = 117, 134 HLT = 118, 135 HVC = 119, 136 ISB = 120, 137 ITasm = 121, 138 Int_eh_sjlj_dispatchsetup = 122, 139 Int_eh_sjlj_longjmp = 123, 140 Int_eh_sjlj_setjmp = 124, 141 Int_eh_sjlj_setjmp_nofp = 125, 142 Int_eh_sjlj_setup_dispatch = 126, 143 JUMPTABLE_ADDRS = 127, 144 JUMPTABLE_INSTS = 128, 145 JUMPTABLE_TBB = 129, 146 JUMPTABLE_TBH = 130, 147 LDA = 131, 148 LDAB = 132, 149 LDAEX = 133, 150 LDAEXB = 134, 151 LDAEXD = 135, 152 LDAEXH = 136, 153 LDAH = 137, 154 LDC2L_OFFSET = 138, 155 LDC2L_OPTION = 139, 156 LDC2L_POST = 140, 157 LDC2L_PRE = 141, 158 LDC2_OFFSET = 142, 159 LDC2_OPTION = 143, 160 LDC2_POST = 144, 161 LDC2_PRE = 145, 162 LDCL_OFFSET = 146, 163 LDCL_OPTION = 147, 164 LDCL_POST = 148, 165 LDCL_PRE = 149, 166 LDC_OFFSET = 150, 167 LDC_OPTION = 151, 168 LDC_POST = 152, 169 LDC_PRE = 153, 170 LDMDA = 154, 171 LDMDA_UPD = 155, 172 LDMDB = 156, 173 LDMDB_UPD = 157, 174 LDMIA = 158, 175 LDMIA_RET = 159, 176 LDMIA_UPD = 160, 177 LDMIB = 161, 178 LDMIB_UPD = 162, 179 LDRBT_POST = 163, 180 LDRBT_POST_IMM = 164, 181 LDRBT_POST_REG = 165, 182 LDRB_POST_IMM = 166, 183 LDRB_POST_REG = 167, 184 LDRB_PRE_IMM = 168, 185 LDRB_PRE_REG = 169, 186 LDRBi12 = 170, 187 LDRBrs = 171, 188 LDRD = 172, 189 LDRD_POST = 173, 190 LDRD_PRE = 174, 191 LDREX = 175, 192 LDREXB = 176, 193 LDREXD = 177, 194 LDREXH = 178, 195 LDRH = 179, 196 LDRHTi = 180, 197 LDRHTr = 181, 198 LDRH_POST = 182, 199 LDRH_PRE = 183, 200 LDRLIT_ga_abs = 184, 201 LDRLIT_ga_pcrel = 185, 202 LDRLIT_ga_pcrel_ldr = 186, 203 LDRSB = 187, 204 LDRSBTi = 188, 205 LDRSBTr = 189, 206 LDRSB_POST = 190, 207 LDRSB_PRE = 191, 208 LDRSH = 192, 209 LDRSHTi = 193, 210 LDRSHTr = 194, 211 LDRSH_POST = 195, 212 LDRSH_PRE = 196, 213 LDRT_POST = 197, 214 LDRT_POST_IMM = 198, 215 LDRT_POST_REG = 199, 216 LDR_POST_IMM = 200, 217 LDR_POST_REG = 201, 218 LDR_PRE_IMM = 202, 219 LDR_PRE_REG = 203, 220 LDRcp = 204, 221 LDRi12 = 205, 222 LDRrs = 206, 223 LEApcrel = 207, 224 LEApcrelJT = 208, 225 LSLi = 209, 226 LSLr = 210, 227 LSRi = 211, 228 LSRr = 212, 229 MCR = 213, 230 MCR2 = 214, 231 MCRR = 215, 232 MCRR2 = 216, 233 MEMCPY = 217, 234 MLA = 218, 235 MLAv5 = 219, 236 MLS = 220, 237 MOVCCi = 221, 238 MOVCCi16 = 222, 239 MOVCCi32imm = 223, 240 MOVCCr = 224, 241 MOVCCsi = 225, 242 MOVCCsr = 226, 243 MOVPCLR = 227, 244 MOVPCRX = 228, 245 MOVTi16 = 229, 246 MOVTi16_ga_pcrel = 230, 247 MOV_ga_pcrel = 231, 248 MOV_ga_pcrel_ldr = 232, 249 MOVi = 233, 250 MOVi16 = 234, 251 MOVi16_ga_pcrel = 235, 252 MOVi32imm = 236, 253 MOVr = 237, 254 MOVr_TC = 238, 255 MOVsi = 239, 256 MOVsr = 240, 257 MOVsra_flag = 241, 258 MOVsrl_flag = 242, 259 MRC = 243, 260 MRC2 = 244, 261 MRRC = 245, 262 MRRC2 = 246, 263 MRS = 247, 264 MRSbanked = 248, 265 MRSsys = 249, 266 MSR = 250, 267 MSRbanked = 251, 268 MSRi = 252, 269 MUL = 253, 270 MULv5 = 254, 271 MVNCCi = 255, 272 MVNi = 256, 273 MVNr = 257, 274 MVNsi = 258, 275 MVNsr = 259, 276 ORRri = 260, 277 ORRrr = 261, 278 ORRrsi = 262, 279 ORRrsr = 263, 280 PICADD = 264, 281 PICLDR = 265, 282 PICLDRB = 266, 283 PICLDRH = 267, 284 PICLDRSB = 268, 285 PICLDRSH = 269, 286 PICSTR = 270, 287 PICSTRB = 271, 288 PICSTRH = 272, 289 PKHBT = 273, 290 PKHTB = 274, 291 PLDWi12 = 275, 292 PLDWrs = 276, 293 PLDi12 = 277, 294 PLDrs = 278, 295 PLIi12 = 279, 296 PLIrs = 280, 297 QADD = 281, 298 QADD16 = 282, 299 QADD8 = 283, 300 QASX = 284, 301 QDADD = 285, 302 QDSUB = 286, 303 QSAX = 287, 304 QSUB = 288, 305 QSUB16 = 289, 306 QSUB8 = 290, 307 RBIT = 291, 308 REV = 292, 309 REV16 = 293, 310 REVSH = 294, 311 RFEDA = 295, 312 RFEDA_UPD = 296, 313 RFEDB = 297, 314 RFEDB_UPD = 298, 315 RFEIA = 299, 316 RFEIA_UPD = 300, 317 RFEIB = 301, 318 RFEIB_UPD = 302, 319 RORi = 303, 320 RORr = 304, 321 RRX = 305, 322 RRXi = 306, 323 RSBSri = 307, 324 RSBSrsi = 308, 325 RSBSrsr = 309, 326 RSBri = 310, 327 RSBrr = 311, 328 RSBrsi = 312, 329 RSBrsr = 313, 330 RSCri = 314, 331 RSCrr = 315, 332 RSCrsi = 316, 333 RSCrsr = 317, 334 SADD16 = 318, 335 SADD8 = 319, 336 SASX = 320, 337 SBCri = 321, 338 SBCrr = 322, 339 SBCrsi = 323, 340 SBCrsr = 324, 341 SBFX = 325, 342 SDIV = 326, 343 SEL = 327, 344 SETEND = 328, 345 SETPAN = 329, 346 SHA1C = 330, 347 SHA1H = 331, 348 SHA1M = 332, 349 SHA1P = 333, 350 SHA1SU0 = 334, 351 SHA1SU1 = 335, 352 SHA256H = 336, 353 SHA256H2 = 337, 354 SHA256SU0 = 338, 355 SHA256SU1 = 339, 356 SHADD16 = 340, 357 SHADD8 = 341, 358 SHASX = 342, 359 SHSAX = 343, 360 SHSUB16 = 344, 361 SHSUB8 = 345, 362 SMC = 346, 363 SMLABB = 347, 364 SMLABT = 348, 365 SMLAD = 349, 366 SMLADX = 350, 367 SMLAL = 351, 368 SMLALBB = 352, 369 SMLALBT = 353, 370 SMLALD = 354, 371 SMLALDX = 355, 372 SMLALTB = 356, 373 SMLALTT = 357, 374 SMLALv5 = 358, 375 SMLATB = 359, 376 SMLATT = 360, 377 SMLAWB = 361, 378 SMLAWT = 362, 379 SMLSD = 363, 380 SMLSDX = 364, 381 SMLSLD = 365, 382 SMLSLDX = 366, 383 SMMLA = 367, 384 SMMLAR = 368, 385 SMMLS = 369, 386 SMMLSR = 370, 387 SMMUL = 371, 388 SMMULR = 372, 389 SMUAD = 373, 390 SMUADX = 374, 391 SMULBB = 375, 392 SMULBT = 376, 393 SMULL = 377, 394 SMULLv5 = 378, 395 SMULTB = 379, 396 SMULTT = 380, 397 SMULWB = 381, 398 SMULWT = 382, 399 SMUSD = 383, 400 SMUSDX = 384, 401 SPACE = 385, 402 SRSDA = 386, 403 SRSDA_UPD = 387, 404 SRSDB = 388, 405 SRSDB_UPD = 389, 406 SRSIA = 390, 407 SRSIA_UPD = 391, 408 SRSIB = 392, 409 SRSIB_UPD = 393, 410 SSAT = 394, 411 SSAT16 = 395, 412 SSAX = 396, 413 SSUB16 = 397, 414 SSUB8 = 398, 415 STC2L_OFFSET = 399, 416 STC2L_OPTION = 400, 417 STC2L_POST = 401, 418 STC2L_PRE = 402, 419 STC2_OFFSET = 403, 420 STC2_OPTION = 404, 421 STC2_POST = 405, 422 STC2_PRE = 406, 423 STCL_OFFSET = 407, 424 STCL_OPTION = 408, 425 STCL_POST = 409, 426 STCL_PRE = 410, 427 STC_OFFSET = 411, 428 STC_OPTION = 412, 429 STC_POST = 413, 430 STC_PRE = 414, 431 STL = 415, 432 STLB = 416, 433 STLEX = 417, 434 STLEXB = 418, 435 STLEXD = 419, 436 STLEXH = 420, 437 STLH = 421, 438 STMDA = 422, 439 STMDA_UPD = 423, 440 STMDB = 424, 441 STMDB_UPD = 425, 442 STMIA = 426, 443 STMIA_UPD = 427, 444 STMIB = 428, 445 STMIB_UPD = 429, 446 STRBT_POST = 430, 447 STRBT_POST_IMM = 431, 448 STRBT_POST_REG = 432, 449 STRB_POST_IMM = 433, 450 STRB_POST_REG = 434, 451 STRB_PRE_IMM = 435, 452 STRB_PRE_REG = 436, 453 STRBi12 = 437, 454 STRBi_preidx = 438, 455 STRBr_preidx = 439, 456 STRBrs = 440, 457 STRD = 441, 458 STRD_POST = 442, 459 STRD_PRE = 443, 460 STREX = 444, 461 STREXB = 445, 462 STREXD = 446, 463 STREXH = 447, 464 STRH = 448, 465 STRHTi = 449, 466 STRHTr = 450, 467 STRH_POST = 451, 468 STRH_PRE = 452, 469 STRH_preidx = 453, 470 STRT_POST = 454, 471 STRT_POST_IMM = 455, 472 STRT_POST_REG = 456, 473 STR_POST_IMM = 457, 474 STR_POST_REG = 458, 475 STR_PRE_IMM = 459, 476 STR_PRE_REG = 460, 477 STRi12 = 461, 478 STRi_preidx = 462, 479 STRr_preidx = 463, 480 STRrs = 464, 481 SUBS_PC_LR = 465, 482 SUBSri = 466, 483 SUBSrr = 467, 484 SUBSrsi = 468, 485 SUBSrsr = 469, 486 SUBri = 470, 487 SUBrr = 471, 488 SUBrsi = 472, 489 SUBrsr = 473, 490 SVC = 474, 491 SWP = 475, 492 SWPB = 476, 493 SXTAB = 477, 494 SXTAB16 = 478, 495 SXTAH = 479, 496 SXTB = 480, 497 SXTB16 = 481, 498 SXTH = 482, 499 TAILJMPd = 483, 500 TAILJMPr = 484, 501 TCRETURNdi = 485, 502 TCRETURNri = 486, 503 TEQri = 487, 504 TEQrr = 488, 505 TEQrsi = 489, 506 TEQrsr = 490, 507 TPsoft = 491, 508 TRAP = 492, 509 TRAPNaCl = 493, 510 TSTri = 494, 511 TSTrr = 495, 512 TSTrsi = 496, 513 TSTrsr = 497, 514 UADD16 = 498, 515 UADD8 = 499, 516 UASX = 500, 517 UBFX = 501, 518 UDF = 502, 519 UDIV = 503, 520 UHADD16 = 504, 521 UHADD8 = 505, 522 UHASX = 506, 523 UHSAX = 507, 524 UHSUB16 = 508, 525 UHSUB8 = 509, 526 UMAAL = 510, 527 UMLAL = 511, 528 UMLALv5 = 512, 529 UMULL = 513, 530 UMULLv5 = 514, 531 UQADD16 = 515, 532 UQADD8 = 516, 533 UQASX = 517, 534 UQSAX = 518, 535 UQSUB16 = 519, 536 UQSUB8 = 520, 537 USAD8 = 521, 538 USADA8 = 522, 539 USAT = 523, 540 USAT16 = 524, 541 USAX = 525, 542 USUB16 = 526, 543 USUB8 = 527, 544 UXTAB = 528, 545 UXTAB16 = 529, 546 UXTAH = 530, 547 UXTB = 531, 548 UXTB16 = 532, 549 UXTH = 533, 550 VABALsv2i64 = 534, 551 VABALsv4i32 = 535, 552 VABALsv8i16 = 536, 553 VABALuv2i64 = 537, 554 VABALuv4i32 = 538, 555 VABALuv8i16 = 539, 556 VABAsv16i8 = 540, 557 VABAsv2i32 = 541, 558 VABAsv4i16 = 542, 559 VABAsv4i32 = 543, 560 VABAsv8i16 = 544, 561 VABAsv8i8 = 545, 562 VABAuv16i8 = 546, 563 VABAuv2i32 = 547, 564 VABAuv4i16 = 548, 565 VABAuv4i32 = 549, 566 VABAuv8i16 = 550, 567 VABAuv8i8 = 551, 568 VABDLsv2i64 = 552, 569 VABDLsv4i32 = 553, 570 VABDLsv8i16 = 554, 571 VABDLuv2i64 = 555, 572 VABDLuv4i32 = 556, 573 VABDLuv8i16 = 557, 574 VABDfd = 558, 575 VABDfq = 559, 576 VABDhd = 560, 577 VABDhq = 561, 578 VABDsv16i8 = 562, 579 VABDsv2i32 = 563, 580 VABDsv4i16 = 564, 581 VABDsv4i32 = 565, 582 VABDsv8i16 = 566, 583 VABDsv8i8 = 567, 584 VABDuv16i8 = 568, 585 VABDuv2i32 = 569, 586 VABDuv4i16 = 570, 587 VABDuv4i32 = 571, 588 VABDuv8i16 = 572, 589 VABDuv8i8 = 573, 590 VABSD = 574, 591 VABSH = 575, 592 VABSS = 576, 593 VABSfd = 577, 594 VABSfq = 578, 595 VABShd = 579, 596 VABShq = 580, 597 VABSv16i8 = 581, 598 VABSv2i32 = 582, 599 VABSv4i16 = 583, 600 VABSv4i32 = 584, 601 VABSv8i16 = 585, 602 VABSv8i8 = 586, 603 VACGEfd = 587, 604 VACGEfq = 588, 605 VACGEhd = 589, 606 VACGEhq = 590, 607 VACGTfd = 591, 608 VACGTfq = 592, 609 VACGThd = 593, 610 VACGThq = 594, 611 VADDD = 595, 612 VADDH = 596, 613 VADDHNv2i32 = 597, 614 VADDHNv4i16 = 598, 615 VADDHNv8i8 = 599, 616 VADDLsv2i64 = 600, 617 VADDLsv4i32 = 601, 618 VADDLsv8i16 = 602, 619 VADDLuv2i64 = 603, 620 VADDLuv4i32 = 604, 621 VADDLuv8i16 = 605, 622 VADDS = 606, 623 VADDWsv2i64 = 607, 624 VADDWsv4i32 = 608, 625 VADDWsv8i16 = 609, 626 VADDWuv2i64 = 610, 627 VADDWuv4i32 = 611, 628 VADDWuv8i16 = 612, 629 VADDfd = 613, 630 VADDfq = 614, 631 VADDhd = 615, 632 VADDhq = 616, 633 VADDv16i8 = 617, 634 VADDv1i64 = 618, 635 VADDv2i32 = 619, 636 VADDv2i64 = 620, 637 VADDv4i16 = 621, 638 VADDv4i32 = 622, 639 VADDv8i16 = 623, 640 VADDv8i8 = 624, 641 VANDd = 625, 642 VANDq = 626, 643 VBICd = 627, 644 VBICiv2i32 = 628, 645 VBICiv4i16 = 629, 646 VBICiv4i32 = 630, 647 VBICiv8i16 = 631, 648 VBICq = 632, 649 VBIFd = 633, 650 VBIFq = 634, 651 VBITd = 635, 652 VBITq = 636, 653 VBSLd = 637, 654 VBSLq = 638, 655 VCEQfd = 639, 656 VCEQfq = 640, 657 VCEQhd = 641, 658 VCEQhq = 642, 659 VCEQv16i8 = 643, 660 VCEQv2i32 = 644, 661 VCEQv4i16 = 645, 662 VCEQv4i32 = 646, 663 VCEQv8i16 = 647, 664 VCEQv8i8 = 648, 665 VCEQzv16i8 = 649, 666 VCEQzv2f32 = 650, 667 VCEQzv2i32 = 651, 668 VCEQzv4f16 = 652, 669 VCEQzv4f32 = 653, 670 VCEQzv4i16 = 654, 671 VCEQzv4i32 = 655, 672 VCEQzv8f16 = 656, 673 VCEQzv8i16 = 657, 674 VCEQzv8i8 = 658, 675 VCGEfd = 659, 676 VCGEfq = 660, 677 VCGEhd = 661, 678 VCGEhq = 662, 679 VCGEsv16i8 = 663, 680 VCGEsv2i32 = 664, 681 VCGEsv4i16 = 665, 682 VCGEsv4i32 = 666, 683 VCGEsv8i16 = 667, 684 VCGEsv8i8 = 668, 685 VCGEuv16i8 = 669, 686 VCGEuv2i32 = 670, 687 VCGEuv4i16 = 671, 688 VCGEuv4i32 = 672, 689 VCGEuv8i16 = 673, 690 VCGEuv8i8 = 674, 691 VCGEzv16i8 = 675, 692 VCGEzv2f32 = 676, 693 VCGEzv2i32 = 677, 694 VCGEzv4f16 = 678, 695 VCGEzv4f32 = 679, 696 VCGEzv4i16 = 680, 697 VCGEzv4i32 = 681, 698 VCGEzv8f16 = 682, 699 VCGEzv8i16 = 683, 700 VCGEzv8i8 = 684, 701 VCGTfd = 685, 702 VCGTfq = 686, 703 VCGThd = 687, 704 VCGThq = 688, 705 VCGTsv16i8 = 689, 706 VCGTsv2i32 = 690, 707 VCGTsv4i16 = 691, 708 VCGTsv4i32 = 692, 709 VCGTsv8i16 = 693, 710 VCGTsv8i8 = 694, 711 VCGTuv16i8 = 695, 712 VCGTuv2i32 = 696, 713 VCGTuv4i16 = 697, 714 VCGTuv4i32 = 698, 715 VCGTuv8i16 = 699, 716 VCGTuv8i8 = 700, 717 VCGTzv16i8 = 701, 718 VCGTzv2f32 = 702, 719 VCGTzv2i32 = 703, 720 VCGTzv4f16 = 704, 721 VCGTzv4f32 = 705, 722 VCGTzv4i16 = 706, 723 VCGTzv4i32 = 707, 724 VCGTzv8f16 = 708, 725 VCGTzv8i16 = 709, 726 VCGTzv8i8 = 710, 727 VCLEzv16i8 = 711, 728 VCLEzv2f32 = 712, 729 VCLEzv2i32 = 713, 730 VCLEzv4f16 = 714, 731 VCLEzv4f32 = 715, 732 VCLEzv4i16 = 716, 733 VCLEzv4i32 = 717, 734 VCLEzv8f16 = 718, 735 VCLEzv8i16 = 719, 736 VCLEzv8i8 = 720, 737 VCLSv16i8 = 721, 738 VCLSv2i32 = 722, 739 VCLSv4i16 = 723, 740 VCLSv4i32 = 724, 741 VCLSv8i16 = 725, 742 VCLSv8i8 = 726, 743 VCLTzv16i8 = 727, 744 VCLTzv2f32 = 728, 745 VCLTzv2i32 = 729, 746 VCLTzv4f16 = 730, 747 VCLTzv4f32 = 731, 748 VCLTzv4i16 = 732, 749 VCLTzv4i32 = 733, 750 VCLTzv8f16 = 734, 751 VCLTzv8i16 = 735, 752 VCLTzv8i8 = 736, 753 VCLZv16i8 = 737, 754 VCLZv2i32 = 738, 755 VCLZv4i16 = 739, 756 VCLZv4i32 = 740, 757 VCLZv8i16 = 741, 758 VCLZv8i8 = 742, 759 VCMPD = 743, 760 VCMPED = 744, 761 VCMPEH = 745, 762 VCMPES = 746, 763 VCMPEZD = 747, 764 VCMPEZH = 748, 765 VCMPEZS = 749, 766 VCMPH = 750, 767 VCMPS = 751, 768 VCMPZD = 752, 769 VCMPZH = 753, 770 VCMPZS = 754, 771 VCNTd = 755, 772 VCNTq = 756, 773 VCVTANSDf = 757, 774 VCVTANSDh = 758, 775 VCVTANSQf = 759, 776 VCVTANSQh = 760, 777 VCVTANUDf = 761, 778 VCVTANUDh = 762, 779 VCVTANUQf = 763, 780 VCVTANUQh = 764, 781 VCVTASD = 765, 782 VCVTASH = 766, 783 VCVTASS = 767, 784 VCVTAUD = 768, 785 VCVTAUH = 769, 786 VCVTAUS = 770, 787 VCVTBDH = 771, 788 VCVTBHD = 772, 789 VCVTBHS = 773, 790 VCVTBSH = 774, 791 VCVTDS = 775, 792 VCVTMNSDf = 776, 793 VCVTMNSDh = 777, 794 VCVTMNSQf = 778, 795 VCVTMNSQh = 779, 796 VCVTMNUDf = 780, 797 VCVTMNUDh = 781, 798 VCVTMNUQf = 782, 799 VCVTMNUQh = 783, 800 VCVTMSD = 784, 801 VCVTMSH = 785, 802 VCVTMSS = 786, 803 VCVTMUD = 787, 804 VCVTMUH = 788, 805 VCVTMUS = 789, 806 VCVTNNSDf = 790, 807 VCVTNNSDh = 791, 808 VCVTNNSQf = 792, 809 VCVTNNSQh = 793, 810 VCVTNNUDf = 794, 811 VCVTNNUDh = 795, 812 VCVTNNUQf = 796, 813 VCVTNNUQh = 797, 814 VCVTNSD = 798, 815 VCVTNSH = 799, 816 VCVTNSS = 800, 817 VCVTNUD = 801, 818 VCVTNUH = 802, 819 VCVTNUS = 803, 820 VCVTPNSDf = 804, 821 VCVTPNSDh = 805, 822 VCVTPNSQf = 806, 823 VCVTPNSQh = 807, 824 VCVTPNUDf = 808, 825 VCVTPNUDh = 809, 826 VCVTPNUQf = 810, 827 VCVTPNUQh = 811, 828 VCVTPSD = 812, 829 VCVTPSH = 813, 830 VCVTPSS = 814, 831 VCVTPUD = 815, 832 VCVTPUH = 816, 833 VCVTPUS = 817, 834 VCVTSD = 818, 835 VCVTTDH = 819, 836 VCVTTHD = 820, 837 VCVTTHS = 821, 838 VCVTTSH = 822, 839 VCVTf2h = 823, 840 VCVTf2sd = 824, 841 VCVTf2sq = 825, 842 VCVTf2ud = 826, 843 VCVTf2uq = 827, 844 VCVTf2xsd = 828, 845 VCVTf2xsq = 829, 846 VCVTf2xud = 830, 847 VCVTf2xuq = 831, 848 VCVTh2f = 832, 849 VCVTh2sd = 833, 850 VCVTh2sq = 834, 851 VCVTh2ud = 835, 852 VCVTh2uq = 836, 853 VCVTh2xsd = 837, 854 VCVTh2xsq = 838, 855 VCVTh2xud = 839, 856 VCVTh2xuq = 840, 857 VCVTs2fd = 841, 858 VCVTs2fq = 842, 859 VCVTs2hd = 843, 860 VCVTs2hq = 844, 861 VCVTu2fd = 845, 862 VCVTu2fq = 846, 863 VCVTu2hd = 847, 864 VCVTu2hq = 848, 865 VCVTxs2fd = 849, 866 VCVTxs2fq = 850, 867 VCVTxs2hd = 851, 868 VCVTxs2hq = 852, 869 VCVTxu2fd = 853, 870 VCVTxu2fq = 854, 871 VCVTxu2hd = 855, 872 VCVTxu2hq = 856, 873 VDIVD = 857, 874 VDIVH = 858, 875 VDIVS = 859, 876 VDUP16d = 860, 877 VDUP16q = 861, 878 VDUP32d = 862, 879 VDUP32q = 863, 880 VDUP8d = 864, 881 VDUP8q = 865, 882 VDUPLN16d = 866, 883 VDUPLN16q = 867, 884 VDUPLN32d = 868, 885 VDUPLN32q = 869, 886 VDUPLN8d = 870, 887 VDUPLN8q = 871, 888 VEORd = 872, 889 VEORq = 873, 890 VEXTd16 = 874, 891 VEXTd32 = 875, 892 VEXTd8 = 876, 893 VEXTq16 = 877, 894 VEXTq32 = 878, 895 VEXTq64 = 879, 896 VEXTq8 = 880, 897 VFMAD = 881, 898 VFMAH = 882, 899 VFMAS = 883, 900 VFMAfd = 884, 901 VFMAfq = 885, 902 VFMAhd = 886, 903 VFMAhq = 887, 904 VFMSD = 888, 905 VFMSH = 889, 906 VFMSS = 890, 907 VFMSfd = 891, 908 VFMSfq = 892, 909 VFMShd = 893, 910 VFMShq = 894, 911 VFNMAD = 895, 912 VFNMAH = 896, 913 VFNMAS = 897, 914 VFNMSD = 898, 915 VFNMSH = 899, 916 VFNMSS = 900, 917 VGETLNi32 = 901, 918 VGETLNs16 = 902, 919 VGETLNs8 = 903, 920 VGETLNu16 = 904, 921 VGETLNu8 = 905, 922 VHADDsv16i8 = 906, 923 VHADDsv2i32 = 907, 924 VHADDsv4i16 = 908, 925 VHADDsv4i32 = 909, 926 VHADDsv8i16 = 910, 927 VHADDsv8i8 = 911, 928 VHADDuv16i8 = 912, 929 VHADDuv2i32 = 913, 930 VHADDuv4i16 = 914, 931 VHADDuv4i32 = 915, 932 VHADDuv8i16 = 916, 933 VHADDuv8i8 = 917, 934 VHSUBsv16i8 = 918, 935 VHSUBsv2i32 = 919, 936 VHSUBsv4i16 = 920, 937 VHSUBsv4i32 = 921, 938 VHSUBsv8i16 = 922, 939 VHSUBsv8i8 = 923, 940 VHSUBuv16i8 = 924, 941 VHSUBuv2i32 = 925, 942 VHSUBuv4i16 = 926, 943 VHSUBuv4i32 = 927, 944 VHSUBuv8i16 = 928, 945 VHSUBuv8i8 = 929, 946 VINSH = 930, 947 VLD1DUPd16 = 931, 948 VLD1DUPd16wb_fixed = 932, 949 VLD1DUPd16wb_register = 933, 950 VLD1DUPd32 = 934, 951 VLD1DUPd32wb_fixed = 935, 952 VLD1DUPd32wb_register = 936, 953 VLD1DUPd8 = 937, 954 VLD1DUPd8wb_fixed = 938, 955 VLD1DUPd8wb_register = 939, 956 VLD1DUPq16 = 940, 957 VLD1DUPq16wb_fixed = 941, 958 VLD1DUPq16wb_register = 942, 959 VLD1DUPq32 = 943, 960 VLD1DUPq32wb_fixed = 944, 961 VLD1DUPq32wb_register = 945, 962 VLD1DUPq8 = 946, 963 VLD1DUPq8wb_fixed = 947, 964 VLD1DUPq8wb_register = 948, 965 VLD1LNd16 = 949, 966 VLD1LNd16_UPD = 950, 967 VLD1LNd32 = 951, 968 VLD1LNd32_UPD = 952, 969 VLD1LNd8 = 953, 970 VLD1LNd8_UPD = 954, 971 VLD1LNdAsm_16 = 955, 972 VLD1LNdAsm_32 = 956, 973 VLD1LNdAsm_8 = 957, 974 VLD1LNdWB_fixed_Asm_16 = 958, 975 VLD1LNdWB_fixed_Asm_32 = 959, 976 VLD1LNdWB_fixed_Asm_8 = 960, 977 VLD1LNdWB_register_Asm_16 = 961, 978 VLD1LNdWB_register_Asm_32 = 962, 979 VLD1LNdWB_register_Asm_8 = 963, 980 VLD1LNq16Pseudo = 964, 981 VLD1LNq16Pseudo_UPD = 965, 982 VLD1LNq32Pseudo = 966, 983 VLD1LNq32Pseudo_UPD = 967, 984 VLD1LNq8Pseudo = 968, 985 VLD1LNq8Pseudo_UPD = 969, 986 VLD1d16 = 970, 987 VLD1d16Q = 971, 988 VLD1d16Qwb_fixed = 972, 989 VLD1d16Qwb_register = 973, 990 VLD1d16T = 974, 991 VLD1d16Twb_fixed = 975, 992 VLD1d16Twb_register = 976, 993 VLD1d16wb_fixed = 977, 994 VLD1d16wb_register = 978, 995 VLD1d32 = 979, 996 VLD1d32Q = 980, 997 VLD1d32Qwb_fixed = 981, 998 VLD1d32Qwb_register = 982, 999 VLD1d32T = 983, 1000 VLD1d32Twb_fixed = 984, 1001 VLD1d32Twb_register = 985, 1002 VLD1d32wb_fixed = 986, 1003 VLD1d32wb_register = 987, 1004 VLD1d64 = 988, 1005 VLD1d64Q = 989, 1006 VLD1d64QPseudo = 990, 1007 VLD1d64QPseudoWB_fixed = 991, 1008 VLD1d64QPseudoWB_register = 992, 1009 VLD1d64Qwb_fixed = 993, 1010 VLD1d64Qwb_register = 994, 1011 VLD1d64T = 995, 1012 VLD1d64TPseudo = 996, 1013 VLD1d64TPseudoWB_fixed = 997, 1014 VLD1d64TPseudoWB_register = 998, 1015 VLD1d64Twb_fixed = 999, 1016 VLD1d64Twb_register = 1000, 1017 VLD1d64wb_fixed = 1001, 1018 VLD1d64wb_register = 1002, 1019 VLD1d8 = 1003, 1020 VLD1d8Q = 1004, 1021 VLD1d8Qwb_fixed = 1005, 1022 VLD1d8Qwb_register = 1006, 1023 VLD1d8T = 1007, 1024 VLD1d8Twb_fixed = 1008, 1025 VLD1d8Twb_register = 1009, 1026 VLD1d8wb_fixed = 1010, 1027 VLD1d8wb_register = 1011, 1028 VLD1q16 = 1012, 1029 VLD1q16wb_fixed = 1013, 1030 VLD1q16wb_register = 1014, 1031 VLD1q32 = 1015, 1032 VLD1q32wb_fixed = 1016, 1033 VLD1q32wb_register = 1017, 1034 VLD1q64 = 1018, 1035 VLD1q64wb_fixed = 1019, 1036 VLD1q64wb_register = 1020, 1037 VLD1q8 = 1021, 1038 VLD1q8wb_fixed = 1022, 1039 VLD1q8wb_register = 1023, 1040 VLD2DUPd16 = 1024, 1041 VLD2DUPd16wb_fixed = 1025, 1042 VLD2DUPd16wb_register = 1026, 1043 VLD2DUPd16x2 = 1027, 1044 VLD2DUPd16x2wb_fixed = 1028, 1045 VLD2DUPd16x2wb_register = 1029, 1046 VLD2DUPd32 = 1030, 1047 VLD2DUPd32wb_fixed = 1031, 1048 VLD2DUPd32wb_register = 1032, 1049 VLD2DUPd32x2 = 1033, 1050 VLD2DUPd32x2wb_fixed = 1034, 1051 VLD2DUPd32x2wb_register = 1035, 1052 VLD2DUPd8 = 1036, 1053 VLD2DUPd8wb_fixed = 1037, 1054 VLD2DUPd8wb_register = 1038, 1055 VLD2DUPd8x2 = 1039, 1056 VLD2DUPd8x2wb_fixed = 1040, 1057 VLD2DUPd8x2wb_register = 1041, 1058 VLD2LNd16 = 1042, 1059 VLD2LNd16Pseudo = 1043, 1060 VLD2LNd16Pseudo_UPD = 1044, 1061 VLD2LNd16_UPD = 1045, 1062 VLD2LNd32 = 1046, 1063 VLD2LNd32Pseudo = 1047, 1064 VLD2LNd32Pseudo_UPD = 1048, 1065 VLD2LNd32_UPD = 1049, 1066 VLD2LNd8 = 1050, 1067 VLD2LNd8Pseudo = 1051, 1068 VLD2LNd8Pseudo_UPD = 1052, 1069 VLD2LNd8_UPD = 1053, 1070 VLD2LNdAsm_16 = 1054, 1071 VLD2LNdAsm_32 = 1055, 1072 VLD2LNdAsm_8 = 1056, 1073 VLD2LNdWB_fixed_Asm_16 = 1057, 1074 VLD2LNdWB_fixed_Asm_32 = 1058, 1075 VLD2LNdWB_fixed_Asm_8 = 1059, 1076 VLD2LNdWB_register_Asm_16 = 1060, 1077 VLD2LNdWB_register_Asm_32 = 1061, 1078 VLD2LNdWB_register_Asm_8 = 1062, 1079 VLD2LNq16 = 1063, 1080 VLD2LNq16Pseudo = 1064, 1081 VLD2LNq16Pseudo_UPD = 1065, 1082 VLD2LNq16_UPD = 1066, 1083 VLD2LNq32 = 1067, 1084 VLD2LNq32Pseudo = 1068, 1085 VLD2LNq32Pseudo_UPD = 1069, 1086 VLD2LNq32_UPD = 1070, 1087 VLD2LNqAsm_16 = 1071, 1088 VLD2LNqAsm_32 = 1072, 1089 VLD2LNqWB_fixed_Asm_16 = 1073, 1090 VLD2LNqWB_fixed_Asm_32 = 1074, 1091 VLD2LNqWB_register_Asm_16 = 1075, 1092 VLD2LNqWB_register_Asm_32 = 1076, 1093 VLD2b16 = 1077, 1094 VLD2b16wb_fixed = 1078, 1095 VLD2b16wb_register = 1079, 1096 VLD2b32 = 1080, 1097 VLD2b32wb_fixed = 1081, 1098 VLD2b32wb_register = 1082, 1099 VLD2b8 = 1083, 1100 VLD2b8wb_fixed = 1084, 1101 VLD2b8wb_register = 1085, 1102 VLD2d16 = 1086, 1103 VLD2d16wb_fixed = 1087, 1104 VLD2d16wb_register = 1088, 1105 VLD2d32 = 1089, 1106 VLD2d32wb_fixed = 1090, 1107 VLD2d32wb_register = 1091, 1108 VLD2d8 = 1092, 1109 VLD2d8wb_fixed = 1093, 1110 VLD2d8wb_register = 1094, 1111 VLD2q16 = 1095, 1112 VLD2q16Pseudo = 1096, 1113 VLD2q16PseudoWB_fixed = 1097, 1114 VLD2q16PseudoWB_register = 1098, 1115 VLD2q16wb_fixed = 1099, 1116 VLD2q16wb_register = 1100, 1117 VLD2q32 = 1101, 1118 VLD2q32Pseudo = 1102, 1119 VLD2q32PseudoWB_fixed = 1103, 1120 VLD2q32PseudoWB_register = 1104, 1121 VLD2q32wb_fixed = 1105, 1122 VLD2q32wb_register = 1106, 1123 VLD2q8 = 1107, 1124 VLD2q8Pseudo = 1108, 1125 VLD2q8PseudoWB_fixed = 1109, 1126 VLD2q8PseudoWB_register = 1110, 1127 VLD2q8wb_fixed = 1111, 1128 VLD2q8wb_register = 1112, 1129 VLD3DUPd16 = 1113, 1130 VLD3DUPd16Pseudo = 1114, 1131 VLD3DUPd16Pseudo_UPD = 1115, 1132 VLD3DUPd16_UPD = 1116, 1133 VLD3DUPd32 = 1117, 1134 VLD3DUPd32Pseudo = 1118, 1135 VLD3DUPd32Pseudo_UPD = 1119, 1136 VLD3DUPd32_UPD = 1120, 1137 VLD3DUPd8 = 1121, 1138 VLD3DUPd8Pseudo = 1122, 1139 VLD3DUPd8Pseudo_UPD = 1123, 1140 VLD3DUPd8_UPD = 1124, 1141 VLD3DUPdAsm_16 = 1125, 1142 VLD3DUPdAsm_32 = 1126, 1143 VLD3DUPdAsm_8 = 1127, 1144 VLD3DUPdWB_fixed_Asm_16 = 1128, 1145 VLD3DUPdWB_fixed_Asm_32 = 1129, 1146 VLD3DUPdWB_fixed_Asm_8 = 1130, 1147 VLD3DUPdWB_register_Asm_16 = 1131, 1148 VLD3DUPdWB_register_Asm_32 = 1132, 1149 VLD3DUPdWB_register_Asm_8 = 1133, 1150 VLD3DUPq16 = 1134, 1151 VLD3DUPq16_UPD = 1135, 1152 VLD3DUPq32 = 1136, 1153 VLD3DUPq32_UPD = 1137, 1154 VLD3DUPq8 = 1138, 1155 VLD3DUPq8_UPD = 1139, 1156 VLD3DUPqAsm_16 = 1140, 1157 VLD3DUPqAsm_32 = 1141, 1158 VLD3DUPqAsm_8 = 1142, 1159 VLD3DUPqWB_fixed_Asm_16 = 1143, 1160 VLD3DUPqWB_fixed_Asm_32 = 1144, 1161 VLD3DUPqWB_fixed_Asm_8 = 1145, 1162 VLD3DUPqWB_register_Asm_16 = 1146, 1163 VLD3DUPqWB_register_Asm_32 = 1147, 1164 VLD3DUPqWB_register_Asm_8 = 1148, 1165 VLD3LNd16 = 1149, 1166 VLD3LNd16Pseudo = 1150, 1167 VLD3LNd16Pseudo_UPD = 1151, 1168 VLD3LNd16_UPD = 1152, 1169 VLD3LNd32 = 1153, 1170 VLD3LNd32Pseudo = 1154, 1171 VLD3LNd32Pseudo_UPD = 1155, 1172 VLD3LNd32_UPD = 1156, 1173 VLD3LNd8 = 1157, 1174 VLD3LNd8Pseudo = 1158, 1175 VLD3LNd8Pseudo_UPD = 1159, 1176 VLD3LNd8_UPD = 1160, 1177 VLD3LNdAsm_16 = 1161, 1178 VLD3LNdAsm_32 = 1162, 1179 VLD3LNdAsm_8 = 1163, 1180 VLD3LNdWB_fixed_Asm_16 = 1164, 1181 VLD3LNdWB_fixed_Asm_32 = 1165, 1182 VLD3LNdWB_fixed_Asm_8 = 1166, 1183 VLD3LNdWB_register_Asm_16 = 1167, 1184 VLD3LNdWB_register_Asm_32 = 1168, 1185 VLD3LNdWB_register_Asm_8 = 1169, 1186 VLD3LNq16 = 1170, 1187 VLD3LNq16Pseudo = 1171, 1188 VLD3LNq16Pseudo_UPD = 1172, 1189 VLD3LNq16_UPD = 1173, 1190 VLD3LNq32 = 1174, 1191 VLD3LNq32Pseudo = 1175, 1192 VLD3LNq32Pseudo_UPD = 1176, 1193 VLD3LNq32_UPD = 1177, 1194 VLD3LNqAsm_16 = 1178, 1195 VLD3LNqAsm_32 = 1179, 1196 VLD3LNqWB_fixed_Asm_16 = 1180, 1197 VLD3LNqWB_fixed_Asm_32 = 1181, 1198 VLD3LNqWB_register_Asm_16 = 1182, 1199 VLD3LNqWB_register_Asm_32 = 1183, 1200 VLD3d16 = 1184, 1201 VLD3d16Pseudo = 1185, 1202 VLD3d16Pseudo_UPD = 1186, 1203 VLD3d16_UPD = 1187, 1204 VLD3d32 = 1188, 1205 VLD3d32Pseudo = 1189, 1206 VLD3d32Pseudo_UPD = 1190, 1207 VLD3d32_UPD = 1191, 1208 VLD3d8 = 1192, 1209 VLD3d8Pseudo = 1193, 1210 VLD3d8Pseudo_UPD = 1194, 1211 VLD3d8_UPD = 1195, 1212 VLD3dAsm_16 = 1196, 1213 VLD3dAsm_32 = 1197, 1214 VLD3dAsm_8 = 1198, 1215 VLD3dWB_fixed_Asm_16 = 1199, 1216 VLD3dWB_fixed_Asm_32 = 1200, 1217 VLD3dWB_fixed_Asm_8 = 1201, 1218 VLD3dWB_register_Asm_16 = 1202, 1219 VLD3dWB_register_Asm_32 = 1203, 1220 VLD3dWB_register_Asm_8 = 1204, 1221 VLD3q16 = 1205, 1222 VLD3q16Pseudo_UPD = 1206, 1223 VLD3q16_UPD = 1207, 1224 VLD3q16oddPseudo = 1208, 1225 VLD3q16oddPseudo_UPD = 1209, 1226 VLD3q32 = 1210, 1227 VLD3q32Pseudo_UPD = 1211, 1228 VLD3q32_UPD = 1212, 1229 VLD3q32oddPseudo = 1213, 1230 VLD3q32oddPseudo_UPD = 1214, 1231 VLD3q8 = 1215, 1232 VLD3q8Pseudo_UPD = 1216, 1233 VLD3q8_UPD = 1217, 1234 VLD3q8oddPseudo = 1218, 1235 VLD3q8oddPseudo_UPD = 1219, 1236 VLD3qAsm_16 = 1220, 1237 VLD3qAsm_32 = 1221, 1238 VLD3qAsm_8 = 1222, 1239 VLD3qWB_fixed_Asm_16 = 1223, 1240 VLD3qWB_fixed_Asm_32 = 1224, 1241 VLD3qWB_fixed_Asm_8 = 1225, 1242 VLD3qWB_register_Asm_16 = 1226, 1243 VLD3qWB_register_Asm_32 = 1227, 1244 VLD3qWB_register_Asm_8 = 1228, 1245 VLD4DUPd16 = 1229, 1246 VLD4DUPd16Pseudo = 1230, 1247 VLD4DUPd16Pseudo_UPD = 1231, 1248 VLD4DUPd16_UPD = 1232, 1249 VLD4DUPd32 = 1233, 1250 VLD4DUPd32Pseudo = 1234, 1251 VLD4DUPd32Pseudo_UPD = 1235, 1252 VLD4DUPd32_UPD = 1236, 1253 VLD4DUPd8 = 1237, 1254 VLD4DUPd8Pseudo = 1238, 1255 VLD4DUPd8Pseudo_UPD = 1239, 1256 VLD4DUPd8_UPD = 1240, 1257 VLD4DUPdAsm_16 = 1241, 1258 VLD4DUPdAsm_32 = 1242, 1259 VLD4DUPdAsm_8 = 1243, 1260 VLD4DUPdWB_fixed_Asm_16 = 1244, 1261 VLD4DUPdWB_fixed_Asm_32 = 1245, 1262 VLD4DUPdWB_fixed_Asm_8 = 1246, 1263 VLD4DUPdWB_register_Asm_16 = 1247, 1264 VLD4DUPdWB_register_Asm_32 = 1248, 1265 VLD4DUPdWB_register_Asm_8 = 1249, 1266 VLD4DUPq16 = 1250, 1267 VLD4DUPq16_UPD = 1251, 1268 VLD4DUPq32 = 1252, 1269 VLD4DUPq32_UPD = 1253, 1270 VLD4DUPq8 = 1254, 1271 VLD4DUPq8_UPD = 1255, 1272 VLD4DUPqAsm_16 = 1256, 1273 VLD4DUPqAsm_32 = 1257, 1274 VLD4DUPqAsm_8 = 1258, 1275 VLD4DUPqWB_fixed_Asm_16 = 1259, 1276 VLD4DUPqWB_fixed_Asm_32 = 1260, 1277 VLD4DUPqWB_fixed_Asm_8 = 1261, 1278 VLD4DUPqWB_register_Asm_16 = 1262, 1279 VLD4DUPqWB_register_Asm_32 = 1263, 1280 VLD4DUPqWB_register_Asm_8 = 1264, 1281 VLD4LNd16 = 1265, 1282 VLD4LNd16Pseudo = 1266, 1283 VLD4LNd16Pseudo_UPD = 1267, 1284 VLD4LNd16_UPD = 1268, 1285 VLD4LNd32 = 1269, 1286 VLD4LNd32Pseudo = 1270, 1287 VLD4LNd32Pseudo_UPD = 1271, 1288 VLD4LNd32_UPD = 1272, 1289 VLD4LNd8 = 1273, 1290 VLD4LNd8Pseudo = 1274, 1291 VLD4LNd8Pseudo_UPD = 1275, 1292 VLD4LNd8_UPD = 1276, 1293 VLD4LNdAsm_16 = 1277, 1294 VLD4LNdAsm_32 = 1278, 1295 VLD4LNdAsm_8 = 1279, 1296 VLD4LNdWB_fixed_Asm_16 = 1280, 1297 VLD4LNdWB_fixed_Asm_32 = 1281, 1298 VLD4LNdWB_fixed_Asm_8 = 1282, 1299 VLD4LNdWB_register_Asm_16 = 1283, 1300 VLD4LNdWB_register_Asm_32 = 1284, 1301 VLD4LNdWB_register_Asm_8 = 1285, 1302 VLD4LNq16 = 1286, 1303 VLD4LNq16Pseudo = 1287, 1304 VLD4LNq16Pseudo_UPD = 1288, 1305 VLD4LNq16_UPD = 1289, 1306 VLD4LNq32 = 1290, 1307 VLD4LNq32Pseudo = 1291, 1308 VLD4LNq32Pseudo_UPD = 1292, 1309 VLD4LNq32_UPD = 1293, 1310 VLD4LNqAsm_16 = 1294, 1311 VLD4LNqAsm_32 = 1295, 1312 VLD4LNqWB_fixed_Asm_16 = 1296, 1313 VLD4LNqWB_fixed_Asm_32 = 1297, 1314 VLD4LNqWB_register_Asm_16 = 1298, 1315 VLD4LNqWB_register_Asm_32 = 1299, 1316 VLD4d16 = 1300, 1317 VLD4d16Pseudo = 1301, 1318 VLD4d16Pseudo_UPD = 1302, 1319 VLD4d16_UPD = 1303, 1320 VLD4d32 = 1304, 1321 VLD4d32Pseudo = 1305, 1322 VLD4d32Pseudo_UPD = 1306, 1323 VLD4d32_UPD = 1307, 1324 VLD4d8 = 1308, 1325 VLD4d8Pseudo = 1309, 1326 VLD4d8Pseudo_UPD = 1310, 1327 VLD4d8_UPD = 1311, 1328 VLD4dAsm_16 = 1312, 1329 VLD4dAsm_32 = 1313, 1330 VLD4dAsm_8 = 1314, 1331 VLD4dWB_fixed_Asm_16 = 1315, 1332 VLD4dWB_fixed_Asm_32 = 1316, 1333 VLD4dWB_fixed_Asm_8 = 1317, 1334 VLD4dWB_register_Asm_16 = 1318, 1335 VLD4dWB_register_Asm_32 = 1319, 1336 VLD4dWB_register_Asm_8 = 1320, 1337 VLD4q16 = 1321, 1338 VLD4q16Pseudo_UPD = 1322, 1339 VLD4q16_UPD = 1323, 1340 VLD4q16oddPseudo = 1324, 1341 VLD4q16oddPseudo_UPD = 1325, 1342 VLD4q32 = 1326, 1343 VLD4q32Pseudo_UPD = 1327, 1344 VLD4q32_UPD = 1328, 1345 VLD4q32oddPseudo = 1329, 1346 VLD4q32oddPseudo_UPD = 1330, 1347 VLD4q8 = 1331, 1348 VLD4q8Pseudo_UPD = 1332, 1349 VLD4q8_UPD = 1333, 1350 VLD4q8oddPseudo = 1334, 1351 VLD4q8oddPseudo_UPD = 1335, 1352 VLD4qAsm_16 = 1336, 1353 VLD4qAsm_32 = 1337, 1354 VLD4qAsm_8 = 1338, 1355 VLD4qWB_fixed_Asm_16 = 1339, 1356 VLD4qWB_fixed_Asm_32 = 1340, 1357 VLD4qWB_fixed_Asm_8 = 1341, 1358 VLD4qWB_register_Asm_16 = 1342, 1359 VLD4qWB_register_Asm_32 = 1343, 1360 VLD4qWB_register_Asm_8 = 1344, 1361 VLDMDDB_UPD = 1345, 1362 VLDMDIA = 1346, 1363 VLDMDIA_UPD = 1347, 1364 VLDMQIA = 1348, 1365 VLDMSDB_UPD = 1349, 1366 VLDMSIA = 1350, 1367 VLDMSIA_UPD = 1351, 1368 VLDRD = 1352, 1369 VLDRH = 1353, 1370 VLDRS = 1354, 1371 VLLDM = 1355, 1372 VLSTM = 1356, 1373 VMAXNMD = 1357, 1374 VMAXNMH = 1358, 1375 VMAXNMNDf = 1359, 1376 VMAXNMNDh = 1360, 1377 VMAXNMNQf = 1361, 1378 VMAXNMNQh = 1362, 1379 VMAXNMS = 1363, 1380 VMAXfd = 1364, 1381 VMAXfq = 1365, 1382 VMAXhd = 1366, 1383 VMAXhq = 1367, 1384 VMAXsv16i8 = 1368, 1385 VMAXsv2i32 = 1369, 1386 VMAXsv4i16 = 1370, 1387 VMAXsv4i32 = 1371, 1388 VMAXsv8i16 = 1372, 1389 VMAXsv8i8 = 1373, 1390 VMAXuv16i8 = 1374, 1391 VMAXuv2i32 = 1375, 1392 VMAXuv4i16 = 1376, 1393 VMAXuv4i32 = 1377, 1394 VMAXuv8i16 = 1378, 1395 VMAXuv8i8 = 1379, 1396 VMINNMD = 1380, 1397 VMINNMH = 1381, 1398 VMINNMNDf = 1382, 1399 VMINNMNDh = 1383, 1400 VMINNMNQf = 1384, 1401 VMINNMNQh = 1385, 1402 VMINNMS = 1386, 1403 VMINfd = 1387, 1404 VMINfq = 1388, 1405 VMINhd = 1389, 1406 VMINhq = 1390, 1407 VMINsv16i8 = 1391, 1408 VMINsv2i32 = 1392, 1409 VMINsv4i16 = 1393, 1410 VMINsv4i32 = 1394, 1411 VMINsv8i16 = 1395, 1412 VMINsv8i8 = 1396, 1413 VMINuv16i8 = 1397, 1414 VMINuv2i32 = 1398, 1415 VMINuv4i16 = 1399, 1416 VMINuv4i32 = 1400, 1417 VMINuv8i16 = 1401, 1418 VMINuv8i8 = 1402, 1419 VMLAD = 1403, 1420 VMLAH = 1404, 1421 VMLALslsv2i32 = 1405, 1422 VMLALslsv4i16 = 1406, 1423 VMLALsluv2i32 = 1407, 1424 VMLALsluv4i16 = 1408, 1425 VMLALsv2i64 = 1409, 1426 VMLALsv4i32 = 1410, 1427 VMLALsv8i16 = 1411, 1428 VMLALuv2i64 = 1412, 1429 VMLALuv4i32 = 1413, 1430 VMLALuv8i16 = 1414, 1431 VMLAS = 1415, 1432 VMLAfd = 1416, 1433 VMLAfq = 1417, 1434 VMLAhd = 1418, 1435 VMLAhq = 1419, 1436 VMLAslfd = 1420, 1437 VMLAslfq = 1421, 1438 VMLAslhd = 1422, 1439 VMLAslhq = 1423, 1440 VMLAslv2i32 = 1424, 1441 VMLAslv4i16 = 1425, 1442 VMLAslv4i32 = 1426, 1443 VMLAslv8i16 = 1427, 1444 VMLAv16i8 = 1428, 1445 VMLAv2i32 = 1429, 1446 VMLAv4i16 = 1430, 1447 VMLAv4i32 = 1431, 1448 VMLAv8i16 = 1432, 1449 VMLAv8i8 = 1433, 1450 VMLSD = 1434, 1451 VMLSH = 1435, 1452 VMLSLslsv2i32 = 1436, 1453 VMLSLslsv4i16 = 1437, 1454 VMLSLsluv2i32 = 1438, 1455 VMLSLsluv4i16 = 1439, 1456 VMLSLsv2i64 = 1440, 1457 VMLSLsv4i32 = 1441, 1458 VMLSLsv8i16 = 1442, 1459 VMLSLuv2i64 = 1443, 1460 VMLSLuv4i32 = 1444, 1461 VMLSLuv8i16 = 1445, 1462 VMLSS = 1446, 1463 VMLSfd = 1447, 1464 VMLSfq = 1448, 1465 VMLShd = 1449, 1466 VMLShq = 1450, 1467 VMLSslfd = 1451, 1468 VMLSslfq = 1452, 1469 VMLSslhd = 1453, 1470 VMLSslhq = 1454, 1471 VMLSslv2i32 = 1455, 1472 VMLSslv4i16 = 1456, 1473 VMLSslv4i32 = 1457, 1474 VMLSslv8i16 = 1458, 1475 VMLSv16i8 = 1459, 1476 VMLSv2i32 = 1460, 1477 VMLSv4i16 = 1461, 1478 VMLSv4i32 = 1462, 1479 VMLSv8i16 = 1463, 1480 VMLSv8i8 = 1464, 1481 VMOVD = 1465, 1482 VMOVD0 = 1466, 1483 VMOVDRR = 1467, 1484 VMOVDcc = 1468, 1485 VMOVH = 1469, 1486 VMOVHR = 1470, 1487 VMOVLsv2i64 = 1471, 1488 VMOVLsv4i32 = 1472, 1489 VMOVLsv8i16 = 1473, 1490 VMOVLuv2i64 = 1474, 1491 VMOVLuv4i32 = 1475, 1492 VMOVLuv8i16 = 1476, 1493 VMOVNv2i32 = 1477, 1494 VMOVNv4i16 = 1478, 1495 VMOVNv8i8 = 1479, 1496 VMOVQ0 = 1480, 1497 VMOVRH = 1481, 1498 VMOVRRD = 1482, 1499 VMOVRRS = 1483, 1500 VMOVRS = 1484, 1501 VMOVS = 1485, 1502 VMOVSR = 1486, 1503 VMOVSRR = 1487, 1504 VMOVScc = 1488, 1505 VMOVv16i8 = 1489, 1506 VMOVv1i64 = 1490, 1507 VMOVv2f32 = 1491, 1508 VMOVv2i32 = 1492, 1509 VMOVv2i64 = 1493, 1510 VMOVv4f32 = 1494, 1511 VMOVv4i16 = 1495, 1512 VMOVv4i32 = 1496, 1513 VMOVv8i16 = 1497, 1514 VMOVv8i8 = 1498, 1515 VMRS = 1499, 1516 VMRS_FPEXC = 1500, 1517 VMRS_FPINST = 1501, 1518 VMRS_FPINST2 = 1502, 1519 VMRS_FPSID = 1503, 1520 VMRS_MVFR0 = 1504, 1521 VMRS_MVFR1 = 1505, 1522 VMRS_MVFR2 = 1506, 1523 VMSR = 1507, 1524 VMSR_FPEXC = 1508, 1525 VMSR_FPINST = 1509, 1526 VMSR_FPINST2 = 1510, 1527 VMSR_FPSID = 1511, 1528 VMULD = 1512, 1529 VMULH = 1513, 1530 VMULLp64 = 1514, 1531 VMULLp8 = 1515, 1532 VMULLslsv2i32 = 1516, 1533 VMULLslsv4i16 = 1517, 1534 VMULLsluv2i32 = 1518, 1535 VMULLsluv4i16 = 1519, 1536 VMULLsv2i64 = 1520, 1537 VMULLsv4i32 = 1521, 1538 VMULLsv8i16 = 1522, 1539 VMULLuv2i64 = 1523, 1540 VMULLuv4i32 = 1524, 1541 VMULLuv8i16 = 1525, 1542 VMULS = 1526, 1543 VMULfd = 1527, 1544 VMULfq = 1528, 1545 VMULhd = 1529, 1546 VMULhq = 1530, 1547 VMULpd = 1531, 1548 VMULpq = 1532, 1549 VMULslfd = 1533, 1550 VMULslfq = 1534, 1551 VMULslhd = 1535, 1552 VMULslhq = 1536, 1553 VMULslv2i32 = 1537, 1554 VMULslv4i16 = 1538, 1555 VMULslv4i32 = 1539, 1556 VMULslv8i16 = 1540, 1557 VMULv16i8 = 1541, 1558 VMULv2i32 = 1542, 1559 VMULv4i16 = 1543, 1560 VMULv4i32 = 1544, 1561 VMULv8i16 = 1545, 1562 VMULv8i8 = 1546, 1563 VMVNd = 1547, 1564 VMVNq = 1548, 1565 VMVNv2i32 = 1549, 1566 VMVNv4i16 = 1550, 1567 VMVNv4i32 = 1551, 1568 VMVNv8i16 = 1552, 1569 VNEGD = 1553, 1570 VNEGH = 1554, 1571 VNEGS = 1555, 1572 VNEGf32q = 1556, 1573 VNEGfd = 1557, 1574 VNEGhd = 1558, 1575 VNEGhq = 1559, 1576 VNEGs16d = 1560, 1577 VNEGs16q = 1561, 1578 VNEGs32d = 1562, 1579 VNEGs32q = 1563, 1580 VNEGs8d = 1564, 1581 VNEGs8q = 1565, 1582 VNMLAD = 1566, 1583 VNMLAH = 1567, 1584 VNMLAS = 1568, 1585 VNMLSD = 1569, 1586 VNMLSH = 1570, 1587 VNMLSS = 1571, 1588 VNMULD = 1572, 1589 VNMULH = 1573, 1590 VNMULS = 1574, 1591 VORNd = 1575, 1592 VORNq = 1576, 1593 VORRd = 1577, 1594 VORRiv2i32 = 1578, 1595 VORRiv4i16 = 1579, 1596 VORRiv4i32 = 1580, 1597 VORRiv8i16 = 1581, 1598 VORRq = 1582, 1599 VPADALsv16i8 = 1583, 1600 VPADALsv2i32 = 1584, 1601 VPADALsv4i16 = 1585, 1602 VPADALsv4i32 = 1586, 1603 VPADALsv8i16 = 1587, 1604 VPADALsv8i8 = 1588, 1605 VPADALuv16i8 = 1589, 1606 VPADALuv2i32 = 1590, 1607 VPADALuv4i16 = 1591, 1608 VPADALuv4i32 = 1592, 1609 VPADALuv8i16 = 1593, 1610 VPADALuv8i8 = 1594, 1611 VPADDLsv16i8 = 1595, 1612 VPADDLsv2i32 = 1596, 1613 VPADDLsv4i16 = 1597, 1614 VPADDLsv4i32 = 1598, 1615 VPADDLsv8i16 = 1599, 1616 VPADDLsv8i8 = 1600, 1617 VPADDLuv16i8 = 1601, 1618 VPADDLuv2i32 = 1602, 1619 VPADDLuv4i16 = 1603, 1620 VPADDLuv4i32 = 1604, 1621 VPADDLuv8i16 = 1605, 1622 VPADDLuv8i8 = 1606, 1623 VPADDf = 1607, 1624 VPADDh = 1608, 1625 VPADDi16 = 1609, 1626 VPADDi32 = 1610, 1627 VPADDi8 = 1611, 1628 VPMAXf = 1612, 1629 VPMAXh = 1613, 1630 VPMAXs16 = 1614, 1631 VPMAXs32 = 1615, 1632 VPMAXs8 = 1616, 1633 VPMAXu16 = 1617, 1634 VPMAXu32 = 1618, 1635 VPMAXu8 = 1619, 1636 VPMINf = 1620, 1637 VPMINh = 1621, 1638 VPMINs16 = 1622, 1639 VPMINs32 = 1623, 1640 VPMINs8 = 1624, 1641 VPMINu16 = 1625, 1642 VPMINu32 = 1626, 1643 VPMINu8 = 1627, 1644 VQABSv16i8 = 1628, 1645 VQABSv2i32 = 1629, 1646 VQABSv4i16 = 1630, 1647 VQABSv4i32 = 1631, 1648 VQABSv8i16 = 1632, 1649 VQABSv8i8 = 1633, 1650 VQADDsv16i8 = 1634, 1651 VQADDsv1i64 = 1635, 1652 VQADDsv2i32 = 1636, 1653 VQADDsv2i64 = 1637, 1654 VQADDsv4i16 = 1638, 1655 VQADDsv4i32 = 1639, 1656 VQADDsv8i16 = 1640, 1657 VQADDsv8i8 = 1641, 1658 VQADDuv16i8 = 1642, 1659 VQADDuv1i64 = 1643, 1660 VQADDuv2i32 = 1644, 1661 VQADDuv2i64 = 1645, 1662 VQADDuv4i16 = 1646, 1663 VQADDuv4i32 = 1647, 1664 VQADDuv8i16 = 1648, 1665 VQADDuv8i8 = 1649, 1666 VQDMLALslv2i32 = 1650, 1667 VQDMLALslv4i16 = 1651, 1668 VQDMLALv2i64 = 1652, 1669 VQDMLALv4i32 = 1653, 1670 VQDMLSLslv2i32 = 1654, 1671 VQDMLSLslv4i16 = 1655, 1672 VQDMLSLv2i64 = 1656, 1673 VQDMLSLv4i32 = 1657, 1674 VQDMULHslv2i32 = 1658, 1675 VQDMULHslv4i16 = 1659, 1676 VQDMULHslv4i32 = 1660, 1677 VQDMULHslv8i16 = 1661, 1678 VQDMULHv2i32 = 1662, 1679 VQDMULHv4i16 = 1663, 1680 VQDMULHv4i32 = 1664, 1681 VQDMULHv8i16 = 1665, 1682 VQDMULLslv2i32 = 1666, 1683 VQDMULLslv4i16 = 1667, 1684 VQDMULLv2i64 = 1668, 1685 VQDMULLv4i32 = 1669, 1686 VQMOVNsuv2i32 = 1670, 1687 VQMOVNsuv4i16 = 1671, 1688 VQMOVNsuv8i8 = 1672, 1689 VQMOVNsv2i32 = 1673, 1690 VQMOVNsv4i16 = 1674, 1691 VQMOVNsv8i8 = 1675, 1692 VQMOVNuv2i32 = 1676, 1693 VQMOVNuv4i16 = 1677, 1694 VQMOVNuv8i8 = 1678, 1695 VQNEGv16i8 = 1679, 1696 VQNEGv2i32 = 1680, 1697 VQNEGv4i16 = 1681, 1698 VQNEGv4i32 = 1682, 1699 VQNEGv8i16 = 1683, 1700 VQNEGv8i8 = 1684, 1701 VQRDMLAHslv2i32 = 1685, 1702 VQRDMLAHslv4i16 = 1686, 1703 VQRDMLAHslv4i32 = 1687, 1704 VQRDMLAHslv8i16 = 1688, 1705 VQRDMLAHv2i32 = 1689, 1706 VQRDMLAHv4i16 = 1690, 1707 VQRDMLAHv4i32 = 1691, 1708 VQRDMLAHv8i16 = 1692, 1709 VQRDMLSHslv2i32 = 1693, 1710 VQRDMLSHslv4i16 = 1694, 1711 VQRDMLSHslv4i32 = 1695, 1712 VQRDMLSHslv8i16 = 1696, 1713 VQRDMLSHv2i32 = 1697, 1714 VQRDMLSHv4i16 = 1698, 1715 VQRDMLSHv4i32 = 1699, 1716 VQRDMLSHv8i16 = 1700, 1717 VQRDMULHslv2i32 = 1701, 1718 VQRDMULHslv4i16 = 1702, 1719 VQRDMULHslv4i32 = 1703, 1720 VQRDMULHslv8i16 = 1704, 1721 VQRDMULHv2i32 = 1705, 1722 VQRDMULHv4i16 = 1706, 1723 VQRDMULHv4i32 = 1707, 1724 VQRDMULHv8i16 = 1708, 1725 VQRSHLsv16i8 = 1709, 1726 VQRSHLsv1i64 = 1710, 1727 VQRSHLsv2i32 = 1711, 1728 VQRSHLsv2i64 = 1712, 1729 VQRSHLsv4i16 = 1713, 1730 VQRSHLsv4i32 = 1714, 1731 VQRSHLsv8i16 = 1715, 1732 VQRSHLsv8i8 = 1716, 1733 VQRSHLuv16i8 = 1717, 1734 VQRSHLuv1i64 = 1718, 1735 VQRSHLuv2i32 = 1719, 1736 VQRSHLuv2i64 = 1720, 1737 VQRSHLuv4i16 = 1721, 1738 VQRSHLuv4i32 = 1722, 1739 VQRSHLuv8i16 = 1723, 1740 VQRSHLuv8i8 = 1724, 1741 VQRSHRNsv2i32 = 1725, 1742 VQRSHRNsv4i16 = 1726, 1743 VQRSHRNsv8i8 = 1727, 1744 VQRSHRNuv2i32 = 1728, 1745 VQRSHRNuv4i16 = 1729, 1746 VQRSHRNuv8i8 = 1730, 1747 VQRSHRUNv2i32 = 1731, 1748 VQRSHRUNv4i16 = 1732, 1749 VQRSHRUNv8i8 = 1733, 1750 VQSHLsiv16i8 = 1734, 1751 VQSHLsiv1i64 = 1735, 1752 VQSHLsiv2i32 = 1736, 1753 VQSHLsiv2i64 = 1737, 1754 VQSHLsiv4i16 = 1738, 1755 VQSHLsiv4i32 = 1739, 1756 VQSHLsiv8i16 = 1740, 1757 VQSHLsiv8i8 = 1741, 1758 VQSHLsuv16i8 = 1742, 1759 VQSHLsuv1i64 = 1743, 1760 VQSHLsuv2i32 = 1744, 1761 VQSHLsuv2i64 = 1745, 1762 VQSHLsuv4i16 = 1746, 1763 VQSHLsuv4i32 = 1747, 1764 VQSHLsuv8i16 = 1748, 1765 VQSHLsuv8i8 = 1749, 1766 VQSHLsv16i8 = 1750, 1767 VQSHLsv1i64 = 1751, 1768 VQSHLsv2i32 = 1752, 1769 VQSHLsv2i64 = 1753, 1770 VQSHLsv4i16 = 1754, 1771 VQSHLsv4i32 = 1755, 1772 VQSHLsv8i16 = 1756, 1773 VQSHLsv8i8 = 1757, 1774 VQSHLuiv16i8 = 1758, 1775 VQSHLuiv1i64 = 1759, 1776 VQSHLuiv2i32 = 1760, 1777 VQSHLuiv2i64 = 1761, 1778 VQSHLuiv4i16 = 1762, 1779 VQSHLuiv4i32 = 1763, 1780 VQSHLuiv8i16 = 1764, 1781 VQSHLuiv8i8 = 1765, 1782 VQSHLuv16i8 = 1766, 1783 VQSHLuv1i64 = 1767, 1784 VQSHLuv2i32 = 1768, 1785 VQSHLuv2i64 = 1769, 1786 VQSHLuv4i16 = 1770, 1787 VQSHLuv4i32 = 1771, 1788 VQSHLuv8i16 = 1772, 1789 VQSHLuv8i8 = 1773, 1790 VQSHRNsv2i32 = 1774, 1791 VQSHRNsv4i16 = 1775, 1792 VQSHRNsv8i8 = 1776, 1793 VQSHRNuv2i32 = 1777, 1794 VQSHRNuv4i16 = 1778, 1795 VQSHRNuv8i8 = 1779, 1796 VQSHRUNv2i32 = 1780, 1797 VQSHRUNv4i16 = 1781, 1798 VQSHRUNv8i8 = 1782, 1799 VQSUBsv16i8 = 1783, 1800 VQSUBsv1i64 = 1784, 1801 VQSUBsv2i32 = 1785, 1802 VQSUBsv2i64 = 1786, 1803 VQSUBsv4i16 = 1787, 1804 VQSUBsv4i32 = 1788, 1805 VQSUBsv8i16 = 1789, 1806 VQSUBsv8i8 = 1790, 1807 VQSUBuv16i8 = 1791, 1808 VQSUBuv1i64 = 1792, 1809 VQSUBuv2i32 = 1793, 1810 VQSUBuv2i64 = 1794, 1811 VQSUBuv4i16 = 1795, 1812 VQSUBuv4i32 = 1796, 1813 VQSUBuv8i16 = 1797, 1814 VQSUBuv8i8 = 1798, 1815 VRADDHNv2i32 = 1799, 1816 VRADDHNv4i16 = 1800, 1817 VRADDHNv8i8 = 1801, 1818 VRECPEd = 1802, 1819 VRECPEfd = 1803, 1820 VRECPEfq = 1804, 1821 VRECPEhd = 1805, 1822 VRECPEhq = 1806, 1823 VRECPEq = 1807, 1824 VRECPSfd = 1808, 1825 VRECPSfq = 1809, 1826 VRECPShd = 1810, 1827 VRECPShq = 1811, 1828 VREV16d8 = 1812, 1829 VREV16q8 = 1813, 1830 VREV32d16 = 1814, 1831 VREV32d8 = 1815, 1832 VREV32q16 = 1816, 1833 VREV32q8 = 1817, 1834 VREV64d16 = 1818, 1835 VREV64d32 = 1819, 1836 VREV64d8 = 1820, 1837 VREV64q16 = 1821, 1838 VREV64q32 = 1822, 1839 VREV64q8 = 1823, 1840 VRHADDsv16i8 = 1824, 1841 VRHADDsv2i32 = 1825, 1842 VRHADDsv4i16 = 1826, 1843 VRHADDsv4i32 = 1827, 1844 VRHADDsv8i16 = 1828, 1845 VRHADDsv8i8 = 1829, 1846 VRHADDuv16i8 = 1830, 1847 VRHADDuv2i32 = 1831, 1848 VRHADDuv4i16 = 1832, 1849 VRHADDuv4i32 = 1833, 1850 VRHADDuv8i16 = 1834, 1851 VRHADDuv8i8 = 1835, 1852 VRINTAD = 1836, 1853 VRINTAH = 1837, 1854 VRINTANDf = 1838, 1855 VRINTANDh = 1839, 1856 VRINTANQf = 1840, 1857 VRINTANQh = 1841, 1858 VRINTAS = 1842, 1859 VRINTMD = 1843, 1860 VRINTMH = 1844, 1861 VRINTMNDf = 1845, 1862 VRINTMNDh = 1846, 1863 VRINTMNQf = 1847, 1864 VRINTMNQh = 1848, 1865 VRINTMS = 1849, 1866 VRINTND = 1850, 1867 VRINTNH = 1851, 1868 VRINTNNDf = 1852, 1869 VRINTNNDh = 1853, 1870 VRINTNNQf = 1854, 1871 VRINTNNQh = 1855, 1872 VRINTNS = 1856, 1873 VRINTPD = 1857, 1874 VRINTPH = 1858, 1875 VRINTPNDf = 1859, 1876 VRINTPNDh = 1860, 1877 VRINTPNQf = 1861, 1878 VRINTPNQh = 1862, 1879 VRINTPS = 1863, 1880 VRINTRD = 1864, 1881 VRINTRH = 1865, 1882 VRINTRS = 1866, 1883 VRINTXD = 1867, 1884 VRINTXH = 1868, 1885 VRINTXNDf = 1869, 1886 VRINTXNDh = 1870, 1887 VRINTXNQf = 1871, 1888 VRINTXNQh = 1872, 1889 VRINTXS = 1873, 1890 VRINTZD = 1874, 1891 VRINTZH = 1875, 1892 VRINTZNDf = 1876, 1893 VRINTZNDh = 1877, 1894 VRINTZNQf = 1878, 1895 VRINTZNQh = 1879, 1896 VRINTZS = 1880, 1897 VRSHLsv16i8 = 1881, 1898 VRSHLsv1i64 = 1882, 1899 VRSHLsv2i32 = 1883, 1900 VRSHLsv2i64 = 1884, 1901 VRSHLsv4i16 = 1885, 1902 VRSHLsv4i32 = 1886, 1903 VRSHLsv8i16 = 1887, 1904 VRSHLsv8i8 = 1888, 1905 VRSHLuv16i8 = 1889, 1906 VRSHLuv1i64 = 1890, 1907 VRSHLuv2i32 = 1891, 1908 VRSHLuv2i64 = 1892, 1909 VRSHLuv4i16 = 1893, 1910 VRSHLuv4i32 = 1894, 1911 VRSHLuv8i16 = 1895, 1912 VRSHLuv8i8 = 1896, 1913 VRSHRNv2i32 = 1897, 1914 VRSHRNv4i16 = 1898, 1915 VRSHRNv8i8 = 1899, 1916 VRSHRsv16i8 = 1900, 1917 VRSHRsv1i64 = 1901, 1918 VRSHRsv2i32 = 1902, 1919 VRSHRsv2i64 = 1903, 1920 VRSHRsv4i16 = 1904, 1921 VRSHRsv4i32 = 1905, 1922 VRSHRsv8i16 = 1906, 1923 VRSHRsv8i8 = 1907, 1924 VRSHRuv16i8 = 1908, 1925 VRSHRuv1i64 = 1909, 1926 VRSHRuv2i32 = 1910, 1927 VRSHRuv2i64 = 1911, 1928 VRSHRuv4i16 = 1912, 1929 VRSHRuv4i32 = 1913, 1930 VRSHRuv8i16 = 1914, 1931 VRSHRuv8i8 = 1915, 1932 VRSQRTEd = 1916, 1933 VRSQRTEfd = 1917, 1934 VRSQRTEfq = 1918, 1935 VRSQRTEhd = 1919, 1936 VRSQRTEhq = 1920, 1937 VRSQRTEq = 1921, 1938 VRSQRTSfd = 1922, 1939 VRSQRTSfq = 1923, 1940 VRSQRTShd = 1924, 1941 VRSQRTShq = 1925, 1942 VRSRAsv16i8 = 1926, 1943 VRSRAsv1i64 = 1927, 1944 VRSRAsv2i32 = 1928, 1945 VRSRAsv2i64 = 1929, 1946 VRSRAsv4i16 = 1930, 1947 VRSRAsv4i32 = 1931, 1948 VRSRAsv8i16 = 1932, 1949 VRSRAsv8i8 = 1933, 1950 VRSRAuv16i8 = 1934, 1951 VRSRAuv1i64 = 1935, 1952 VRSRAuv2i32 = 1936, 1953 VRSRAuv2i64 = 1937, 1954 VRSRAuv4i16 = 1938, 1955 VRSRAuv4i32 = 1939, 1956 VRSRAuv8i16 = 1940, 1957 VRSRAuv8i8 = 1941, 1958 VRSUBHNv2i32 = 1942, 1959 VRSUBHNv4i16 = 1943, 1960 VRSUBHNv8i8 = 1944, 1961 VSELEQD = 1945, 1962 VSELEQH = 1946, 1963 VSELEQS = 1947, 1964 VSELGED = 1948, 1965 VSELGEH = 1949, 1966 VSELGES = 1950, 1967 VSELGTD = 1951, 1968 VSELGTH = 1952, 1969 VSELGTS = 1953, 1970 VSELVSD = 1954, 1971 VSELVSH = 1955, 1972 VSELVSS = 1956, 1973 VSETLNi16 = 1957, 1974 VSETLNi32 = 1958, 1975 VSETLNi8 = 1959, 1976 VSHLLi16 = 1960, 1977 VSHLLi32 = 1961, 1978 VSHLLi8 = 1962, 1979 VSHLLsv2i64 = 1963, 1980 VSHLLsv4i32 = 1964, 1981 VSHLLsv8i16 = 1965, 1982 VSHLLuv2i64 = 1966, 1983 VSHLLuv4i32 = 1967, 1984 VSHLLuv8i16 = 1968, 1985 VSHLiv16i8 = 1969, 1986 VSHLiv1i64 = 1970, 1987 VSHLiv2i32 = 1971, 1988 VSHLiv2i64 = 1972, 1989 VSHLiv4i16 = 1973, 1990 VSHLiv4i32 = 1974, 1991 VSHLiv8i16 = 1975, 1992 VSHLiv8i8 = 1976, 1993 VSHLsv16i8 = 1977, 1994 VSHLsv1i64 = 1978, 1995 VSHLsv2i32 = 1979, 1996 VSHLsv2i64 = 1980, 1997 VSHLsv4i16 = 1981, 1998 VSHLsv4i32 = 1982, 1999 VSHLsv8i16 = 1983, 2000 VSHLsv8i8 = 1984, 2001 VSHLuv16i8 = 1985, 2002 VSHLuv1i64 = 1986, 2003 VSHLuv2i32 = 1987, 2004 VSHLuv2i64 = 1988, 2005 VSHLuv4i16 = 1989, 2006 VSHLuv4i32 = 1990, 2007 VSHLuv8i16 = 1991, 2008 VSHLuv8i8 = 1992, 2009 VSHRNv2i32 = 1993, 2010 VSHRNv4i16 = 1994, 2011 VSHRNv8i8 = 1995, 2012 VSHRsv16i8 = 1996, 2013 VSHRsv1i64 = 1997, 2014 VSHRsv2i32 = 1998, 2015 VSHRsv2i64 = 1999, 2016 VSHRsv4i16 = 2000, 2017 VSHRsv4i32 = 2001, 2018 VSHRsv8i16 = 2002, 2019 VSHRsv8i8 = 2003, 2020 VSHRuv16i8 = 2004, 2021 VSHRuv1i64 = 2005, 2022 VSHRuv2i32 = 2006, 2023 VSHRuv2i64 = 2007, 2024 VSHRuv4i16 = 2008, 2025 VSHRuv4i32 = 2009, 2026 VSHRuv8i16 = 2010, 2027 VSHRuv8i8 = 2011, 2028 VSHTOD = 2012, 2029 VSHTOH = 2013, 2030 VSHTOS = 2014, 2031 VSITOD = 2015, 2032 VSITOH = 2016, 2033 VSITOS = 2017, 2034 VSLIv16i8 = 2018, 2035 VSLIv1i64 = 2019, 2036 VSLIv2i32 = 2020, 2037 VSLIv2i64 = 2021, 2038 VSLIv4i16 = 2022, 2039 VSLIv4i32 = 2023, 2040 VSLIv8i16 = 2024, 2041 VSLIv8i8 = 2025, 2042 VSLTOD = 2026, 2043 VSLTOH = 2027, 2044 VSLTOS = 2028, 2045 VSQRTD = 2029, 2046 VSQRTH = 2030, 2047 VSQRTS = 2031, 2048 VSRAsv16i8 = 2032, 2049 VSRAsv1i64 = 2033, 2050 VSRAsv2i32 = 2034, 2051 VSRAsv2i64 = 2035, 2052 VSRAsv4i16 = 2036, 2053 VSRAsv4i32 = 2037, 2054 VSRAsv8i16 = 2038, 2055 VSRAsv8i8 = 2039, 2056 VSRAuv16i8 = 2040, 2057 VSRAuv1i64 = 2041, 2058 VSRAuv2i32 = 2042, 2059 VSRAuv2i64 = 2043, 2060 VSRAuv4i16 = 2044, 2061 VSRAuv4i32 = 2045, 2062 VSRAuv8i16 = 2046, 2063 VSRAuv8i8 = 2047, 2064 VSRIv16i8 = 2048, 2065 VSRIv1i64 = 2049, 2066 VSRIv2i32 = 2050, 2067 VSRIv2i64 = 2051, 2068 VSRIv4i16 = 2052, 2069 VSRIv4i32 = 2053, 2070 VSRIv8i16 = 2054, 2071 VSRIv8i8 = 2055, 2072 VST1LNd16 = 2056, 2073 VST1LNd16_UPD = 2057, 2074 VST1LNd32 = 2058, 2075 VST1LNd32_UPD = 2059, 2076 VST1LNd8 = 2060, 2077 VST1LNd8_UPD = 2061, 2078 VST1LNdAsm_16 = 2062, 2079 VST1LNdAsm_32 = 2063, 2080 VST1LNdAsm_8 = 2064, 2081 VST1LNdWB_fixed_Asm_16 = 2065, 2082 VST1LNdWB_fixed_Asm_32 = 2066, 2083 VST1LNdWB_fixed_Asm_8 = 2067, 2084 VST1LNdWB_register_Asm_16 = 2068, 2085 VST1LNdWB_register_Asm_32 = 2069, 2086 VST1LNdWB_register_Asm_8 = 2070, 2087 VST1LNq16Pseudo = 2071, 2088 VST1LNq16Pseudo_UPD = 2072, 2089 VST1LNq32Pseudo = 2073, 2090 VST1LNq32Pseudo_UPD = 2074, 2091 VST1LNq8Pseudo = 2075, 2092 VST1LNq8Pseudo_UPD = 2076, 2093 VST1d16 = 2077, 2094 VST1d16Q = 2078, 2095 VST1d16Qwb_fixed = 2079, 2096 VST1d16Qwb_register = 2080, 2097 VST1d16T = 2081, 2098 VST1d16Twb_fixed = 2082, 2099 VST1d16Twb_register = 2083, 2100 VST1d16wb_fixed = 2084, 2101 VST1d16wb_register = 2085, 2102 VST1d32 = 2086, 2103 VST1d32Q = 2087, 2104 VST1d32Qwb_fixed = 2088, 2105 VST1d32Qwb_register = 2089, 2106 VST1d32T = 2090, 2107 VST1d32Twb_fixed = 2091, 2108 VST1d32Twb_register = 2092, 2109 VST1d32wb_fixed = 2093, 2110 VST1d32wb_register = 2094, 2111 VST1d64 = 2095, 2112 VST1d64Q = 2096, 2113 VST1d64QPseudo = 2097, 2114 VST1d64QPseudoWB_fixed = 2098, 2115 VST1d64QPseudoWB_register = 2099, 2116 VST1d64Qwb_fixed = 2100, 2117 VST1d64Qwb_register = 2101, 2118 VST1d64T = 2102, 2119 VST1d64TPseudo = 2103, 2120 VST1d64TPseudoWB_fixed = 2104, 2121 VST1d64TPseudoWB_register = 2105, 2122 VST1d64Twb_fixed = 2106, 2123 VST1d64Twb_register = 2107, 2124 VST1d64wb_fixed = 2108, 2125 VST1d64wb_register = 2109, 2126 VST1d8 = 2110, 2127 VST1d8Q = 2111, 2128 VST1d8Qwb_fixed = 2112, 2129 VST1d8Qwb_register = 2113, 2130 VST1d8T = 2114, 2131 VST1d8Twb_fixed = 2115, 2132 VST1d8Twb_register = 2116, 2133 VST1d8wb_fixed = 2117, 2134 VST1d8wb_register = 2118, 2135 VST1q16 = 2119, 2136 VST1q16wb_fixed = 2120, 2137 VST1q16wb_register = 2121, 2138 VST1q32 = 2122, 2139 VST1q32wb_fixed = 2123, 2140 VST1q32wb_register = 2124, 2141 VST1q64 = 2125, 2142 VST1q64wb_fixed = 2126, 2143 VST1q64wb_register = 2127, 2144 VST1q8 = 2128, 2145 VST1q8wb_fixed = 2129, 2146 VST1q8wb_register = 2130, 2147 VST2LNd16 = 2131, 2148 VST2LNd16Pseudo = 2132, 2149 VST2LNd16Pseudo_UPD = 2133, 2150 VST2LNd16_UPD = 2134, 2151 VST2LNd32 = 2135, 2152 VST2LNd32Pseudo = 2136, 2153 VST2LNd32Pseudo_UPD = 2137, 2154 VST2LNd32_UPD = 2138, 2155 VST2LNd8 = 2139, 2156 VST2LNd8Pseudo = 2140, 2157 VST2LNd8Pseudo_UPD = 2141, 2158 VST2LNd8_UPD = 2142, 2159 VST2LNdAsm_16 = 2143, 2160 VST2LNdAsm_32 = 2144, 2161 VST2LNdAsm_8 = 2145, 2162 VST2LNdWB_fixed_Asm_16 = 2146, 2163 VST2LNdWB_fixed_Asm_32 = 2147, 2164 VST2LNdWB_fixed_Asm_8 = 2148, 2165 VST2LNdWB_register_Asm_16 = 2149, 2166 VST2LNdWB_register_Asm_32 = 2150, 2167 VST2LNdWB_register_Asm_8 = 2151, 2168 VST2LNq16 = 2152, 2169 VST2LNq16Pseudo = 2153, 2170 VST2LNq16Pseudo_UPD = 2154, 2171 VST2LNq16_UPD = 2155, 2172 VST2LNq32 = 2156, 2173 VST2LNq32Pseudo = 2157, 2174 VST2LNq32Pseudo_UPD = 2158, 2175 VST2LNq32_UPD = 2159, 2176 VST2LNqAsm_16 = 2160, 2177 VST2LNqAsm_32 = 2161, 2178 VST2LNqWB_fixed_Asm_16 = 2162, 2179 VST2LNqWB_fixed_Asm_32 = 2163, 2180 VST2LNqWB_register_Asm_16 = 2164, 2181 VST2LNqWB_register_Asm_32 = 2165, 2182 VST2b16 = 2166, 2183 VST2b16wb_fixed = 2167, 2184 VST2b16wb_register = 2168, 2185 VST2b32 = 2169, 2186 VST2b32wb_fixed = 2170, 2187 VST2b32wb_register = 2171, 2188 VST2b8 = 2172, 2189 VST2b8wb_fixed = 2173, 2190 VST2b8wb_register = 2174, 2191 VST2d16 = 2175, 2192 VST2d16wb_fixed = 2176, 2193 VST2d16wb_register = 2177, 2194 VST2d32 = 2178, 2195 VST2d32wb_fixed = 2179, 2196 VST2d32wb_register = 2180, 2197 VST2d8 = 2181, 2198 VST2d8wb_fixed = 2182, 2199 VST2d8wb_register = 2183, 2200 VST2q16 = 2184, 2201 VST2q16Pseudo = 2185, 2202 VST2q16PseudoWB_fixed = 2186, 2203 VST2q16PseudoWB_register = 2187, 2204 VST2q16wb_fixed = 2188, 2205 VST2q16wb_register = 2189, 2206 VST2q32 = 2190, 2207 VST2q32Pseudo = 2191, 2208 VST2q32PseudoWB_fixed = 2192, 2209 VST2q32PseudoWB_register = 2193, 2210 VST2q32wb_fixed = 2194, 2211 VST2q32wb_register = 2195, 2212 VST2q8 = 2196, 2213 VST2q8Pseudo = 2197, 2214 VST2q8PseudoWB_fixed = 2198, 2215 VST2q8PseudoWB_register = 2199, 2216 VST2q8wb_fixed = 2200, 2217 VST2q8wb_register = 2201, 2218 VST3LNd16 = 2202, 2219 VST3LNd16Pseudo = 2203, 2220 VST3LNd16Pseudo_UPD = 2204, 2221 VST3LNd16_UPD = 2205, 2222 VST3LNd32 = 2206, 2223 VST3LNd32Pseudo = 2207, 2224 VST3LNd32Pseudo_UPD = 2208, 2225 VST3LNd32_UPD = 2209, 2226 VST3LNd8 = 2210, 2227 VST3LNd8Pseudo = 2211, 2228 VST3LNd8Pseudo_UPD = 2212, 2229 VST3LNd8_UPD = 2213, 2230 VST3LNdAsm_16 = 2214, 2231 VST3LNdAsm_32 = 2215, 2232 VST3LNdAsm_8 = 2216, 2233 VST3LNdWB_fixed_Asm_16 = 2217, 2234 VST3LNdWB_fixed_Asm_32 = 2218, 2235 VST3LNdWB_fixed_Asm_8 = 2219, 2236 VST3LNdWB_register_Asm_16 = 2220, 2237 VST3LNdWB_register_Asm_32 = 2221, 2238 VST3LNdWB_register_Asm_8 = 2222, 2239 VST3LNq16 = 2223, 2240 VST3LNq16Pseudo = 2224, 2241 VST3LNq16Pseudo_UPD = 2225, 2242 VST3LNq16_UPD = 2226, 2243 VST3LNq32 = 2227, 2244 VST3LNq32Pseudo = 2228, 2245 VST3LNq32Pseudo_UPD = 2229, 2246 VST3LNq32_UPD = 2230, 2247 VST3LNqAsm_16 = 2231, 2248 VST3LNqAsm_32 = 2232, 2249 VST3LNqWB_fixed_Asm_16 = 2233, 2250 VST3LNqWB_fixed_Asm_32 = 2234, 2251 VST3LNqWB_register_Asm_16 = 2235, 2252 VST3LNqWB_register_Asm_32 = 2236, 2253 VST3d16 = 2237, 2254 VST3d16Pseudo = 2238, 2255 VST3d16Pseudo_UPD = 2239, 2256 VST3d16_UPD = 2240, 2257 VST3d32 = 2241, 2258 VST3d32Pseudo = 2242, 2259 VST3d32Pseudo_UPD = 2243, 2260 VST3d32_UPD = 2244, 2261 VST3d8 = 2245, 2262 VST3d8Pseudo = 2246, 2263 VST3d8Pseudo_UPD = 2247, 2264 VST3d8_UPD = 2248, 2265 VST3dAsm_16 = 2249, 2266 VST3dAsm_32 = 2250, 2267 VST3dAsm_8 = 2251, 2268 VST3dWB_fixed_Asm_16 = 2252, 2269 VST3dWB_fixed_Asm_32 = 2253, 2270 VST3dWB_fixed_Asm_8 = 2254, 2271 VST3dWB_register_Asm_16 = 2255, 2272 VST3dWB_register_Asm_32 = 2256, 2273 VST3dWB_register_Asm_8 = 2257, 2274 VST3q16 = 2258, 2275 VST3q16Pseudo_UPD = 2259, 2276 VST3q16_UPD = 2260, 2277 VST3q16oddPseudo = 2261, 2278 VST3q16oddPseudo_UPD = 2262, 2279 VST3q32 = 2263, 2280 VST3q32Pseudo_UPD = 2264, 2281 VST3q32_UPD = 2265, 2282 VST3q32oddPseudo = 2266, 2283 VST3q32oddPseudo_UPD = 2267, 2284 VST3q8 = 2268, 2285 VST3q8Pseudo_UPD = 2269, 2286 VST3q8_UPD = 2270, 2287 VST3q8oddPseudo = 2271, 2288 VST3q8oddPseudo_UPD = 2272, 2289 VST3qAsm_16 = 2273, 2290 VST3qAsm_32 = 2274, 2291 VST3qAsm_8 = 2275, 2292 VST3qWB_fixed_Asm_16 = 2276, 2293 VST3qWB_fixed_Asm_32 = 2277, 2294 VST3qWB_fixed_Asm_8 = 2278, 2295 VST3qWB_register_Asm_16 = 2279, 2296 VST3qWB_register_Asm_32 = 2280, 2297 VST3qWB_register_Asm_8 = 2281, 2298 VST4LNd16 = 2282, 2299 VST4LNd16Pseudo = 2283, 2300 VST4LNd16Pseudo_UPD = 2284, 2301 VST4LNd16_UPD = 2285, 2302 VST4LNd32 = 2286, 2303 VST4LNd32Pseudo = 2287, 2304 VST4LNd32Pseudo_UPD = 2288, 2305 VST4LNd32_UPD = 2289, 2306 VST4LNd8 = 2290, 2307 VST4LNd8Pseudo = 2291, 2308 VST4LNd8Pseudo_UPD = 2292, 2309 VST4LNd8_UPD = 2293, 2310 VST4LNdAsm_16 = 2294, 2311 VST4LNdAsm_32 = 2295, 2312 VST4LNdAsm_8 = 2296, 2313 VST4LNdWB_fixed_Asm_16 = 2297, 2314 VST4LNdWB_fixed_Asm_32 = 2298, 2315 VST4LNdWB_fixed_Asm_8 = 2299, 2316 VST4LNdWB_register_Asm_16 = 2300, 2317 VST4LNdWB_register_Asm_32 = 2301, 2318 VST4LNdWB_register_Asm_8 = 2302, 2319 VST4LNq16 = 2303, 2320 VST4LNq16Pseudo = 2304, 2321 VST4LNq16Pseudo_UPD = 2305, 2322 VST4LNq16_UPD = 2306, 2323 VST4LNq32 = 2307, 2324 VST4LNq32Pseudo = 2308, 2325 VST4LNq32Pseudo_UPD = 2309, 2326 VST4LNq32_UPD = 2310, 2327 VST4LNqAsm_16 = 2311, 2328 VST4LNqAsm_32 = 2312, 2329 VST4LNqWB_fixed_Asm_16 = 2313, 2330 VST4LNqWB_fixed_Asm_32 = 2314, 2331 VST4LNqWB_register_Asm_16 = 2315, 2332 VST4LNqWB_register_Asm_32 = 2316, 2333 VST4d16 = 2317, 2334 VST4d16Pseudo = 2318, 2335 VST4d16Pseudo_UPD = 2319, 2336 VST4d16_UPD = 2320, 2337 VST4d32 = 2321, 2338 VST4d32Pseudo = 2322, 2339 VST4d32Pseudo_UPD = 2323, 2340 VST4d32_UPD = 2324, 2341 VST4d8 = 2325, 2342 VST4d8Pseudo = 2326, 2343 VST4d8Pseudo_UPD = 2327, 2344 VST4d8_UPD = 2328, 2345 VST4dAsm_16 = 2329, 2346 VST4dAsm_32 = 2330, 2347 VST4dAsm_8 = 2331, 2348 VST4dWB_fixed_Asm_16 = 2332, 2349 VST4dWB_fixed_Asm_32 = 2333, 2350 VST4dWB_fixed_Asm_8 = 2334, 2351 VST4dWB_register_Asm_16 = 2335, 2352 VST4dWB_register_Asm_32 = 2336, 2353 VST4dWB_register_Asm_8 = 2337, 2354 VST4q16 = 2338, 2355 VST4q16Pseudo_UPD = 2339, 2356 VST4q16_UPD = 2340, 2357 VST4q16oddPseudo = 2341, 2358 VST4q16oddPseudo_UPD = 2342, 2359 VST4q32 = 2343, 2360 VST4q32Pseudo_UPD = 2344, 2361 VST4q32_UPD = 2345, 2362 VST4q32oddPseudo = 2346, 2363 VST4q32oddPseudo_UPD = 2347, 2364 VST4q8 = 2348, 2365 VST4q8Pseudo_UPD = 2349, 2366 VST4q8_UPD = 2350, 2367 VST4q8oddPseudo = 2351, 2368 VST4q8oddPseudo_UPD = 2352, 2369 VST4qAsm_16 = 2353, 2370 VST4qAsm_32 = 2354, 2371 VST4qAsm_8 = 2355, 2372 VST4qWB_fixed_Asm_16 = 2356, 2373 VST4qWB_fixed_Asm_32 = 2357, 2374 VST4qWB_fixed_Asm_8 = 2358, 2375 VST4qWB_register_Asm_16 = 2359, 2376 VST4qWB_register_Asm_32 = 2360, 2377 VST4qWB_register_Asm_8 = 2361, 2378 VSTMDDB_UPD = 2362, 2379 VSTMDIA = 2363, 2380 VSTMDIA_UPD = 2364, 2381 VSTMQIA = 2365, 2382 VSTMSDB_UPD = 2366, 2383 VSTMSIA = 2367, 2384 VSTMSIA_UPD = 2368, 2385 VSTRD = 2369, 2386 VSTRH = 2370, 2387 VSTRS = 2371, 2388 VSUBD = 2372, 2389 VSUBH = 2373, 2390 VSUBHNv2i32 = 2374, 2391 VSUBHNv4i16 = 2375, 2392 VSUBHNv8i8 = 2376, 2393 VSUBLsv2i64 = 2377, 2394 VSUBLsv4i32 = 2378, 2395 VSUBLsv8i16 = 2379, 2396 VSUBLuv2i64 = 2380, 2397 VSUBLuv4i32 = 2381, 2398 VSUBLuv8i16 = 2382, 2399 VSUBS = 2383, 2400 VSUBWsv2i64 = 2384, 2401 VSUBWsv4i32 = 2385, 2402 VSUBWsv8i16 = 2386, 2403 VSUBWuv2i64 = 2387, 2404 VSUBWuv4i32 = 2388, 2405 VSUBWuv8i16 = 2389, 2406 VSUBfd = 2390, 2407 VSUBfq = 2391, 2408 VSUBhd = 2392, 2409 VSUBhq = 2393, 2410 VSUBv16i8 = 2394, 2411 VSUBv1i64 = 2395, 2412 VSUBv2i32 = 2396, 2413 VSUBv2i64 = 2397, 2414 VSUBv4i16 = 2398, 2415 VSUBv4i32 = 2399, 2416 VSUBv8i16 = 2400, 2417 VSUBv8i8 = 2401, 2418 VSWPd = 2402, 2419 VSWPq = 2403, 2420 VTBL1 = 2404, 2421 VTBL2 = 2405, 2422 VTBL3 = 2406, 2423 VTBL3Pseudo = 2407, 2424 VTBL4 = 2408, 2425 VTBL4Pseudo = 2409, 2426 VTBX1 = 2410, 2427 VTBX2 = 2411, 2428 VTBX3 = 2412, 2429 VTBX3Pseudo = 2413, 2430 VTBX4 = 2414, 2431 VTBX4Pseudo = 2415, 2432 VTOSHD = 2416, 2433 VTOSHH = 2417, 2434 VTOSHS = 2418, 2435 VTOSIRD = 2419, 2436 VTOSIRH = 2420, 2437 VTOSIRS = 2421, 2438 VTOSIZD = 2422, 2439 VTOSIZH = 2423, 2440 VTOSIZS = 2424, 2441 VTOSLD = 2425, 2442 VTOSLH = 2426, 2443 VTOSLS = 2427, 2444 VTOUHD = 2428, 2445 VTOUHH = 2429, 2446 VTOUHS = 2430, 2447 VTOUIRD = 2431, 2448 VTOUIRH = 2432, 2449 VTOUIRS = 2433, 2450 VTOUIZD = 2434, 2451 VTOUIZH = 2435, 2452 VTOUIZS = 2436, 2453 VTOULD = 2437, 2454 VTOULH = 2438, 2455 VTOULS = 2439, 2456 VTRNd16 = 2440, 2457 VTRNd32 = 2441, 2458 VTRNd8 = 2442, 2459 VTRNq16 = 2443, 2460 VTRNq32 = 2444, 2461 VTRNq8 = 2445, 2462 VTSTv16i8 = 2446, 2463 VTSTv2i32 = 2447, 2464 VTSTv4i16 = 2448, 2465 VTSTv4i32 = 2449, 2466 VTSTv8i16 = 2450, 2467 VTSTv8i8 = 2451, 2468 VUHTOD = 2452, 2469 VUHTOH = 2453, 2470 VUHTOS = 2454, 2471 VUITOD = 2455, 2472 VUITOH = 2456, 2473 VUITOS = 2457, 2474 VULTOD = 2458, 2475 VULTOH = 2459, 2476 VULTOS = 2460, 2477 VUZPd16 = 2461, 2478 VUZPd8 = 2462, 2479 VUZPq16 = 2463, 2480 VUZPq32 = 2464, 2481 VUZPq8 = 2465, 2482 VZIPd16 = 2466, 2483 VZIPd8 = 2467, 2484 VZIPq16 = 2468, 2485 VZIPq32 = 2469, 2486 VZIPq8 = 2470, 2487 WIN__CHKSTK = 2471, 2488 WIN__DBZCHK = 2472, 2489 sysLDMDA = 2473, 2490 sysLDMDA_UPD = 2474, 2491 sysLDMDB = 2475, 2492 sysLDMDB_UPD = 2476, 2493 sysLDMIA = 2477, 2494 sysLDMIA_UPD = 2478, 2495 sysLDMIB = 2479, 2496 sysLDMIB_UPD = 2480, 2497 sysSTMDA = 2481, 2498 sysSTMDA_UPD = 2482, 2499 sysSTMDB = 2483, 2500 sysSTMDB_UPD = 2484, 2501 sysSTMIA = 2485, 2502 sysSTMIA_UPD = 2486, 2503 sysSTMIB = 2487, 2504 sysSTMIB_UPD = 2488, 2505 t2ABS = 2489, 2506 t2ADCri = 2490, 2507 t2ADCrr = 2491, 2508 t2ADCrs = 2492, 2509 t2ADDSri = 2493, 2510 t2ADDSrr = 2494, 2511 t2ADDSrs = 2495, 2512 t2ADDri = 2496, 2513 t2ADDri12 = 2497, 2514 t2ADDrr = 2498, 2515 t2ADDrs = 2499, 2516 t2ADR = 2500, 2517 t2ANDri = 2501, 2518 t2ANDrr = 2502, 2519 t2ANDrs = 2503, 2520 t2ASRri = 2504, 2521 t2ASRrr = 2505, 2522 t2B = 2506, 2523 t2BFC = 2507, 2524 t2BFI = 2508, 2525 t2BICri = 2509, 2526 t2BICrr = 2510, 2527 t2BICrs = 2511, 2528 t2BR_JT = 2512, 2529 t2BXJ = 2513, 2530 t2Bcc = 2514, 2531 t2CDP = 2515, 2532 t2CDP2 = 2516, 2533 t2CLREX = 2517, 2534 t2CLZ = 2518, 2535 t2CMNri = 2519, 2536 t2CMNzrr = 2520, 2537 t2CMNzrs = 2521, 2538 t2CMPri = 2522, 2539 t2CMPrr = 2523, 2540 t2CMPrs = 2524, 2541 t2CPS1p = 2525, 2542 t2CPS2p = 2526, 2543 t2CPS3p = 2527, 2544 t2CRC32B = 2528, 2545 t2CRC32CB = 2529, 2546 t2CRC32CH = 2530, 2547 t2CRC32CW = 2531, 2548 t2CRC32H = 2532, 2549 t2CRC32W = 2533, 2550 t2DBG = 2534, 2551 t2DCPS1 = 2535, 2552 t2DCPS2 = 2536, 2553 t2DCPS3 = 2537, 2554 t2DMB = 2538, 2555 t2DSB = 2539, 2556 t2EORri = 2540, 2557 t2EORrr = 2541, 2558 t2EORrs = 2542, 2559 t2HINT = 2543, 2560 t2HVC = 2544, 2561 t2ISB = 2545, 2562 t2IT = 2546, 2563 t2Int_eh_sjlj_setjmp = 2547, 2564 t2Int_eh_sjlj_setjmp_nofp = 2548, 2565 t2LDA = 2549, 2566 t2LDAB = 2550, 2567 t2LDAEX = 2551, 2568 t2LDAEXB = 2552, 2569 t2LDAEXD = 2553, 2570 t2LDAEXH = 2554, 2571 t2LDAH = 2555, 2572 t2LDC2L_OFFSET = 2556, 2573 t2LDC2L_OPTION = 2557, 2574 t2LDC2L_POST = 2558, 2575 t2LDC2L_PRE = 2559, 2576 t2LDC2_OFFSET = 2560, 2577 t2LDC2_OPTION = 2561, 2578 t2LDC2_POST = 2562, 2579 t2LDC2_PRE = 2563, 2580 t2LDCL_OFFSET = 2564, 2581 t2LDCL_OPTION = 2565, 2582 t2LDCL_POST = 2566, 2583 t2LDCL_PRE = 2567, 2584 t2LDC_OFFSET = 2568, 2585 t2LDC_OPTION = 2569, 2586 t2LDC_POST = 2570, 2587 t2LDC_PRE = 2571, 2588 t2LDMDB = 2572, 2589 t2LDMDB_UPD = 2573, 2590 t2LDMIA = 2574, 2591 t2LDMIA_RET = 2575, 2592 t2LDMIA_UPD = 2576, 2593 t2LDRBT = 2577, 2594 t2LDRB_POST = 2578, 2595 t2LDRB_PRE = 2579, 2596 t2LDRBi12 = 2580, 2597 t2LDRBi8 = 2581, 2598 t2LDRBpci = 2582, 2599 t2LDRBpcrel = 2583, 2600 t2LDRBs = 2584, 2601 t2LDRD_POST = 2585, 2602 t2LDRD_PRE = 2586, 2603 t2LDRDi8 = 2587, 2604 t2LDREX = 2588, 2605 t2LDREXB = 2589, 2606 t2LDREXD = 2590, 2607 t2LDREXH = 2591, 2608 t2LDRHT = 2592, 2609 t2LDRH_POST = 2593, 2610 t2LDRH_PRE = 2594, 2611 t2LDRHi12 = 2595, 2612 t2LDRHi8 = 2596, 2613 t2LDRHpci = 2597, 2614 t2LDRHpcrel = 2598, 2615 t2LDRHs = 2599, 2616 t2LDRSBT = 2600, 2617 t2LDRSB_POST = 2601, 2618 t2LDRSB_PRE = 2602, 2619 t2LDRSBi12 = 2603, 2620 t2LDRSBi8 = 2604, 2621 t2LDRSBpci = 2605, 2622 t2LDRSBpcrel = 2606, 2623 t2LDRSBs = 2607, 2624 t2LDRSHT = 2608, 2625 t2LDRSH_POST = 2609, 2626 t2LDRSH_PRE = 2610, 2627 t2LDRSHi12 = 2611, 2628 t2LDRSHi8 = 2612, 2629 t2LDRSHpci = 2613, 2630 t2LDRSHpcrel = 2614, 2631 t2LDRSHs = 2615, 2632 t2LDRT = 2616, 2633 t2LDR_POST = 2617, 2634 t2LDR_PRE = 2618, 2635 t2LDRi12 = 2619, 2636 t2LDRi8 = 2620, 2637 t2LDRpci = 2621, 2638 t2LDRpci_pic = 2622, 2639 t2LDRpcrel = 2623, 2640 t2LDRs = 2624, 2641 t2LEApcrel = 2625, 2642 t2LEApcrelJT = 2626, 2643 t2LSLri = 2627, 2644 t2LSLrr = 2628, 2645 t2LSRri = 2629, 2646 t2LSRrr = 2630, 2647 t2MCR = 2631, 2648 t2MCR2 = 2632, 2649 t2MCRR = 2633, 2650 t2MCRR2 = 2634, 2651 t2MLA = 2635, 2652 t2MLS = 2636, 2653 t2MOVCCasr = 2637, 2654 t2MOVCCi = 2638, 2655 t2MOVCCi16 = 2639, 2656 t2MOVCCi32imm = 2640, 2657 t2MOVCClsl = 2641, 2658 t2MOVCClsr = 2642, 2659 t2MOVCCr = 2643, 2660 t2MOVCCror = 2644, 2661 t2MOVSsi = 2645, 2662 t2MOVSsr = 2646, 2663 t2MOVTi16 = 2647, 2664 t2MOVTi16_ga_pcrel = 2648, 2665 t2MOV_ga_pcrel = 2649, 2666 t2MOVi = 2650, 2667 t2MOVi16 = 2651, 2668 t2MOVi16_ga_pcrel = 2652, 2669 t2MOVi32imm = 2653, 2670 t2MOVr = 2654, 2671 t2MOVsi = 2655, 2672 t2MOVsr = 2656, 2673 t2MOVsra_flag = 2657, 2674 t2MOVsrl_flag = 2658, 2675 t2MRC = 2659, 2676 t2MRC2 = 2660, 2677 t2MRRC = 2661, 2678 t2MRRC2 = 2662, 2679 t2MRS_AR = 2663, 2680 t2MRS_M = 2664, 2681 t2MRSbanked = 2665, 2682 t2MRSsys_AR = 2666, 2683 t2MSR_AR = 2667, 2684 t2MSR_M = 2668, 2685 t2MSRbanked = 2669, 2686 t2MUL = 2670, 2687 t2MVNCCi = 2671, 2688 t2MVNi = 2672, 2689 t2MVNr = 2673, 2690 t2MVNs = 2674, 2691 t2ORNri = 2675, 2692 t2ORNrr = 2676, 2693 t2ORNrs = 2677, 2694 t2ORRri = 2678, 2695 t2ORRrr = 2679, 2696 t2ORRrs = 2680, 2697 t2PKHBT = 2681, 2698 t2PKHTB = 2682, 2699 t2PLDWi12 = 2683, 2700 t2PLDWi8 = 2684, 2701 t2PLDWs = 2685, 2702 t2PLDi12 = 2686, 2703 t2PLDi8 = 2687, 2704 t2PLDpci = 2688, 2705 t2PLDs = 2689, 2706 t2PLIi12 = 2690, 2707 t2PLIi8 = 2691, 2708 t2PLIpci = 2692, 2709 t2PLIs = 2693, 2710 t2QADD = 2694, 2711 t2QADD16 = 2695, 2712 t2QADD8 = 2696, 2713 t2QASX = 2697, 2714 t2QDADD = 2698, 2715 t2QDSUB = 2699, 2716 t2QSAX = 2700, 2717 t2QSUB = 2701, 2718 t2QSUB16 = 2702, 2719 t2QSUB8 = 2703, 2720 t2RBIT = 2704, 2721 t2REV = 2705, 2722 t2REV16 = 2706, 2723 t2REVSH = 2707, 2724 t2RFEDB = 2708, 2725 t2RFEDBW = 2709, 2726 t2RFEIA = 2710, 2727 t2RFEIAW = 2711, 2728 t2RORri = 2712, 2729 t2RORrr = 2713, 2730 t2RRX = 2714, 2731 t2RSBSri = 2715, 2732 t2RSBSrs = 2716, 2733 t2RSBri = 2717, 2734 t2RSBrr = 2718, 2735 t2RSBrs = 2719, 2736 t2SADD16 = 2720, 2737 t2SADD8 = 2721, 2738 t2SASX = 2722, 2739 t2SBCri = 2723, 2740 t2SBCrr = 2724, 2741 t2SBCrs = 2725, 2742 t2SBFX = 2726, 2743 t2SDIV = 2727, 2744 t2SEL = 2728, 2745 t2SETPAN = 2729, 2746 t2SG = 2730, 2747 t2SHADD16 = 2731, 2748 t2SHADD8 = 2732, 2749 t2SHASX = 2733, 2750 t2SHSAX = 2734, 2751 t2SHSUB16 = 2735, 2752 t2SHSUB8 = 2736, 2753 t2SMC = 2737, 2754 t2SMLABB = 2738, 2755 t2SMLABT = 2739, 2756 t2SMLAD = 2740, 2757 t2SMLADX = 2741, 2758 t2SMLAL = 2742, 2759 t2SMLALBB = 2743, 2760 t2SMLALBT = 2744, 2761 t2SMLALD = 2745, 2762 t2SMLALDX = 2746, 2763 t2SMLALTB = 2747, 2764 t2SMLALTT = 2748, 2765 t2SMLATB = 2749, 2766 t2SMLATT = 2750, 2767 t2SMLAWB = 2751, 2768 t2SMLAWT = 2752, 2769 t2SMLSD = 2753, 2770 t2SMLSDX = 2754, 2771 t2SMLSLD = 2755, 2772 t2SMLSLDX = 2756, 2773 t2SMMLA = 2757, 2774 t2SMMLAR = 2758, 2775 t2SMMLS = 2759, 2776 t2SMMLSR = 2760, 2777 t2SMMUL = 2761, 2778 t2SMMULR = 2762, 2779 t2SMUAD = 2763, 2780 t2SMUADX = 2764, 2781 t2SMULBB = 2765, 2782 t2SMULBT = 2766, 2783 t2SMULL = 2767, 2784 t2SMULTB = 2768, 2785 t2SMULTT = 2769, 2786 t2SMULWB = 2770, 2787 t2SMULWT = 2771, 2788 t2SMUSD = 2772, 2789 t2SMUSDX = 2773, 2790 t2SRSDB = 2774, 2791 t2SRSDB_UPD = 2775, 2792 t2SRSIA = 2776, 2793 t2SRSIA_UPD = 2777, 2794 t2SSAT = 2778, 2795 t2SSAT16 = 2779, 2796 t2SSAX = 2780, 2797 t2SSUB16 = 2781, 2798 t2SSUB8 = 2782, 2799 t2STC2L_OFFSET = 2783, 2800 t2STC2L_OPTION = 2784, 2801 t2STC2L_POST = 2785, 2802 t2STC2L_PRE = 2786, 2803 t2STC2_OFFSET = 2787, 2804 t2STC2_OPTION = 2788, 2805 t2STC2_POST = 2789, 2806 t2STC2_PRE = 2790, 2807 t2STCL_OFFSET = 2791, 2808 t2STCL_OPTION = 2792, 2809 t2STCL_POST = 2793, 2810 t2STCL_PRE = 2794, 2811 t2STC_OFFSET = 2795, 2812 t2STC_OPTION = 2796, 2813 t2STC_POST = 2797, 2814 t2STC_PRE = 2798, 2815 t2STL = 2799, 2816 t2STLB = 2800, 2817 t2STLEX = 2801, 2818 t2STLEXB = 2802, 2819 t2STLEXD = 2803, 2820 t2STLEXH = 2804, 2821 t2STLH = 2805, 2822 t2STMDB = 2806, 2823 t2STMDB_UPD = 2807, 2824 t2STMIA = 2808, 2825 t2STMIA_UPD = 2809, 2826 t2STRBT = 2810, 2827 t2STRB_POST = 2811, 2828 t2STRB_PRE = 2812, 2829 t2STRB_preidx = 2813, 2830 t2STRBi12 = 2814, 2831 t2STRBi8 = 2815, 2832 t2STRBs = 2816, 2833 t2STRD_POST = 2817, 2834 t2STRD_PRE = 2818, 2835 t2STRDi8 = 2819, 2836 t2STREX = 2820, 2837 t2STREXB = 2821, 2838 t2STREXD = 2822, 2839 t2STREXH = 2823, 2840 t2STRHT = 2824, 2841 t2STRH_POST = 2825, 2842 t2STRH_PRE = 2826, 2843 t2STRH_preidx = 2827, 2844 t2STRHi12 = 2828, 2845 t2STRHi8 = 2829, 2846 t2STRHs = 2830, 2847 t2STRT = 2831, 2848 t2STR_POST = 2832, 2849 t2STR_PRE = 2833, 2850 t2STR_preidx = 2834, 2851 t2STRi12 = 2835, 2852 t2STRi8 = 2836, 2853 t2STRs = 2837, 2854 t2SUBS_PC_LR = 2838, 2855 t2SUBSri = 2839, 2856 t2SUBSrr = 2840, 2857 t2SUBSrs = 2841, 2858 t2SUBri = 2842, 2859 t2SUBri12 = 2843, 2860 t2SUBrr = 2844, 2861 t2SUBrs = 2845, 2862 t2SXTAB = 2846, 2863 t2SXTAB16 = 2847, 2864 t2SXTAH = 2848, 2865 t2SXTB = 2849, 2866 t2SXTB16 = 2850, 2867 t2SXTH = 2851, 2868 t2TBB = 2852, 2869 t2TBB_JT = 2853, 2870 t2TBH = 2854, 2871 t2TBH_JT = 2855, 2872 t2TEQri = 2856, 2873 t2TEQrr = 2857, 2874 t2TEQrs = 2858, 2875 t2TSTri = 2859, 2876 t2TSTrr = 2860, 2877 t2TSTrs = 2861, 2878 t2TT = 2862, 2879 t2TTA = 2863, 2880 t2TTAT = 2864, 2881 t2TTT = 2865, 2882 t2UADD16 = 2866, 2883 t2UADD8 = 2867, 2884 t2UASX = 2868, 2885 t2UBFX = 2869, 2886 t2UDF = 2870, 2887 t2UDIV = 2871, 2888 t2UHADD16 = 2872, 2889 t2UHADD8 = 2873, 2890 t2UHASX = 2874, 2891 t2UHSAX = 2875, 2892 t2UHSUB16 = 2876, 2893 t2UHSUB8 = 2877, 2894 t2UMAAL = 2878, 2895 t2UMLAL = 2879, 2896 t2UMULL = 2880, 2897 t2UQADD16 = 2881, 2898 t2UQADD8 = 2882, 2899 t2UQASX = 2883, 2900 t2UQSAX = 2884, 2901 t2UQSUB16 = 2885, 2902 t2UQSUB8 = 2886, 2903 t2USAD8 = 2887, 2904 t2USADA8 = 2888, 2905 t2USAT = 2889, 2906 t2USAT16 = 2890, 2907 t2USAX = 2891, 2908 t2USUB16 = 2892, 2909 t2USUB8 = 2893, 2910 t2UXTAB = 2894, 2911 t2UXTAB16 = 2895, 2912 t2UXTAH = 2896, 2913 t2UXTB = 2897, 2914 t2UXTB16 = 2898, 2915 t2UXTH = 2899, 2916 tADC = 2900, 2917 tADDframe = 2901, 2918 tADDhirr = 2902, 2919 tADDi3 = 2903, 2920 tADDi8 = 2904, 2921 tADDrSP = 2905, 2922 tADDrSPi = 2906, 2923 tADDrr = 2907, 2924 tADDspi = 2908, 2925 tADDspr = 2909, 2926 tADJCALLSTACKDOWN = 2910, 2927 tADJCALLSTACKUP = 2911, 2928 tADR = 2912, 2929 tAND = 2913, 2930 tASRri = 2914, 2931 tASRrr = 2915, 2932 tB = 2916, 2933 tBIC = 2917, 2934 tBKPT = 2918, 2935 tBL = 2919, 2936 tBLXNSr = 2920, 2937 tBLXi = 2921, 2938 tBLXr = 2922, 2939 tBRIND = 2923, 2940 tBR_JTr = 2924, 2941 tBX = 2925, 2942 tBXNS = 2926, 2943 tBX_CALL = 2927, 2944 tBX_RET = 2928, 2945 tBX_RET_vararg = 2929, 2946 tBcc = 2930, 2947 tBfar = 2931, 2948 tCBNZ = 2932, 2949 tCBZ = 2933, 2950 tCMNz = 2934, 2951 tCMPhir = 2935, 2952 tCMPi8 = 2936, 2953 tCMPr = 2937, 2954 tCPS = 2938, 2955 tEOR = 2939, 2956 tHINT = 2940, 2957 tHLT = 2941, 2958 tInt_eh_sjlj_longjmp = 2942, 2959 tInt_eh_sjlj_setjmp = 2943, 2960 tLDMIA = 2944, 2961 tLDMIA_UPD = 2945, 2962 tLDRBi = 2946, 2963 tLDRBr = 2947, 2964 tLDRHi = 2948, 2965 tLDRHr = 2949, 2966 tLDRLIT_ga_abs = 2950, 2967 tLDRLIT_ga_pcrel = 2951, 2968 tLDRSB = 2952, 2969 tLDRSH = 2953, 2970 tLDRi = 2954, 2971 tLDRpci = 2955, 2972 tLDRpci_pic = 2956, 2973 tLDRr = 2957, 2974 tLDRspi = 2958, 2975 tLEApcrel = 2959, 2976 tLEApcrelJT = 2960, 2977 tLSLri = 2961, 2978 tLSLrr = 2962, 2979 tLSRri = 2963, 2980 tLSRrr = 2964, 2981 tMOVCCr_pseudo = 2965, 2982 tMOVSr = 2966, 2983 tMOVi8 = 2967, 2984 tMOVr = 2968, 2985 tMUL = 2969, 2986 tMVN = 2970, 2987 tORR = 2971, 2988 tPICADD = 2972, 2989 tPOP = 2973, 2990 tPOP_RET = 2974, 2991 tPUSH = 2975, 2992 tREV = 2976, 2993 tREV16 = 2977, 2994 tREVSH = 2978, 2995 tROR = 2979, 2996 tRSB = 2980, 2997 tSBC = 2981, 2998 tSETEND = 2982, 2999 tSTMIA_UPD = 2983, 3000 tSTRBi = 2984, 3001 tSTRBr = 2985, 3002 tSTRHi = 2986, 3003 tSTRHr = 2987, 3004 tSTRi = 2988, 3005 tSTRr = 2989, 3006 tSTRspi = 2990, 3007 tSUBi3 = 2991, 3008 tSUBi8 = 2992, 3009 tSUBrr = 2993, 3010 tSUBspi = 2994, 3011 tSVC = 2995, 3012 tSXTB = 2996, 3013 tSXTH = 2997, 3014 tTAILJMPd = 2998, 3015 tTAILJMPdND = 2999, 3016 tTAILJMPr = 3000, 3017 tTPsoft = 3001, 3018 tTRAP = 3002, 3019 tTST = 3003, 3020 tUDF = 3004, 3021 tUXTB = 3005, 3022 tUXTH = 3006, 3023 INSTRUCTION_LIST_END = 3007 3024 }; 3025 3026namespace Sched { 3027 enum { 3028 NoInstrModel = 0, 3029 IIC_iALUi_WriteALU_ReadALU = 1, 3030 IIC_iALUr_WriteALU_ReadALU_ReadALU = 2, 3031 IIC_iALUsr_WriteALUsi_ReadALU = 3, 3032 IIC_iALUsr_WriteALUsr_ReadALUsr = 4, 3033 IIC_iALUsr_WriteALUSsr_ReadALUsr = 5, 3034 IIC_iBITi_WriteALU_ReadALU = 6, 3035 IIC_iBITr_WriteALU_ReadALU_ReadALU = 7, 3036 IIC_iBITsr_WriteALUsi_ReadALU = 8, 3037 IIC_iBITsr_WriteALUsr_ReadALUsr = 9, 3038 IIC_Br_WriteBr = 10, 3039 IIC_iUNAsi = 11, 3040 IIC_Br_WriteBrL = 12, 3041 WriteBrL = 13, 3042 IIC_Br_WriteBrTbl = 14, 3043 WriteBr = 15, 3044 IIC_iUNAr_WriteALU = 16, 3045 IIC_iCMPi_WriteCMP_ReadALU = 17, 3046 IIC_iCMPr_WriteCMP_ReadALU_ReadALU = 18, 3047 IIC_iCMPsr_WriteCMPsi_ReadALU = 19, 3048 IIC_iCMPsr_WriteCMPsr_ReadALU = 20, 3049 IIC_fpUNA64 = 21, 3050 IIC_fpUNA16 = 22, 3051 IIC_fpUNA32 = 23, 3052 IIC_fpSTAT = 24, 3053 IIC_iLoad_m = 25, 3054 IIC_iLoad_mu = 26, 3055 IIC_iLoad_mBr = 27, 3056 IIC_iLoad_bh_ru = 28, 3057 IIC_iLoad_bh_iu = 29, 3058 IIC_iLoad_bh_r = 30, 3059 IIC_iLoad_bh_si = 31, 3060 IIC_iLoad_d_r = 32, 3061 IIC_iLoad_d_ru = 33, 3062 IIC_iLoad_i = 34, 3063 IIC_iLoadiALU = 35, 3064 IIC_iLoad_ru = 36, 3065 IIC_iLoad_iu = 37, 3066 IIC_iLoad_r = 38, 3067 IIC_iLoad_si = 39, 3068 IIC_iMAC32 = 40, 3069 IIC_iCMOVi_WriteALU = 41, 3070 IIC_iMOVi_WriteALU = 42, 3071 IIC_iCMOVix2 = 43, 3072 IIC_iCMOVr_WriteALU = 44, 3073 IIC_iCMOVsr_WriteALU = 45, 3074 IIC_iMOVix2addpc = 46, 3075 IIC_iMOVix2ld = 47, 3076 IIC_iMOVix2 = 48, 3077 IIC_iMOVr_WriteALU = 49, 3078 IIC_iMOVsr_WriteALU = 50, 3079 IIC_iMOVsi_WriteALU = 51, 3080 IIC_iMUL32 = 52, 3081 IIC_iMVNi_WriteALU = 53, 3082 IIC_iMVNr_WriteALU = 54, 3083 IIC_iMVNsr_WriteALU = 55, 3084 IIC_iALUr_WriteALU_ReadALU = 56, 3085 IIC_iStore_r = 57, 3086 IIC_iStore_bh_r = 58, 3087 IIC_iALUsi_WriteALUsi_ReadALU = 59, 3088 IIC_iBITsi_WriteALUsi_ReadALU = 60, 3089 IIC_Preload_WritePreLd = 61, 3090 IIC_iDIV = 62, 3091 IIC_iMAC16 = 63, 3092 IIC_iMAC64 = 64, 3093 IIC_iMUL16 = 65, 3094 IIC_iMUL64 = 66, 3095 IIC_iStore_m = 67, 3096 IIC_iStore_mu = 68, 3097 IIC_iStore_bh_ru = 69, 3098 IIC_iStore_bh_iu = 70, 3099 IIC_iStore_ru = 71, 3100 IIC_iStore_bh_si = 72, 3101 IIC_iStore_d_r = 73, 3102 IIC_iStore_d_ru = 74, 3103 IIC_iStore_iu = 75, 3104 IIC_iStore_si = 76, 3105 IIC_Br = 77, 3106 IIC_iEXTAr_WriteALUsr = 78, 3107 IIC_iEXTr_WriteALUsi = 79, 3108 IIC_iTSTi_WriteCMP_ReadALU = 80, 3109 IIC_iTSTr_WriteCMP_ReadALU_ReadALU = 81, 3110 IIC_iTSTsr_WriteCMPsi_ReadALU = 82, 3111 IIC_iTSTsr_WriteCMPsr_ReadALU = 83, 3112 WriteALU_ReadALU_ReadALU = 84, 3113 IIC_VABAD = 85, 3114 IIC_VABAQ = 86, 3115 IIC_VSUBi4Q = 87, 3116 IIC_VBIND = 88, 3117 IIC_VBINQ = 89, 3118 IIC_VSUBi4D = 90, 3119 IIC_VUNAD = 91, 3120 IIC_VUNAQ = 92, 3121 IIC_VUNAiQ = 93, 3122 IIC_VUNAiD = 94, 3123 IIC_fpALU64 = 95, 3124 IIC_fpALU16 = 96, 3125 IIC_VBINi4D = 97, 3126 IIC_VSHLiD = 98, 3127 IIC_fpALU32 = 99, 3128 IIC_VSUBiD = 100, 3129 IIC_VBINiQ = 101, 3130 IIC_VBINiD = 102, 3131 IIC_VMOVImm = 103, 3132 IIC_VCNTiD = 104, 3133 IIC_VCNTiQ = 105, 3134 IIC_fpCMP64 = 106, 3135 IIC_fpCMP16 = 107, 3136 IIC_fpCMP32 = 108, 3137 IIC_fpCVTSH = 109, 3138 IIC_fpCVTHS = 110, 3139 IIC_fpCVTDS = 111, 3140 IIC_fpCVTSD = 112, 3141 IIC_fpDIV64 = 113, 3142 IIC_fpDIV16 = 114, 3143 IIC_fpDIV32 = 115, 3144 IIC_VMOVIS = 116, 3145 IIC_VMOVD = 117, 3146 IIC_VMOVQ = 118, 3147 IIC_VEXTD = 119, 3148 IIC_VEXTQ = 120, 3149 IIC_fpFMAC64 = 121, 3150 IIC_fpFMAC16 = 122, 3151 IIC_fpFMAC32 = 123, 3152 IIC_VFMACD = 124, 3153 IIC_VFMACQ = 125, 3154 IIC_VMOVSI = 126, 3155 IIC_VBINi4Q = 127, 3156 IIC_VLD1dup = 128, 3157 IIC_VLD1dupu = 129, 3158 IIC_VLD1ln = 130, 3159 IIC_VLD1lnu = 131, 3160 IIC_VLD1 = 132, 3161 IIC_VLD1x4 = 133, 3162 IIC_VLD1x2u = 134, 3163 IIC_VLD1x3 = 135, 3164 IIC_VLD1u = 136, 3165 IIC_VLD1x2 = 137, 3166 IIC_VLD2dup = 138, 3167 IIC_VLD2dupu = 139, 3168 IIC_VLD2ln = 140, 3169 IIC_VLD2lnu = 141, 3170 IIC_VLD2 = 142, 3171 IIC_VLD2u = 143, 3172 IIC_VLD2x2 = 144, 3173 IIC_VLD2x2u = 145, 3174 IIC_VLD3dup = 146, 3175 IIC_VLD3dupu = 147, 3176 IIC_VLD3ln = 148, 3177 IIC_VLD3lnu = 149, 3178 IIC_VLD3 = 150, 3179 IIC_VLD3u = 151, 3180 IIC_VLD4dup = 152, 3181 IIC_VLD4dupu = 153, 3182 IIC_VLD4ln = 154, 3183 IIC_VLD4lnu = 155, 3184 IIC_VLD4 = 156, 3185 IIC_VLD4u = 157, 3186 IIC_fpLoad_mu = 158, 3187 IIC_fpLoad_m = 159, 3188 IIC_fpLoad64 = 160, 3189 IIC_fpLoad16 = 161, 3190 IIC_fpLoad32 = 162, 3191 IIC_fpStore_m = 163, 3192 IIC_fpMAC64 = 164, 3193 IIC_fpMAC16 = 165, 3194 IIC_VMACi32D = 166, 3195 IIC_VMACi16D = 167, 3196 IIC_fpMAC32 = 168, 3197 IIC_VMACD = 169, 3198 IIC_VMACQ = 170, 3199 IIC_VMACi32Q = 171, 3200 IIC_VMACi16Q = 172, 3201 IIC_fpMOVID = 173, 3202 IIC_fpMOVIS = 174, 3203 IIC_VQUNAiD = 175, 3204 IIC_VMOVN = 176, 3205 IIC_fpMOVSI = 177, 3206 IIC_fpMOVDI = 178, 3207 IIC_fpMUL64 = 179, 3208 IIC_fpMUL16 = 180, 3209 IIC_VMULi16D = 181, 3210 IIC_VMULi32D = 182, 3211 IIC_fpMUL32 = 183, 3212 IIC_VFMULD = 184, 3213 IIC_VFMULQ = 185, 3214 IIC_VMULi16Q = 186, 3215 IIC_VMULi32Q = 187, 3216 IIC_VSHLiQ = 188, 3217 IIC_VPALiQ = 189, 3218 IIC_VPALiD = 190, 3219 IIC_VPBIND = 191, 3220 IIC_VQUNAiQ = 192, 3221 IIC_VSHLi4Q = 193, 3222 IIC_VSHLi4D = 194, 3223 IIC_VRECSD = 195, 3224 IIC_VRECSQ = 196, 3225 IIC_VMOVISL = 197, 3226 IIC_fpCVTID_WriteCvtFP = 198, 3227 IIC_fpCVTIH_WriteCvtFP = 199, 3228 IIC_fpCVTIS_WriteCvtFP = 200, 3229 IIC_fpCVTID = 201, 3230 IIC_fpCVTIH = 202, 3231 IIC_fpCVTIS = 203, 3232 IIC_fpSQRT64 = 204, 3233 IIC_fpSQRT16 = 205, 3234 IIC_fpSQRT32 = 206, 3235 IIC_VST1ln = 207, 3236 IIC_VST1lnu = 208, 3237 IIC_VST1 = 209, 3238 IIC_VST1x4 = 210, 3239 IIC_VLD1x4u = 211, 3240 IIC_VST1x3 = 212, 3241 IIC_VLD1x3u = 213, 3242 IIC_VST1x4u = 214, 3243 IIC_VST1x3u = 215, 3244 IIC_VST1x2 = 216, 3245 IIC_VST2ln = 217, 3246 IIC_VST2lnu = 218, 3247 IIC_VST2 = 219, 3248 IIC_VST2x2 = 220, 3249 IIC_VST2x2u = 221, 3250 IIC_VST3ln = 222, 3251 IIC_VST3lnu = 223, 3252 IIC_VST3 = 224, 3253 IIC_VST3u = 225, 3254 IIC_VST4ln = 226, 3255 IIC_VST4lnu = 227, 3256 IIC_VST4 = 228, 3257 IIC_VST4u = 229, 3258 IIC_fpStore_mu = 230, 3259 IIC_fpStore64 = 231, 3260 IIC_fpStore16 = 232, 3261 IIC_fpStore32 = 233, 3262 IIC_VSUBiQ = 234, 3263 IIC_VTB1 = 235, 3264 IIC_VTB2 = 236, 3265 IIC_VTB3 = 237, 3266 IIC_VTB4 = 238, 3267 IIC_VTBX1 = 239, 3268 IIC_VTBX2 = 240, 3269 IIC_VTBX3 = 241, 3270 IIC_VTBX4 = 242, 3271 IIC_fpCVTDI_WriteCvtFP = 243, 3272 IIC_fpCVTHI_WriteCvtFP = 244, 3273 IIC_fpCVTSI_WriteCvtFP = 245, 3274 IIC_fpCVTDI = 246, 3275 IIC_fpCVTHI = 247, 3276 IIC_fpCVTSI = 248, 3277 IIC_VPERMD = 249, 3278 IIC_VPERMQ = 250, 3279 IIC_VPERMQ3 = 251, 3280 IIC_iALUsi_WriteALUsi_ReadALUsr = 252, 3281 IIC_iBITi = 253, 3282 IIC_iCMPsi_WriteCMPsi_ReadALU_ReadALU = 254, 3283 IIC_iCMPi_WriteCMP = 255, 3284 IIC_iCMPr_WriteCMP = 256, 3285 IIC_iCMPsi_WriteCMPsi = 257, 3286 IIC_iALUx = 258, 3287 IIC_iLoad_bh_i = 259, 3288 IIC_iLoad_d_i = 260, 3289 IIC_iCMOVsi_WriteALU = 261, 3290 IIC_iMOVi = 262, 3291 IIC_iMVNsi_WriteALU = 263, 3292 IIC_iALUsir_WriteALUsi_ReadALU = 264, 3293 IIC_iStore_bh_i = 265, 3294 IIC_iStore_i = 266, 3295 IIC_iEXTAsr = 267, 3296 IIC_iEXTr = 268, 3297 IIC_iTSTi_WriteCMP = 269, 3298 IIC_iTSTr_WriteCMP = 270, 3299 IIC_iTSTsi_WriteCMPsi = 271, 3300 IIC_iALUr_WriteALU = 272, 3301 IIC_iALUi_WriteALU = 273, 3302 IIC_iBITr_WriteALU = 274, 3303 IIC_iPop = 275, 3304 IIC_iPop_Br_WriteBrL = 276, 3305 IIC_iTSTr_WriteALU = 277, 3306 ANDri_BICri_EORri_ORRri = 278, 3307 ANDrr_BICrr_EORrr_ORRrr = 279, 3308 ANDrsi_BICrsi_EORrsi_ORRrsi = 280, 3309 ANDrsr_BICrsr_EORrsr_ORRrsr = 281, 3310 MOVCCsi_MOVCCsr = 282, 3311 MOVsi_MOVsr = 283, 3312 MOVsra_flag_MOVsrl_flag = 284, 3313 MVNsr = 285, 3314 MVNr = 286, 3315 MOVCCi32imm = 287, 3316 MOVi32imm = 288, 3317 MOV_ga_pcrel = 289, 3318 MOV_ga_pcrel_ldr = 290, 3319 SEL = 291, 3320 BFC_BFI_SBFX_UBFX = 292, 3321 MLA_MLAv5_MLS_SMMLA_SMMLAR_SMMLS_SMMLSR = 293, 3322 MUL_MULv5_SMMUL_SMMULR = 294, 3323 SMLAL_SMLALBB_SMLALBT_SMLALTB_SMLALTT_SMLALv5_UMAAL_UMLAL_UMLALv5 = 295, 3324 SMULL_SMULLv5_UMULL_UMULLv5 = 296, 3325 SMLAD_SMLADX_SMLALD_SMLALDX_SMLSD_SMLSDX_SMLSLD_SMLSLDX_SMUAD_SMUADX_SMUSD_SMUSDX = 297, 3326 SMULBB_SMULBT_SMULTB_SMULTT_SMULWB_SMULWT = 298, 3327 SMLABB_SMLABT_SMLATB_SMLATT_SMLAWB_SMLAWT = 299, 3328 LDRi12_PICLDR = 300, 3329 LDRrs = 301, 3330 LDRBi12_LDRH_LDRSB_LDRSH_PICLDRB_PICLDRH_PICLDRSB_PICLDRSH = 302, 3331 LDRHTi_LDRHTr_LDRH_POST_LDRH_PRE_LDRSBTi_LDRSBTr_LDRSB_POST_LDRSB_PRE_LDRSHTi_LDRSHTr_LDRSH_POST_LDRSH_PRE = 303, 3332 SXTB_SXTB16_SXTH_UXTB_UXTB16_UXTH = 304, 3333 t2SXTB_t2SXTB16_t2SXTH_t2UXTB_t2UXTB16_t2UXTH = 305, 3334 t2MOVCCi32imm = 306, 3335 t2MOVi32imm = 307, 3336 t2MOV_ga_pcrel = 308, 3337 t2MOVi16_ga_pcrel = 309, 3338 t2SEL = 310, 3339 t2BFC_t2SBFX_t2UBFX = 311, 3340 t2BFI = 312, 3341 QADD_QADD16_QADD8_QASX_QDADD_QDSUB_QSAX_QSUB_QSUB16_QSUB8_UQADD16_UQADD8_UQASX_UQSAX_UQSUB16_UQSUB8 = 313, 3342 SSAT_SSAT16_USAT_USAT16_t2QADD_t2QADD16_t2QADD8_t2QASX_t2QDADD_t2QDSUB_t2QSAX_t2QSUB_t2QSUB16_t2QSUB8_t2SSAT_t2SSAT16_t2UQADD16_t2UQADD8_t2UQASX_t2UQSAX_t2UQSUB16_t2UQSUB8_t2USAT_t2USAT16 = 314, 3343 SADD16_SADD8_SASX_SSAX_SSUB16_SSUB8_UADD16_UADD8_UASX_USAX_USUB16_USUB8 = 315, 3344 t2SADD16_t2SADD8_t2SASX_t2SSAX_t2SSUB16_t2SSUB8_t2UADD16_t2UADD8_t2UASX_t2USAX_t2USUB16_t2USUB8 = 316, 3345 SHADD16_SHADD8_SHASX_SHSAX_SHSUB16_SHSUB8_UHADD16_UHADD8_UHASX_UHSAX_UHSUB16_UHSUB8 = 317, 3346 SXTAB_SXTAB16_SXTAH_UXTAB_UXTAB16_UXTAH = 318, 3347 t2SHADD16_t2SHADD8_t2SHASX_t2SHSAX_t2SHSUB16_t2SHSUB8_t2UHADD16_t2UHADD8_t2UHASX_t2UHSAX_t2UHSUB16_t2UHSUB8 = 319, 3348 t2SXTAB_t2SXTAB16_t2SXTAH_t2UXTAB_t2UXTAB16_t2UXTAH = 320, 3349 USAD8 = 321, 3350 USADA8 = 322, 3351 SMUSD_SMUSDX = 323, 3352 t2MUL_t2SMMUL_t2SMMULR = 324, 3353 t2SMULBB_t2SMULBT_t2SMULTB_t2SMULTT_t2SMULWB_t2SMULWT = 325, 3354 t2SMUSD_t2SMUSDX = 326, 3355 t2MLA_t2MLS_t2SMMLA_t2SMMLAR_t2SMMLS_t2SMMLSR = 327, 3356 SMUAD_SMUADX = 328, 3357 t2SMUAD_t2SMUADX = 329, 3358 SMLSD_SMLSDX = 330, 3359 t2SMLABB_t2SMLABT_t2SMLATB_t2SMLATT_t2SMLAWB_t2SMLAWT = 331, 3360 t2SMLSD_t2SMLSDX = 332, 3361 SMLAD_SMLADX = 333, 3362 t2SMLAD_t2SMLADX = 334, 3363 SMULL_UMULL = 335, 3364 t2SMULL_t2UMULL = 336, 3365 t2SMLAL_t2SMLALBB_t2SMLALBT_t2SMLALD_t2SMLALDX_t2SMLALTB_t2SMLALTT_t2SMLSLD_t2SMLSLDX_t2UMAAL_t2UMLAL = 337, 3366 SDIV_UDIV_t2SDIV_t2UDIV = 338, 3367 LDRBi12 = 339, 3368 LDRBrs_t2LDRBs_t2LDRHs = 340, 3369 LDREX_LDREXB_LDREXD_LDREXH_tLDRpci_pic = 341, 3370 LDRi12 = 342, 3371 t2LDRBi12_t2LDRBi8_t2LDRBpci_t2LDRHi12_t2LDRHi8_t2LDRHpci_tLDRBi_tLDRHi = 343, 3372 t2LDRi12_t2LDRi8_t2LDRpci_tLDRi_tLDRpci_tLDRspi = 344, 3373 t2LDRpci_pic = 345, 3374 t2LDRs = 346, 3375 tLDRBr_tLDRHr = 347, 3376 tLDRr = 348, 3377 LDRH_PICLDRB_PICLDRH = 349, 3378 LDRcp = 350, 3379 t2LDRSBi12_t2LDRSBi8_t2LDRSBpci_t2LDRSHi12_t2LDRSHi8_t2LDRSHpci = 351, 3380 t2LDRSBpcrel_t2LDRSHpcrel = 352, 3381 t2LDRSBs_t2LDRSHs = 353, 3382 tLDRSB_tLDRSH = 354, 3383 LDRBT_POST_IMM_LDRBT_POST_REG_LDRB_POST_REG_LDRB_PRE_REG = 355, 3384 LDRB_POST_IMM_LDRB_PRE_IMM_t2LDRB_POST_t2LDRB_PRE_t2LDRH_POST_t2LDRH_PRE = 356, 3385 LDRHTi_LDRHTr_LDRH_POST_LDRH_PRE = 357, 3386 LDRT_POST_IMM_LDRT_POST_REG_LDR_POST_REG_LDR_PRE_REG = 358, 3387 LDR_POST_IMM_LDR_PRE_IMM_t2LDR_POST_t2LDR_PRE = 359, 3388 t2LDRBT_t2LDRHT = 360, 3389 t2LDRT = 361, 3390 t2LDRSBT_t2LDRSHT = 362, 3391 t2LDRSB_POST_t2LDRSB_PRE_t2LDRSH_POST_t2LDRSH_PRE = 363, 3392 LDRD = 364, 3393 t2LDRDi8 = 365, 3394 LDRD_POST_LDRD_PRE_t2LDRD_POST_t2LDRD_PRE = 366, 3395 LDMDA_LDMDB_LDMIA_LDMIB_sysLDMDA_sysLDMDB_sysLDMIA_sysLDMIB_t2LDMDB_t2LDMIA_tLDMIA = 367, 3396 LDMDA_UPD_LDMDB_UPD_LDMIA_UPD_LDMIB_UPD_sysLDMDA_UPD_sysLDMDB_UPD_sysLDMIA_UPD_sysLDMIB_UPD_t2LDMDB_UPD_t2LDMIA_UPD_tLDMIA_UPD = 368, 3397 LDMIA_RET_t2LDMIA_RET = 369, 3398 tPOP = 370, 3399 tPOP_RET = 371, 3400 PICSTR_STRi12_tSTRr = 372, 3401 PICSTRB_PICSTRH_STRBi12_STRH_tSTRBr_tSTRHr = 373, 3402 STRBrs_t2STRBs_t2STRHs = 374, 3403 STREX_STREXB_STREXD_STREXH = 375, 3404 STRrs_t2STRs = 376, 3405 t2STRBi12_t2STRBi8_t2STRHi12_t2STRHi8_tSTRBi_tSTRHi = 377, 3406 t2STRi12_t2STRi8_tSTRi_tSTRspi = 378, 3407 STRBT_POST_STRT_POST = 379, 3408 STRBT_POST_IMM_STRBT_POST_REG_STRB_POST_REG_STRB_PRE_REG_STRHTi_STRHTr_STRH_POST_STRH_PRE = 380, 3409 STRB_POST_IMM_STRB_PRE_IMM_t2STRB_POST_t2STRB_PRE_t2STRH_POST = 381, 3410 STRBi_preidx_STRBr_preidx_STRH_preidx_STRT_POST_IMM_STRT_POST_REG_STR_POST_REG_STR_PRE_REG_STRi_preidx_STRr_preidx_t2STRB_preidx_t2STRH_preidx_t2STR_preidx = 382, 3411 STR_POST_IMM_STR_PRE_IMM_t2STRH_PRE_t2STR_POST_t2STR_PRE = 383, 3412 t2STRBT_t2STRHT = 384, 3413 t2STRT = 385, 3414 STRD_t2STRDi8 = 386, 3415 STRD_POST_STRD_PRE_t2STRD_POST_t2STRD_PRE = 387, 3416 STMDA_STMDB_STMIA_STMIB_sysSTMDA_sysSTMDB_sysSTMIA_sysSTMIB_t2STMDB_t2STMIA = 388, 3417 STMDA_UPD_STMDB_UPD_STMIA_UPD_STMIB_UPD_sysSTMDA_UPD_sysSTMDB_UPD_sysSTMIA_UPD_sysSTMIB_UPD_t2STMDB_UPD_t2STMIA_UPD_tSTMIA_UPD = 389, 3418 tPUSH = 390, 3419 LDRLIT_ga_abs_tLDRLIT_ga_abs = 391, 3420 LDRLIT_ga_pcrel_tLDRLIT_ga_pcrel = 392, 3421 LDRLIT_ga_pcrel_ldr = 393, 3422 ITasm = 394, 3423 t2IT = 395, 3424 VADDLsv2i64_VADDLsv4i32_VADDLsv8i16_VADDLuv2i64_VADDLuv4i32_VADDLuv8i16_VNEGs16d_VNEGs32d_VNEGs8d_VPADDLsv16i8_VPADDLsv2i32_VPADDLsv4i16_VPADDLsv4i32_VPADDLsv8i16_VPADDLsv8i8_VPADDLuv16i8_VPADDLuv2i32_VPADDLuv4i16_VPADDLuv4i32_VPADDLuv8i16_VPADDLuv8i8_VPADDi16_VPADDi32_VPADDi8_VSHLLi16_VSHLLi32_VSHLLi8_VSHLLsv2i64_VSHLLsv4i32_VSHLLsv8i16_VSHLLuv2i64_VSHLLuv4i32_VSHLLuv8i16_VSHLiv16i8_VSHLiv1i64_VSHLiv2i32_VSHLiv2i64_VSHLiv4i16_VSHLiv4i32_VSHLiv8i16_VSHLiv8i8_VSHLsv1i64_VSHLsv2i32_VSHLsv4i16_VSHLsv8i8_VSHLuv1i64_VSHLuv2i32_VSHLuv4i16_VSHLuv8i8_VSHRsv16i8_VSHRsv1i64_VSHRsv2i32_VSHRsv2i64_VSHRsv4i16_VSHRsv4i32_VSHRsv8i16_VSHRsv8i8_VSHRuv16i8_VSHRuv1i64_VSHRuv2i32_VSHRuv2i64_VSHRuv4i16_VSHRuv4i32_VSHRuv8i16_VSHRuv8i8_VSLIv1i64_VSLIv2i32_VSLIv4i16_VSLIv8i8_VSRIv1i64_VSRIv2i32_VSRIv4i16_VSRIv8i8_VSUBLsv2i64_VSUBLsv4i32_VSUBLsv8i16_VSUBLuv2i64_VSUBLuv4i32_VSUBLuv8i16 = 396, 3425 VADDWsv2i64_VADDWsv4i32_VADDWsv8i16_VADDWuv2i64_VADDWuv4i32_VADDWuv8i16_VSUBWsv2i64_VSUBWsv4i32_VSUBWsv8i16_VSUBWuv2i64_VSUBWuv4i32_VSUBWuv8i16_VSUBv1i64_VSUBv2i32_VSUBv4i16_VSUBv8i8 = 397, 3426 VADDv16i8_VADDv2i64_VADDv4i32_VADDv8i16_VANDq_VBICq_VBIFq_VBITq_VEORq_VORNq_VORRq = 398, 3427 VADDv1i64_VADDv2i32_VADDv4i16_VADDv8i8_VANDd_VBICd_VBIFd_VBITd_VEORd_VORNd_VORRd = 399, 3428 VBICiv2i32_VBICiv4i16_VBICiv4i32_VBICiv8i16_VORRiv2i32_VORRiv4i16_VORRiv4i32_VORRiv8i16 = 400, 3429 VBSLd_VCLSv2i32_VCLSv4i16_VCLSv8i8_VCLZv2i32_VCLZv4i16_VCLZv8i8_VCNTd = 401, 3430 VBSLq_VCLSv16i8_VCLSv4i32_VCLSv8i16_VCLZv16i8_VCLZv4i32_VCLZv8i16_VCNTq = 402, 3431 VHADDsv16i8_VHADDsv4i32_VHADDsv8i16_VHADDuv16i8_VHADDuv4i32_VHADDuv8i16_VRHADDsv16i8_VRHADDsv4i32_VRHADDsv8i16_VRHADDuv16i8_VRHADDuv4i32_VRHADDuv8i16_VTSTv16i8_VTSTv4i32_VTSTv8i16 = 403, 3432 VHADDsv2i32_VHADDsv4i16_VHADDsv8i8_VHADDuv2i32_VHADDuv4i16_VHADDuv8i8_VRHADDsv2i32_VRHADDsv4i16_VRHADDsv8i8_VRHADDuv2i32_VRHADDuv4i16_VRHADDuv8i8_VTSTv2i32_VTSTv4i16_VTSTv8i8 = 404, 3433 VHSUBsv16i8_VHSUBsv4i32_VHSUBsv8i16_VHSUBuv16i8_VHSUBuv4i32_VHSUBuv8i16 = 405, 3434 VHSUBsv2i32_VHSUBsv4i16_VHSUBsv8i8_VHSUBuv2i32_VHSUBuv4i16_VHSUBuv8i8 = 406, 3435 VNEGf32q = 407, 3436 VNEGfd = 408, 3437 VNEGs16q_VNEGs32q_VNEGs8q_VSHLsv16i8_VSHLsv2i64_VSHLsv4i32_VSHLsv8i16_VSHLuv16i8_VSHLuv2i64_VSHLuv4i32_VSHLuv8i16_VSLIv16i8_VSLIv2i64_VSLIv4i32_VSLIv8i16_VSRIv16i8_VSRIv2i64_VSRIv4i32_VSRIv8i16 = 409, 3438 VQSHLsiv16i8_VQSHLsiv1i64_VQSHLsiv2i32_VQSHLsiv2i64_VQSHLsiv4i16_VQSHLsiv4i32_VQSHLsiv8i16_VQSHLsiv8i8_VQSHLsuv16i8_VQSHLsuv1i64_VQSHLsuv2i32_VQSHLsuv2i64_VQSHLsuv4i16_VQSHLsuv4i32_VQSHLsuv8i16_VQSHLsuv8i8_VQSHLsv1i64_VQSHLsv2i32_VQSHLsv4i16_VQSHLsv8i8_VQSHLuiv16i8_VQSHLuiv1i64_VQSHLuiv2i32_VQSHLuiv2i64_VQSHLuiv4i16_VQSHLuiv4i32_VQSHLuiv8i16_VQSHLuiv8i8_VQSHLuv1i64_VQSHLuv2i32_VQSHLuv4i16_VQSHLuv8i8 = 410, 3439 VQSHLsv16i8_VQSHLsv2i64_VQSHLsv4i32_VQSHLsv8i16_VQSHLuv16i8_VQSHLuv2i64_VQSHLuv4i32_VQSHLuv8i16 = 411, 3440 VSUBv16i8_VSUBv2i64_VSUBv4i32_VSUBv8i16 = 412, 3441 VEXTd16_VEXTd32_VEXTd8 = 413, 3442 VEXTq16_VEXTq32_VEXTq64_VEXTq8 = 414, 3443 VREV16d8_VREV32d16_VREV32d8_VREV64d16_VREV64d32_VREV64d8 = 415, 3444 VREV16q8_VREV32q16_VREV32q8_VREV64q16_VREV64q32_VREV64q8 = 416, 3445 VABALsv2i64_VABALsv4i32_VABALsv8i16_VABALuv2i64_VABALuv4i32_VABALuv8i16_VABAsv2i32_VABAsv4i16_VABAsv8i8_VABAuv2i32_VABAuv4i16_VABAuv8i8 = 417, 3446 VABAsv16i8_VABAsv4i32_VABAsv8i16_VABAuv16i8_VABAuv4i32_VABAuv8i16 = 418, 3447 VABSfd = 419, 3448 VABSfq = 420, 3449 VABSv16i8_VABSv4i32_VABSv8i16 = 421, 3450 VABSv2i32_VABSv4i16_VABSv8i8 = 422, 3451 VACGEfd_VACGEhd_VACGTfd_VACGThd_VCEQfd_VCEQhd_VCGEfd_VCGEhd_VCGTfd_VCGThd = 423, 3452 VACGEfq_VACGEhq_VACGTfq_VACGThq_VCEQfq_VCEQhq_VCGEfq_VCGEhq_VCGTfq_VCGThq = 424, 3453 VCEQv16i8_VCEQv4i32_VCEQv8i16_VCGEsv16i8_VCGEsv4i32_VCGEsv8i16_VCGEuv16i8_VCGEuv4i32_VCGEuv8i16_VCGTsv16i8_VCGTsv4i32_VCGTsv8i16_VCGTuv16i8_VCGTuv4i32_VCGTuv8i16_VQSUBsv16i8_VQSUBsv2i64_VQSUBsv4i32_VQSUBsv8i16_VQSUBuv16i8_VQSUBuv2i64_VQSUBuv4i32_VQSUBuv8i16 = 425, 3454 VCEQv2i32_VCEQv4i16_VCEQv8i8_VCGEsv2i32_VCGEsv4i16_VCGEsv8i8_VCGEuv2i32_VCGEuv4i16_VCGEuv8i8_VCGTsv2i32_VCGTsv4i16_VCGTsv8i8_VCGTuv2i32_VCGTuv4i16_VCGTuv8i8_VQSUBsv1i64_VQSUBsv2i32_VQSUBsv4i16_VQSUBsv8i8_VQSUBuv1i64_VQSUBuv2i32_VQSUBuv4i16_VQSUBuv8i8 = 426, 3455 VCEQzv16i8_VCEQzv2f32_VCEQzv2i32_VCEQzv4f16_VCEQzv4f32_VCEQzv4i16_VCEQzv4i32_VCEQzv8f16_VCEQzv8i16_VCEQzv8i8_VCGEzv16i8_VCGEzv2f32_VCGEzv2i32_VCGEzv4f16_VCGEzv4f32_VCGEzv4i16_VCGEzv4i32_VCGEzv8f16_VCGEzv8i16_VCGEzv8i8_VCGTzv16i8_VCGTzv2f32_VCGTzv2i32_VCGTzv4f16_VCGTzv4f32_VCGTzv4i16_VCGTzv4i32_VCGTzv8f16_VCGTzv8i16_VCGTzv8i8_VCLEzv16i8_VCLEzv2f32_VCLEzv2i32_VCLEzv4f16_VCLEzv4f32_VCLEzv4i16_VCLEzv4i32_VCLEzv8f16_VCLEzv8i16_VCLEzv8i8_VCLTzv16i8_VCLTzv2f32_VCLTzv2i32_VCLTzv4f16_VCLTzv4f32_VCLTzv4i16_VCLTzv4i32_VCLTzv8f16_VCLTzv8i16_VCLTzv8i8 = 427, 3456 VPADALsv16i8_VPADALsv4i32_VPADALsv8i16_VPADALuv16i8_VPADALuv4i32_VPADALuv8i16 = 428, 3457 VPADALsv2i32_VPADALsv4i16_VPADALsv8i8_VPADALuv2i32_VPADALuv4i16_VPADALuv8i8_VRSRAsv16i8_VRSRAsv1i64_VRSRAsv2i32_VRSRAsv2i64_VRSRAsv4i16_VRSRAsv4i32_VRSRAsv8i16_VRSRAsv8i8_VRSRAuv16i8_VRSRAuv1i64_VRSRAuv2i32_VRSRAuv2i64_VRSRAuv4i16_VRSRAuv4i32_VRSRAuv8i16_VRSRAuv8i8_VSRAsv16i8_VSRAsv1i64_VSRAsv2i32_VSRAsv2i64_VSRAsv4i16_VSRAsv4i32_VSRAsv8i16_VSRAsv8i8_VSRAuv16i8_VSRAuv1i64_VSRAuv2i32_VSRAuv2i64_VSRAuv4i16_VSRAuv4i32_VSRAuv8i16_VSRAuv8i8 = 429, 3458 VQABSv16i8_VQABSv4i32_VQABSv8i16_VQNEGv16i8_VQNEGv4i32_VQNEGv8i16 = 430, 3459 VQABSv2i32_VQABSv4i16_VQABSv8i8_VQNEGv2i32_VQNEGv4i16_VQNEGv8i8 = 431, 3460 VQADDsv16i8_VQADDsv2i64_VQADDsv4i32_VQADDsv8i16_VQADDuv16i8_VQADDuv2i64_VQADDuv4i32_VQADDuv8i16 = 432, 3461 VQADDsv1i64_VQADDsv2i32_VQADDsv4i16_VQADDsv8i8_VQADDuv1i64_VQADDuv2i32_VQADDuv4i16_VQADDuv8i8 = 433, 3462 VQRSHLsv16i8_VQRSHLsv2i64_VQRSHLsv4i32_VQRSHLsv8i16_VQRSHLuv16i8_VQRSHLuv2i64_VQRSHLuv4i32_VQRSHLuv8i16_VRSHLsv16i8_VRSHLsv2i64_VRSHLsv4i32_VRSHLsv8i16_VRSHLuv16i8_VRSHLuv2i64_VRSHLuv4i32_VRSHLuv8i16 = 434, 3463 VQRSHLsv1i64_VQRSHLsv2i32_VQRSHLsv4i16_VQRSHLsv8i8_VQRSHLuv1i64_VQRSHLuv2i32_VQRSHLuv4i16_VQRSHLuv8i8_VRSHLsv1i64_VRSHLsv2i32_VRSHLsv4i16_VRSHLsv8i8_VRSHLuv1i64_VRSHLuv2i32_VRSHLuv4i16_VRSHLuv8i8_VRSHRsv16i8_VRSHRsv1i64_VRSHRsv2i32_VRSHRsv2i64_VRSHRsv4i16_VRSHRsv4i32_VRSHRsv8i16_VRSHRsv8i8_VRSHRuv16i8_VRSHRuv1i64_VRSHRuv2i32_VRSHRuv2i64_VRSHRuv4i16_VRSHRuv4i32_VRSHRuv8i16_VRSHRuv8i8 = 435, 3464 VRECPEd_VRECPEfd_VRECPEhd_VRSQRTEd_VRSQRTEfd_VRSQRTEhd = 436, 3465 VRECPEfq_VRECPEhq_VRECPEq_VRSQRTEfq_VRSQRTEhq_VRSQRTEq = 437, 3466 VADDHNv2i32_VADDHNv4i16_VADDHNv8i8_VSUBHNv2i32_VSUBHNv4i16_VSUBHNv8i8 = 438, 3467 VSHRNv2i32_VSHRNv4i16_VSHRNv8i8 = 439, 3468 VQRSHRNsv2i32_VQRSHRNsv4i16_VQRSHRNsv8i8_VQRSHRNuv2i32_VQRSHRNuv4i16_VQRSHRNuv8i8_VQRSHRUNv2i32_VQRSHRUNv4i16_VQRSHRUNv8i8_VQSHRNsv2i32_VQSHRNsv4i16_VQSHRNsv8i8_VQSHRNuv2i32_VQSHRNuv4i16_VQSHRNuv8i8_VQSHRUNv2i32_VQSHRUNv4i16_VQSHRUNv8i8_VRSHRNv2i32_VRSHRNv4i16_VRSHRNv8i8 = 440, 3469 VRADDHNv2i32_VRADDHNv4i16_VRADDHNv8i8_VRSUBHNv2i32_VRSUBHNv4i16_VRSUBHNv8i8 = 441, 3470 VTBL1 = 442, 3471 VTBX1 = 443, 3472 VTBL2 = 444, 3473 VTBX2 = 445, 3474 VTBL3_VTBL3Pseudo = 446, 3475 VTBX3_VTBX3Pseudo = 447, 3476 VTBL4_VTBL4Pseudo = 448, 3477 VTBX4_VTBX4Pseudo = 449, 3478 VSWPd_VSWPq = 450, 3479 VTRNd16_VTRNd32_VTRNd8_VUZPd16_VUZPd8_VZIPd16_VZIPd8 = 451, 3480 VTRNq16_VTRNq32_VTRNq8 = 452, 3481 VUZPq16_VUZPq32_VUZPq8_VZIPq16_VZIPq32_VZIPq8 = 453, 3482 VABSD_VNEGD = 454, 3483 VABSS_VNEGS = 455, 3484 VCMPD_VCMPED_VCMPEZD_VCMPZD = 456, 3485 VCMPES_VCMPEZS_VCMPS_VCMPZS = 457, 3486 VABDLsv2i64_VABDLsv4i32_VABDLsv8i16_VABDLuv2i64_VABDLuv4i32_VABDLuv8i16_VABDsv16i8_VABDsv4i32_VABDsv8i16_VABDuv16i8_VABDuv4i32_VABDuv8i16_VMAXsv16i8_VMAXsv4i32_VMAXsv8i16_VMAXuv16i8_VMAXuv4i32_VMAXuv8i16_VMINsv16i8_VMINsv4i32_VMINsv8i16_VMINuv16i8_VMINuv4i32_VMINuv8i16 = 458, 3487 VABDfd_VABDhd_VADDfd_VMAXfd_VMAXhd_VMINfd_VMINhd_VSUBfd = 459, 3488 VABDfq_VABDhq_VADDfq_VMAXfq_VMAXhq_VMINfq_VMINhq_VSUBfq = 460, 3489 VABDsv2i32_VABDsv4i16_VABDsv8i8_VABDuv2i32_VABDuv4i16_VABDuv8i8_VMAXsv2i32_VMAXsv4i16_VMAXsv8i8_VMAXuv2i32_VMAXuv4i16_VMAXuv8i8_VMINsv2i32_VMINsv4i16_VMINsv8i8_VMINuv2i32_VMINuv4i16_VMINuv8i8_VPMAXs16_VPMAXs32_VPMAXs8_VPMAXu16_VPMAXu32_VPMAXu8_VPMINs16_VPMINs32_VPMINs8_VPMINu16_VPMINu32_VPMINu8 = 461, 3490 VADDS_VSUBS = 462, 3491 VMAXNMD_VMAXNMH_VMAXNMNDf_VMAXNMNDh_VMAXNMNQf_VMAXNMNQh_VMAXNMS_VMINNMD_VMINNMH_VMINNMNDf_VMINNMNDh_VMINNMNQf_VMINNMNQh_VMINNMS = 463, 3492 VPADDf_VPMAXf_VPMAXh_VPMINf_VPMINh = 464, 3493 VADDD_VSUBD = 465, 3494 VRECPSfd_VRECPShd_VRSQRTSfd_VRSQRTShd = 466, 3495 VRECPSfq_VRECPShq_VRSQRTSfq_VRSQRTShq = 467, 3496 VMULLp64 = 468, 3497 VMULLp8_VMULLslsv2i32_VMULLslsv4i16_VMULLsluv2i32_VMULLsluv4i16_VMULLsv4i32_VMULLsv8i16_VMULLuv4i32_VMULLuv8i16_VMULpd_VMULslhd_VMULslv4i16_VMULv4i16_VMULv8i8_VQDMULHslv4i16_VQDMULHv4i16_VQDMULLslv2i32_VQDMULLslv4i16_VQDMULLv4i32_VQRDMULHslv4i16_VQRDMULHv4i16 = 469, 3498 VMULLsv2i64_VMULLuv2i64_VMULslv2i32_VMULv2i32_VQDMULHslv2i32_VQDMULHv2i32_VQDMULLv2i64_VQRDMULHslv2i32_VQRDMULHv2i32 = 470, 3499 VMULS_VNMULS = 471, 3500 VMULfd = 472, 3501 VMULfq = 473, 3502 VMULpq_VMULslhq_VMULslv8i16_VMULv16i8_VMULv8i16_VQDMULHslv8i16_VQDMULHv8i16_VQRDMULHslv8i16_VQRDMULHv8i16 = 474, 3503 VMULslfd = 475, 3504 VMULslfq = 476, 3505 VMULslv4i32_VMULv4i32_VQDMULHslv4i32_VQDMULHv4i32_VQRDMULHslv4i32_VQRDMULHv4i32 = 477, 3506 VMULD_VNMULD = 478, 3507 VFMAD_VFMSD_VFNMAD_VFNMSD = 479, 3508 VFMAS_VFMSS_VFNMAS_VFNMSS = 480, 3509 VFNMAH_VFNMSH = 481, 3510 VMLAD_VMLSD_VNMLAD_VNMLSD = 482, 3511 VMLAH_VMLSH_VNMLAH_VNMLSH = 483, 3512 VMLALslsv2i32_VMLALsluv2i32_VMLALsv2i64_VMLALuv2i64_VMLAslv2i32_VMLAv2i32_VMLSLslsv2i32_VMLSLsluv2i32_VMLSLsv2i64_VMLSLuv2i64_VMLSslv2i32_VMLSv2i32_VQDMLALslv2i32_VQDMLALv2i64_VQDMLSLslv2i32_VQDMLSLv2i64 = 484, 3513 VMLALslsv4i16_VMLALsluv4i16_VMLALsv4i32_VMLALsv8i16_VMLALuv4i32_VMLALuv8i16_VMLAslv4i16_VMLAv4i16_VMLAv8i8_VMLSLslsv4i16_VMLSLsluv4i16_VMLSLsv4i32_VMLSLsv8i16_VMLSLuv4i32_VMLSLuv8i16_VMLSslv4i16_VMLSv4i16_VMLSv8i8_VQDMLALslv4i16_VQDMLALv4i32_VQDMLSLslv4i16_VQDMLSLv4i32 = 485, 3514 VMLAS_VMLSS_VNMLAS_VNMLSS = 486, 3515 VMLAfd_VMLAhd_VMLAslfd_VMLAslhd_VMLSfd_VMLShd_VMLSslfd_VMLSslhd = 487, 3516 VMLAfq_VMLAhq_VMLAslfq_VMLAslhq_VMLSfq_VMLShq_VMLSslfq_VMLSslhq = 488, 3517 VMLAslv4i32_VMLAv4i32_VMLSslv4i32_VMLSv4i32 = 489, 3518 VMLAslv8i16_VMLAv16i8_VMLAv8i16_VMLSslv8i16_VMLSv16i8_VMLSv8i16 = 490, 3519 VFMAfd_VFMSfd = 491, 3520 VFMAfq_VFMSfq = 492, 3521 VCVTANSDf_VCVTANSDh_VCVTANSQf_VCVTANSQh_VCVTANUDf_VCVTANUDh_VCVTANUQf_VCVTANUQh_VCVTASD_VCVTASH_VCVTASS_VCVTAUD_VCVTAUH_VCVTAUS_VCVTBDH_VCVTBHD_VCVTMNSDf_VCVTMNSDh_VCVTMNSQf_VCVTMNSQh_VCVTMNUDf_VCVTMNUDh_VCVTMNUQf_VCVTMNUQh_VCVTMSD_VCVTMSH_VCVTMSS_VCVTMUD_VCVTMUH_VCVTMUS_VCVTNNSDf_VCVTNNSDh_VCVTNNSQf_VCVTNNSQh_VCVTNNUDf_VCVTNNUDh_VCVTNNUQf_VCVTNNUQh_VCVTNSD_VCVTNSH_VCVTNSS_VCVTNUD_VCVTNUH_VCVTNUS_VCVTPNSDf_VCVTPNSDh_VCVTPNSQf_VCVTPNSQh_VCVTPNUDf_VCVTPNUDh_VCVTPNUQf_VCVTPNUQh_VCVTPSD_VCVTPSH_VCVTPSS_VCVTPUD_VCVTPUH_VCVTPUS_VCVTTDH_VCVTTHD = 493, 3522 VCVTBHS_VCVTTHS = 494, 3523 VCVTBSH_VCVTTSH = 495, 3524 VCVTDS = 496, 3525 VCVTSD = 497, 3526 VCVTf2h_VCVTf2sq_VCVTf2uq_VCVTf2xsq_VCVTf2xuq_VCVTh2f_VCVTh2sq_VCVTh2uq_VCVTh2xsq_VCVTh2xuq_VCVTs2fq_VCVTs2hq_VCVTu2fq_VCVTu2hq_VCVTxs2fq_VCVTxs2hq_VCVTxu2fq_VCVTxu2hq = 498, 3527 VCVTf2sd_VCVTf2ud_VCVTf2xsd_VCVTf2xud_VCVTh2sd_VCVTh2ud_VCVTh2xsd_VCVTh2xud_VCVTs2fd_VCVTs2hd_VCVTu2fd_VCVTu2hd_VCVTxs2fd_VCVTxs2hd_VCVTxu2fd_VCVTxu2hd = 499, 3528 VSITOD_VUITOD = 500, 3529 VSITOH_VUITOH = 501, 3530 VSITOS_VUITOS = 502, 3531 VTOSHD_VTOSLD_VTOUHD_VTOULD = 503, 3532 VTOSHH_VTOSLH_VTOUHH_VTOULH = 504, 3533 VTOSHS_VTOSLS_VTOUHS_VTOULS = 505, 3534 VTOSIRD_VTOSIZD_VTOUIRD_VTOUIZD = 506, 3535 VTOSIRH_VTOSIZH_VTOUIRH_VTOUIZH = 507, 3536 VTOSIRS_VTOSIZS_VTOUIRS_VTOUIZS = 508, 3537 FCONSTD_VMOVD_VMOVDcc = 509, 3538 FCONSTS_VMOVS_VMOVScc = 510, 3539 VMOVv16i8_VMOVv1i64_VMOVv2f32_VMOVv2i32_VMOVv2i64_VMOVv4f32_VMOVv4i16_VMOVv4i32_VMOVv8i16_VMOVv8i8_VMVNv2i32_VMVNv4i16_VMVNv4i32_VMVNv8i16 = 511, 3540 VMVNd_VMVNq = 512, 3541 VMOVLsv2i64_VMOVLsv4i32_VMOVLsv8i16_VMOVLuv2i64_VMOVLuv4i32_VMOVLuv8i16 = 513, 3542 VMOVNv2i32_VMOVNv4i16_VMOVNv8i8 = 514, 3543 VQMOVNsuv2i32_VQMOVNsuv4i16_VQMOVNsuv8i8_VQMOVNsv2i32_VQMOVNsv4i16_VQMOVNsv8i8_VQMOVNuv2i32_VQMOVNuv4i16_VQMOVNuv8i8 = 515, 3544 VDUPLN16d_VDUPLN32d_VDUPLN8d = 516, 3545 VDUPLN16q_VDUPLN32q_VDUPLN8q = 517, 3546 VDUP16d_VDUP16q_VDUP32d_VDUP32q_VDUP8d_VDUP8q = 518, 3547 VMOVRS = 519, 3548 VMOVSR = 520, 3549 VSETLNi16_VSETLNi32_VSETLNi8 = 521, 3550 VMOVRRD_VMOVRRS = 522, 3551 VMOVDRR = 523, 3552 VMOVSRR = 524, 3553 VGETLNi32_VGETLNu16_VGETLNu8 = 525, 3554 VGETLNs16_VGETLNs8 = 526, 3555 VMRS_VMRS_FPEXC_VMRS_FPINST_VMRS_FPINST2_VMRS_FPSID_VMRS_MVFR0_VMRS_MVFR1_VMRS_MVFR2 = 527, 3556 VMSR_VMSR_FPEXC_VMSR_FPINST_VMSR_FPINST2_VMSR_FPSID = 528, 3557 FMSTAT = 529, 3558 VLDRD = 530, 3559 VLDRS = 531, 3560 VSTRD = 532, 3561 VSTRS = 533, 3562 VLDMQIA = 534, 3563 VSTMQIA = 535, 3564 VLDMDIA_VLDMSIA = 536, 3565 VLDMDDB_UPD_VLDMDIA_UPD_VLDMSDB_UPD_VLDMSIA_UPD = 537, 3566 VSTMDIA_VSTMSIA = 538, 3567 VSTMDDB_UPD_VSTMDIA_UPD_VSTMSDB_UPD_VSTMSIA_UPD = 539, 3568 VLD1d16_VLD1d32_VLD1d64_VLD1d8 = 540, 3569 VLD1q16_VLD1q32_VLD1q64_VLD1q8 = 541, 3570 VLD1d16wb_fixed_VLD1d16wb_register_VLD1d32wb_fixed_VLD1d32wb_register_VLD1d64wb_fixed_VLD1d64wb_register_VLD1d8wb_fixed_VLD1d8wb_register = 542, 3571 VLD1q16wb_fixed_VLD1q16wb_register_VLD1q32wb_fixed_VLD1q32wb_register_VLD1q64wb_fixed_VLD1q64wb_register_VLD1q8wb_fixed_VLD1q8wb_register = 543, 3572 VLD1d16T_VLD1d32T_VLD1d64T_VLD1d64TPseudo_VLD1d64TPseudoWB_fixed_VLD1d64TPseudoWB_register_VLD1d8T = 544, 3573 VLD1d16Twb_fixed_VLD1d16Twb_register_VLD1d32Twb_fixed_VLD1d32Twb_register_VLD1d64Twb_fixed_VLD1d64Twb_register_VLD1d8Twb_fixed_VLD1d8Twb_register = 545, 3574 VLD1d16Q_VLD1d32Q_VLD1d64Q_VLD1d64QPseudo_VLD1d64QPseudoWB_fixed_VLD1d64QPseudoWB_register_VLD1d8Q = 546, 3575 VLD1d16Qwb_fixed_VLD1d16Qwb_register_VLD1d32Qwb_fixed_VLD1d32Qwb_register_VLD1d64Qwb_fixed_VLD1d64Qwb_register_VLD1d8Qwb_fixed_VLD1d8Qwb_register = 547, 3576 VLD2b16_VLD2b32_VLD2b8_VLD2d16_VLD2d32_VLD2d8 = 548, 3577 VLD2q16_VLD2q16Pseudo_VLD2q32_VLD2q32Pseudo_VLD2q8_VLD2q8Pseudo = 549, 3578 VLD2b16wb_fixed_VLD2b16wb_register_VLD2b32wb_fixed_VLD2b32wb_register_VLD2b8wb_fixed_VLD2b8wb_register_VLD2d16wb_fixed_VLD2d16wb_register_VLD2d32wb_fixed_VLD2d32wb_register_VLD2d8wb_fixed_VLD2d8wb_register = 550, 3579 VLD2q16PseudoWB_fixed_VLD2q16PseudoWB_register_VLD2q16wb_fixed_VLD2q16wb_register_VLD2q32PseudoWB_fixed_VLD2q32PseudoWB_register_VLD2q32wb_fixed_VLD2q32wb_register_VLD2q8PseudoWB_fixed_VLD2q8PseudoWB_register_VLD2q8wb_fixed_VLD2q8wb_register = 551, 3580 VLD3d16_VLD3d32_VLD3d8_VLD3q16_VLD3q32_VLD3q8 = 552, 3581 VLD3d16Pseudo_VLD3d32Pseudo_VLD3d8Pseudo_VLD3q16oddPseudo_VLD3q32oddPseudo_VLD3q8oddPseudo = 553, 3582 VLD3d16_UPD_VLD3d32_UPD_VLD3d8_UPD_VLD3q16_UPD_VLD3q32_UPD_VLD3q8_UPD = 554, 3583 VLD3d16Pseudo_UPD_VLD3d32Pseudo_UPD_VLD3d8Pseudo_UPD_VLD3q16Pseudo_UPD_VLD3q16oddPseudo_UPD_VLD3q32Pseudo_UPD_VLD3q32oddPseudo_UPD_VLD3q8Pseudo_UPD_VLD3q8oddPseudo_UPD = 555, 3584 VLD4d16_VLD4d32_VLD4d8_VLD4q16_VLD4q32_VLD4q8 = 556, 3585 VLD4d16Pseudo_VLD4d32Pseudo_VLD4d8Pseudo_VLD4q16oddPseudo_VLD4q32oddPseudo_VLD4q8oddPseudo = 557, 3586 VLD4d16_UPD_VLD4d32_UPD_VLD4d8_UPD_VLD4q16_UPD_VLD4q32_UPD_VLD4q8_UPD = 558, 3587 VLD4d16Pseudo_UPD_VLD4d32Pseudo_UPD_VLD4d8Pseudo_UPD_VLD4q16Pseudo_UPD_VLD4q16oddPseudo_UPD_VLD4q32Pseudo_UPD_VLD4q32oddPseudo_UPD_VLD4q8Pseudo_UPD_VLD4q8oddPseudo_UPD = 559, 3588 VLD1DUPd16_VLD1DUPd32_VLD1DUPd8_VLD1DUPq16_VLD1DUPq32_VLD1DUPq8 = 560, 3589 VLD1LNd16_VLD1LNd32_VLD1LNd8_VLD1LNq16Pseudo_VLD1LNq32Pseudo_VLD1LNq8Pseudo = 561, 3590 VLD1DUPd16wb_fixed_VLD1DUPd16wb_register_VLD1DUPd32wb_fixed_VLD1DUPd32wb_register_VLD1DUPd8wb_fixed_VLD1DUPd8wb_register_VLD1DUPq16wb_fixed_VLD1DUPq16wb_register_VLD1DUPq32wb_fixed_VLD1DUPq32wb_register_VLD1DUPq8wb_fixed_VLD1DUPq8wb_register = 562, 3591 VLD1LNd16_UPD_VLD1LNd32_UPD_VLD1LNd8_UPD_VLD1LNq16Pseudo_UPD_VLD1LNq32Pseudo_UPD_VLD1LNq8Pseudo_UPD = 563, 3592 VLD2DUPd16_VLD2DUPd16x2_VLD2DUPd32_VLD2DUPd32x2_VLD2DUPd8_VLD2DUPd8x2 = 564, 3593 VLD2LNd16_VLD2LNd16Pseudo_VLD2LNd32_VLD2LNd32Pseudo_VLD2LNd8_VLD2LNd8Pseudo_VLD2LNq16_VLD2LNq16Pseudo_VLD2LNq32_VLD2LNq32Pseudo = 565, 3594 VLD2LNd16_UPD_VLD2LNd32_UPD_VLD2LNd8_UPD_VLD2LNq16_UPD_VLD2LNq32_UPD = 566, 3595 VLD2DUPd16wb_fixed_VLD2DUPd16wb_register_VLD2DUPd16x2wb_fixed_VLD2DUPd16x2wb_register_VLD2DUPd32wb_fixed_VLD2DUPd32wb_register_VLD2DUPd32x2wb_fixed_VLD2DUPd32x2wb_register_VLD2DUPd8wb_fixed_VLD2DUPd8wb_register_VLD2DUPd8x2wb_fixed_VLD2DUPd8x2wb_register = 567, 3596 VLD2LNd16Pseudo_UPD_VLD2LNd32Pseudo_UPD_VLD2LNd8Pseudo_UPD_VLD2LNq16Pseudo_UPD_VLD2LNq32Pseudo_UPD = 568, 3597 VLD3DUPd16_VLD3DUPd16Pseudo_VLD3DUPd32_VLD3DUPd32Pseudo_VLD3DUPd8_VLD3DUPd8Pseudo_VLD3DUPq16_VLD3DUPq32_VLD3DUPq8 = 569, 3598 VLD3LNd16_VLD3LNd16Pseudo_VLD3LNd32_VLD3LNd32Pseudo_VLD3LNd8_VLD3LNd8Pseudo_VLD3LNq16_VLD3LNq16Pseudo_VLD3LNq32_VLD3LNq32Pseudo = 570, 3599 VLD3DUPd16_UPD_VLD3DUPd32_UPD_VLD3DUPd8_UPD_VLD3DUPq16_UPD_VLD3DUPq32_UPD_VLD3DUPq8_UPD = 571, 3600 VLD3LNd16_UPD_VLD3LNd32_UPD_VLD3LNd8_UPD_VLD3LNq16_UPD_VLD3LNq32_UPD = 572, 3601 VLD3DUPd16Pseudo_UPD_VLD3DUPd32Pseudo_UPD_VLD3DUPd8Pseudo_UPD = 573, 3602 VLD3LNd16Pseudo_UPD_VLD3LNd32Pseudo_UPD_VLD3LNd8Pseudo_UPD_VLD3LNq16Pseudo_UPD_VLD3LNq32Pseudo_UPD = 574, 3603 VLD4DUPd16_VLD4DUPd16Pseudo_VLD4DUPd32_VLD4DUPd32Pseudo_VLD4DUPd8_VLD4DUPd8Pseudo_VLD4DUPq16_VLD4DUPq32_VLD4DUPq8 = 575, 3604 VLD4LNd16_VLD4LNd16Pseudo_VLD4LNd32_VLD4LNd32Pseudo_VLD4LNd8_VLD4LNd8Pseudo_VLD4LNq16_VLD4LNq16Pseudo_VLD4LNq32_VLD4LNq32Pseudo = 576, 3605 VLD4DUPd16_UPD_VLD4DUPd32_UPD_VLD4DUPd8_UPD_VLD4DUPq16_UPD_VLD4DUPq32_UPD_VLD4DUPq8_UPD = 577, 3606 VLD4LNd16_UPD_VLD4LNd32_UPD_VLD4LNd8_UPD_VLD4LNq16_UPD_VLD4LNq32_UPD = 578, 3607 VLD4DUPd16Pseudo_UPD_VLD4DUPd32Pseudo_UPD_VLD4DUPd8Pseudo_UPD = 579, 3608 VLD4LNd16Pseudo_UPD_VLD4LNd32Pseudo_UPD_VLD4LNd8Pseudo_UPD_VLD4LNq16Pseudo_UPD_VLD4LNq32Pseudo_UPD = 580, 3609 VST1d16_VST1d32_VST1d64_VST1d8 = 581, 3610 VST1q16_VST1q32_VST1q64_VST1q8 = 582, 3611 VST1d16wb_fixed_VST1d16wb_register_VST1d32wb_fixed_VST1d32wb_register_VST1d64wb_fixed_VST1d64wb_register_VST1d8wb_fixed_VST1d8wb_register = 583, 3612 VST1q16wb_fixed_VST1q16wb_register_VST1q32wb_fixed_VST1q32wb_register_VST1q64wb_fixed_VST1q64wb_register_VST1q8wb_fixed_VST1q8wb_register = 584, 3613 VST1d16T_VST1d32T_VST1d64T_VST1d64TPseudo_VST1d8T = 585, 3614 VST1d16Twb_fixed_VST1d16Twb_register_VST1d32Twb_fixed_VST1d32Twb_register_VST1d64Twb_fixed_VST1d64Twb_register_VST1d8Twb_fixed_VST1d8Twb_register = 586, 3615 VST1d64TPseudoWB_fixed_VST1d64TPseudoWB_register = 587, 3616 VST1d16Q_VST1d32Q_VST1d64Q_VST1d64QPseudo_VST1d8Q = 588, 3617 VST1d16Qwb_fixed_VST1d16Qwb_register_VST1d32Qwb_fixed_VST1d32Qwb_register_VST1d64Qwb_fixed_VST1d64Qwb_register_VST1d8Qwb_fixed_VST1d8Qwb_register = 589, 3618 VST1d64QPseudoWB_fixed_VST1d64QPseudoWB_register = 590, 3619 VST2b16_VST2b32_VST2b8_VST2d16_VST2d32_VST2d8 = 591, 3620 VST2b16wb_fixed_VST2b16wb_register_VST2b32wb_fixed_VST2b32wb_register_VST2b8wb_fixed_VST2b8wb_register_VST2d16wb_fixed_VST2d16wb_register_VST2d32wb_fixed_VST2d32wb_register_VST2d8wb_fixed_VST2d8wb_register = 592, 3621 VST2q16_VST2q16Pseudo_VST2q32_VST2q32Pseudo_VST2q8_VST2q8Pseudo = 593, 3622 VST2q16PseudoWB_fixed_VST2q16PseudoWB_register_VST2q32PseudoWB_fixed_VST2q32PseudoWB_register_VST2q8PseudoWB_fixed_VST2q8PseudoWB_register = 594, 3623 VST2q16wb_fixed_VST2q16wb_register_VST2q32wb_fixed_VST2q32wb_register_VST2q8wb_fixed_VST2q8wb_register = 595, 3624 VST3d16_VST3d16Pseudo_VST3d32_VST3d32Pseudo_VST3d8_VST3d8Pseudo_VST3q16_VST3q16oddPseudo_VST3q32_VST3q32oddPseudo_VST3q8_VST3q8oddPseudo = 596, 3625 VST3d16Pseudo_UPD_VST3d16_UPD_VST3d32Pseudo_UPD_VST3d32_UPD_VST3d8Pseudo_UPD_VST3d8_UPD_VST3q16Pseudo_UPD_VST3q16_UPD_VST3q16oddPseudo_UPD_VST3q32Pseudo_UPD_VST3q32_UPD_VST3q32oddPseudo_UPD_VST3q8Pseudo_UPD_VST3q8_UPD_VST3q8oddPseudo_UPD = 597, 3626 VST4d16_VST4d16Pseudo_VST4d32_VST4d32Pseudo_VST4d8_VST4d8Pseudo_VST4q16_VST4q16oddPseudo_VST4q32_VST4q32oddPseudo_VST4q8_VST4q8oddPseudo = 598, 3627 VST4d16Pseudo_UPD_VST4d16_UPD_VST4d32Pseudo_UPD_VST4d32_UPD_VST4d8Pseudo_UPD_VST4d8_UPD_VST4q16Pseudo_UPD_VST4q16_UPD_VST4q16oddPseudo_UPD_VST4q32Pseudo_UPD_VST4q32_UPD_VST4q32oddPseudo_UPD_VST4q8Pseudo_UPD_VST4q8_UPD_VST4q8oddPseudo_UPD = 599, 3628 VST1LNd16_VST1LNd32_VST1LNd8_VST1LNq16Pseudo_VST1LNq32Pseudo_VST1LNq8Pseudo = 600, 3629 VST1LNd16_UPD_VST1LNd32_UPD_VST1LNd8_UPD_VST1LNq16Pseudo_UPD_VST1LNq32Pseudo_UPD_VST1LNq8Pseudo_UPD = 601, 3630 VST2LNd16_VST2LNd16Pseudo_VST2LNd32_VST2LNd32Pseudo_VST2LNd8_VST2LNd8Pseudo_VST2LNq16_VST2LNq16Pseudo_VST2LNq32_VST2LNq32Pseudo = 602, 3631 VST2LNd16Pseudo_UPD_VST2LNd16_UPD_VST2LNd32Pseudo_UPD_VST2LNd32_UPD_VST2LNd8Pseudo_UPD_VST2LNd8_UPD_VST2LNq16Pseudo_UPD_VST2LNq16_UPD_VST2LNq32Pseudo_UPD_VST2LNq32_UPD = 603, 3632 VST3LNd16_VST3LNd16Pseudo_VST3LNd32_VST3LNd32Pseudo_VST3LNd8_VST3LNd8Pseudo_VST3LNq16_VST3LNq16Pseudo_VST3LNq32_VST3LNq32Pseudo = 604, 3633 VST3LNd16Pseudo_UPD_VST3LNd16_UPD_VST3LNd32Pseudo_UPD_VST3LNd32_UPD_VST3LNd8Pseudo_UPD_VST3LNd8_UPD_VST3LNq16Pseudo_UPD_VST3LNq16_UPD_VST3LNq32Pseudo_UPD_VST3LNq32_UPD = 605, 3634 VST4LNd16_VST4LNd16Pseudo_VST4LNd32_VST4LNd32Pseudo_VST4LNd8_VST4LNd8Pseudo_VST4LNq16_VST4LNq16Pseudo_VST4LNq32_VST4LNq32Pseudo = 606, 3635 VST4LNd16Pseudo_UPD_VST4LNd16_UPD_VST4LNd32Pseudo_UPD_VST4LNd32_UPD_VST4LNd8Pseudo_UPD_VST4LNd8_UPD_VST4LNq16Pseudo_UPD_VST4LNq16_UPD_VST4LNq32Pseudo_UPD_VST4LNq32_UPD = 607, 3636 VDIVS = 608, 3637 VSQRTS = 609, 3638 VDIVD = 610, 3639 VSQRTD = 611, 3640 ABS = 612, 3641 SCHED_LIST_END = 613 3642 }; 3643} // end Sched namespace 3644} // end ARM namespace 3645} // end llvm namespace 3646#endif // GET_INSTRINFO_ENUM 3647 3648/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 3649|* *| 3650|* Target Instruction Descriptors *| 3651|* *| 3652|* Automatically generated file, do not edit! *| 3653|* *| 3654\*===----------------------------------------------------------------------===*/ 3655 3656 3657#ifdef GET_INSTRINFO_MC_DESC 3658#undef GET_INSTRINFO_MC_DESC 3659namespace llvm { 3660 3661static const MCPhysReg ImplicitList1[] = { ARM::CPSR, 0 }; 3662static const MCPhysReg ImplicitList2[] = { ARM::SP, 0 }; 3663static const MCPhysReg ImplicitList3[] = { ARM::LR, 0 }; 3664static const MCPhysReg ImplicitList4[] = { ARM::PC, 0 }; 3665static const MCPhysReg ImplicitList5[] = { ARM::FPSCR_NZCV, 0 }; 3666static const MCPhysReg ImplicitList6[] = { ARM::R7, ARM::LR, ARM::SP, 0 }; 3667static const MCPhysReg ImplicitList7[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, 0 }; 3668static const MCPhysReg ImplicitList8[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, 0 }; 3669static const MCPhysReg ImplicitList9[] = { ARM::R0, ARM::R12, ARM::LR, ARM::CPSR, 0 }; 3670static const MCPhysReg ImplicitList10[] = { ARM::FPSCR, 0 }; 3671static const MCPhysReg ImplicitList11[] = { ARM::R4, 0 }; 3672static const MCPhysReg ImplicitList12[] = { ARM::R4, ARM::SP, 0 }; 3673static const MCPhysReg ImplicitList13[] = { ARM::ITSTATE, 0 }; 3674static const MCPhysReg ImplicitList14[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15, 0 }; 3675static const MCPhysReg ImplicitList15[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::CPSR, 0 }; 3676 3677static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 3678static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 3679static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 3680static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 3681static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 3682static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 3683static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 3684static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 3685static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; 3686static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 3687static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 3688static const MCOperandInfo OperandInfo13[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 3689static const MCOperandInfo OperandInfo14[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3690static const MCOperandInfo OperandInfo15[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3691static const MCOperandInfo OperandInfo16[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3692static const MCOperandInfo OperandInfo17[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3693static const MCOperandInfo OperandInfo18[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3694static const MCOperandInfo OperandInfo19[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3695static const MCOperandInfo OperandInfo20[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3696static const MCOperandInfo OperandInfo21[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3697static const MCOperandInfo OperandInfo22[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3698static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3699static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3700static const MCOperandInfo OperandInfo25[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3701static const MCOperandInfo OperandInfo26[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 3702static const MCOperandInfo OperandInfo27[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 3703static const MCOperandInfo OperandInfo28[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3704static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 3705static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 3706static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 3707static const MCOperandInfo OperandInfo32[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3708static const MCOperandInfo OperandInfo33[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3709static const MCOperandInfo OperandInfo34[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 3710static const MCOperandInfo OperandInfo35[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3711static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3712static const MCOperandInfo OperandInfo37[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 3713static const MCOperandInfo OperandInfo38[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 3714static const MCOperandInfo OperandInfo39[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 3715static const MCOperandInfo OperandInfo40[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 3716static const MCOperandInfo OperandInfo41[] = { { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3717static const MCOperandInfo OperandInfo42[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3718static const MCOperandInfo OperandInfo43[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 3719static const MCOperandInfo OperandInfo44[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3720static const MCOperandInfo OperandInfo45[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3721static const MCOperandInfo OperandInfo46[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3722static const MCOperandInfo OperandInfo47[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 3723static const MCOperandInfo OperandInfo48[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 3724static const MCOperandInfo OperandInfo49[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3725static const MCOperandInfo OperandInfo50[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3726static const MCOperandInfo OperandInfo51[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3727static const MCOperandInfo OperandInfo52[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 3728static const MCOperandInfo OperandInfo53[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 3729static const MCOperandInfo OperandInfo54[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3730static const MCOperandInfo OperandInfo55[] = { { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3731static const MCOperandInfo OperandInfo56[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 3732static const MCOperandInfo OperandInfo57[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 3733static const MCOperandInfo OperandInfo58[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3734static const MCOperandInfo OperandInfo59[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3735static const MCOperandInfo OperandInfo60[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3736static const MCOperandInfo OperandInfo61[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3737static const MCOperandInfo OperandInfo62[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3738static const MCOperandInfo OperandInfo63[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3739static const MCOperandInfo OperandInfo64[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3740static const MCOperandInfo OperandInfo65[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((2 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3741static const MCOperandInfo OperandInfo66[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3742static const MCOperandInfo OperandInfo67[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3743static const MCOperandInfo OperandInfo68[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3744static const MCOperandInfo OperandInfo69[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3745static const MCOperandInfo OperandInfo70[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3746static const MCOperandInfo OperandInfo71[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3747static const MCOperandInfo OperandInfo72[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3748static const MCOperandInfo OperandInfo73[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 3749static const MCOperandInfo OperandInfo74[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3750static const MCOperandInfo OperandInfo75[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 3751static const MCOperandInfo OperandInfo76[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 3752static const MCOperandInfo OperandInfo77[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3753static const MCOperandInfo OperandInfo78[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3754static const MCOperandInfo OperandInfo79[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3755static const MCOperandInfo OperandInfo80[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3756static const MCOperandInfo OperandInfo81[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3757static const MCOperandInfo OperandInfo82[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3758static const MCOperandInfo OperandInfo83[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3759static const MCOperandInfo OperandInfo84[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3760static const MCOperandInfo OperandInfo85[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 3761static const MCOperandInfo OperandInfo86[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3762static const MCOperandInfo OperandInfo87[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 3763static const MCOperandInfo OperandInfo88[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3764static const MCOperandInfo OperandInfo89[] = { { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3765static const MCOperandInfo OperandInfo90[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3766static const MCOperandInfo OperandInfo91[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3767static const MCOperandInfo OperandInfo92[] = { { ARM::GPRwithAPSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3768static const MCOperandInfo OperandInfo93[] = { { ARM::GPRwithAPSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 3769static const MCOperandInfo OperandInfo94[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3770static const MCOperandInfo OperandInfo95[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3771static const MCOperandInfo OperandInfo96[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3772static const MCOperandInfo OperandInfo97[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3773static const MCOperandInfo OperandInfo98[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3774static const MCOperandInfo OperandInfo99[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3775static const MCOperandInfo OperandInfo100[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3776static const MCOperandInfo OperandInfo101[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3777static const MCOperandInfo OperandInfo102[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3778static const MCOperandInfo OperandInfo103[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 3779static const MCOperandInfo OperandInfo104[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 3780static const MCOperandInfo OperandInfo105[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3781static const MCOperandInfo OperandInfo106[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3782static const MCOperandInfo OperandInfo107[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 3783static const MCOperandInfo OperandInfo108[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3784static const MCOperandInfo OperandInfo109[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3785static const MCOperandInfo OperandInfo110[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3786static const MCOperandInfo OperandInfo111[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3787static const MCOperandInfo OperandInfo112[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3788static const MCOperandInfo OperandInfo113[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3789static const MCOperandInfo OperandInfo114[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 3790static const MCOperandInfo OperandInfo115[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3791static const MCOperandInfo OperandInfo116[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3792static const MCOperandInfo OperandInfo117[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3793static const MCOperandInfo OperandInfo118[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3794static const MCOperandInfo OperandInfo119[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3795static const MCOperandInfo OperandInfo120[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3796static const MCOperandInfo OperandInfo121[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3797static const MCOperandInfo OperandInfo122[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3798static const MCOperandInfo OperandInfo123[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3799static const MCOperandInfo OperandInfo124[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3800static const MCOperandInfo OperandInfo125[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3801static const MCOperandInfo OperandInfo126[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3802static const MCOperandInfo OperandInfo127[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3803static const MCOperandInfo OperandInfo128[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3804static const MCOperandInfo OperandInfo129[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3805static const MCOperandInfo OperandInfo130[] = { { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 3806static const MCOperandInfo OperandInfo131[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3807static const MCOperandInfo OperandInfo132[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3808static const MCOperandInfo OperandInfo133[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3809static const MCOperandInfo OperandInfo134[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3810static const MCOperandInfo OperandInfo135[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3811static const MCOperandInfo OperandInfo136[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3812static const MCOperandInfo OperandInfo137[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3813static const MCOperandInfo OperandInfo138[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3814static const MCOperandInfo OperandInfo139[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3815static const MCOperandInfo OperandInfo140[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3816static const MCOperandInfo OperandInfo141[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3817static const MCOperandInfo OperandInfo142[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3818static const MCOperandInfo OperandInfo143[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3819static const MCOperandInfo OperandInfo144[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3820static const MCOperandInfo OperandInfo145[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3821static const MCOperandInfo OperandInfo146[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3822static const MCOperandInfo OperandInfo147[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 3823static const MCOperandInfo OperandInfo148[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 3824static const MCOperandInfo OperandInfo149[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 3825static const MCOperandInfo OperandInfo150[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3826static const MCOperandInfo OperandInfo151[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3827static const MCOperandInfo OperandInfo152[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3828static const MCOperandInfo OperandInfo153[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3829static const MCOperandInfo OperandInfo154[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3830static const MCOperandInfo OperandInfo155[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3831static const MCOperandInfo OperandInfo156[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3832static const MCOperandInfo OperandInfo157[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3833static const MCOperandInfo OperandInfo158[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3834static const MCOperandInfo OperandInfo159[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3835static const MCOperandInfo OperandInfo160[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3836static const MCOperandInfo OperandInfo161[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3837static const MCOperandInfo OperandInfo162[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3838static const MCOperandInfo OperandInfo163[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3839static const MCOperandInfo OperandInfo164[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3840static const MCOperandInfo OperandInfo165[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3841static const MCOperandInfo OperandInfo166[] = { { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3842static const MCOperandInfo OperandInfo167[] = { { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3843static const MCOperandInfo OperandInfo168[] = { { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3844static const MCOperandInfo OperandInfo169[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3845static const MCOperandInfo OperandInfo170[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3846static const MCOperandInfo OperandInfo171[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3847static const MCOperandInfo OperandInfo172[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3848static const MCOperandInfo OperandInfo173[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3849static const MCOperandInfo OperandInfo174[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3850static const MCOperandInfo OperandInfo175[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3851static const MCOperandInfo OperandInfo176[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3852static const MCOperandInfo OperandInfo177[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3853static const MCOperandInfo OperandInfo178[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3854static const MCOperandInfo OperandInfo179[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((2 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3855static const MCOperandInfo OperandInfo180[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3856static const MCOperandInfo OperandInfo181[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3857static const MCOperandInfo OperandInfo182[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3858static const MCOperandInfo OperandInfo183[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3859static const MCOperandInfo OperandInfo184[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((3 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3860static const MCOperandInfo OperandInfo185[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3861static const MCOperandInfo OperandInfo186[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((2 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3862static const MCOperandInfo OperandInfo187[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((3 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((2 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3863static const MCOperandInfo OperandInfo188[] = { { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3864static const MCOperandInfo OperandInfo189[] = { { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3865static const MCOperandInfo OperandInfo190[] = { { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3866static const MCOperandInfo OperandInfo191[] = { { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3867static const MCOperandInfo OperandInfo192[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3868static const MCOperandInfo OperandInfo193[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((4 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3869static const MCOperandInfo OperandInfo194[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((2 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((3 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3870static const MCOperandInfo OperandInfo195[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((4 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((2 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((3 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3871static const MCOperandInfo OperandInfo196[] = { { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3872static const MCOperandInfo OperandInfo197[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3873static const MCOperandInfo OperandInfo198[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3874static const MCOperandInfo OperandInfo199[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 3875static const MCOperandInfo OperandInfo200[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 3876static const MCOperandInfo OperandInfo201[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 3877static const MCOperandInfo OperandInfo202[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3878static const MCOperandInfo OperandInfo203[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3879static const MCOperandInfo OperandInfo204[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3880static const MCOperandInfo OperandInfo205[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3881static const MCOperandInfo OperandInfo206[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3882static const MCOperandInfo OperandInfo207[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3883static const MCOperandInfo OperandInfo208[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 3884static const MCOperandInfo OperandInfo209[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3885static const MCOperandInfo OperandInfo210[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3886static const MCOperandInfo OperandInfo211[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3887static const MCOperandInfo OperandInfo212[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 3888static const MCOperandInfo OperandInfo213[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3889static const MCOperandInfo OperandInfo214[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3890static const MCOperandInfo OperandInfo215[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3891static const MCOperandInfo OperandInfo216[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3892static const MCOperandInfo OperandInfo217[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3893static const MCOperandInfo OperandInfo218[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3894static const MCOperandInfo OperandInfo219[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 3895static const MCOperandInfo OperandInfo220[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3896static const MCOperandInfo OperandInfo221[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3897static const MCOperandInfo OperandInfo222[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3898static const MCOperandInfo OperandInfo223[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3899static const MCOperandInfo OperandInfo224[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3900static const MCOperandInfo OperandInfo225[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3901static const MCOperandInfo OperandInfo226[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3902static const MCOperandInfo OperandInfo227[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3903static const MCOperandInfo OperandInfo228[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3904static const MCOperandInfo OperandInfo229[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3905static const MCOperandInfo OperandInfo230[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3906static const MCOperandInfo OperandInfo231[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3907static const MCOperandInfo OperandInfo232[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3908static const MCOperandInfo OperandInfo233[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3909static const MCOperandInfo OperandInfo234[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3910static const MCOperandInfo OperandInfo235[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3911static const MCOperandInfo OperandInfo236[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3912static const MCOperandInfo OperandInfo237[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3913static const MCOperandInfo OperandInfo238[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3914static const MCOperandInfo OperandInfo239[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3915static const MCOperandInfo OperandInfo240[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3916static const MCOperandInfo OperandInfo241[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3917static const MCOperandInfo OperandInfo242[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3918static const MCOperandInfo OperandInfo243[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3919static const MCOperandInfo OperandInfo244[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3920static const MCOperandInfo OperandInfo245[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3921static const MCOperandInfo OperandInfo246[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3922static const MCOperandInfo OperandInfo247[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3923static const MCOperandInfo OperandInfo248[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3924static const MCOperandInfo OperandInfo249[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3925static const MCOperandInfo OperandInfo250[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3926static const MCOperandInfo OperandInfo251[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3927static const MCOperandInfo OperandInfo252[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3928static const MCOperandInfo OperandInfo253[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3929static const MCOperandInfo OperandInfo254[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3930static const MCOperandInfo OperandInfo255[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3931static const MCOperandInfo OperandInfo256[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3932static const MCOperandInfo OperandInfo257[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3933static const MCOperandInfo OperandInfo258[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3934static const MCOperandInfo OperandInfo259[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3935static const MCOperandInfo OperandInfo260[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3936static const MCOperandInfo OperandInfo261[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3937static const MCOperandInfo OperandInfo262[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3938static const MCOperandInfo OperandInfo263[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3939static const MCOperandInfo OperandInfo264[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3940static const MCOperandInfo OperandInfo265[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3941static const MCOperandInfo OperandInfo266[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3942static const MCOperandInfo OperandInfo267[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3943static const MCOperandInfo OperandInfo268[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3944static const MCOperandInfo OperandInfo269[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3945static const MCOperandInfo OperandInfo270[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3946static const MCOperandInfo OperandInfo271[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3947static const MCOperandInfo OperandInfo272[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3948static const MCOperandInfo OperandInfo273[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 3949static const MCOperandInfo OperandInfo274[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3950static const MCOperandInfo OperandInfo275[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3951static const MCOperandInfo OperandInfo276[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3952static const MCOperandInfo OperandInfo277[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3953static const MCOperandInfo OperandInfo278[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3954static const MCOperandInfo OperandInfo279[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3955static const MCOperandInfo OperandInfo280[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3956static const MCOperandInfo OperandInfo281[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3957static const MCOperandInfo OperandInfo282[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3958static const MCOperandInfo OperandInfo283[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3959static const MCOperandInfo OperandInfo284[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3960static const MCOperandInfo OperandInfo285[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3961static const MCOperandInfo OperandInfo286[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3962static const MCOperandInfo OperandInfo287[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3963static const MCOperandInfo OperandInfo288[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3964static const MCOperandInfo OperandInfo289[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3965static const MCOperandInfo OperandInfo290[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 3966static const MCOperandInfo OperandInfo291[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 3967static const MCOperandInfo OperandInfo292[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3968static const MCOperandInfo OperandInfo293[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3969static const MCOperandInfo OperandInfo294[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3970static const MCOperandInfo OperandInfo295[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3971static const MCOperandInfo OperandInfo296[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((2 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3972static const MCOperandInfo OperandInfo297[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3973static const MCOperandInfo OperandInfo298[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3974static const MCOperandInfo OperandInfo299[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 3975static const MCOperandInfo OperandInfo300[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3976static const MCOperandInfo OperandInfo301[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3977static const MCOperandInfo OperandInfo302[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3978static const MCOperandInfo OperandInfo303[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3979static const MCOperandInfo OperandInfo304[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3980static const MCOperandInfo OperandInfo305[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3981static const MCOperandInfo OperandInfo306[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3982static const MCOperandInfo OperandInfo307[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3983static const MCOperandInfo OperandInfo308[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3984static const MCOperandInfo OperandInfo309[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 3985static const MCOperandInfo OperandInfo310[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 3986static const MCOperandInfo OperandInfo311[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3987static const MCOperandInfo OperandInfo312[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3988static const MCOperandInfo OperandInfo313[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3989static const MCOperandInfo OperandInfo314[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3990static const MCOperandInfo OperandInfo315[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3991static const MCOperandInfo OperandInfo316[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3992static const MCOperandInfo OperandInfo317[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; 3993static const MCOperandInfo OperandInfo318[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3994static const MCOperandInfo OperandInfo319[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3995static const MCOperandInfo OperandInfo320[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3996static const MCOperandInfo OperandInfo321[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3997static const MCOperandInfo OperandInfo322[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3998static const MCOperandInfo OperandInfo323[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 3999static const MCOperandInfo OperandInfo324[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4000static const MCOperandInfo OperandInfo325[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4001static const MCOperandInfo OperandInfo326[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4002static const MCOperandInfo OperandInfo327[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4003static const MCOperandInfo OperandInfo328[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4004static const MCOperandInfo OperandInfo329[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4005static const MCOperandInfo OperandInfo330[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4006static const MCOperandInfo OperandInfo331[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4007static const MCOperandInfo OperandInfo332[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4008static const MCOperandInfo OperandInfo333[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4009static const MCOperandInfo OperandInfo334[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, (1 << MCOI::EARLY_CLOBBER) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4010static const MCOperandInfo OperandInfo335[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4011static const MCOperandInfo OperandInfo336[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4012static const MCOperandInfo OperandInfo337[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4013static const MCOperandInfo OperandInfo338[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4014static const MCOperandInfo OperandInfo339[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4015static const MCOperandInfo OperandInfo340[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4016static const MCOperandInfo OperandInfo341[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4017static const MCOperandInfo OperandInfo342[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4018static const MCOperandInfo OperandInfo343[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4019static const MCOperandInfo OperandInfo344[] = { { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4020static const MCOperandInfo OperandInfo345[] = { { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4021static const MCOperandInfo OperandInfo346[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4022static const MCOperandInfo OperandInfo347[] = { { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4023static const MCOperandInfo OperandInfo348[] = { { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4024static const MCOperandInfo OperandInfo349[] = { { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4025static const MCOperandInfo OperandInfo350[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4026static const MCOperandInfo OperandInfo351[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4027static const MCOperandInfo OperandInfo352[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4028static const MCOperandInfo OperandInfo353[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4029static const MCOperandInfo OperandInfo354[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4030static const MCOperandInfo OperandInfo355[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4031static const MCOperandInfo OperandInfo356[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4032static const MCOperandInfo OperandInfo357[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4033static const MCOperandInfo OperandInfo358[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4034static const MCOperandInfo OperandInfo359[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4035static const MCOperandInfo OperandInfo360[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4036static const MCOperandInfo OperandInfo361[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4037static const MCOperandInfo OperandInfo362[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4038static const MCOperandInfo OperandInfo363[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; 4039static const MCOperandInfo OperandInfo364[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4040static const MCOperandInfo OperandInfo365[] = { { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4041static const MCOperandInfo OperandInfo366[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4042 4043extern const MCInstrDesc ARMInsts[] = { 4044 { 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #0 = PHI 4045 { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM 4046 { 2, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2 = CFI_INSTRUCTION 4047 { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #3 = EH_LABEL 4048 { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #4 = GC_LABEL 4049 { 5, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #5 = KILL 4050 { 6, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = EXTRACT_SUBREG 4051 { 7, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #7 = INSERT_SUBREG 4052 { 8, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #8 = IMPLICIT_DEF 4053 { 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #9 = SUBREG_TO_REG 4054 { 10, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #10 = COPY_TO_REGCLASS 4055 { 11, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #11 = DBG_VALUE 4056 { 12, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #12 = REG_SEQUENCE 4057 { 13, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #13 = COPY 4058 { 14, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #14 = BUNDLE 4059 { 15, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #15 = LIFETIME_START 4060 { 16, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #16 = LIFETIME_END 4061 { 17, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #17 = STACKMAP 4062 { 18, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #18 = PATCHPOINT 4063 { 19, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #19 = LOAD_STACK_GUARD 4064 { 20, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #20 = STATEPOINT 4065 { 21, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #21 = LOCAL_ESCAPE 4066 { 22, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #22 = FAULTING_LOAD_OP 4067 { 23, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #23 = G_ADD 4068 { 24, 2, 1, 8, 612, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr }, // Inst #24 = ABS 4069 { 25, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo14, -1 ,nullptr }, // Inst #25 = ADCri 4070 { 26, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo15, -1 ,nullptr }, // Inst #26 = ADCrr 4071 { 27, 7, 1, 4, 3, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo16, -1 ,nullptr }, // Inst #27 = ADCrsi 4072 { 28, 8, 1, 4, 4, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo17, -1 ,nullptr }, // Inst #28 = ADCrsr 4073 { 29, 5, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr }, // Inst #29 = ADDSri 4074 { 30, 5, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo19, -1 ,nullptr }, // Inst #30 = ADDSrr 4075 { 31, 6, 1, 4, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo20, -1 ,nullptr }, // Inst #31 = ADDSrsi 4076 { 32, 7, 1, 4, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo21, -1 ,nullptr }, // Inst #32 = ADDSrsr 4077 { 33, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #33 = ADDri 4078 { 34, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #34 = ADDrr 4079 { 35, 7, 1, 4, 3, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #35 = ADDrsi 4080 { 36, 8, 1, 4, 4, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #36 = ADDrsr 4081 { 37, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo23, -1 ,nullptr }, // Inst #37 = ADJCALLSTACKDOWN 4082 { 38, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo24, -1 ,nullptr }, // Inst #38 = ADJCALLSTACKUP 4083 { 39, 4, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xd01ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #39 = ADR 4084 { 40, 3, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #40 = AESD 4085 { 41, 3, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #41 = AESE 4086 { 42, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #42 = AESIMC 4087 { 43, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #43 = AESMC 4088 { 44, 6, 1, 4, 278, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #44 = ANDri 4089 { 45, 6, 1, 4, 279, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #45 = ANDrr 4090 { 46, 7, 1, 4, 280, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #46 = ANDrsi 4091 { 47, 8, 1, 4, 281, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #47 = ANDrsr 4092 { 48, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #48 = ASRi 4093 { 49, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #49 = ASRr 4094 { 50, 1, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #50 = B 4095 { 51, 4, 0, 0, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo30, -1 ,nullptr }, // Inst #51 = BCCZi64 4096 { 52, 6, 0, 0, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr }, // Inst #52 = BCCi64 4097 { 53, 5, 1, 4, 292, 0|(1ULL<<MCID::Predicable), 0x201ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #53 = BFC 4098 { 54, 6, 1, 4, 292, 0|(1ULL<<MCID::Predicable), 0x201ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #54 = BFI 4099 { 55, 6, 1, 4, 278, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #55 = BICri 4100 { 56, 6, 1, 4, 279, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #56 = BICrr 4101 { 57, 7, 1, 4, 280, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #57 = BICrsi 4102 { 58, 8, 1, 4, 281, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #58 = BICrsr 4103 { 59, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #59 = BKPT 4104 { 60, 1, 0, 4, 12, 0|(1ULL<<MCID::Call), 0x100ULL, ImplicitList2, ImplicitList3, OperandInfo29, -1 ,nullptr }, // Inst #60 = BL 4105 { 61, 1, 0, 4, 12, 0|(1ULL<<MCID::Call), 0x180ULL, ImplicitList2, ImplicitList3, OperandInfo34, -1 ,nullptr }, // Inst #61 = BLX 4106 { 62, 3, 0, 4, 12, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x180ULL, ImplicitList2, ImplicitList3, OperandInfo35, -1 ,nullptr }, // Inst #62 = BLX_pred 4107 { 63, 1, 0, 4, 13, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #63 = BLXi 4108 { 64, 3, 0, 4, 12, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0x100ULL, ImplicitList2, ImplicitList3, OperandInfo36, -1 ,nullptr }, // Inst #64 = BL_pred 4109 { 65, 1, 0, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo29, -1 ,nullptr }, // Inst #65 = BMOVPCB_CALL 4110 { 66, 1, 0, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo37, -1 ,nullptr }, // Inst #66 = BMOVPCRX_CALL 4111 { 67, 3, 0, 4, 14, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #67 = BR_JTadd 4112 { 68, 4, 0, 4, 14, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #68 = BR_JTm 4113 { 69, 2, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #69 = BR_JTr 4114 { 70, 1, 0, 4, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x180ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #70 = BX 4115 { 71, 3, 0, 4, 15, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #71 = BXJ 4116 { 72, 1, 0, 8, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo37, -1 ,nullptr }, // Inst #72 = BX_CALL 4117 { 73, 2, 0, 4, 10, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x180ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #73 = BX_RET 4118 { 74, 3, 0, 4, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #74 = BX_pred 4119 { 75, 3, 0, 4, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #75 = Bcc 4120 { 76, 8, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #76 = CDP 4121 { 77, 6, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #77 = CDP2 4122 { 78, 0, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #78 = CLREX 4123 { 79, 4, 1, 4, 16, 0|(1ULL<<MCID::Predicable), 0x600ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #79 = CLZ 4124 { 80, 4, 0, 4, 17, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo25, -1 ,nullptr }, // Inst #80 = CMNri 4125 { 81, 4, 0, 4, 18, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x201ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #81 = CMNzrr 4126 { 82, 5, 0, 4, 19, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #82 = CMNzrsi 4127 { 83, 6, 0, 4, 20, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #83 = CMNzrsr 4128 { 84, 4, 0, 4, 17, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo25, -1 ,nullptr }, // Inst #84 = CMPri 4129 { 85, 4, 0, 4, 18, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #85 = CMPrr 4130 { 86, 5, 0, 4, 19, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #86 = CMPrsi 4131 { 87, 6, 0, 4, 20, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #87 = CMPrsr 4132 { 88, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #88 = CONSTPOOL_ENTRY 4133 { 89, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #89 = COPY_STRUCT_BYVAL_I32 4134 { 90, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #90 = CPS1p 4135 { 91, 2, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #91 = CPS2p 4136 { 92, 3, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #92 = CPS3p 4137 { 93, 3, 1, 4, 0, 0, 0xd00ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #93 = CRC32B 4138 { 94, 3, 1, 4, 0, 0, 0xd00ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #94 = CRC32CB 4139 { 95, 3, 1, 4, 0, 0, 0xd00ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #95 = CRC32CH 4140 { 96, 3, 1, 4, 0, 0, 0xd00ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #96 = CRC32CW 4141 { 97, 3, 1, 4, 0, 0, 0xd00ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #97 = CRC32H 4142 { 98, 3, 1, 4, 0, 0, 0xd00ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #98 = CRC32W 4143 { 99, 3, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #99 = DBG 4144 { 100, 1, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #100 = DMB 4145 { 101, 1, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #101 = DSB 4146 { 102, 6, 1, 4, 278, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #102 = EORri 4147 { 103, 6, 1, 4, 279, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #103 = EORrr 4148 { 104, 7, 1, 4, 280, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #104 = EORrsi 4149 { 105, 8, 1, 4, 281, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #105 = EORrsr 4150 { 106, 2, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, ImplicitList4, OperandInfo41, -1 ,nullptr }, // Inst #106 = ERET 4151 { 107, 4, 1, 4, 509, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x8c00ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #107 = FCONSTD 4152 { 108, 4, 1, 4, 22, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #108 = FCONSTH 4153 { 109, 4, 1, 4, 510, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x8c00ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #109 = FCONSTS 4154 { 110, 5, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #110 = FLDMXDB_UPD 4155 { 111, 4, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b04ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #111 = FLDMXIA 4156 { 112, 5, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #112 = FLDMXIA_UPD 4157 { 113, 2, 0, 4, 529, 0|(1ULL<<MCID::Predicable), 0x8c00ULL, ImplicitList5, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #113 = FMSTAT 4158 { 114, 5, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #114 = FSTMXDB_UPD 4159 { 115, 4, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b04ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #115 = FSTMXIA 4160 { 116, 5, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #116 = FSTMXIA_UPD 4161 { 117, 3, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #117 = HINT 4162 { 118, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #118 = HLT 4163 { 119, 1, 0, 4, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #119 = HVC 4164 { 120, 1, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #120 = ISB 4165 { 121, 2, 0, 0, 394, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,&getITDeprecationInfo }, // Inst #121 = ITasm 4166 { 122, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #122 = Int_eh_sjlj_dispatchsetup 4167 { 123, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList6, OperandInfo13, -1 ,nullptr }, // Inst #123 = Int_eh_sjlj_longjmp 4168 { 124, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo13, -1 ,nullptr }, // Inst #124 = Int_eh_sjlj_setjmp 4169 { 125, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList8, OperandInfo13, -1 ,nullptr }, // Inst #125 = Int_eh_sjlj_setjmp_nofp 4170 { 126, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #126 = Int_eh_sjlj_setup_dispatch 4171 { 127, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #127 = JUMPTABLE_ADDRS 4172 { 128, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #128 = JUMPTABLE_INSTS 4173 { 129, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #129 = JUMPTABLE_TBB 4174 { 130, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #130 = JUMPTABLE_TBH 4175 { 131, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x580ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #131 = LDA 4176 { 132, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x580ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #132 = LDAB 4177 { 133, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #133 = LDAEX 4178 { 134, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #134 = LDAEXB 4179 { 135, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x580ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #135 = LDAEXD 4180 { 136, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #136 = LDAEXH 4181 { 137, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x580ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #137 = LDAH 4182 { 138, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #138 = LDC2L_OFFSET 4183 { 139, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #139 = LDC2L_OPTION 4184 { 140, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #140 = LDC2L_POST 4185 { 141, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #141 = LDC2L_PRE 4186 { 142, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #142 = LDC2_OFFSET 4187 { 143, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #143 = LDC2_OPTION 4188 { 144, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #144 = LDC2_POST 4189 { 145, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #145 = LDC2_PRE 4190 { 146, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #146 = LDCL_OFFSET 4191 { 147, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #147 = LDCL_OPTION 4192 { 148, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #148 = LDCL_POST 4193 { 149, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #149 = LDCL_PRE 4194 { 150, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #150 = LDC_OFFSET 4195 { 151, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #151 = LDC_OPTION 4196 { 152, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #152 = LDC_POST 4197 { 153, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #153 = LDC_PRE 4198 { 154, 4, 0, 4, 367, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,&getARMLoadDeprecationInfo }, // Inst #154 = LDMDA 4199 { 155, 5, 1, 4, 368, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,&getARMLoadDeprecationInfo }, // Inst #155 = LDMDA_UPD 4200 { 156, 4, 0, 4, 367, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,&getARMLoadDeprecationInfo }, // Inst #156 = LDMDB 4201 { 157, 5, 1, 4, 368, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,&getARMLoadDeprecationInfo }, // Inst #157 = LDMDB_UPD 4202 { 158, 4, 0, 4, 367, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,&getARMLoadDeprecationInfo }, // Inst #158 = LDMIA 4203 { 159, 5, 1, 4, 369, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #159 = LDMIA_RET 4204 { 160, 5, 1, 4, 368, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,&getARMLoadDeprecationInfo }, // Inst #160 = LDMIA_UPD 4205 { 161, 4, 0, 4, 367, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,&getARMLoadDeprecationInfo }, // Inst #161 = LDMIB 4206 { 162, 5, 1, 4, 368, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,&getARMLoadDeprecationInfo }, // Inst #162 = LDMIB_UPD 4207 { 163, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #163 = LDRBT_POST 4208 { 164, 7, 2, 4, 355, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #164 = LDRBT_POST_IMM 4209 { 165, 7, 2, 4, 355, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #165 = LDRBT_POST_REG 4210 { 166, 7, 2, 4, 356, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #166 = LDRB_POST_IMM 4211 { 167, 7, 2, 4, 355, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #167 = LDRB_POST_REG 4212 { 168, 6, 2, 4, 356, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x322ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #168 = LDRB_PRE_IMM 4213 { 169, 7, 2, 4, 355, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x322ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #169 = LDRB_PRE_REG 4214 { 170, 5, 1, 4, 339, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x310ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #170 = LDRBi12 4215 { 171, 6, 1, 4, 340, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x300ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #171 = LDRBrs 4216 { 172, 7, 2, 4, 364, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x403ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #172 = LDRD 4217 { 173, 8, 3, 4, 366, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x443ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #173 = LDRD_POST 4218 { 174, 8, 3, 4, 366, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x423ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #174 = LDRD_PRE 4219 { 175, 4, 1, 4, 341, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #175 = LDREX 4220 { 176, 4, 1, 4, 341, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #176 = LDREXB 4221 { 177, 4, 1, 4, 341, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x580ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #177 = LDREXD 4222 { 178, 4, 1, 4, 341, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #178 = LDREXH 4223 { 179, 6, 1, 4, 349, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x403ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #179 = LDRH 4224 { 180, 6, 2, 4, 357, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #180 = LDRHTi 4225 { 181, 7, 2, 4, 357, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #181 = LDRHTr 4226 { 182, 7, 2, 4, 357, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #182 = LDRH_POST 4227 { 183, 7, 2, 4, 357, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x423ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #183 = LDRH_PRE 4228 { 184, 2, 1, 0, 391, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #184 = LDRLIT_ga_abs 4229 { 185, 2, 1, 0, 392, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #185 = LDRLIT_ga_pcrel 4230 { 186, 2, 1, 0, 393, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #186 = LDRLIT_ga_pcrel_ldr 4231 { 187, 6, 1, 4, 302, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x403ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #187 = LDRSB 4232 { 188, 6, 2, 4, 303, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #188 = LDRSBTi 4233 { 189, 7, 2, 4, 303, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #189 = LDRSBTr 4234 { 190, 7, 2, 4, 303, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #190 = LDRSB_POST 4235 { 191, 7, 2, 4, 303, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x423ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #191 = LDRSB_PRE 4236 { 192, 6, 1, 4, 302, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x403ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #192 = LDRSH 4237 { 193, 6, 2, 4, 303, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #193 = LDRSHTi 4238 { 194, 7, 2, 4, 303, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #194 = LDRSHTr 4239 { 195, 7, 2, 4, 303, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x443ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #195 = LDRSH_POST 4240 { 196, 7, 2, 4, 303, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x423ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #196 = LDRSH_PRE 4241 { 197, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #197 = LDRT_POST 4242 { 198, 7, 2, 4, 358, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #198 = LDRT_POST_IMM 4243 { 199, 7, 2, 4, 358, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #199 = LDRT_POST_REG 4244 { 200, 7, 2, 4, 359, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #200 = LDR_POST_IMM 4245 { 201, 7, 2, 4, 358, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x342ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #201 = LDR_POST_REG 4246 { 202, 6, 2, 4, 359, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x322ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #202 = LDR_PRE_IMM 4247 { 203, 7, 2, 4, 358, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x322ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #203 = LDR_PRE_REG 4248 { 204, 5, 1, 4, 350, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x310ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #204 = LDRcp 4249 { 205, 5, 1, 4, 342, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x310ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #205 = LDRi12 4250 { 206, 6, 1, 4, 301, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x300ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #206 = LDRrs 4251 { 207, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #207 = LEApcrel 4252 { 208, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #208 = LEApcrelJT 4253 { 209, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #209 = LSLi 4254 { 210, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #210 = LSLr 4255 { 211, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #211 = LSRi 4256 { 212, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #212 = LSRr 4257 { 213, 8, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo72, -1 ,&getMCRDeprecationInfo }, // Inst #213 = MCR 4258 { 214, 6, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #214 = MCR2 4259 { 215, 7, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #215 = MCRR 4260 { 216, 5, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #216 = MCRR2 4261 { 217, 5, 2, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #217 = MEMCPY 4262 { 218, 7, 1, 4, 293, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #218 = MLA 4263 { 219, 7, 1, 4, 293, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #219 = MLAv5 4264 { 220, 6, 1, 4, 293, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #220 = MLS 4265 { 221, 5, 1, 4, 41, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #221 = MOVCCi 4266 { 222, 5, 1, 4, 42, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #222 = MOVCCi16 4267 { 223, 5, 1, 8, 287, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #223 = MOVCCi32imm 4268 { 224, 5, 1, 4, 44, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Select)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #224 = MOVCCr 4269 { 225, 6, 1, 4, 282, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #225 = MOVCCsi 4270 { 226, 7, 1, 4, 282, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #226 = MOVCCsr 4271 { 227, 2, 0, 4, 10, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x180ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #227 = MOVPCLR 4272 { 228, 1, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #228 = MOVPCRX 4273 { 229, 5, 1, 4, 42, 0|(1ULL<<MCID::Predicable), 0x2201ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #229 = MOVTi16 4274 { 230, 4, 1, 0, 42, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #230 = MOVTi16_ga_pcrel 4275 { 231, 2, 1, 0, 289, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #231 = MOV_ga_pcrel 4276 { 232, 2, 1, 0, 290, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #232 = MOV_ga_pcrel_ldr 4277 { 233, 5, 1, 4, 42, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #233 = MOVi 4278 { 234, 4, 1, 4, 42, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #234 = MOVi16 4279 { 235, 3, 1, 0, 42, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #235 = MOVi16_ga_pcrel 4280 { 236, 2, 1, 0, 288, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #236 = MOVi32imm 4281 { 237, 5, 1, 4, 49, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2201ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #237 = MOVr 4282 { 238, 5, 1, 4, 49, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2201ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #238 = MOVr_TC 4283 { 239, 6, 1, 4, 283, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x3501ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #239 = MOVsi 4284 { 240, 7, 1, 4, 283, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2281ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #240 = MOVsr 4285 { 241, 2, 1, 0, 284, 0|(1ULL<<MCID::Pseudo), 0x2000ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr }, // Inst #241 = MOVsra_flag 4286 { 242, 2, 1, 0, 284, 0|(1ULL<<MCID::Pseudo), 0x2000ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr }, // Inst #242 = MOVsrl_flag 4287 { 243, 8, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #243 = MRC 4288 { 244, 6, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #244 = MRC2 4289 { 245, 7, 2, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #245 = MRRC 4290 { 246, 5, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #246 = MRRC2 4291 { 247, 3, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #247 = MRS 4292 { 248, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #248 = MRSbanked 4293 { 249, 3, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #249 = MRSsys 4294 { 250, 4, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #250 = MSR 4295 { 251, 4, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #251 = MSRbanked 4296 { 252, 4, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #252 = MSRi 4297 { 253, 6, 1, 4, 294, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #253 = MUL 4298 { 254, 6, 1, 4, 294, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #254 = MULv5 4299 { 255, 5, 1, 4, 41, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #255 = MVNCCi 4300 { 256, 5, 1, 4, 53, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #256 = MVNi 4301 { 257, 5, 1, 4, 286, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2201ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #257 = MVNr 4302 { 258, 6, 1, 4, 55, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x3501ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #258 = MVNsi 4303 { 259, 7, 1, 4, 285, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2281ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #259 = MVNsr 4304 { 260, 6, 1, 4, 278, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #260 = ORRri 4305 { 261, 6, 1, 4, 279, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #261 = ORRrr 4306 { 262, 7, 1, 4, 280, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #262 = ORRrsi 4307 { 263, 8, 1, 4, 281, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #263 = ORRrsr 4308 { 264, 5, 1, 4, 56, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #264 = PICADD 4309 { 265, 5, 1, 4, 300, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #265 = PICLDR 4310 { 266, 5, 1, 4, 349, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #266 = PICLDRB 4311 { 267, 5, 1, 4, 349, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #267 = PICLDRH 4312 { 268, 5, 1, 4, 302, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #268 = PICLDRSB 4313 { 269, 5, 1, 4, 302, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #269 = PICLDRSH 4314 { 270, 5, 0, 4, 372, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #270 = PICSTR 4315 { 271, 5, 0, 4, 373, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #271 = PICSTRB 4316 { 272, 5, 0, 4, 373, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #272 = PICSTRH 4317 { 273, 6, 1, 4, 59, 0|(1ULL<<MCID::Predicable), 0x600ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #273 = PKHBT 4318 { 274, 6, 1, 4, 60, 0|(1ULL<<MCID::Predicable), 0x600ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #274 = PKHTB 4319 { 275, 2, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd10ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #275 = PLDWi12 4320 { 276, 3, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd00ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #276 = PLDWrs 4321 { 277, 2, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd10ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #277 = PLDi12 4322 { 278, 3, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd00ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #278 = PLDrs 4323 { 279, 2, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd10ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #279 = PLIi12 4324 { 280, 3, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xd00ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #280 = PLIrs 4325 { 281, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #281 = QADD 4326 { 282, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #282 = QADD16 4327 { 283, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #283 = QADD8 4328 { 284, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #284 = QASX 4329 { 285, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #285 = QDADD 4330 { 286, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #286 = QDSUB 4331 { 287, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #287 = QSAX 4332 { 288, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #288 = QSUB 4333 { 289, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #289 = QSUB16 4334 { 290, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #290 = QSUB8 4335 { 291, 4, 1, 4, 16, 0|(1ULL<<MCID::Predicable), 0x600ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #291 = RBIT 4336 { 292, 4, 1, 4, 16, 0|(1ULL<<MCID::Predicable), 0x600ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #292 = REV 4337 { 293, 4, 1, 4, 16, 0|(1ULL<<MCID::Predicable), 0x600ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #293 = REV16 4338 { 294, 4, 1, 4, 16, 0|(1ULL<<MCID::Predicable), 0x600ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #294 = REVSH 4339 { 295, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #295 = RFEDA 4340 { 296, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #296 = RFEDA_UPD 4341 { 297, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #297 = RFEDB 4342 { 298, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #298 = RFEDB_UPD 4343 { 299, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #299 = RFEIA 4344 { 300, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #300 = RFEIA_UPD 4345 { 301, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #301 = RFEIB 4346 { 302, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #302 = RFEIB_UPD 4347 { 303, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #303 = RORi 4348 { 304, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #304 = RORr 4349 { 305, 2, 1, 0, 51, 0|(1ULL<<MCID::Pseudo), 0x2000ULL, ImplicitList1, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #305 = RRX 4350 { 306, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #306 = RRXi 4351 { 307, 5, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr }, // Inst #307 = RSBSri 4352 { 308, 6, 1, 4, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo20, -1 ,nullptr }, // Inst #308 = RSBSrsi 4353 { 309, 7, 1, 4, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo21, -1 ,nullptr }, // Inst #309 = RSBSrsr 4354 { 310, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #310 = RSBri 4355 { 311, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x201ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #311 = RSBrr 4356 { 312, 7, 1, 4, 3, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #312 = RSBrsi 4357 { 313, 8, 1, 4, 4, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #313 = RSBrsr 4358 { 314, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo14, -1 ,nullptr }, // Inst #314 = RSCri 4359 { 315, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo15, -1 ,nullptr }, // Inst #315 = RSCrr 4360 { 316, 7, 1, 4, 3, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo16, -1 ,nullptr }, // Inst #316 = RSCrsi 4361 { 317, 8, 1, 4, 4, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo22, -1 ,nullptr }, // Inst #317 = RSCrsr 4362 { 318, 5, 1, 4, 315, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #318 = SADD16 4363 { 319, 5, 1, 4, 315, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #319 = SADD8 4364 { 320, 5, 1, 4, 315, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #320 = SASX 4365 { 321, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo14, -1 ,nullptr }, // Inst #321 = SBCri 4366 { 322, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo15, -1 ,nullptr }, // Inst #322 = SBCrr 4367 { 323, 7, 1, 4, 3, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo16, -1 ,nullptr }, // Inst #323 = SBCrsi 4368 { 324, 8, 1, 4, 4, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo17, -1 ,nullptr }, // Inst #324 = SBCrsr 4369 { 325, 6, 1, 4, 292, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x201ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #325 = SBFX 4370 { 326, 5, 1, 4, 338, 0|(1ULL<<MCID::Predicable), 0x600ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #326 = SDIV 4371 { 327, 5, 1, 4, 291, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #327 = SEL 4372 { 328, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5, ARM::HasV8Ops ,nullptr }, // Inst #328 = SETEND 4373 { 329, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #329 = SETPAN 4374 { 330, 4, 1, 4, 0, 0, 0x11280ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #330 = SHA1C 4375 { 331, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #331 = SHA1H 4376 { 332, 4, 1, 4, 0, 0, 0x11280ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #332 = SHA1M 4377 { 333, 4, 1, 4, 0, 0, 0x11280ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #333 = SHA1P 4378 { 334, 4, 1, 4, 0, 0, 0x11280ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #334 = SHA1SU0 4379 { 335, 3, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #335 = SHA1SU1 4380 { 336, 4, 1, 4, 0, 0, 0x11280ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #336 = SHA256H 4381 { 337, 4, 1, 4, 0, 0, 0x11280ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #337 = SHA256H2 4382 { 338, 3, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #338 = SHA256SU0 4383 { 339, 4, 1, 4, 0, 0, 0x11280ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #339 = SHA256SU1 4384 { 340, 5, 1, 4, 317, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #340 = SHADD16 4385 { 341, 5, 1, 4, 317, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #341 = SHADD8 4386 { 342, 5, 1, 4, 317, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #342 = SHASX 4387 { 343, 5, 1, 4, 317, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #343 = SHSAX 4388 { 344, 5, 1, 4, 317, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #344 = SHSUB16 4389 { 345, 5, 1, 4, 317, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #345 = SHSUB8 4390 { 346, 3, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #346 = SMC 4391 { 347, 6, 1, 4, 299, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #347 = SMLABB 4392 { 348, 6, 1, 4, 299, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #348 = SMLABT 4393 { 349, 6, 1, 4, 333, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #349 = SMLAD 4394 { 350, 6, 1, 4, 333, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #350 = SMLADX 4395 { 351, 9, 2, 4, 295, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #351 = SMLAL 4396 { 352, 6, 2, 4, 295, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #352 = SMLALBB 4397 { 353, 6, 2, 4, 295, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #353 = SMLALBT 4398 { 354, 6, 2, 4, 297, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #354 = SMLALD 4399 { 355, 6, 2, 4, 297, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #355 = SMLALDX 4400 { 356, 6, 2, 4, 295, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #356 = SMLALTB 4401 { 357, 6, 2, 4, 295, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #357 = SMLALTT 4402 { 358, 9, 2, 4, 295, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #358 = SMLALv5 4403 { 359, 6, 1, 4, 299, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #359 = SMLATB 4404 { 360, 6, 1, 4, 299, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #360 = SMLATT 4405 { 361, 6, 1, 4, 299, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #361 = SMLAWB 4406 { 362, 6, 1, 4, 299, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #362 = SMLAWT 4407 { 363, 6, 1, 4, 330, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #363 = SMLSD 4408 { 364, 6, 1, 4, 330, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #364 = SMLSDX 4409 { 365, 6, 2, 4, 297, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #365 = SMLSLD 4410 { 366, 6, 2, 4, 297, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #366 = SMLSLDX 4411 { 367, 6, 1, 4, 293, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #367 = SMMLA 4412 { 368, 6, 1, 4, 293, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #368 = SMMLAR 4413 { 369, 6, 1, 4, 293, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #369 = SMMLS 4414 { 370, 6, 1, 4, 293, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #370 = SMMLSR 4415 { 371, 5, 1, 4, 294, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #371 = SMMUL 4416 { 372, 5, 1, 4, 294, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #372 = SMMULR 4417 { 373, 5, 1, 4, 328, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #373 = SMUAD 4418 { 374, 5, 1, 4, 328, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #374 = SMUADX 4419 { 375, 5, 1, 4, 298, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #375 = SMULBB 4420 { 376, 5, 1, 4, 298, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #376 = SMULBT 4421 { 377, 7, 2, 4, 335, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #377 = SMULL 4422 { 378, 7, 2, 4, 296, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #378 = SMULLv5 4423 { 379, 5, 1, 4, 298, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #379 = SMULTB 4424 { 380, 5, 1, 4, 298, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #380 = SMULTT 4425 { 381, 5, 1, 4, 298, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #381 = SMULWB 4426 { 382, 5, 1, 4, 298, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #382 = SMULWT 4427 { 383, 5, 1, 4, 323, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #383 = SMUSD 4428 { 384, 5, 1, 4, 323, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #384 = SMUSDX 4429 { 385, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #385 = SPACE 4430 { 386, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #386 = SRSDA 4431 { 387, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #387 = SRSDA_UPD 4432 { 388, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #388 = SRSDB 4433 { 389, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #389 = SRSDB_UPD 4434 { 390, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #390 = SRSIA 4435 { 391, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #391 = SRSIA_UPD 4436 { 392, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #392 = SRSIB 4437 { 393, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #393 = SRSIB_UPD 4438 { 394, 6, 1, 4, 314, 0|(1ULL<<MCID::Predicable), 0x680ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #394 = SSAT 4439 { 395, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x680ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #395 = SSAT16 4440 { 396, 5, 1, 4, 315, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #396 = SSAX 4441 { 397, 5, 1, 4, 315, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #397 = SSUB16 4442 { 398, 5, 1, 4, 315, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #398 = SSUB8 4443 { 399, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #399 = STC2L_OFFSET 4444 { 400, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #400 = STC2L_OPTION 4445 { 401, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #401 = STC2L_POST 4446 { 402, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #402 = STC2L_PRE 4447 { 403, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #403 = STC2_OFFSET 4448 { 404, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #404 = STC2_OPTION 4449 { 405, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #405 = STC2_POST 4450 { 406, 4, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #406 = STC2_PRE 4451 { 407, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #407 = STCL_OFFSET 4452 { 408, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #408 = STCL_OPTION 4453 { 409, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #409 = STCL_POST 4454 { 410, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #410 = STCL_PRE 4455 { 411, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #411 = STC_OFFSET 4456 { 412, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #412 = STC_OPTION 4457 { 413, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #413 = STC_POST 4458 { 414, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #414 = STC_PRE 4459 { 415, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x580ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #415 = STL 4460 { 416, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x580ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #416 = STLB 4461 { 417, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #417 = STLEX 4462 { 418, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #418 = STLEXB 4463 { 419, 5, 1, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x580ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #419 = STLEXD 4464 { 420, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #420 = STLEXH 4465 { 421, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x580ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #421 = STLH 4466 { 422, 4, 0, 4, 388, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,&getARMStoreDeprecationInfo }, // Inst #422 = STMDA 4467 { 423, 5, 1, 4, 389, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,&getARMStoreDeprecationInfo }, // Inst #423 = STMDA_UPD 4468 { 424, 4, 0, 4, 388, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,&getARMStoreDeprecationInfo }, // Inst #424 = STMDB 4469 { 425, 5, 1, 4, 389, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,&getARMStoreDeprecationInfo }, // Inst #425 = STMDB_UPD 4470 { 426, 4, 0, 4, 388, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,&getARMStoreDeprecationInfo }, // Inst #426 = STMIA 4471 { 427, 5, 1, 4, 389, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,&getARMStoreDeprecationInfo }, // Inst #427 = STMIA_UPD 4472 { 428, 4, 0, 4, 388, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,&getARMStoreDeprecationInfo }, // Inst #428 = STMIB 4473 { 429, 5, 1, 4, 389, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,&getARMStoreDeprecationInfo }, // Inst #429 = STMIB_UPD 4474 { 430, 4, 0, 0, 379, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #430 = STRBT_POST 4475 { 431, 7, 1, 4, 380, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x3c2ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #431 = STRBT_POST_IMM 4476 { 432, 7, 1, 4, 380, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x3c2ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #432 = STRBT_POST_REG 4477 { 433, 7, 1, 4, 381, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #433 = STRB_POST_IMM 4478 { 434, 7, 1, 4, 380, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #434 = STRB_POST_REG 4479 { 435, 6, 1, 4, 381, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3a2ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #435 = STRB_PRE_IMM 4480 { 436, 7, 1, 4, 380, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3a2ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #436 = STRB_PRE_REG 4481 { 437, 5, 0, 4, 373, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x390ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #437 = STRBi12 4482 { 438, 7, 1, 4, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #438 = STRBi_preidx 4483 { 439, 7, 1, 4, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #439 = STRBr_preidx 4484 { 440, 6, 0, 4, 374, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x380ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #440 = STRBrs 4485 { 441, 7, 0, 4, 386, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x483ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #441 = STRD 4486 { 442, 8, 1, 4, 387, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4c3ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #442 = STRD_POST 4487 { 443, 8, 1, 4, 387, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4a3ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #443 = STRD_PRE 4488 { 444, 5, 1, 4, 375, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #444 = STREX 4489 { 445, 5, 1, 4, 375, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #445 = STREXB 4490 { 446, 5, 1, 4, 375, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x580ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #446 = STREXD 4491 { 447, 5, 1, 4, 375, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #447 = STREXH 4492 { 448, 6, 0, 4, 373, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x483ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #448 = STRH 4493 { 449, 6, 1, 4, 380, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4c3ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #449 = STRHTi 4494 { 450, 7, 1, 4, 380, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4c3ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #450 = STRHTr 4495 { 451, 7, 1, 4, 380, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x4c3ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #451 = STRH_POST 4496 { 452, 7, 1, 4, 380, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x4a3ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #452 = STRH_PRE 4497 { 453, 7, 1, 4, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #453 = STRH_preidx 4498 { 454, 4, 0, 0, 379, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #454 = STRT_POST 4499 { 455, 7, 1, 4, 382, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #455 = STRT_POST_IMM 4500 { 456, 7, 1, 4, 382, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #456 = STRT_POST_REG 4501 { 457, 7, 1, 4, 383, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #457 = STR_POST_IMM 4502 { 458, 7, 1, 4, 382, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #458 = STR_POST_REG 4503 { 459, 6, 1, 4, 383, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3a2ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #459 = STR_PRE_IMM 4504 { 460, 7, 1, 4, 382, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x3a2ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #460 = STR_PRE_REG 4505 { 461, 5, 0, 4, 372, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x390ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #461 = STRi12 4506 { 462, 7, 1, 4, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #462 = STRi_preidx 4507 { 463, 7, 1, 4, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #463 = STRr_preidx 4508 { 464, 6, 0, 4, 376, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x380ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #464 = STRrs 4509 { 465, 3, 0, 4, 77, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #465 = SUBS_PC_LR 4510 { 466, 5, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr }, // Inst #466 = SUBSri 4511 { 467, 5, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo19, -1 ,nullptr }, // Inst #467 = SUBSrr 4512 { 468, 6, 1, 4, 3, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo20, -1 ,nullptr }, // Inst #468 = SUBSrsi 4513 { 469, 7, 1, 4, 5, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo21, -1 ,nullptr }, // Inst #469 = SUBSrsr 4514 { 470, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #470 = SUBri 4515 { 471, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #471 = SUBrr 4516 { 472, 7, 1, 4, 3, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #472 = SUBrsi 4517 { 473, 8, 1, 4, 4, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #473 = SUBrsr 4518 { 474, 3, 0, 4, 10, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, ImplicitList2, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #474 = SVC 4519 { 475, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #475 = SWP 4520 { 476, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #476 = SWPB 4521 { 477, 6, 1, 4, 318, 0|(1ULL<<MCID::Predicable), 0x700ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #477 = SXTAB 4522 { 478, 6, 1, 4, 318, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x700ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #478 = SXTAB16 4523 { 479, 6, 1, 4, 318, 0|(1ULL<<MCID::Predicable), 0x700ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #479 = SXTAH 4524 { 480, 5, 1, 4, 304, 0|(1ULL<<MCID::Predicable), 0x700ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #480 = SXTB 4525 { 481, 5, 1, 4, 304, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x700ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #481 = SXTB16 4526 { 482, 5, 1, 4, 304, 0|(1ULL<<MCID::Predicable), 0x700ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #482 = SXTH 4527 { 483, 1, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #483 = TAILJMPd 4528 { 484, 1, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #484 = TAILJMPr 4529 { 485, 1, 0, 0, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #485 = TCRETURNdi 4530 { 486, 1, 0, 0, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #486 = TCRETURNri 4531 { 487, 4, 0, 4, 80, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo25, -1 ,nullptr }, // Inst #487 = TEQri 4532 { 488, 4, 0, 4, 81, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x201ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #488 = TEQrr 4533 { 489, 5, 0, 4, 82, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #489 = TEQrsi 4534 { 490, 6, 0, 4, 83, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #490 = TEQrsr 4535 { 491, 0, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList9, nullptr, -1 ,nullptr }, // Inst #491 = TPsoft 4536 { 492, 0, 0, 4, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #492 = TRAP 4537 { 493, 0, 0, 4, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #493 = TRAPNaCl 4538 { 494, 4, 0, 4, 80, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo25, -1 ,nullptr }, // Inst #494 = TSTri 4539 { 495, 4, 0, 4, 81, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x201ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #495 = TSTrr 4540 { 496, 5, 0, 4, 82, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr }, // Inst #496 = TSTrsi 4541 { 497, 6, 0, 4, 83, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr }, // Inst #497 = TSTrsr 4542 { 498, 5, 1, 4, 315, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #498 = UADD16 4543 { 499, 5, 1, 4, 315, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #499 = UADD8 4544 { 500, 5, 1, 4, 315, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #500 = UASX 4545 { 501, 6, 1, 4, 292, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x201ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #501 = UBFX 4546 { 502, 1, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #502 = UDF 4547 { 503, 5, 1, 4, 338, 0|(1ULL<<MCID::Predicable), 0x600ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #503 = UDIV 4548 { 504, 5, 1, 4, 317, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #504 = UHADD16 4549 { 505, 5, 1, 4, 317, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #505 = UHADD8 4550 { 506, 5, 1, 4, 317, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #506 = UHASX 4551 { 507, 5, 1, 4, 317, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #507 = UHSAX 4552 { 508, 5, 1, 4, 317, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #508 = UHSUB16 4553 { 509, 5, 1, 4, 317, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #509 = UHSUB8 4554 { 510, 6, 2, 4, 295, 0|(1ULL<<MCID::Predicable), 0x80ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #510 = UMAAL 4555 { 511, 9, 2, 4, 295, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #511 = UMLAL 4556 { 512, 9, 2, 4, 295, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #512 = UMLALv5 4557 { 513, 7, 2, 4, 335, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #513 = UMULL 4558 { 514, 7, 2, 4, 296, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #514 = UMULLv5 4559 { 515, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #515 = UQADD16 4560 { 516, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #516 = UQADD8 4561 { 517, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #517 = UQASX 4562 { 518, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #518 = UQSAX 4563 { 519, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #519 = UQSUB16 4564 { 520, 5, 1, 4, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #520 = UQSUB8 4565 { 521, 5, 1, 4, 321, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #521 = USAD8 4566 { 522, 6, 1, 4, 322, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #522 = USADA8 4567 { 523, 6, 1, 4, 314, 0|(1ULL<<MCID::Predicable), 0x680ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #523 = USAT 4568 { 524, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x680ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #524 = USAT16 4569 { 525, 5, 1, 4, 315, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #525 = USAX 4570 { 526, 5, 1, 4, 315, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #526 = USUB16 4571 { 527, 5, 1, 4, 315, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #527 = USUB8 4572 { 528, 6, 1, 4, 318, 0|(1ULL<<MCID::Predicable), 0x700ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #528 = UXTAB 4573 { 529, 6, 1, 4, 318, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x700ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #529 = UXTAB16 4574 { 530, 6, 1, 4, 318, 0|(1ULL<<MCID::Predicable), 0x700ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #530 = UXTAH 4575 { 531, 5, 1, 4, 304, 0|(1ULL<<MCID::Predicable), 0x700ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #531 = UXTB 4576 { 532, 5, 1, 4, 304, 0|(1ULL<<MCID::Predicable), 0x700ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #532 = UXTB16 4577 { 533, 5, 1, 4, 304, 0|(1ULL<<MCID::Predicable), 0x700ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #533 = UXTH 4578 { 534, 6, 1, 4, 417, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #534 = VABALsv2i64 4579 { 535, 6, 1, 4, 417, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #535 = VABALsv4i32 4580 { 536, 6, 1, 4, 417, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #536 = VABALsv8i16 4581 { 537, 6, 1, 4, 417, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #537 = VABALuv2i64 4582 { 538, 6, 1, 4, 417, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #538 = VABALuv4i32 4583 { 539, 6, 1, 4, 417, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #539 = VABALuv8i16 4584 { 540, 6, 1, 4, 418, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #540 = VABAsv16i8 4585 { 541, 6, 1, 4, 417, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #541 = VABAsv2i32 4586 { 542, 6, 1, 4, 417, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #542 = VABAsv4i16 4587 { 543, 6, 1, 4, 418, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #543 = VABAsv4i32 4588 { 544, 6, 1, 4, 418, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #544 = VABAsv8i16 4589 { 545, 6, 1, 4, 417, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #545 = VABAsv8i8 4590 { 546, 6, 1, 4, 418, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #546 = VABAuv16i8 4591 { 547, 6, 1, 4, 417, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #547 = VABAuv2i32 4592 { 548, 6, 1, 4, 417, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #548 = VABAuv4i16 4593 { 549, 6, 1, 4, 418, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #549 = VABAuv4i32 4594 { 550, 6, 1, 4, 418, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #550 = VABAuv8i16 4595 { 551, 6, 1, 4, 417, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #551 = VABAuv8i8 4596 { 552, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #552 = VABDLsv2i64 4597 { 553, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #553 = VABDLsv4i32 4598 { 554, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #554 = VABDLsv8i16 4599 { 555, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #555 = VABDLuv2i64 4600 { 556, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #556 = VABDLuv4i32 4601 { 557, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #557 = VABDLuv8i16 4602 { 558, 5, 1, 4, 459, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #558 = VABDfd 4603 { 559, 5, 1, 4, 460, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #559 = VABDfq 4604 { 560, 5, 1, 4, 459, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #560 = VABDhd 4605 { 561, 5, 1, 4, 460, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #561 = VABDhq 4606 { 562, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #562 = VABDsv16i8 4607 { 563, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #563 = VABDsv2i32 4608 { 564, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #564 = VABDsv4i16 4609 { 565, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #565 = VABDsv4i32 4610 { 566, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #566 = VABDsv8i16 4611 { 567, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #567 = VABDsv8i8 4612 { 568, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #568 = VABDuv16i8 4613 { 569, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #569 = VABDuv2i32 4614 { 570, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #570 = VABDuv4i16 4615 { 571, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #571 = VABDuv4i32 4616 { 572, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #572 = VABDuv8i16 4617 { 573, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #573 = VABDuv8i8 4618 { 574, 4, 1, 4, 454, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #574 = VABSD 4619 { 575, 4, 1, 4, 22, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #575 = VABSH 4620 { 576, 4, 1, 4, 455, 0|(1ULL<<MCID::Predicable), 0x28780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #576 = VABSS 4621 { 577, 4, 1, 4, 419, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #577 = VABSfd 4622 { 578, 4, 1, 4, 420, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #578 = VABSfq 4623 { 579, 4, 1, 4, 91, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #579 = VABShd 4624 { 580, 4, 1, 4, 92, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #580 = VABShq 4625 { 581, 4, 1, 4, 421, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #581 = VABSv16i8 4626 { 582, 4, 1, 4, 422, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #582 = VABSv2i32 4627 { 583, 4, 1, 4, 422, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #583 = VABSv4i16 4628 { 584, 4, 1, 4, 421, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #584 = VABSv4i32 4629 { 585, 4, 1, 4, 421, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #585 = VABSv8i16 4630 { 586, 4, 1, 4, 422, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #586 = VABSv8i8 4631 { 587, 5, 1, 4, 423, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #587 = VACGEfd 4632 { 588, 5, 1, 4, 424, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #588 = VACGEfq 4633 { 589, 5, 1, 4, 423, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #589 = VACGEhd 4634 { 590, 5, 1, 4, 424, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #590 = VACGEhq 4635 { 591, 5, 1, 4, 423, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #591 = VACGTfd 4636 { 592, 5, 1, 4, 424, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #592 = VACGTfq 4637 { 593, 5, 1, 4, 423, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #593 = VACGThd 4638 { 594, 5, 1, 4, 424, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #594 = VACGThq 4639 { 595, 5, 1, 4, 465, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #595 = VADDD 4640 { 596, 5, 1, 4, 96, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #596 = VADDH 4641 { 597, 5, 1, 4, 438, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #597 = VADDHNv2i32 4642 { 598, 5, 1, 4, 438, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #598 = VADDHNv4i16 4643 { 599, 5, 1, 4, 438, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #599 = VADDHNv8i8 4644 { 600, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #600 = VADDLsv2i64 4645 { 601, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #601 = VADDLsv4i32 4646 { 602, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #602 = VADDLsv8i16 4647 { 603, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #603 = VADDLuv2i64 4648 { 604, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #604 = VADDLuv4i32 4649 { 605, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #605 = VADDLuv8i16 4650 { 606, 5, 1, 4, 462, 0|(1ULL<<MCID::Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #606 = VADDS 4651 { 607, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #607 = VADDWsv2i64 4652 { 608, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #608 = VADDWsv4i32 4653 { 609, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #609 = VADDWsv8i16 4654 { 610, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #610 = VADDWuv2i64 4655 { 611, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #611 = VADDWuv4i32 4656 { 612, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #612 = VADDWuv8i16 4657 { 613, 5, 1, 4, 459, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #613 = VADDfd 4658 { 614, 5, 1, 4, 460, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #614 = VADDfq 4659 { 615, 5, 1, 4, 88, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #615 = VADDhd 4660 { 616, 5, 1, 4, 89, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #616 = VADDhq 4661 { 617, 5, 1, 4, 398, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #617 = VADDv16i8 4662 { 618, 5, 1, 4, 399, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #618 = VADDv1i64 4663 { 619, 5, 1, 4, 399, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #619 = VADDv2i32 4664 { 620, 5, 1, 4, 398, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #620 = VADDv2i64 4665 { 621, 5, 1, 4, 399, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #621 = VADDv4i16 4666 { 622, 5, 1, 4, 398, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #622 = VADDv4i32 4667 { 623, 5, 1, 4, 398, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #623 = VADDv8i16 4668 { 624, 5, 1, 4, 399, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #624 = VADDv8i8 4669 { 625, 5, 1, 4, 399, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #625 = VANDd 4670 { 626, 5, 1, 4, 398, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #626 = VANDq 4671 { 627, 5, 1, 4, 399, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #627 = VBICd 4672 { 628, 5, 1, 4, 400, 0|(1ULL<<MCID::Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #628 = VBICiv2i32 4673 { 629, 5, 1, 4, 400, 0|(1ULL<<MCID::Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #629 = VBICiv4i16 4674 { 630, 5, 1, 4, 400, 0|(1ULL<<MCID::Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #630 = VBICiv4i32 4675 { 631, 5, 1, 4, 400, 0|(1ULL<<MCID::Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #631 = VBICiv8i16 4676 { 632, 5, 1, 4, 398, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #632 = VBICq 4677 { 633, 6, 1, 4, 399, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #633 = VBIFd 4678 { 634, 6, 1, 4, 398, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #634 = VBIFq 4679 { 635, 6, 1, 4, 399, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #635 = VBITd 4680 { 636, 6, 1, 4, 398, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #636 = VBITq 4681 { 637, 6, 1, 4, 401, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #637 = VBSLd 4682 { 638, 6, 1, 4, 402, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #638 = VBSLq 4683 { 639, 5, 1, 4, 423, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #639 = VCEQfd 4684 { 640, 5, 1, 4, 424, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #640 = VCEQfq 4685 { 641, 5, 1, 4, 423, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #641 = VCEQhd 4686 { 642, 5, 1, 4, 424, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #642 = VCEQhq 4687 { 643, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #643 = VCEQv16i8 4688 { 644, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #644 = VCEQv2i32 4689 { 645, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #645 = VCEQv4i16 4690 { 646, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #646 = VCEQv4i32 4691 { 647, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #647 = VCEQv8i16 4692 { 648, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #648 = VCEQv8i8 4693 { 649, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #649 = VCEQzv16i8 4694 { 650, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #650 = VCEQzv2f32 4695 { 651, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #651 = VCEQzv2i32 4696 { 652, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #652 = VCEQzv4f16 4697 { 653, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #653 = VCEQzv4f32 4698 { 654, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #654 = VCEQzv4i16 4699 { 655, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #655 = VCEQzv4i32 4700 { 656, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #656 = VCEQzv8f16 4701 { 657, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #657 = VCEQzv8i16 4702 { 658, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #658 = VCEQzv8i8 4703 { 659, 5, 1, 4, 423, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #659 = VCGEfd 4704 { 660, 5, 1, 4, 424, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #660 = VCGEfq 4705 { 661, 5, 1, 4, 423, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #661 = VCGEhd 4706 { 662, 5, 1, 4, 424, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #662 = VCGEhq 4707 { 663, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #663 = VCGEsv16i8 4708 { 664, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #664 = VCGEsv2i32 4709 { 665, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #665 = VCGEsv4i16 4710 { 666, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #666 = VCGEsv4i32 4711 { 667, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #667 = VCGEsv8i16 4712 { 668, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #668 = VCGEsv8i8 4713 { 669, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #669 = VCGEuv16i8 4714 { 670, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #670 = VCGEuv2i32 4715 { 671, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #671 = VCGEuv4i16 4716 { 672, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #672 = VCGEuv4i32 4717 { 673, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #673 = VCGEuv8i16 4718 { 674, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #674 = VCGEuv8i8 4719 { 675, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #675 = VCGEzv16i8 4720 { 676, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #676 = VCGEzv2f32 4721 { 677, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #677 = VCGEzv2i32 4722 { 678, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #678 = VCGEzv4f16 4723 { 679, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #679 = VCGEzv4f32 4724 { 680, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #680 = VCGEzv4i16 4725 { 681, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #681 = VCGEzv4i32 4726 { 682, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #682 = VCGEzv8f16 4727 { 683, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #683 = VCGEzv8i16 4728 { 684, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #684 = VCGEzv8i8 4729 { 685, 5, 1, 4, 423, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #685 = VCGTfd 4730 { 686, 5, 1, 4, 424, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #686 = VCGTfq 4731 { 687, 5, 1, 4, 423, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #687 = VCGThd 4732 { 688, 5, 1, 4, 424, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #688 = VCGThq 4733 { 689, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #689 = VCGTsv16i8 4734 { 690, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #690 = VCGTsv2i32 4735 { 691, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #691 = VCGTsv4i16 4736 { 692, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #692 = VCGTsv4i32 4737 { 693, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #693 = VCGTsv8i16 4738 { 694, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #694 = VCGTsv8i8 4739 { 695, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #695 = VCGTuv16i8 4740 { 696, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #696 = VCGTuv2i32 4741 { 697, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #697 = VCGTuv4i16 4742 { 698, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #698 = VCGTuv4i32 4743 { 699, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #699 = VCGTuv8i16 4744 { 700, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #700 = VCGTuv8i8 4745 { 701, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #701 = VCGTzv16i8 4746 { 702, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #702 = VCGTzv2f32 4747 { 703, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #703 = VCGTzv2i32 4748 { 704, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #704 = VCGTzv4f16 4749 { 705, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #705 = VCGTzv4f32 4750 { 706, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #706 = VCGTzv4i16 4751 { 707, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #707 = VCGTzv4i32 4752 { 708, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #708 = VCGTzv8f16 4753 { 709, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #709 = VCGTzv8i16 4754 { 710, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #710 = VCGTzv8i8 4755 { 711, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #711 = VCLEzv16i8 4756 { 712, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #712 = VCLEzv2f32 4757 { 713, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #713 = VCLEzv2i32 4758 { 714, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #714 = VCLEzv4f16 4759 { 715, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #715 = VCLEzv4f32 4760 { 716, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #716 = VCLEzv4i16 4761 { 717, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #717 = VCLEzv4i32 4762 { 718, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #718 = VCLEzv8f16 4763 { 719, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #719 = VCLEzv8i16 4764 { 720, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #720 = VCLEzv8i8 4765 { 721, 4, 1, 4, 402, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #721 = VCLSv16i8 4766 { 722, 4, 1, 4, 401, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #722 = VCLSv2i32 4767 { 723, 4, 1, 4, 401, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #723 = VCLSv4i16 4768 { 724, 4, 1, 4, 402, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #724 = VCLSv4i32 4769 { 725, 4, 1, 4, 402, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #725 = VCLSv8i16 4770 { 726, 4, 1, 4, 401, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #726 = VCLSv8i8 4771 { 727, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #727 = VCLTzv16i8 4772 { 728, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #728 = VCLTzv2f32 4773 { 729, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #729 = VCLTzv2i32 4774 { 730, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #730 = VCLTzv4f16 4775 { 731, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #731 = VCLTzv4f32 4776 { 732, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #732 = VCLTzv4i16 4777 { 733, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #733 = VCLTzv4i32 4778 { 734, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #734 = VCLTzv8f16 4779 { 735, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #735 = VCLTzv8i16 4780 { 736, 4, 1, 4, 427, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #736 = VCLTzv8i8 4781 { 737, 4, 1, 4, 402, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #737 = VCLZv16i8 4782 { 738, 4, 1, 4, 401, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #738 = VCLZv2i32 4783 { 739, 4, 1, 4, 401, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #739 = VCLZv4i16 4784 { 740, 4, 1, 4, 402, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #740 = VCLZv4i32 4785 { 741, 4, 1, 4, 402, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #741 = VCLZv8i16 4786 { 742, 4, 1, 4, 401, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #742 = VCLZv8i8 4787 { 743, 4, 0, 4, 456, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, ImplicitList5, OperandInfo137, -1 ,nullptr }, // Inst #743 = VCMPD 4788 { 744, 4, 0, 4, 456, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, ImplicitList5, OperandInfo137, -1 ,nullptr }, // Inst #744 = VCMPED 4789 { 745, 4, 0, 4, 107, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, ImplicitList5, OperandInfo138, -1 ,nullptr }, // Inst #745 = VCMPEH 4790 { 746, 4, 0, 4, 457, 0|(1ULL<<MCID::Predicable), 0x28780ULL, nullptr, ImplicitList5, OperandInfo138, -1 ,nullptr }, // Inst #746 = VCMPES 4791 { 747, 3, 0, 4, 456, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, ImplicitList5, OperandInfo145, -1 ,nullptr }, // Inst #747 = VCMPEZD 4792 { 748, 3, 0, 4, 107, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, ImplicitList5, OperandInfo146, -1 ,nullptr }, // Inst #748 = VCMPEZH 4793 { 749, 3, 0, 4, 457, 0|(1ULL<<MCID::Predicable), 0x28780ULL, nullptr, ImplicitList5, OperandInfo146, -1 ,nullptr }, // Inst #749 = VCMPEZS 4794 { 750, 4, 0, 4, 107, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, ImplicitList5, OperandInfo138, -1 ,nullptr }, // Inst #750 = VCMPH 4795 { 751, 4, 0, 4, 457, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28780ULL, nullptr, ImplicitList5, OperandInfo138, -1 ,nullptr }, // Inst #751 = VCMPS 4796 { 752, 3, 0, 4, 456, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, ImplicitList5, OperandInfo145, -1 ,nullptr }, // Inst #752 = VCMPZD 4797 { 753, 3, 0, 4, 107, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, ImplicitList5, OperandInfo146, -1 ,nullptr }, // Inst #753 = VCMPZH 4798 { 754, 3, 0, 4, 457, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28780ULL, nullptr, ImplicitList5, OperandInfo146, -1 ,nullptr }, // Inst #754 = VCMPZS 4799 { 755, 4, 1, 4, 401, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #755 = VCNTd 4800 { 756, 4, 1, 4, 402, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #756 = VCNTq 4801 { 757, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #757 = VCVTANSDf 4802 { 758, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #758 = VCVTANSDh 4803 { 759, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #759 = VCVTANSQf 4804 { 760, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #760 = VCVTANSQh 4805 { 761, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #761 = VCVTANUDf 4806 { 762, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #762 = VCVTANUDh 4807 { 763, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #763 = VCVTANUQf 4808 { 764, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #764 = VCVTANUQh 4809 { 765, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #765 = VCVTASD 4810 { 766, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #766 = VCVTASH 4811 { 767, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #767 = VCVTASS 4812 { 768, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #768 = VCVTAUD 4813 { 769, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #769 = VCVTAUH 4814 { 770, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #770 = VCVTAUS 4815 { 771, 4, 1, 4, 493, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #771 = VCVTBDH 4816 { 772, 4, 1, 4, 493, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #772 = VCVTBHD 4817 { 773, 4, 1, 4, 494, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #773 = VCVTBHS 4818 { 774, 4, 1, 4, 495, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #774 = VCVTBSH 4819 { 775, 4, 1, 4, 496, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #775 = VCVTDS 4820 { 776, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #776 = VCVTMNSDf 4821 { 777, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #777 = VCVTMNSDh 4822 { 778, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #778 = VCVTMNSQf 4823 { 779, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #779 = VCVTMNSQh 4824 { 780, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #780 = VCVTMNUDf 4825 { 781, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #781 = VCVTMNUDh 4826 { 782, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #782 = VCVTMNUQf 4827 { 783, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #783 = VCVTMNUQh 4828 { 784, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #784 = VCVTMSD 4829 { 785, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #785 = VCVTMSH 4830 { 786, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #786 = VCVTMSS 4831 { 787, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #787 = VCVTMUD 4832 { 788, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #788 = VCVTMUH 4833 { 789, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #789 = VCVTMUS 4834 { 790, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #790 = VCVTNNSDf 4835 { 791, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #791 = VCVTNNSDh 4836 { 792, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #792 = VCVTNNSQf 4837 { 793, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #793 = VCVTNNSQh 4838 { 794, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #794 = VCVTNNUDf 4839 { 795, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #795 = VCVTNNUDh 4840 { 796, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #796 = VCVTNNUQf 4841 { 797, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #797 = VCVTNNUQh 4842 { 798, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #798 = VCVTNSD 4843 { 799, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #799 = VCVTNSH 4844 { 800, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #800 = VCVTNSS 4845 { 801, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #801 = VCVTNUD 4846 { 802, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #802 = VCVTNUH 4847 { 803, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #803 = VCVTNUS 4848 { 804, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #804 = VCVTPNSDf 4849 { 805, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #805 = VCVTPNSDh 4850 { 806, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #806 = VCVTPNSQf 4851 { 807, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #807 = VCVTPNSQh 4852 { 808, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #808 = VCVTPNUDf 4853 { 809, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #809 = VCVTPNUDh 4854 { 810, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #810 = VCVTPNUQf 4855 { 811, 2, 1, 4, 493, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #811 = VCVTPNUQh 4856 { 812, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #812 = VCVTPSD 4857 { 813, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #813 = VCVTPSH 4858 { 814, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #814 = VCVTPSS 4859 { 815, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #815 = VCVTPUD 4860 { 816, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #816 = VCVTPUH 4861 { 817, 2, 1, 4, 493, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #817 = VCVTPUS 4862 { 818, 4, 1, 4, 497, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #818 = VCVTSD 4863 { 819, 4, 1, 4, 493, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #819 = VCVTTDH 4864 { 820, 4, 1, 4, 493, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #820 = VCVTTHD 4865 { 821, 4, 1, 4, 494, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #821 = VCVTTHS 4866 { 822, 4, 1, 4, 495, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #822 = VCVTTSH 4867 { 823, 4, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #823 = VCVTf2h 4868 { 824, 4, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #824 = VCVTf2sd 4869 { 825, 4, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #825 = VCVTf2sq 4870 { 826, 4, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #826 = VCVTf2ud 4871 { 827, 4, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #827 = VCVTf2uq 4872 { 828, 5, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #828 = VCVTf2xsd 4873 { 829, 5, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #829 = VCVTf2xsq 4874 { 830, 5, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #830 = VCVTf2xud 4875 { 831, 5, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #831 = VCVTf2xuq 4876 { 832, 4, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #832 = VCVTh2f 4877 { 833, 4, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #833 = VCVTh2sd 4878 { 834, 4, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #834 = VCVTh2sq 4879 { 835, 4, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #835 = VCVTh2ud 4880 { 836, 4, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #836 = VCVTh2uq 4881 { 837, 5, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #837 = VCVTh2xsd 4882 { 838, 5, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #838 = VCVTh2xsq 4883 { 839, 5, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #839 = VCVTh2xud 4884 { 840, 5, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #840 = VCVTh2xuq 4885 { 841, 4, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #841 = VCVTs2fd 4886 { 842, 4, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #842 = VCVTs2fq 4887 { 843, 4, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #843 = VCVTs2hd 4888 { 844, 4, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #844 = VCVTs2hq 4889 { 845, 4, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #845 = VCVTu2fd 4890 { 846, 4, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #846 = VCVTu2fq 4891 { 847, 4, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #847 = VCVTu2hd 4892 { 848, 4, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #848 = VCVTu2hq 4893 { 849, 5, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #849 = VCVTxs2fd 4894 { 850, 5, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #850 = VCVTxs2fq 4895 { 851, 5, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #851 = VCVTxs2hd 4896 { 852, 5, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #852 = VCVTxs2hq 4897 { 853, 5, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #853 = VCVTxu2fd 4898 { 854, 5, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #854 = VCVTxu2fq 4899 { 855, 5, 1, 4, 499, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #855 = VCVTxu2hd 4900 { 856, 5, 1, 4, 498, 0|(1ULL<<MCID::Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #856 = VCVTxu2hq 4901 { 857, 5, 1, 4, 610, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #857 = VDIVD 4902 { 858, 5, 1, 4, 114, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #858 = VDIVH 4903 { 859, 5, 1, 4, 608, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #859 = VDIVS 4904 { 860, 4, 1, 4, 518, 0|(1ULL<<MCID::Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #860 = VDUP16d 4905 { 861, 4, 1, 4, 518, 0|(1ULL<<MCID::Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #861 = VDUP16q 4906 { 862, 4, 1, 4, 518, 0|(1ULL<<MCID::Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #862 = VDUP32d 4907 { 863, 4, 1, 4, 518, 0|(1ULL<<MCID::Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #863 = VDUP32q 4908 { 864, 4, 1, 4, 518, 0|(1ULL<<MCID::Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #864 = VDUP8d 4909 { 865, 4, 1, 4, 518, 0|(1ULL<<MCID::Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #865 = VDUP8q 4910 { 866, 5, 1, 4, 516, 0|(1ULL<<MCID::Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #866 = VDUPLN16d 4911 { 867, 5, 1, 4, 517, 0|(1ULL<<MCID::Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #867 = VDUPLN16q 4912 { 868, 5, 1, 4, 516, 0|(1ULL<<MCID::Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #868 = VDUPLN32d 4913 { 869, 5, 1, 4, 517, 0|(1ULL<<MCID::Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #869 = VDUPLN32q 4914 { 870, 5, 1, 4, 516, 0|(1ULL<<MCID::Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #870 = VDUPLN8d 4915 { 871, 5, 1, 4, 517, 0|(1ULL<<MCID::Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #871 = VDUPLN8q 4916 { 872, 5, 1, 4, 399, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #872 = VEORd 4917 { 873, 5, 1, 4, 398, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #873 = VEORq 4918 { 874, 6, 1, 4, 413, 0|(1ULL<<MCID::Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #874 = VEXTd16 4919 { 875, 6, 1, 4, 413, 0|(1ULL<<MCID::Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #875 = VEXTd32 4920 { 876, 6, 1, 4, 413, 0|(1ULL<<MCID::Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #876 = VEXTd8 4921 { 877, 6, 1, 4, 414, 0|(1ULL<<MCID::Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #877 = VEXTq16 4922 { 878, 6, 1, 4, 414, 0|(1ULL<<MCID::Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #878 = VEXTq32 4923 { 879, 6, 1, 4, 414, 0|(1ULL<<MCID::Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #879 = VEXTq64 4924 { 880, 6, 1, 4, 414, 0|(1ULL<<MCID::Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #880 = VEXTq8 4925 { 881, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #881 = VFMAD 4926 { 882, 6, 1, 4, 122, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #882 = VFMAH 4927 { 883, 6, 1, 4, 480, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #883 = VFMAS 4928 { 884, 6, 1, 4, 491, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #884 = VFMAfd 4929 { 885, 6, 1, 4, 492, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #885 = VFMAfq 4930 { 886, 6, 1, 4, 124, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #886 = VFMAhd 4931 { 887, 6, 1, 4, 125, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #887 = VFMAhq 4932 { 888, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #888 = VFMSD 4933 { 889, 6, 1, 4, 122, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #889 = VFMSH 4934 { 890, 6, 1, 4, 480, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #890 = VFMSS 4935 { 891, 6, 1, 4, 491, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #891 = VFMSfd 4936 { 892, 6, 1, 4, 492, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #892 = VFMSfq 4937 { 893, 6, 1, 4, 124, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #893 = VFMShd 4938 { 894, 6, 1, 4, 125, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #894 = VFMShq 4939 { 895, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #895 = VFNMAD 4940 { 896, 6, 1, 4, 481, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #896 = VFNMAH 4941 { 897, 6, 1, 4, 480, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #897 = VFNMAS 4942 { 898, 6, 1, 4, 479, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #898 = VFNMSD 4943 { 899, 6, 1, 4, 481, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #899 = VFNMSH 4944 { 900, 6, 1, 4, 480, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #900 = VFNMSS 4945 { 901, 5, 1, 4, 525, 0|(1ULL<<MCID::Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #901 = VGETLNi32 4946 { 902, 5, 1, 4, 526, 0|(1ULL<<MCID::Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #902 = VGETLNs16 4947 { 903, 5, 1, 4, 526, 0|(1ULL<<MCID::Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #903 = VGETLNs8 4948 { 904, 5, 1, 4, 525, 0|(1ULL<<MCID::Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #904 = VGETLNu16 4949 { 905, 5, 1, 4, 525, 0|(1ULL<<MCID::Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #905 = VGETLNu8 4950 { 906, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #906 = VHADDsv16i8 4951 { 907, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #907 = VHADDsv2i32 4952 { 908, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #908 = VHADDsv4i16 4953 { 909, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #909 = VHADDsv4i32 4954 { 910, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #910 = VHADDsv8i16 4955 { 911, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #911 = VHADDsv8i8 4956 { 912, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #912 = VHADDuv16i8 4957 { 913, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #913 = VHADDuv2i32 4958 { 914, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #914 = VHADDuv4i16 4959 { 915, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #915 = VHADDuv4i32 4960 { 916, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #916 = VHADDuv8i16 4961 { 917, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #917 = VHADDuv8i8 4962 { 918, 5, 1, 4, 405, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #918 = VHSUBsv16i8 4963 { 919, 5, 1, 4, 406, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #919 = VHSUBsv2i32 4964 { 920, 5, 1, 4, 406, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #920 = VHSUBsv4i16 4965 { 921, 5, 1, 4, 405, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #921 = VHSUBsv4i32 4966 { 922, 5, 1, 4, 405, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #922 = VHSUBsv8i16 4967 { 923, 5, 1, 4, 406, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #923 = VHSUBsv8i8 4968 { 924, 5, 1, 4, 405, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #924 = VHSUBuv16i8 4969 { 925, 5, 1, 4, 406, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #925 = VHSUBuv2i32 4970 { 926, 5, 1, 4, 406, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #926 = VHSUBuv4i16 4971 { 927, 5, 1, 4, 405, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #927 = VHSUBuv4i32 4972 { 928, 5, 1, 4, 405, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #928 = VHSUBuv8i16 4973 { 929, 5, 1, 4, 406, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #929 = VHSUBuv8i8 4974 { 930, 2, 1, 4, 22, 0, 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #930 = VINSH 4975 { 931, 5, 1, 4, 560, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #931 = VLD1DUPd16 4976 { 932, 6, 2, 4, 562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #932 = VLD1DUPd16wb_fixed 4977 { 933, 7, 2, 4, 562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #933 = VLD1DUPd16wb_register 4978 { 934, 5, 1, 4, 560, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #934 = VLD1DUPd32 4979 { 935, 6, 2, 4, 562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #935 = VLD1DUPd32wb_fixed 4980 { 936, 7, 2, 4, 562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #936 = VLD1DUPd32wb_register 4981 { 937, 5, 1, 4, 560, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #937 = VLD1DUPd8 4982 { 938, 6, 2, 4, 562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #938 = VLD1DUPd8wb_fixed 4983 { 939, 7, 2, 4, 562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #939 = VLD1DUPd8wb_register 4984 { 940, 5, 1, 4, 560, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #940 = VLD1DUPq16 4985 { 941, 6, 2, 4, 562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #941 = VLD1DUPq16wb_fixed 4986 { 942, 7, 2, 4, 562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #942 = VLD1DUPq16wb_register 4987 { 943, 5, 1, 4, 560, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #943 = VLD1DUPq32 4988 { 944, 6, 2, 4, 562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #944 = VLD1DUPq32wb_fixed 4989 { 945, 7, 2, 4, 562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #945 = VLD1DUPq32wb_register 4990 { 946, 5, 1, 4, 560, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #946 = VLD1DUPq8 4991 { 947, 6, 2, 4, 562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #947 = VLD1DUPq8wb_fixed 4992 { 948, 7, 2, 4, 562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #948 = VLD1DUPq8wb_register 4993 { 949, 7, 1, 4, 561, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #949 = VLD1LNd16 4994 { 950, 9, 2, 4, 563, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr }, // Inst #950 = VLD1LNd16_UPD 4995 { 951, 7, 1, 4, 561, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #951 = VLD1LNd32 4996 { 952, 9, 2, 4, 563, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr }, // Inst #952 = VLD1LNd32_UPD 4997 { 953, 7, 1, 4, 561, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #953 = VLD1LNd8 4998 { 954, 9, 2, 4, 563, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr }, // Inst #954 = VLD1LNd8_UPD 4999 { 955, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #955 = VLD1LNdAsm_16 5000 { 956, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #956 = VLD1LNdAsm_32 5001 { 957, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #957 = VLD1LNdAsm_8 5002 { 958, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #958 = VLD1LNdWB_fixed_Asm_16 5003 { 959, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #959 = VLD1LNdWB_fixed_Asm_32 5004 { 960, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #960 = VLD1LNdWB_fixed_Asm_8 5005 { 961, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #961 = VLD1LNdWB_register_Asm_16 5006 { 962, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #962 = VLD1LNdWB_register_Asm_32 5007 { 963, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #963 = VLD1LNdWB_register_Asm_8 5008 { 964, 7, 1, 4, 561, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #964 = VLD1LNq16Pseudo 5009 { 965, 9, 2, 4, 563, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #965 = VLD1LNq16Pseudo_UPD 5010 { 966, 7, 1, 4, 561, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #966 = VLD1LNq32Pseudo 5011 { 967, 9, 2, 4, 563, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #967 = VLD1LNq32Pseudo_UPD 5012 { 968, 7, 1, 4, 561, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #968 = VLD1LNq8Pseudo 5013 { 969, 9, 2, 4, 563, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #969 = VLD1LNq8Pseudo_UPD 5014 { 970, 5, 1, 4, 540, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #970 = VLD1d16 5015 { 971, 5, 1, 4, 546, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #971 = VLD1d16Q 5016 { 972, 6, 2, 4, 547, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #972 = VLD1d16Qwb_fixed 5017 { 973, 7, 2, 4, 547, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #973 = VLD1d16Qwb_register 5018 { 974, 5, 1, 4, 544, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #974 = VLD1d16T 5019 { 975, 6, 2, 4, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #975 = VLD1d16Twb_fixed 5020 { 976, 7, 2, 4, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #976 = VLD1d16Twb_register 5021 { 977, 6, 2, 4, 542, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #977 = VLD1d16wb_fixed 5022 { 978, 7, 2, 4, 542, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #978 = VLD1d16wb_register 5023 { 979, 5, 1, 4, 540, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #979 = VLD1d32 5024 { 980, 5, 1, 4, 546, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #980 = VLD1d32Q 5025 { 981, 6, 2, 4, 547, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #981 = VLD1d32Qwb_fixed 5026 { 982, 7, 2, 4, 547, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #982 = VLD1d32Qwb_register 5027 { 983, 5, 1, 4, 544, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #983 = VLD1d32T 5028 { 984, 6, 2, 4, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #984 = VLD1d32Twb_fixed 5029 { 985, 7, 2, 4, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #985 = VLD1d32Twb_register 5030 { 986, 6, 2, 4, 542, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #986 = VLD1d32wb_fixed 5031 { 987, 7, 2, 4, 542, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #987 = VLD1d32wb_register 5032 { 988, 5, 1, 4, 540, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #988 = VLD1d64 5033 { 989, 5, 1, 4, 546, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #989 = VLD1d64Q 5034 { 990, 5, 1, 4, 546, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #990 = VLD1d64QPseudo 5035 { 991, 6, 2, 4, 546, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #991 = VLD1d64QPseudoWB_fixed 5036 { 992, 7, 2, 4, 546, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #992 = VLD1d64QPseudoWB_register 5037 { 993, 6, 2, 4, 547, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #993 = VLD1d64Qwb_fixed 5038 { 994, 7, 2, 4, 547, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #994 = VLD1d64Qwb_register 5039 { 995, 5, 1, 4, 544, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #995 = VLD1d64T 5040 { 996, 5, 1, 4, 544, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #996 = VLD1d64TPseudo 5041 { 997, 6, 2, 4, 544, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #997 = VLD1d64TPseudoWB_fixed 5042 { 998, 7, 2, 4, 544, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #998 = VLD1d64TPseudoWB_register 5043 { 999, 6, 2, 4, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #999 = VLD1d64Twb_fixed 5044 { 1000, 7, 2, 4, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #1000 = VLD1d64Twb_register 5045 { 1001, 6, 2, 4, 542, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1001 = VLD1d64wb_fixed 5046 { 1002, 7, 2, 4, 542, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #1002 = VLD1d64wb_register 5047 { 1003, 5, 1, 4, 540, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1003 = VLD1d8 5048 { 1004, 5, 1, 4, 546, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1004 = VLD1d8Q 5049 { 1005, 6, 2, 4, 547, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1005 = VLD1d8Qwb_fixed 5050 { 1006, 7, 2, 4, 547, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #1006 = VLD1d8Qwb_register 5051 { 1007, 5, 1, 4, 544, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1007 = VLD1d8T 5052 { 1008, 6, 2, 4, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1008 = VLD1d8Twb_fixed 5053 { 1009, 7, 2, 4, 545, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #1009 = VLD1d8Twb_register 5054 { 1010, 6, 2, 4, 542, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1010 = VLD1d8wb_fixed 5055 { 1011, 7, 2, 4, 542, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #1011 = VLD1d8wb_register 5056 { 1012, 5, 1, 4, 541, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1012 = VLD1q16 5057 { 1013, 6, 2, 4, 543, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1013 = VLD1q16wb_fixed 5058 { 1014, 7, 2, 4, 543, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1014 = VLD1q16wb_register 5059 { 1015, 5, 1, 4, 541, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1015 = VLD1q32 5060 { 1016, 6, 2, 4, 543, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1016 = VLD1q32wb_fixed 5061 { 1017, 7, 2, 4, 543, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1017 = VLD1q32wb_register 5062 { 1018, 5, 1, 4, 541, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1018 = VLD1q64 5063 { 1019, 6, 2, 4, 543, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1019 = VLD1q64wb_fixed 5064 { 1020, 7, 2, 4, 543, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1020 = VLD1q64wb_register 5065 { 1021, 5, 1, 4, 541, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1021 = VLD1q8 5066 { 1022, 6, 2, 4, 543, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1022 = VLD1q8wb_fixed 5067 { 1023, 7, 2, 4, 543, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1023 = VLD1q8wb_register 5068 { 1024, 5, 1, 4, 564, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1024 = VLD2DUPd16 5069 { 1025, 6, 2, 4, 567, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1025 = VLD2DUPd16wb_fixed 5070 { 1026, 7, 2, 4, 567, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1026 = VLD2DUPd16wb_register 5071 { 1027, 5, 1, 4, 564, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1027 = VLD2DUPd16x2 5072 { 1028, 6, 2, 4, 567, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1028 = VLD2DUPd16x2wb_fixed 5073 { 1029, 7, 2, 4, 567, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1029 = VLD2DUPd16x2wb_register 5074 { 1030, 5, 1, 4, 564, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1030 = VLD2DUPd32 5075 { 1031, 6, 2, 4, 567, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1031 = VLD2DUPd32wb_fixed 5076 { 1032, 7, 2, 4, 567, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1032 = VLD2DUPd32wb_register 5077 { 1033, 5, 1, 4, 564, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1033 = VLD2DUPd32x2 5078 { 1034, 6, 2, 4, 567, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1034 = VLD2DUPd32x2wb_fixed 5079 { 1035, 7, 2, 4, 567, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1035 = VLD2DUPd32x2wb_register 5080 { 1036, 5, 1, 4, 564, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1036 = VLD2DUPd8 5081 { 1037, 6, 2, 4, 567, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1037 = VLD2DUPd8wb_fixed 5082 { 1038, 7, 2, 4, 567, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1038 = VLD2DUPd8wb_register 5083 { 1039, 5, 1, 4, 564, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1039 = VLD2DUPd8x2 5084 { 1040, 6, 2, 4, 567, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1040 = VLD2DUPd8x2wb_fixed 5085 { 1041, 7, 2, 4, 567, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1041 = VLD2DUPd8x2wb_register 5086 { 1042, 9, 2, 4, 565, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr }, // Inst #1042 = VLD2LNd16 5087 { 1043, 7, 1, 4, 565, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #1043 = VLD2LNd16Pseudo 5088 { 1044, 9, 2, 4, 568, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #1044 = VLD2LNd16Pseudo_UPD 5089 { 1045, 11, 3, 4, 566, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo179, -1 ,nullptr }, // Inst #1045 = VLD2LNd16_UPD 5090 { 1046, 9, 2, 4, 565, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr }, // Inst #1046 = VLD2LNd32 5091 { 1047, 7, 1, 4, 565, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #1047 = VLD2LNd32Pseudo 5092 { 1048, 9, 2, 4, 568, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #1048 = VLD2LNd32Pseudo_UPD 5093 { 1049, 11, 3, 4, 566, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo179, -1 ,nullptr }, // Inst #1049 = VLD2LNd32_UPD 5094 { 1050, 9, 2, 4, 565, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr }, // Inst #1050 = VLD2LNd8 5095 { 1051, 7, 1, 4, 565, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #1051 = VLD2LNd8Pseudo 5096 { 1052, 9, 2, 4, 568, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #1052 = VLD2LNd8Pseudo_UPD 5097 { 1053, 11, 3, 4, 566, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo179, -1 ,nullptr }, // Inst #1053 = VLD2LNd8_UPD 5098 { 1054, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1054 = VLD2LNdAsm_16 5099 { 1055, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1055 = VLD2LNdAsm_32 5100 { 1056, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1056 = VLD2LNdAsm_8 5101 { 1057, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1057 = VLD2LNdWB_fixed_Asm_16 5102 { 1058, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1058 = VLD2LNdWB_fixed_Asm_32 5103 { 1059, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1059 = VLD2LNdWB_fixed_Asm_8 5104 { 1060, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1060 = VLD2LNdWB_register_Asm_16 5105 { 1061, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1061 = VLD2LNdWB_register_Asm_32 5106 { 1062, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1062 = VLD2LNdWB_register_Asm_8 5107 { 1063, 9, 2, 4, 565, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr }, // Inst #1063 = VLD2LNq16 5108 { 1064, 7, 1, 4, 565, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1064 = VLD2LNq16Pseudo 5109 { 1065, 9, 2, 4, 568, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1065 = VLD2LNq16Pseudo_UPD 5110 { 1066, 11, 3, 4, 566, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo179, -1 ,nullptr }, // Inst #1066 = VLD2LNq16_UPD 5111 { 1067, 9, 2, 4, 565, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr }, // Inst #1067 = VLD2LNq32 5112 { 1068, 7, 1, 4, 565, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1068 = VLD2LNq32Pseudo 5113 { 1069, 9, 2, 4, 568, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1069 = VLD2LNq32Pseudo_UPD 5114 { 1070, 11, 3, 4, 566, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo179, -1 ,nullptr }, // Inst #1070 = VLD2LNq32_UPD 5115 { 1071, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1071 = VLD2LNqAsm_16 5116 { 1072, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1072 = VLD2LNqAsm_32 5117 { 1073, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1073 = VLD2LNqWB_fixed_Asm_16 5118 { 1074, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1074 = VLD2LNqWB_fixed_Asm_32 5119 { 1075, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1075 = VLD2LNqWB_register_Asm_16 5120 { 1076, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1076 = VLD2LNqWB_register_Asm_32 5121 { 1077, 5, 1, 4, 548, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1077 = VLD2b16 5122 { 1078, 6, 2, 4, 550, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1078 = VLD2b16wb_fixed 5123 { 1079, 7, 2, 4, 550, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1079 = VLD2b16wb_register 5124 { 1080, 5, 1, 4, 548, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1080 = VLD2b32 5125 { 1081, 6, 2, 4, 550, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1081 = VLD2b32wb_fixed 5126 { 1082, 7, 2, 4, 550, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1082 = VLD2b32wb_register 5127 { 1083, 5, 1, 4, 548, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1083 = VLD2b8 5128 { 1084, 6, 2, 4, 550, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1084 = VLD2b8wb_fixed 5129 { 1085, 7, 2, 4, 550, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1085 = VLD2b8wb_register 5130 { 1086, 5, 1, 4, 548, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1086 = VLD2d16 5131 { 1087, 6, 2, 4, 550, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1087 = VLD2d16wb_fixed 5132 { 1088, 7, 2, 4, 550, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1088 = VLD2d16wb_register 5133 { 1089, 5, 1, 4, 548, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1089 = VLD2d32 5134 { 1090, 6, 2, 4, 550, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1090 = VLD2d32wb_fixed 5135 { 1091, 7, 2, 4, 550, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1091 = VLD2d32wb_register 5136 { 1092, 5, 1, 4, 548, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1092 = VLD2d8 5137 { 1093, 6, 2, 4, 550, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1093 = VLD2d8wb_fixed 5138 { 1094, 7, 2, 4, 550, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1094 = VLD2d8wb_register 5139 { 1095, 5, 1, 4, 549, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1095 = VLD2q16 5140 { 1096, 5, 1, 4, 549, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1096 = VLD2q16Pseudo 5141 { 1097, 6, 2, 4, 551, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #1097 = VLD2q16PseudoWB_fixed 5142 { 1098, 7, 2, 4, 551, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #1098 = VLD2q16PseudoWB_register 5143 { 1099, 6, 2, 4, 551, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1099 = VLD2q16wb_fixed 5144 { 1100, 7, 2, 4, 551, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #1100 = VLD2q16wb_register 5145 { 1101, 5, 1, 4, 549, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1101 = VLD2q32 5146 { 1102, 5, 1, 4, 549, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1102 = VLD2q32Pseudo 5147 { 1103, 6, 2, 4, 551, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #1103 = VLD2q32PseudoWB_fixed 5148 { 1104, 7, 2, 4, 551, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #1104 = VLD2q32PseudoWB_register 5149 { 1105, 6, 2, 4, 551, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1105 = VLD2q32wb_fixed 5150 { 1106, 7, 2, 4, 551, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #1106 = VLD2q32wb_register 5151 { 1107, 5, 1, 4, 549, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1107 = VLD2q8 5152 { 1108, 5, 1, 4, 549, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1108 = VLD2q8Pseudo 5153 { 1109, 6, 2, 4, 551, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #1109 = VLD2q8PseudoWB_fixed 5154 { 1110, 7, 2, 4, 551, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr }, // Inst #1110 = VLD2q8PseudoWB_register 5155 { 1111, 6, 2, 4, 551, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1111 = VLD2q8wb_fixed 5156 { 1112, 7, 2, 4, 551, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #1112 = VLD2q8wb_register 5157 { 1113, 7, 3, 4, 569, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1113 = VLD3DUPd16 5158 { 1114, 5, 1, 4, 569, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1114 = VLD3DUPd16Pseudo 5159 { 1115, 7, 2, 4, 573, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1115 = VLD3DUPd16Pseudo_UPD 5160 { 1116, 9, 4, 4, 571, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1116 = VLD3DUPd16_UPD 5161 { 1117, 7, 3, 4, 569, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1117 = VLD3DUPd32 5162 { 1118, 5, 1, 4, 569, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1118 = VLD3DUPd32Pseudo 5163 { 1119, 7, 2, 4, 573, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1119 = VLD3DUPd32Pseudo_UPD 5164 { 1120, 9, 4, 4, 571, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1120 = VLD3DUPd32_UPD 5165 { 1121, 7, 3, 4, 569, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1121 = VLD3DUPd8 5166 { 1122, 5, 1, 4, 569, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1122 = VLD3DUPd8Pseudo 5167 { 1123, 7, 2, 4, 573, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1123 = VLD3DUPd8Pseudo_UPD 5168 { 1124, 9, 4, 4, 571, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1124 = VLD3DUPd8_UPD 5169 { 1125, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1125 = VLD3DUPdAsm_16 5170 { 1126, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1126 = VLD3DUPdAsm_32 5171 { 1127, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1127 = VLD3DUPdAsm_8 5172 { 1128, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1128 = VLD3DUPdWB_fixed_Asm_16 5173 { 1129, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1129 = VLD3DUPdWB_fixed_Asm_32 5174 { 1130, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1130 = VLD3DUPdWB_fixed_Asm_8 5175 { 1131, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1131 = VLD3DUPdWB_register_Asm_16 5176 { 1132, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1132 = VLD3DUPdWB_register_Asm_32 5177 { 1133, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1133 = VLD3DUPdWB_register_Asm_8 5178 { 1134, 7, 3, 4, 569, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1134 = VLD3DUPq16 5179 { 1135, 9, 4, 4, 571, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1135 = VLD3DUPq16_UPD 5180 { 1136, 7, 3, 4, 569, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1136 = VLD3DUPq32 5181 { 1137, 9, 4, 4, 571, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1137 = VLD3DUPq32_UPD 5182 { 1138, 7, 3, 4, 569, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1138 = VLD3DUPq8 5183 { 1139, 9, 4, 4, 571, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1139 = VLD3DUPq8_UPD 5184 { 1140, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1140 = VLD3DUPqAsm_16 5185 { 1141, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1141 = VLD3DUPqAsm_32 5186 { 1142, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1142 = VLD3DUPqAsm_8 5187 { 1143, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1143 = VLD3DUPqWB_fixed_Asm_16 5188 { 1144, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1144 = VLD3DUPqWB_fixed_Asm_32 5189 { 1145, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1145 = VLD3DUPqWB_fixed_Asm_8 5190 { 1146, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1146 = VLD3DUPqWB_register_Asm_16 5191 { 1147, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1147 = VLD3DUPqWB_register_Asm_32 5192 { 1148, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1148 = VLD3DUPqWB_register_Asm_8 5193 { 1149, 11, 3, 4, 570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1149 = VLD3LNd16 5194 { 1150, 7, 1, 4, 570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1150 = VLD3LNd16Pseudo 5195 { 1151, 9, 2, 4, 574, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1151 = VLD3LNd16Pseudo_UPD 5196 { 1152, 13, 4, 4, 572, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1152 = VLD3LNd16_UPD 5197 { 1153, 11, 3, 4, 570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1153 = VLD3LNd32 5198 { 1154, 7, 1, 4, 570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1154 = VLD3LNd32Pseudo 5199 { 1155, 9, 2, 4, 574, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1155 = VLD3LNd32Pseudo_UPD 5200 { 1156, 13, 4, 4, 572, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1156 = VLD3LNd32_UPD 5201 { 1157, 11, 3, 4, 570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1157 = VLD3LNd8 5202 { 1158, 7, 1, 4, 570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1158 = VLD3LNd8Pseudo 5203 { 1159, 9, 2, 4, 574, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1159 = VLD3LNd8Pseudo_UPD 5204 { 1160, 13, 4, 4, 572, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1160 = VLD3LNd8_UPD 5205 { 1161, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1161 = VLD3LNdAsm_16 5206 { 1162, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1162 = VLD3LNdAsm_32 5207 { 1163, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1163 = VLD3LNdAsm_8 5208 { 1164, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1164 = VLD3LNdWB_fixed_Asm_16 5209 { 1165, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1165 = VLD3LNdWB_fixed_Asm_32 5210 { 1166, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1166 = VLD3LNdWB_fixed_Asm_8 5211 { 1167, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1167 = VLD3LNdWB_register_Asm_16 5212 { 1168, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1168 = VLD3LNdWB_register_Asm_32 5213 { 1169, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1169 = VLD3LNdWB_register_Asm_8 5214 { 1170, 11, 3, 4, 570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1170 = VLD3LNq16 5215 { 1171, 7, 1, 4, 570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo188, -1 ,nullptr }, // Inst #1171 = VLD3LNq16Pseudo 5216 { 1172, 9, 2, 4, 574, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1172 = VLD3LNq16Pseudo_UPD 5217 { 1173, 13, 4, 4, 572, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1173 = VLD3LNq16_UPD 5218 { 1174, 11, 3, 4, 570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1174 = VLD3LNq32 5219 { 1175, 7, 1, 4, 570, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo188, -1 ,nullptr }, // Inst #1175 = VLD3LNq32Pseudo 5220 { 1176, 9, 2, 4, 574, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1176 = VLD3LNq32Pseudo_UPD 5221 { 1177, 13, 4, 4, 572, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr }, // Inst #1177 = VLD3LNq32_UPD 5222 { 1178, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1178 = VLD3LNqAsm_16 5223 { 1179, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1179 = VLD3LNqAsm_32 5224 { 1180, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1180 = VLD3LNqWB_fixed_Asm_16 5225 { 1181, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1181 = VLD3LNqWB_fixed_Asm_32 5226 { 1182, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1182 = VLD3LNqWB_register_Asm_16 5227 { 1183, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1183 = VLD3LNqWB_register_Asm_32 5228 { 1184, 7, 3, 4, 552, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1184 = VLD3d16 5229 { 1185, 5, 1, 4, 553, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1185 = VLD3d16Pseudo 5230 { 1186, 7, 2, 4, 555, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1186 = VLD3d16Pseudo_UPD 5231 { 1187, 9, 4, 4, 554, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1187 = VLD3d16_UPD 5232 { 1188, 7, 3, 4, 552, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1188 = VLD3d32 5233 { 1189, 5, 1, 4, 553, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1189 = VLD3d32Pseudo 5234 { 1190, 7, 2, 4, 555, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1190 = VLD3d32Pseudo_UPD 5235 { 1191, 9, 4, 4, 554, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1191 = VLD3d32_UPD 5236 { 1192, 7, 3, 4, 552, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1192 = VLD3d8 5237 { 1193, 5, 1, 4, 553, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1193 = VLD3d8Pseudo 5238 { 1194, 7, 2, 4, 555, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1194 = VLD3d8Pseudo_UPD 5239 { 1195, 9, 4, 4, 554, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1195 = VLD3d8_UPD 5240 { 1196, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1196 = VLD3dAsm_16 5241 { 1197, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1197 = VLD3dAsm_32 5242 { 1198, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1198 = VLD3dAsm_8 5243 { 1199, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1199 = VLD3dWB_fixed_Asm_16 5244 { 1200, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1200 = VLD3dWB_fixed_Asm_32 5245 { 1201, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1201 = VLD3dWB_fixed_Asm_8 5246 { 1202, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1202 = VLD3dWB_register_Asm_16 5247 { 1203, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1203 = VLD3dWB_register_Asm_32 5248 { 1204, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1204 = VLD3dWB_register_Asm_8 5249 { 1205, 7, 3, 4, 552, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1205 = VLD3q16 5250 { 1206, 8, 2, 4, 555, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1206 = VLD3q16Pseudo_UPD 5251 { 1207, 9, 4, 4, 554, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1207 = VLD3q16_UPD 5252 { 1208, 6, 1, 4, 553, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1208 = VLD3q16oddPseudo 5253 { 1209, 8, 2, 4, 555, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1209 = VLD3q16oddPseudo_UPD 5254 { 1210, 7, 3, 4, 552, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1210 = VLD3q32 5255 { 1211, 8, 2, 4, 555, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1211 = VLD3q32Pseudo_UPD 5256 { 1212, 9, 4, 4, 554, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1212 = VLD3q32_UPD 5257 { 1213, 6, 1, 4, 553, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1213 = VLD3q32oddPseudo 5258 { 1214, 8, 2, 4, 555, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1214 = VLD3q32oddPseudo_UPD 5259 { 1215, 7, 3, 4, 552, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #1215 = VLD3q8 5260 { 1216, 8, 2, 4, 555, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1216 = VLD3q8Pseudo_UPD 5261 { 1217, 9, 4, 4, 554, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #1217 = VLD3q8_UPD 5262 { 1218, 6, 1, 4, 553, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1218 = VLD3q8oddPseudo 5263 { 1219, 8, 2, 4, 555, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1219 = VLD3q8oddPseudo_UPD 5264 { 1220, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1220 = VLD3qAsm_16 5265 { 1221, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1221 = VLD3qAsm_32 5266 { 1222, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1222 = VLD3qAsm_8 5267 { 1223, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1223 = VLD3qWB_fixed_Asm_16 5268 { 1224, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1224 = VLD3qWB_fixed_Asm_32 5269 { 1225, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1225 = VLD3qWB_fixed_Asm_8 5270 { 1226, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1226 = VLD3qWB_register_Asm_16 5271 { 1227, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1227 = VLD3qWB_register_Asm_32 5272 { 1228, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1228 = VLD3qWB_register_Asm_8 5273 { 1229, 8, 4, 4, 575, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1229 = VLD4DUPd16 5274 { 1230, 5, 1, 4, 575, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1230 = VLD4DUPd16Pseudo 5275 { 1231, 7, 2, 4, 579, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1231 = VLD4DUPd16Pseudo_UPD 5276 { 1232, 10, 5, 4, 577, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1232 = VLD4DUPd16_UPD 5277 { 1233, 8, 4, 4, 575, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1233 = VLD4DUPd32 5278 { 1234, 5, 1, 4, 575, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1234 = VLD4DUPd32Pseudo 5279 { 1235, 7, 2, 4, 579, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1235 = VLD4DUPd32Pseudo_UPD 5280 { 1236, 10, 5, 4, 577, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1236 = VLD4DUPd32_UPD 5281 { 1237, 8, 4, 4, 575, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1237 = VLD4DUPd8 5282 { 1238, 5, 1, 4, 575, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1238 = VLD4DUPd8Pseudo 5283 { 1239, 7, 2, 4, 579, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1239 = VLD4DUPd8Pseudo_UPD 5284 { 1240, 10, 5, 4, 577, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1240 = VLD4DUPd8_UPD 5285 { 1241, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1241 = VLD4DUPdAsm_16 5286 { 1242, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1242 = VLD4DUPdAsm_32 5287 { 1243, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1243 = VLD4DUPdAsm_8 5288 { 1244, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1244 = VLD4DUPdWB_fixed_Asm_16 5289 { 1245, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1245 = VLD4DUPdWB_fixed_Asm_32 5290 { 1246, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1246 = VLD4DUPdWB_fixed_Asm_8 5291 { 1247, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1247 = VLD4DUPdWB_register_Asm_16 5292 { 1248, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1248 = VLD4DUPdWB_register_Asm_32 5293 { 1249, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1249 = VLD4DUPdWB_register_Asm_8 5294 { 1250, 8, 4, 4, 575, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1250 = VLD4DUPq16 5295 { 1251, 10, 5, 4, 577, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1251 = VLD4DUPq16_UPD 5296 { 1252, 8, 4, 4, 575, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1252 = VLD4DUPq32 5297 { 1253, 10, 5, 4, 577, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1253 = VLD4DUPq32_UPD 5298 { 1254, 8, 4, 4, 575, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1254 = VLD4DUPq8 5299 { 1255, 10, 5, 4, 577, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1255 = VLD4DUPq8_UPD 5300 { 1256, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1256 = VLD4DUPqAsm_16 5301 { 1257, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1257 = VLD4DUPqAsm_32 5302 { 1258, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1258 = VLD4DUPqAsm_8 5303 { 1259, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1259 = VLD4DUPqWB_fixed_Asm_16 5304 { 1260, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1260 = VLD4DUPqWB_fixed_Asm_32 5305 { 1261, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1261 = VLD4DUPqWB_fixed_Asm_8 5306 { 1262, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1262 = VLD4DUPqWB_register_Asm_16 5307 { 1263, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1263 = VLD4DUPqWB_register_Asm_32 5308 { 1264, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1264 = VLD4DUPqWB_register_Asm_8 5309 { 1265, 13, 4, 4, 576, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1265 = VLD4LNd16 5310 { 1266, 7, 1, 4, 576, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1266 = VLD4LNd16Pseudo 5311 { 1267, 9, 2, 4, 580, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1267 = VLD4LNd16Pseudo_UPD 5312 { 1268, 15, 5, 4, 578, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1268 = VLD4LNd16_UPD 5313 { 1269, 13, 4, 4, 576, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1269 = VLD4LNd32 5314 { 1270, 7, 1, 4, 576, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1270 = VLD4LNd32Pseudo 5315 { 1271, 9, 2, 4, 580, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1271 = VLD4LNd32Pseudo_UPD 5316 { 1272, 15, 5, 4, 578, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1272 = VLD4LNd32_UPD 5317 { 1273, 13, 4, 4, 576, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1273 = VLD4LNd8 5318 { 1274, 7, 1, 4, 576, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #1274 = VLD4LNd8Pseudo 5319 { 1275, 9, 2, 4, 580, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr }, // Inst #1275 = VLD4LNd8Pseudo_UPD 5320 { 1276, 15, 5, 4, 578, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1276 = VLD4LNd8_UPD 5321 { 1277, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1277 = VLD4LNdAsm_16 5322 { 1278, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1278 = VLD4LNdAsm_32 5323 { 1279, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1279 = VLD4LNdAsm_8 5324 { 1280, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1280 = VLD4LNdWB_fixed_Asm_16 5325 { 1281, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1281 = VLD4LNdWB_fixed_Asm_32 5326 { 1282, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1282 = VLD4LNdWB_fixed_Asm_8 5327 { 1283, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1283 = VLD4LNdWB_register_Asm_16 5328 { 1284, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1284 = VLD4LNdWB_register_Asm_32 5329 { 1285, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1285 = VLD4LNdWB_register_Asm_8 5330 { 1286, 13, 4, 4, 576, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1286 = VLD4LNq16 5331 { 1287, 7, 1, 4, 576, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo188, -1 ,nullptr }, // Inst #1287 = VLD4LNq16Pseudo 5332 { 1288, 9, 2, 4, 580, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1288 = VLD4LNq16Pseudo_UPD 5333 { 1289, 15, 5, 4, 578, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1289 = VLD4LNq16_UPD 5334 { 1290, 13, 4, 4, 576, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1290 = VLD4LNq32 5335 { 1291, 7, 1, 4, 576, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo188, -1 ,nullptr }, // Inst #1291 = VLD4LNq32Pseudo 5336 { 1292, 9, 2, 4, 580, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr }, // Inst #1292 = VLD4LNq32Pseudo_UPD 5337 { 1293, 15, 5, 4, 578, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1293 = VLD4LNq32_UPD 5338 { 1294, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1294 = VLD4LNqAsm_16 5339 { 1295, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1295 = VLD4LNqAsm_32 5340 { 1296, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1296 = VLD4LNqWB_fixed_Asm_16 5341 { 1297, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1297 = VLD4LNqWB_fixed_Asm_32 5342 { 1298, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1298 = VLD4LNqWB_register_Asm_16 5343 { 1299, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #1299 = VLD4LNqWB_register_Asm_32 5344 { 1300, 8, 4, 4, 556, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1300 = VLD4d16 5345 { 1301, 5, 1, 4, 557, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1301 = VLD4d16Pseudo 5346 { 1302, 7, 2, 4, 559, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1302 = VLD4d16Pseudo_UPD 5347 { 1303, 10, 5, 4, 558, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1303 = VLD4d16_UPD 5348 { 1304, 8, 4, 4, 556, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1304 = VLD4d32 5349 { 1305, 5, 1, 4, 557, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1305 = VLD4d32Pseudo 5350 { 1306, 7, 2, 4, 559, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1306 = VLD4d32Pseudo_UPD 5351 { 1307, 10, 5, 4, 558, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1307 = VLD4d32_UPD 5352 { 1308, 8, 4, 4, 556, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1308 = VLD4d8 5353 { 1309, 5, 1, 4, 557, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1309 = VLD4d8Pseudo 5354 { 1310, 7, 2, 4, 559, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #1310 = VLD4d8Pseudo_UPD 5355 { 1311, 10, 5, 4, 558, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1311 = VLD4d8_UPD 5356 { 1312, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1312 = VLD4dAsm_16 5357 { 1313, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1313 = VLD4dAsm_32 5358 { 1314, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1314 = VLD4dAsm_8 5359 { 1315, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1315 = VLD4dWB_fixed_Asm_16 5360 { 1316, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1316 = VLD4dWB_fixed_Asm_32 5361 { 1317, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1317 = VLD4dWB_fixed_Asm_8 5362 { 1318, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1318 = VLD4dWB_register_Asm_16 5363 { 1319, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1319 = VLD4dWB_register_Asm_32 5364 { 1320, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1320 = VLD4dWB_register_Asm_8 5365 { 1321, 8, 4, 4, 556, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1321 = VLD4q16 5366 { 1322, 8, 2, 4, 559, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1322 = VLD4q16Pseudo_UPD 5367 { 1323, 10, 5, 4, 558, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1323 = VLD4q16_UPD 5368 { 1324, 6, 1, 4, 557, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1324 = VLD4q16oddPseudo 5369 { 1325, 8, 2, 4, 559, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1325 = VLD4q16oddPseudo_UPD 5370 { 1326, 8, 4, 4, 556, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1326 = VLD4q32 5371 { 1327, 8, 2, 4, 559, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1327 = VLD4q32Pseudo_UPD 5372 { 1328, 10, 5, 4, 558, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1328 = VLD4q32_UPD 5373 { 1329, 6, 1, 4, 557, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1329 = VLD4q32oddPseudo 5374 { 1330, 8, 2, 4, 559, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1330 = VLD4q32oddPseudo_UPD 5375 { 1331, 8, 4, 4, 556, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #1331 = VLD4q8 5376 { 1332, 8, 2, 4, 559, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1332 = VLD4q8Pseudo_UPD 5377 { 1333, 10, 5, 4, 558, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1333 = VLD4q8_UPD 5378 { 1334, 6, 1, 4, 557, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1334 = VLD4q8oddPseudo 5379 { 1335, 8, 2, 4, 559, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr }, // Inst #1335 = VLD4q8oddPseudo_UPD 5380 { 1336, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1336 = VLD4qAsm_16 5381 { 1337, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1337 = VLD4qAsm_32 5382 { 1338, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1338 = VLD4qAsm_8 5383 { 1339, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1339 = VLD4qWB_fixed_Asm_16 5384 { 1340, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1340 = VLD4qWB_fixed_Asm_32 5385 { 1341, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1341 = VLD4qWB_fixed_Asm_8 5386 { 1342, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1342 = VLD4qWB_register_Asm_16 5387 { 1343, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1343 = VLD4qWB_register_Asm_32 5388 { 1344, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #1344 = VLD4qWB_register_Asm_8 5389 { 1345, 5, 1, 4, 537, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #1345 = VLDMDDB_UPD 5390 { 1346, 4, 0, 4, 536, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x8b84ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #1346 = VLDMDIA 5391 { 1347, 5, 1, 4, 537, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #1347 = VLDMDIA_UPD 5392 { 1348, 4, 1, 4, 534, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0x18004ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1348 = VLDMQIA 5393 { 1349, 5, 1, 4, 537, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #1349 = VLDMSDB_UPD 5394 { 1350, 4, 0, 4, 536, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x18b84ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #1350 = VLDMSIA 5395 { 1351, 5, 1, 4, 537, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #1351 = VLDMSIA_UPD 5396 { 1352, 5, 1, 4, 530, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x18b05ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #1352 = VLDRD 5397 { 1353, 5, 1, 4, 161, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x18b05ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1353 = VLDRH 5398 { 1354, 5, 1, 4, 531, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x18b05ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #1354 = VLDRS 5399 { 1355, 3, 0, 4, 159, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b84ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1355 = VLLDM 5400 { 1356, 3, 0, 4, 163, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b84ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1356 = VLSTM 5401 { 1357, 3, 1, 4, 463, 0, 0x8800ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1357 = VMAXNMD 5402 { 1358, 3, 1, 4, 463, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1358 = VMAXNMH 5403 { 1359, 3, 1, 4, 463, 0, 0x11280ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1359 = VMAXNMNDf 5404 { 1360, 3, 1, 4, 463, 0, 0x11280ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1360 = VMAXNMNDh 5405 { 1361, 3, 1, 4, 463, 0, 0x11280ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1361 = VMAXNMNQf 5406 { 1362, 3, 1, 4, 463, 0, 0x11280ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1362 = VMAXNMNQh 5407 { 1363, 3, 1, 4, 463, 0, 0x8800ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1363 = VMAXNMS 5408 { 1364, 5, 1, 4, 459, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1364 = VMAXfd 5409 { 1365, 5, 1, 4, 460, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1365 = VMAXfq 5410 { 1366, 5, 1, 4, 459, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1366 = VMAXhd 5411 { 1367, 5, 1, 4, 460, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1367 = VMAXhq 5412 { 1368, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1368 = VMAXsv16i8 5413 { 1369, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1369 = VMAXsv2i32 5414 { 1370, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1370 = VMAXsv4i16 5415 { 1371, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1371 = VMAXsv4i32 5416 { 1372, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1372 = VMAXsv8i16 5417 { 1373, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1373 = VMAXsv8i8 5418 { 1374, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1374 = VMAXuv16i8 5419 { 1375, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1375 = VMAXuv2i32 5420 { 1376, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1376 = VMAXuv4i16 5421 { 1377, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1377 = VMAXuv4i32 5422 { 1378, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1378 = VMAXuv8i16 5423 { 1379, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1379 = VMAXuv8i8 5424 { 1380, 3, 1, 4, 463, 0, 0x8800ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1380 = VMINNMD 5425 { 1381, 3, 1, 4, 463, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1381 = VMINNMH 5426 { 1382, 3, 1, 4, 463, 0, 0x11280ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1382 = VMINNMNDf 5427 { 1383, 3, 1, 4, 463, 0, 0x11280ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1383 = VMINNMNDh 5428 { 1384, 3, 1, 4, 463, 0, 0x11280ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1384 = VMINNMNQf 5429 { 1385, 3, 1, 4, 463, 0, 0x11280ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1385 = VMINNMNQh 5430 { 1386, 3, 1, 4, 463, 0, 0x8800ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1386 = VMINNMS 5431 { 1387, 5, 1, 4, 459, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1387 = VMINfd 5432 { 1388, 5, 1, 4, 460, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1388 = VMINfq 5433 { 1389, 5, 1, 4, 459, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1389 = VMINhd 5434 { 1390, 5, 1, 4, 460, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1390 = VMINhq 5435 { 1391, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1391 = VMINsv16i8 5436 { 1392, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1392 = VMINsv2i32 5437 { 1393, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1393 = VMINsv4i16 5438 { 1394, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1394 = VMINsv4i32 5439 { 1395, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1395 = VMINsv8i16 5440 { 1396, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1396 = VMINsv8i8 5441 { 1397, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1397 = VMINuv16i8 5442 { 1398, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1398 = VMINuv2i32 5443 { 1399, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1399 = VMINuv4i16 5444 { 1400, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1400 = VMINuv4i32 5445 { 1401, 5, 1, 4, 458, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1401 = VMINuv8i16 5446 { 1402, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1402 = VMINuv8i8 5447 { 1403, 6, 1, 4, 482, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1403 = VMLAD 5448 { 1404, 6, 1, 4, 483, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #1404 = VMLAH 5449 { 1405, 7, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr }, // Inst #1405 = VMLALslsv2i32 5450 { 1406, 7, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr }, // Inst #1406 = VMLALslsv4i16 5451 { 1407, 7, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr }, // Inst #1407 = VMLALsluv2i32 5452 { 1408, 7, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr }, // Inst #1408 = VMLALsluv4i16 5453 { 1409, 6, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1409 = VMLALsv2i64 5454 { 1410, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1410 = VMLALsv4i32 5455 { 1411, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1411 = VMLALsv8i16 5456 { 1412, 6, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1412 = VMLALuv2i64 5457 { 1413, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1413 = VMLALuv4i32 5458 { 1414, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1414 = VMLALuv8i16 5459 { 1415, 6, 1, 4, 486, 0|(1ULL<<MCID::Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #1415 = VMLAS 5460 { 1416, 6, 1, 4, 487, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1416 = VMLAfd 5461 { 1417, 6, 1, 4, 488, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1417 = VMLAfq 5462 { 1418, 6, 1, 4, 487, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1418 = VMLAhd 5463 { 1419, 6, 1, 4, 488, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1419 = VMLAhq 5464 { 1420, 7, 1, 4, 487, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1420 = VMLAslfd 5465 { 1421, 7, 1, 4, 488, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1421 = VMLAslfq 5466 { 1422, 7, 1, 4, 487, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1422 = VMLAslhd 5467 { 1423, 7, 1, 4, 488, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1423 = VMLAslhq 5468 { 1424, 7, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1424 = VMLAslv2i32 5469 { 1425, 7, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1425 = VMLAslv4i16 5470 { 1426, 7, 1, 4, 489, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1426 = VMLAslv4i32 5471 { 1427, 7, 1, 4, 490, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1427 = VMLAslv8i16 5472 { 1428, 6, 1, 4, 490, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1428 = VMLAv16i8 5473 { 1429, 6, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1429 = VMLAv2i32 5474 { 1430, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1430 = VMLAv4i16 5475 { 1431, 6, 1, 4, 489, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1431 = VMLAv4i32 5476 { 1432, 6, 1, 4, 490, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1432 = VMLAv8i16 5477 { 1433, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1433 = VMLAv8i8 5478 { 1434, 6, 1, 4, 482, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1434 = VMLSD 5479 { 1435, 6, 1, 4, 483, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #1435 = VMLSH 5480 { 1436, 7, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr }, // Inst #1436 = VMLSLslsv2i32 5481 { 1437, 7, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr }, // Inst #1437 = VMLSLslsv4i16 5482 { 1438, 7, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr }, // Inst #1438 = VMLSLsluv2i32 5483 { 1439, 7, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr }, // Inst #1439 = VMLSLsluv4i16 5484 { 1440, 6, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1440 = VMLSLsv2i64 5485 { 1441, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1441 = VMLSLsv4i32 5486 { 1442, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1442 = VMLSLsv8i16 5487 { 1443, 6, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1443 = VMLSLuv2i64 5488 { 1444, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1444 = VMLSLuv4i32 5489 { 1445, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1445 = VMLSLuv8i16 5490 { 1446, 6, 1, 4, 486, 0|(1ULL<<MCID::Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #1446 = VMLSS 5491 { 1447, 6, 1, 4, 487, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1447 = VMLSfd 5492 { 1448, 6, 1, 4, 488, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1448 = VMLSfq 5493 { 1449, 6, 1, 4, 487, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1449 = VMLShd 5494 { 1450, 6, 1, 4, 488, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1450 = VMLShq 5495 { 1451, 7, 1, 4, 487, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1451 = VMLSslfd 5496 { 1452, 7, 1, 4, 488, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1452 = VMLSslfq 5497 { 1453, 7, 1, 4, 487, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1453 = VMLSslhd 5498 { 1454, 7, 1, 4, 488, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1454 = VMLSslhq 5499 { 1455, 7, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1455 = VMLSslv2i32 5500 { 1456, 7, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1456 = VMLSslv4i16 5501 { 1457, 7, 1, 4, 489, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1457 = VMLSslv4i32 5502 { 1458, 7, 1, 4, 490, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1458 = VMLSslv8i16 5503 { 1459, 6, 1, 4, 490, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1459 = VMLSv16i8 5504 { 1460, 6, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1460 = VMLSv2i32 5505 { 1461, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1461 = VMLSv4i16 5506 { 1462, 6, 1, 4, 489, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1462 = VMLSv4i32 5507 { 1463, 6, 1, 4, 490, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1463 = VMLSv8i16 5508 { 1464, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1464 = VMLSv8i8 5509 { 1465, 4, 1, 4, 509, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1465 = VMOVD 5510 { 1466, 1, 1, 4, 103, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1466 = VMOVD0 5511 { 1467, 5, 1, 4, 523, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::RegSequence), 0x18a80ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1467 = VMOVDRR 5512 { 1468, 5, 1, 0, 509, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1468 = VMOVDcc 5513 { 1469, 2, 1, 4, 22, 0, 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1469 = VMOVH 5514 { 1470, 4, 1, 4, 174, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8a00ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1470 = VMOVHR 5515 { 1471, 4, 1, 4, 513, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #1471 = VMOVLsv2i64 5516 { 1472, 4, 1, 4, 513, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #1472 = VMOVLsv4i32 5517 { 1473, 4, 1, 4, 513, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #1473 = VMOVLsv8i16 5518 { 1474, 4, 1, 4, 513, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #1474 = VMOVLuv2i64 5519 { 1475, 4, 1, 4, 513, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #1475 = VMOVLuv4i32 5520 { 1476, 4, 1, 4, 513, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #1476 = VMOVLuv8i16 5521 { 1477, 4, 1, 4, 514, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1477 = VMOVNv2i32 5522 { 1478, 4, 1, 4, 514, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1478 = VMOVNv4i16 5523 { 1479, 4, 1, 4, 514, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1479 = VMOVNv8i8 5524 { 1480, 1, 1, 4, 103, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo212, -1 ,nullptr }, // Inst #1480 = VMOVQ0 5525 { 1481, 4, 1, 4, 177, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8900ULL, nullptr, nullptr, OperandInfo213, -1 ,nullptr }, // Inst #1481 = VMOVRH 5526 { 1482, 5, 2, 4, 522, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtractSubreg), 0x18980ULL, nullptr, nullptr, OperandInfo214, -1 ,nullptr }, // Inst #1482 = VMOVRRD 5527 { 1483, 6, 2, 4, 522, 0|(1ULL<<MCID::Predicable), 0x18980ULL, nullptr, nullptr, OperandInfo215, -1 ,nullptr }, // Inst #1483 = VMOVRRS 5528 { 1484, 4, 1, 4, 519, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::Predicable), 0x18900ULL, nullptr, nullptr, OperandInfo213, -1 ,nullptr }, // Inst #1484 = VMOVRS 5529 { 1485, 4, 1, 4, 510, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #1485 = VMOVS 5530 { 1486, 4, 1, 4, 520, 0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::Predicable), 0x18a00ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1486 = VMOVSR 5531 { 1487, 6, 2, 4, 524, 0|(1ULL<<MCID::Predicable), 0x18a80ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1487 = VMOVSRR 5532 { 1488, 5, 1, 0, 510, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1488 = VMOVScc 5533 { 1489, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1489 = VMOVv16i8 5534 { 1490, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #1490 = VMOVv1i64 5535 { 1491, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #1491 = VMOVv2f32 5536 { 1492, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #1492 = VMOVv2i32 5537 { 1493, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1493 = VMOVv2i64 5538 { 1494, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1494 = VMOVv4f32 5539 { 1495, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #1495 = VMOVv4i16 5540 { 1496, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1496 = VMOVv4i32 5541 { 1497, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1497 = VMOVv8i16 5542 { 1498, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x10f80ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #1498 = VMOVv8i8 5543 { 1499, 3, 1, 4, 527, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #1499 = VMRS 5544 { 1500, 3, 1, 4, 527, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #1500 = VMRS_FPEXC 5545 { 1501, 3, 1, 4, 527, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #1501 = VMRS_FPINST 5546 { 1502, 3, 1, 4, 527, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #1502 = VMRS_FPINST2 5547 { 1503, 3, 1, 4, 527, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #1503 = VMRS_FPSID 5548 { 1504, 3, 1, 4, 527, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #1504 = VMRS_MVFR0 5549 { 1505, 3, 1, 4, 527, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #1505 = VMRS_MVFR1 5550 { 1506, 3, 1, 4, 527, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #1506 = VMRS_MVFR2 5551 { 1507, 3, 0, 4, 528, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList10, OperandInfo35, -1 ,nullptr }, // Inst #1507 = VMSR 5552 { 1508, 3, 0, 4, 528, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList10, OperandInfo35, -1 ,nullptr }, // Inst #1508 = VMSR_FPEXC 5553 { 1509, 3, 0, 4, 528, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList10, OperandInfo35, -1 ,nullptr }, // Inst #1509 = VMSR_FPINST 5554 { 1510, 3, 0, 4, 528, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList10, OperandInfo35, -1 ,nullptr }, // Inst #1510 = VMSR_FPINST2 5555 { 1511, 3, 0, 4, 528, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList10, OperandInfo35, -1 ,nullptr }, // Inst #1511 = VMSR_FPSID 5556 { 1512, 5, 1, 4, 478, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1512 = VMULD 5557 { 1513, 5, 1, 4, 180, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #1513 = VMULH 5558 { 1514, 3, 1, 4, 468, 0, 0x11280ULL, nullptr, nullptr, OperandInfo219, -1 ,nullptr }, // Inst #1514 = VMULLp64 5559 { 1515, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1515 = VMULLp8 5560 { 1516, 6, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr }, // Inst #1516 = VMULLslsv2i32 5561 { 1517, 6, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1517 = VMULLslsv4i16 5562 { 1518, 6, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr }, // Inst #1518 = VMULLsluv2i32 5563 { 1519, 6, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1519 = VMULLsluv4i16 5564 { 1520, 5, 1, 4, 470, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1520 = VMULLsv2i64 5565 { 1521, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1521 = VMULLsv4i32 5566 { 1522, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1522 = VMULLsv8i16 5567 { 1523, 5, 1, 4, 470, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1523 = VMULLuv2i64 5568 { 1524, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1524 = VMULLuv4i32 5569 { 1525, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1525 = VMULLuv8i16 5570 { 1526, 5, 1, 4, 471, 0|(1ULL<<MCID::Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #1526 = VMULS 5571 { 1527, 5, 1, 4, 472, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1527 = VMULfd 5572 { 1528, 5, 1, 4, 473, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1528 = VMULfq 5573 { 1529, 5, 1, 4, 184, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1529 = VMULhd 5574 { 1530, 5, 1, 4, 185, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1530 = VMULhq 5575 { 1531, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1531 = VMULpd 5576 { 1532, 5, 1, 4, 474, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1532 = VMULpq 5577 { 1533, 6, 1, 4, 475, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1533 = VMULslfd 5578 { 1534, 6, 1, 4, 476, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1534 = VMULslfq 5579 { 1535, 6, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1535 = VMULslhd 5580 { 1536, 6, 1, 4, 474, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1536 = VMULslhq 5581 { 1537, 6, 1, 4, 470, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1537 = VMULslv2i32 5582 { 1538, 6, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1538 = VMULslv4i16 5583 { 1539, 6, 1, 4, 477, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1539 = VMULslv4i32 5584 { 1540, 6, 1, 4, 474, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1540 = VMULslv8i16 5585 { 1541, 5, 1, 4, 474, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1541 = VMULv16i8 5586 { 1542, 5, 1, 4, 470, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1542 = VMULv2i32 5587 { 1543, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1543 = VMULv4i16 5588 { 1544, 5, 1, 4, 477, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1544 = VMULv4i32 5589 { 1545, 5, 1, 4, 474, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1545 = VMULv8i16 5590 { 1546, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1546 = VMULv8i8 5591 { 1547, 4, 1, 4, 512, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1547 = VMVNd 5592 { 1548, 4, 1, 4, 512, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1548 = VMVNq 5593 { 1549, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #1549 = VMVNv2i32 5594 { 1550, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #1550 = VMVNv4i16 5595 { 1551, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1551 = VMVNv4i32 5596 { 1552, 4, 1, 4, 511, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1552 = VMVNv8i16 5597 { 1553, 4, 1, 4, 454, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1553 = VNEGD 5598 { 1554, 4, 1, 4, 22, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #1554 = VNEGH 5599 { 1555, 4, 1, 4, 455, 0|(1ULL<<MCID::Predicable), 0x28780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #1555 = VNEGS 5600 { 1556, 4, 1, 4, 407, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1556 = VNEGf32q 5601 { 1557, 4, 1, 4, 408, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1557 = VNEGfd 5602 { 1558, 4, 1, 4, 91, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1558 = VNEGhd 5603 { 1559, 4, 1, 4, 92, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1559 = VNEGhq 5604 { 1560, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1560 = VNEGs16d 5605 { 1561, 4, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1561 = VNEGs16q 5606 { 1562, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1562 = VNEGs32d 5607 { 1563, 4, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1563 = VNEGs32q 5608 { 1564, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1564 = VNEGs8d 5609 { 1565, 4, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1565 = VNEGs8q 5610 { 1566, 6, 1, 4, 482, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1566 = VNMLAD 5611 { 1567, 6, 1, 4, 483, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #1567 = VNMLAH 5612 { 1568, 6, 1, 4, 486, 0|(1ULL<<MCID::Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #1568 = VNMLAS 5613 { 1569, 6, 1, 4, 482, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1569 = VNMLSD 5614 { 1570, 6, 1, 4, 483, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #1570 = VNMLSH 5615 { 1571, 6, 1, 4, 486, 0|(1ULL<<MCID::Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #1571 = VNMLSS 5616 { 1572, 5, 1, 4, 478, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1572 = VNMULD 5617 { 1573, 5, 1, 4, 180, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #1573 = VNMULH 5618 { 1574, 5, 1, 4, 471, 0|(1ULL<<MCID::Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #1574 = VNMULS 5619 { 1575, 5, 1, 4, 399, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1575 = VORNd 5620 { 1576, 5, 1, 4, 398, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1576 = VORNq 5621 { 1577, 5, 1, 4, 399, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1577 = VORRd 5622 { 1578, 5, 1, 4, 400, 0|(1ULL<<MCID::Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #1578 = VORRiv2i32 5623 { 1579, 5, 1, 4, 400, 0|(1ULL<<MCID::Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #1579 = VORRiv4i16 5624 { 1580, 5, 1, 4, 400, 0|(1ULL<<MCID::Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #1580 = VORRiv4i32 5625 { 1581, 5, 1, 4, 400, 0|(1ULL<<MCID::Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #1581 = VORRiv8i16 5626 { 1582, 5, 1, 4, 398, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1582 = VORRq 5627 { 1583, 5, 1, 4, 428, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1583 = VPADALsv16i8 5628 { 1584, 5, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1584 = VPADALsv2i32 5629 { 1585, 5, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1585 = VPADALsv4i16 5630 { 1586, 5, 1, 4, 428, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1586 = VPADALsv4i32 5631 { 1587, 5, 1, 4, 428, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1587 = VPADALsv8i16 5632 { 1588, 5, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1588 = VPADALsv8i8 5633 { 1589, 5, 1, 4, 428, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1589 = VPADALuv16i8 5634 { 1590, 5, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1590 = VPADALuv2i32 5635 { 1591, 5, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1591 = VPADALuv4i16 5636 { 1592, 5, 1, 4, 428, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1592 = VPADALuv4i32 5637 { 1593, 5, 1, 4, 428, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1593 = VPADALuv8i16 5638 { 1594, 5, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1594 = VPADALuv8i8 5639 { 1595, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1595 = VPADDLsv16i8 5640 { 1596, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1596 = VPADDLsv2i32 5641 { 1597, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1597 = VPADDLsv4i16 5642 { 1598, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1598 = VPADDLsv4i32 5643 { 1599, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1599 = VPADDLsv8i16 5644 { 1600, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1600 = VPADDLsv8i8 5645 { 1601, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1601 = VPADDLuv16i8 5646 { 1602, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1602 = VPADDLuv2i32 5647 { 1603, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1603 = VPADDLuv4i16 5648 { 1604, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1604 = VPADDLuv4i32 5649 { 1605, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1605 = VPADDLuv8i16 5650 { 1606, 4, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1606 = VPADDLuv8i8 5651 { 1607, 5, 1, 4, 464, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1607 = VPADDf 5652 { 1608, 5, 1, 4, 191, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1608 = VPADDh 5653 { 1609, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1609 = VPADDi16 5654 { 1610, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1610 = VPADDi32 5655 { 1611, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1611 = VPADDi8 5656 { 1612, 5, 1, 4, 464, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1612 = VPMAXf 5657 { 1613, 5, 1, 4, 464, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1613 = VPMAXh 5658 { 1614, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1614 = VPMAXs16 5659 { 1615, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1615 = VPMAXs32 5660 { 1616, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1616 = VPMAXs8 5661 { 1617, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1617 = VPMAXu16 5662 { 1618, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1618 = VPMAXu32 5663 { 1619, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1619 = VPMAXu8 5664 { 1620, 5, 1, 4, 464, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1620 = VPMINf 5665 { 1621, 5, 1, 4, 464, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1621 = VPMINh 5666 { 1622, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1622 = VPMINs16 5667 { 1623, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1623 = VPMINs32 5668 { 1624, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1624 = VPMINs8 5669 { 1625, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1625 = VPMINu16 5670 { 1626, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1626 = VPMINu32 5671 { 1627, 5, 1, 4, 461, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1627 = VPMINu8 5672 { 1628, 4, 1, 4, 430, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1628 = VQABSv16i8 5673 { 1629, 4, 1, 4, 431, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1629 = VQABSv2i32 5674 { 1630, 4, 1, 4, 431, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1630 = VQABSv4i16 5675 { 1631, 4, 1, 4, 430, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1631 = VQABSv4i32 5676 { 1632, 4, 1, 4, 430, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1632 = VQABSv8i16 5677 { 1633, 4, 1, 4, 431, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1633 = VQABSv8i8 5678 { 1634, 5, 1, 4, 432, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1634 = VQADDsv16i8 5679 { 1635, 5, 1, 4, 433, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1635 = VQADDsv1i64 5680 { 1636, 5, 1, 4, 433, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1636 = VQADDsv2i32 5681 { 1637, 5, 1, 4, 432, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1637 = VQADDsv2i64 5682 { 1638, 5, 1, 4, 433, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1638 = VQADDsv4i16 5683 { 1639, 5, 1, 4, 432, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1639 = VQADDsv4i32 5684 { 1640, 5, 1, 4, 432, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1640 = VQADDsv8i16 5685 { 1641, 5, 1, 4, 433, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1641 = VQADDsv8i8 5686 { 1642, 5, 1, 4, 432, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1642 = VQADDuv16i8 5687 { 1643, 5, 1, 4, 433, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1643 = VQADDuv1i64 5688 { 1644, 5, 1, 4, 433, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1644 = VQADDuv2i32 5689 { 1645, 5, 1, 4, 432, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1645 = VQADDuv2i64 5690 { 1646, 5, 1, 4, 433, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1646 = VQADDuv4i16 5691 { 1647, 5, 1, 4, 432, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1647 = VQADDuv4i32 5692 { 1648, 5, 1, 4, 432, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1648 = VQADDuv8i16 5693 { 1649, 5, 1, 4, 433, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1649 = VQADDuv8i8 5694 { 1650, 7, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr }, // Inst #1650 = VQDMLALslv2i32 5695 { 1651, 7, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr }, // Inst #1651 = VQDMLALslv4i16 5696 { 1652, 6, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1652 = VQDMLALv2i64 5697 { 1653, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1653 = VQDMLALv4i32 5698 { 1654, 7, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr }, // Inst #1654 = VQDMLSLslv2i32 5699 { 1655, 7, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr }, // Inst #1655 = VQDMLSLslv4i16 5700 { 1656, 6, 1, 4, 484, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1656 = VQDMLSLv2i64 5701 { 1657, 6, 1, 4, 485, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1657 = VQDMLSLv4i32 5702 { 1658, 6, 1, 4, 470, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1658 = VQDMULHslv2i32 5703 { 1659, 6, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1659 = VQDMULHslv4i16 5704 { 1660, 6, 1, 4, 477, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1660 = VQDMULHslv4i32 5705 { 1661, 6, 1, 4, 474, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1661 = VQDMULHslv8i16 5706 { 1662, 5, 1, 4, 470, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1662 = VQDMULHv2i32 5707 { 1663, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1663 = VQDMULHv4i16 5708 { 1664, 5, 1, 4, 477, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1664 = VQDMULHv4i32 5709 { 1665, 5, 1, 4, 474, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1665 = VQDMULHv8i16 5710 { 1666, 6, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr }, // Inst #1666 = VQDMULLslv2i32 5711 { 1667, 6, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1667 = VQDMULLslv4i16 5712 { 1668, 5, 1, 4, 470, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1668 = VQDMULLv2i64 5713 { 1669, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1669 = VQDMULLv4i32 5714 { 1670, 4, 1, 4, 515, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1670 = VQMOVNsuv2i32 5715 { 1671, 4, 1, 4, 515, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1671 = VQMOVNsuv4i16 5716 { 1672, 4, 1, 4, 515, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1672 = VQMOVNsuv8i8 5717 { 1673, 4, 1, 4, 515, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1673 = VQMOVNsv2i32 5718 { 1674, 4, 1, 4, 515, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1674 = VQMOVNsv4i16 5719 { 1675, 4, 1, 4, 515, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1675 = VQMOVNsv8i8 5720 { 1676, 4, 1, 4, 515, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1676 = VQMOVNuv2i32 5721 { 1677, 4, 1, 4, 515, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1677 = VQMOVNuv4i16 5722 { 1678, 4, 1, 4, 515, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1678 = VQMOVNuv8i8 5723 { 1679, 4, 1, 4, 430, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1679 = VQNEGv16i8 5724 { 1680, 4, 1, 4, 431, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1680 = VQNEGv2i32 5725 { 1681, 4, 1, 4, 431, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1681 = VQNEGv4i16 5726 { 1682, 4, 1, 4, 430, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1682 = VQNEGv4i32 5727 { 1683, 4, 1, 4, 430, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1683 = VQNEGv8i16 5728 { 1684, 4, 1, 4, 431, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1684 = VQNEGv8i8 5729 { 1685, 7, 1, 4, 166, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1685 = VQRDMLAHslv2i32 5730 { 1686, 7, 1, 4, 167, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1686 = VQRDMLAHslv4i16 5731 { 1687, 7, 1, 4, 171, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11400ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1687 = VQRDMLAHslv4i32 5732 { 1688, 7, 1, 4, 172, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11400ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1688 = VQRDMLAHslv8i16 5733 { 1689, 6, 1, 4, 166, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1689 = VQRDMLAHv2i32 5734 { 1690, 6, 1, 4, 167, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1690 = VQRDMLAHv4i16 5735 { 1691, 6, 1, 4, 171, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1691 = VQRDMLAHv4i32 5736 { 1692, 6, 1, 4, 172, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1692 = VQRDMLAHv8i16 5737 { 1693, 7, 1, 4, 166, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1693 = VQRDMLSHslv2i32 5738 { 1694, 7, 1, 4, 167, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1694 = VQRDMLSHslv4i16 5739 { 1695, 7, 1, 4, 171, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11400ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1695 = VQRDMLSHslv4i32 5740 { 1696, 7, 1, 4, 172, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11400ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1696 = VQRDMLSHslv8i16 5741 { 1697, 6, 1, 4, 166, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1697 = VQRDMLSHv2i32 5742 { 1698, 6, 1, 4, 167, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #1698 = VQRDMLSHv4i16 5743 { 1699, 6, 1, 4, 171, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1699 = VQRDMLSHv4i32 5744 { 1700, 6, 1, 4, 172, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #1700 = VQRDMLSHv8i16 5745 { 1701, 6, 1, 4, 470, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1701 = VQRDMULHslv2i32 5746 { 1702, 6, 1, 4, 469, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1702 = VQRDMULHslv4i16 5747 { 1703, 6, 1, 4, 477, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1703 = VQRDMULHslv4i32 5748 { 1704, 6, 1, 4, 474, 0|(1ULL<<MCID::Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1704 = VQRDMULHslv8i16 5749 { 1705, 5, 1, 4, 470, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1705 = VQRDMULHv2i32 5750 { 1706, 5, 1, 4, 469, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1706 = VQRDMULHv4i16 5751 { 1707, 5, 1, 4, 477, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1707 = VQRDMULHv4i32 5752 { 1708, 5, 1, 4, 474, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1708 = VQRDMULHv8i16 5753 { 1709, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1709 = VQRSHLsv16i8 5754 { 1710, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1710 = VQRSHLsv1i64 5755 { 1711, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1711 = VQRSHLsv2i32 5756 { 1712, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1712 = VQRSHLsv2i64 5757 { 1713, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1713 = VQRSHLsv4i16 5758 { 1714, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1714 = VQRSHLsv4i32 5759 { 1715, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1715 = VQRSHLsv8i16 5760 { 1716, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1716 = VQRSHLsv8i8 5761 { 1717, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1717 = VQRSHLuv16i8 5762 { 1718, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1718 = VQRSHLuv1i64 5763 { 1719, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1719 = VQRSHLuv2i32 5764 { 1720, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1720 = VQRSHLuv2i64 5765 { 1721, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1721 = VQRSHLuv4i16 5766 { 1722, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1722 = VQRSHLuv4i32 5767 { 1723, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1723 = VQRSHLuv8i16 5768 { 1724, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1724 = VQRSHLuv8i8 5769 { 1725, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1725 = VQRSHRNsv2i32 5770 { 1726, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1726 = VQRSHRNsv4i16 5771 { 1727, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1727 = VQRSHRNsv8i8 5772 { 1728, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1728 = VQRSHRNuv2i32 5773 { 1729, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1729 = VQRSHRNuv4i16 5774 { 1730, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1730 = VQRSHRNuv8i8 5775 { 1731, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1731 = VQRSHRUNv2i32 5776 { 1732, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1732 = VQRSHRUNv4i16 5777 { 1733, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1733 = VQRSHRUNv8i8 5778 { 1734, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1734 = VQSHLsiv16i8 5779 { 1735, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1735 = VQSHLsiv1i64 5780 { 1736, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1736 = VQSHLsiv2i32 5781 { 1737, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1737 = VQSHLsiv2i64 5782 { 1738, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1738 = VQSHLsiv4i16 5783 { 1739, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1739 = VQSHLsiv4i32 5784 { 1740, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1740 = VQSHLsiv8i16 5785 { 1741, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1741 = VQSHLsiv8i8 5786 { 1742, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1742 = VQSHLsuv16i8 5787 { 1743, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1743 = VQSHLsuv1i64 5788 { 1744, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1744 = VQSHLsuv2i32 5789 { 1745, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1745 = VQSHLsuv2i64 5790 { 1746, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1746 = VQSHLsuv4i16 5791 { 1747, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1747 = VQSHLsuv4i32 5792 { 1748, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1748 = VQSHLsuv8i16 5793 { 1749, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1749 = VQSHLsuv8i8 5794 { 1750, 5, 1, 4, 411, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1750 = VQSHLsv16i8 5795 { 1751, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1751 = VQSHLsv1i64 5796 { 1752, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1752 = VQSHLsv2i32 5797 { 1753, 5, 1, 4, 411, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1753 = VQSHLsv2i64 5798 { 1754, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1754 = VQSHLsv4i16 5799 { 1755, 5, 1, 4, 411, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1755 = VQSHLsv4i32 5800 { 1756, 5, 1, 4, 411, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1756 = VQSHLsv8i16 5801 { 1757, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1757 = VQSHLsv8i8 5802 { 1758, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1758 = VQSHLuiv16i8 5803 { 1759, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1759 = VQSHLuiv1i64 5804 { 1760, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1760 = VQSHLuiv2i32 5805 { 1761, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1761 = VQSHLuiv2i64 5806 { 1762, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1762 = VQSHLuiv4i16 5807 { 1763, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1763 = VQSHLuiv4i32 5808 { 1764, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1764 = VQSHLuiv8i16 5809 { 1765, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1765 = VQSHLuiv8i8 5810 { 1766, 5, 1, 4, 411, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1766 = VQSHLuv16i8 5811 { 1767, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1767 = VQSHLuv1i64 5812 { 1768, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1768 = VQSHLuv2i32 5813 { 1769, 5, 1, 4, 411, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1769 = VQSHLuv2i64 5814 { 1770, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1770 = VQSHLuv4i16 5815 { 1771, 5, 1, 4, 411, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1771 = VQSHLuv4i32 5816 { 1772, 5, 1, 4, 411, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1772 = VQSHLuv8i16 5817 { 1773, 5, 1, 4, 410, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1773 = VQSHLuv8i8 5818 { 1774, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1774 = VQSHRNsv2i32 5819 { 1775, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1775 = VQSHRNsv4i16 5820 { 1776, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1776 = VQSHRNsv8i8 5821 { 1777, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1777 = VQSHRNuv2i32 5822 { 1778, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1778 = VQSHRNuv4i16 5823 { 1779, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1779 = VQSHRNuv8i8 5824 { 1780, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1780 = VQSHRUNv2i32 5825 { 1781, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1781 = VQSHRUNv4i16 5826 { 1782, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1782 = VQSHRUNv8i8 5827 { 1783, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1783 = VQSUBsv16i8 5828 { 1784, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1784 = VQSUBsv1i64 5829 { 1785, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1785 = VQSUBsv2i32 5830 { 1786, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1786 = VQSUBsv2i64 5831 { 1787, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1787 = VQSUBsv4i16 5832 { 1788, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1788 = VQSUBsv4i32 5833 { 1789, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1789 = VQSUBsv8i16 5834 { 1790, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1790 = VQSUBsv8i8 5835 { 1791, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1791 = VQSUBuv16i8 5836 { 1792, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1792 = VQSUBuv1i64 5837 { 1793, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1793 = VQSUBuv2i32 5838 { 1794, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1794 = VQSUBuv2i64 5839 { 1795, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1795 = VQSUBuv4i16 5840 { 1796, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1796 = VQSUBuv4i32 5841 { 1797, 5, 1, 4, 425, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1797 = VQSUBuv8i16 5842 { 1798, 5, 1, 4, 426, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1798 = VQSUBuv8i8 5843 { 1799, 5, 1, 4, 441, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #1799 = VRADDHNv2i32 5844 { 1800, 5, 1, 4, 441, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #1800 = VRADDHNv4i16 5845 { 1801, 5, 1, 4, 441, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #1801 = VRADDHNv8i8 5846 { 1802, 4, 1, 4, 436, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1802 = VRECPEd 5847 { 1803, 4, 1, 4, 436, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1803 = VRECPEfd 5848 { 1804, 4, 1, 4, 437, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1804 = VRECPEfq 5849 { 1805, 4, 1, 4, 436, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1805 = VRECPEhd 5850 { 1806, 4, 1, 4, 437, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1806 = VRECPEhq 5851 { 1807, 4, 1, 4, 437, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1807 = VRECPEq 5852 { 1808, 5, 1, 4, 466, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1808 = VRECPSfd 5853 { 1809, 5, 1, 4, 467, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1809 = VRECPSfq 5854 { 1810, 5, 1, 4, 466, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1810 = VRECPShd 5855 { 1811, 5, 1, 4, 467, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1811 = VRECPShq 5856 { 1812, 4, 1, 4, 415, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1812 = VREV16d8 5857 { 1813, 4, 1, 4, 416, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1813 = VREV16q8 5858 { 1814, 4, 1, 4, 415, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1814 = VREV32d16 5859 { 1815, 4, 1, 4, 415, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1815 = VREV32d8 5860 { 1816, 4, 1, 4, 416, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1816 = VREV32q16 5861 { 1817, 4, 1, 4, 416, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1817 = VREV32q8 5862 { 1818, 4, 1, 4, 415, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1818 = VREV64d16 5863 { 1819, 4, 1, 4, 415, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1819 = VREV64d32 5864 { 1820, 4, 1, 4, 415, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1820 = VREV64d8 5865 { 1821, 4, 1, 4, 416, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1821 = VREV64q16 5866 { 1822, 4, 1, 4, 416, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1822 = VREV64q32 5867 { 1823, 4, 1, 4, 416, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1823 = VREV64q8 5868 { 1824, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1824 = VRHADDsv16i8 5869 { 1825, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1825 = VRHADDsv2i32 5870 { 1826, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1826 = VRHADDsv4i16 5871 { 1827, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1827 = VRHADDsv4i32 5872 { 1828, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1828 = VRHADDsv8i16 5873 { 1829, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1829 = VRHADDsv8i8 5874 { 1830, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1830 = VRHADDuv16i8 5875 { 1831, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1831 = VRHADDuv2i32 5876 { 1832, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1832 = VRHADDuv4i16 5877 { 1833, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1833 = VRHADDuv4i32 5878 { 1834, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1834 = VRHADDuv8i16 5879 { 1835, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1835 = VRHADDuv8i8 5880 { 1836, 2, 1, 4, 0, 0, 0x8780ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1836 = VRINTAD 5881 { 1837, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1837 = VRINTAH 5882 { 1838, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1838 = VRINTANDf 5883 { 1839, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1839 = VRINTANDh 5884 { 1840, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #1840 = VRINTANQf 5885 { 1841, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #1841 = VRINTANQh 5886 { 1842, 2, 1, 4, 0, 0, 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1842 = VRINTAS 5887 { 1843, 2, 1, 4, 0, 0, 0x8780ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1843 = VRINTMD 5888 { 1844, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1844 = VRINTMH 5889 { 1845, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1845 = VRINTMNDf 5890 { 1846, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1846 = VRINTMNDh 5891 { 1847, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #1847 = VRINTMNQf 5892 { 1848, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #1848 = VRINTMNQh 5893 { 1849, 2, 1, 4, 0, 0, 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1849 = VRINTMS 5894 { 1850, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1850 = VRINTND 5895 { 1851, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1851 = VRINTNH 5896 { 1852, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1852 = VRINTNNDf 5897 { 1853, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1853 = VRINTNNDh 5898 { 1854, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #1854 = VRINTNNQf 5899 { 1855, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #1855 = VRINTNNQh 5900 { 1856, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1856 = VRINTNS 5901 { 1857, 2, 1, 4, 0, 0, 0x8780ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1857 = VRINTPD 5902 { 1858, 2, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1858 = VRINTPH 5903 { 1859, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1859 = VRINTPNDf 5904 { 1860, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1860 = VRINTPNDh 5905 { 1861, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #1861 = VRINTPNQf 5906 { 1862, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #1862 = VRINTPNQh 5907 { 1863, 2, 1, 4, 0, 0, 0x8780ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1863 = VRINTPS 5908 { 1864, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1864 = VRINTRD 5909 { 1865, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #1865 = VRINTRH 5910 { 1866, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #1866 = VRINTRS 5911 { 1867, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1867 = VRINTXD 5912 { 1868, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #1868 = VRINTXH 5913 { 1869, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1869 = VRINTXNDf 5914 { 1870, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1870 = VRINTXNDh 5915 { 1871, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #1871 = VRINTXNQf 5916 { 1872, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #1872 = VRINTXNQh 5917 { 1873, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #1873 = VRINTXS 5918 { 1874, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1874 = VRINTZD 5919 { 1875, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #1875 = VRINTZH 5920 { 1876, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1876 = VRINTZNDf 5921 { 1877, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #1877 = VRINTZNDh 5922 { 1878, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #1878 = VRINTZNQf 5923 { 1879, 2, 1, 4, 0, 0, 0x11000ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #1879 = VRINTZNQh 5924 { 1880, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #1880 = VRINTZS 5925 { 1881, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1881 = VRSHLsv16i8 5926 { 1882, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1882 = VRSHLsv1i64 5927 { 1883, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1883 = VRSHLsv2i32 5928 { 1884, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1884 = VRSHLsv2i64 5929 { 1885, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1885 = VRSHLsv4i16 5930 { 1886, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1886 = VRSHLsv4i32 5931 { 1887, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1887 = VRSHLsv8i16 5932 { 1888, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1888 = VRSHLsv8i8 5933 { 1889, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1889 = VRSHLuv16i8 5934 { 1890, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1890 = VRSHLuv1i64 5935 { 1891, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1891 = VRSHLuv2i32 5936 { 1892, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1892 = VRSHLuv2i64 5937 { 1893, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1893 = VRSHLuv4i16 5938 { 1894, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1894 = VRSHLuv4i32 5939 { 1895, 5, 1, 4, 434, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1895 = VRSHLuv8i16 5940 { 1896, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1896 = VRSHLuv8i8 5941 { 1897, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1897 = VRSHRNv2i32 5942 { 1898, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1898 = VRSHRNv4i16 5943 { 1899, 5, 1, 4, 440, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1899 = VRSHRNv8i8 5944 { 1900, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1900 = VRSHRsv16i8 5945 { 1901, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1901 = VRSHRsv1i64 5946 { 1902, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1902 = VRSHRsv2i32 5947 { 1903, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1903 = VRSHRsv2i64 5948 { 1904, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1904 = VRSHRsv4i16 5949 { 1905, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1905 = VRSHRsv4i32 5950 { 1906, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1906 = VRSHRsv8i16 5951 { 1907, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1907 = VRSHRsv8i8 5952 { 1908, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1908 = VRSHRuv16i8 5953 { 1909, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1909 = VRSHRuv1i64 5954 { 1910, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1910 = VRSHRuv2i32 5955 { 1911, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1911 = VRSHRuv2i64 5956 { 1912, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1912 = VRSHRuv4i16 5957 { 1913, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1913 = VRSHRuv4i32 5958 { 1914, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1914 = VRSHRuv8i16 5959 { 1915, 5, 1, 4, 435, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1915 = VRSHRuv8i8 5960 { 1916, 4, 1, 4, 436, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1916 = VRSQRTEd 5961 { 1917, 4, 1, 4, 436, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1917 = VRSQRTEfd 5962 { 1918, 4, 1, 4, 437, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1918 = VRSQRTEfq 5963 { 1919, 4, 1, 4, 436, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #1919 = VRSQRTEhd 5964 { 1920, 4, 1, 4, 437, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1920 = VRSQRTEhq 5965 { 1921, 4, 1, 4, 437, 0|(1ULL<<MCID::Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #1921 = VRSQRTEq 5966 { 1922, 5, 1, 4, 466, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1922 = VRSQRTSfd 5967 { 1923, 5, 1, 4, 467, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1923 = VRSQRTSfq 5968 { 1924, 5, 1, 4, 466, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1924 = VRSQRTShd 5969 { 1925, 5, 1, 4, 467, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1925 = VRSQRTShq 5970 { 1926, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1926 = VRSRAsv16i8 5971 { 1927, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1927 = VRSRAsv1i64 5972 { 1928, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1928 = VRSRAsv2i32 5973 { 1929, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1929 = VRSRAsv2i64 5974 { 1930, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1930 = VRSRAsv4i16 5975 { 1931, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1931 = VRSRAsv4i32 5976 { 1932, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1932 = VRSRAsv8i16 5977 { 1933, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1933 = VRSRAsv8i8 5978 { 1934, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1934 = VRSRAuv16i8 5979 { 1935, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1935 = VRSRAuv1i64 5980 { 1936, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1936 = VRSRAuv2i32 5981 { 1937, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1937 = VRSRAuv2i64 5982 { 1938, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1938 = VRSRAuv4i16 5983 { 1939, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1939 = VRSRAuv4i32 5984 { 1940, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1940 = VRSRAuv8i16 5985 { 1941, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1941 = VRSRAuv8i8 5986 { 1942, 5, 1, 4, 441, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #1942 = VRSUBHNv2i32 5987 { 1943, 5, 1, 4, 441, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #1943 = VRSUBHNv4i16 5988 { 1944, 5, 1, 4, 441, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #1944 = VRSUBHNv8i8 5989 { 1945, 3, 1, 4, 0, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1945 = VSELEQD 5990 { 1946, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, ImplicitList1, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1946 = VSELEQH 5991 { 1947, 3, 1, 4, 0, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1947 = VSELEQS 5992 { 1948, 3, 1, 4, 0, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1948 = VSELGED 5993 { 1949, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, ImplicitList1, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1949 = VSELGEH 5994 { 1950, 3, 1, 4, 0, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1950 = VSELGES 5995 { 1951, 3, 1, 4, 0, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1951 = VSELGTD 5996 { 1952, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, ImplicitList1, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1952 = VSELGTH 5997 { 1953, 3, 1, 4, 0, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1953 = VSELGTS 5998 { 1954, 3, 1, 4, 0, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1954 = VSELVSD 5999 { 1955, 3, 1, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, ImplicitList1, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1955 = VSELVSH 6000 { 1956, 3, 1, 4, 0, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1956 = VSELVSS 6001 { 1957, 6, 1, 4, 521, 0|(1ULL<<MCID::Predicable), 0x10e00ULL, nullptr, nullptr, OperandInfo232, -1 ,nullptr }, // Inst #1957 = VSETLNi16 6002 { 1958, 6, 1, 4, 521, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::InsertSubreg), 0x10e00ULL, nullptr, nullptr, OperandInfo232, -1 ,nullptr }, // Inst #1958 = VSETLNi32 6003 { 1959, 6, 1, 4, 521, 0|(1ULL<<MCID::Predicable), 0x10e00ULL, nullptr, nullptr, OperandInfo232, -1 ,nullptr }, // Inst #1959 = VSETLNi8 6004 { 1960, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1960 = VSHLLi16 6005 { 1961, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1961 = VSHLLi32 6006 { 1962, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1962 = VSHLLi8 6007 { 1963, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1963 = VSHLLsv2i64 6008 { 1964, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1964 = VSHLLsv4i32 6009 { 1965, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1965 = VSHLLsv8i16 6010 { 1966, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1966 = VSHLLuv2i64 6011 { 1967, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1967 = VSHLLuv4i32 6012 { 1968, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #1968 = VSHLLuv8i16 6013 { 1969, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1969 = VSHLiv16i8 6014 { 1970, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1970 = VSHLiv1i64 6015 { 1971, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1971 = VSHLiv2i32 6016 { 1972, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1972 = VSHLiv2i64 6017 { 1973, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1973 = VSHLiv4i16 6018 { 1974, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1974 = VSHLiv4i32 6019 { 1975, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1975 = VSHLiv8i16 6020 { 1976, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1976 = VSHLiv8i8 6021 { 1977, 5, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1977 = VSHLsv16i8 6022 { 1978, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1978 = VSHLsv1i64 6023 { 1979, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1979 = VSHLsv2i32 6024 { 1980, 5, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1980 = VSHLsv2i64 6025 { 1981, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1981 = VSHLsv4i16 6026 { 1982, 5, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1982 = VSHLsv4i32 6027 { 1983, 5, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1983 = VSHLsv8i16 6028 { 1984, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1984 = VSHLsv8i8 6029 { 1985, 5, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1985 = VSHLuv16i8 6030 { 1986, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1986 = VSHLuv1i64 6031 { 1987, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1987 = VSHLuv2i32 6032 { 1988, 5, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1988 = VSHLuv2i64 6033 { 1989, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1989 = VSHLuv4i16 6034 { 1990, 5, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1990 = VSHLuv4i32 6035 { 1991, 5, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #1991 = VSHLuv8i16 6036 { 1992, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1992 = VSHLuv8i8 6037 { 1993, 5, 1, 4, 439, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1993 = VSHRNv2i32 6038 { 1994, 5, 1, 4, 439, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1994 = VSHRNv4i16 6039 { 1995, 5, 1, 4, 439, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1995 = VSHRNv8i8 6040 { 1996, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1996 = VSHRsv16i8 6041 { 1997, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1997 = VSHRsv1i64 6042 { 1998, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #1998 = VSHRsv2i32 6043 { 1999, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #1999 = VSHRsv2i64 6044 { 2000, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2000 = VSHRsv4i16 6045 { 2001, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2001 = VSHRsv4i32 6046 { 2002, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2002 = VSHRsv8i16 6047 { 2003, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2003 = VSHRsv8i8 6048 { 2004, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2004 = VSHRuv16i8 6049 { 2005, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2005 = VSHRuv1i64 6050 { 2006, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2006 = VSHRuv2i32 6051 { 2007, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2007 = VSHRuv2i64 6052 { 2008, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2008 = VSHRuv4i16 6053 { 2009, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2009 = VSHRuv4i32 6054 { 2010, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #2010 = VSHRuv8i16 6055 { 2011, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #2011 = VSHRuv8i8 6056 { 2012, 5, 1, 4, 198, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2012 = VSHTOD 6057 { 2013, 5, 1, 4, 199, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2013 = VSHTOH 6058 { 2014, 5, 1, 4, 200, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2014 = VSHTOS 6059 { 2015, 4, 1, 4, 500, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2015 = VSITOD 6060 { 2016, 4, 1, 4, 501, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2016 = VSITOH 6061 { 2017, 4, 1, 4, 502, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2017 = VSITOS 6062 { 2018, 6, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo235, -1 ,nullptr }, // Inst #2018 = VSLIv16i8 6063 { 2019, 6, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr }, // Inst #2019 = VSLIv1i64 6064 { 2020, 6, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr }, // Inst #2020 = VSLIv2i32 6065 { 2021, 6, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo235, -1 ,nullptr }, // Inst #2021 = VSLIv2i64 6066 { 2022, 6, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr }, // Inst #2022 = VSLIv4i16 6067 { 2023, 6, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo235, -1 ,nullptr }, // Inst #2023 = VSLIv4i32 6068 { 2024, 6, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo235, -1 ,nullptr }, // Inst #2024 = VSLIv8i16 6069 { 2025, 6, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo236, -1 ,nullptr }, // Inst #2025 = VSLIv8i8 6070 { 2026, 5, 1, 4, 198, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2026 = VSLTOD 6071 { 2027, 5, 1, 4, 199, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2027 = VSLTOH 6072 { 2028, 5, 1, 4, 200, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2028 = VSLTOS 6073 { 2029, 4, 1, 4, 611, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #2029 = VSQRTD 6074 { 2030, 4, 1, 4, 205, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2030 = VSQRTH 6075 { 2031, 4, 1, 4, 609, 0|(1ULL<<MCID::Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2031 = VSQRTS 6076 { 2032, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2032 = VSRAsv16i8 6077 { 2033, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2033 = VSRAsv1i64 6078 { 2034, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2034 = VSRAsv2i32 6079 { 2035, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2035 = VSRAsv2i64 6080 { 2036, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2036 = VSRAsv4i16 6081 { 2037, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2037 = VSRAsv4i32 6082 { 2038, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2038 = VSRAsv8i16 6083 { 2039, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2039 = VSRAsv8i8 6084 { 2040, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2040 = VSRAuv16i8 6085 { 2041, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2041 = VSRAuv1i64 6086 { 2042, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2042 = VSRAuv2i32 6087 { 2043, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2043 = VSRAuv2i64 6088 { 2044, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2044 = VSRAuv4i16 6089 { 2045, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2045 = VSRAuv4i32 6090 { 2046, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2046 = VSRAuv8i16 6091 { 2047, 6, 1, 4, 429, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2047 = VSRAuv8i8 6092 { 2048, 6, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2048 = VSRIv16i8 6093 { 2049, 6, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2049 = VSRIv1i64 6094 { 2050, 6, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2050 = VSRIv2i32 6095 { 2051, 6, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2051 = VSRIv2i64 6096 { 2052, 6, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2052 = VSRIv4i16 6097 { 2053, 6, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2053 = VSRIv4i32 6098 { 2054, 6, 1, 4, 409, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #2054 = VSRIv8i16 6099 { 2055, 6, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #2055 = VSRIv8i8 6100 { 2056, 6, 0, 4, 600, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr }, // Inst #2056 = VST1LNd16 6101 { 2057, 8, 1, 4, 601, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #2057 = VST1LNd16_UPD 6102 { 2058, 6, 0, 4, 600, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr }, // Inst #2058 = VST1LNd32 6103 { 2059, 8, 1, 4, 601, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #2059 = VST1LNd32_UPD 6104 { 2060, 6, 0, 4, 600, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo237, -1 ,nullptr }, // Inst #2060 = VST1LNd8 6105 { 2061, 8, 1, 4, 601, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #2061 = VST1LNd8_UPD 6106 { 2062, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2062 = VST1LNdAsm_16 6107 { 2063, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2063 = VST1LNdAsm_32 6108 { 2064, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2064 = VST1LNdAsm_8 6109 { 2065, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2065 = VST1LNdWB_fixed_Asm_16 6110 { 2066, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2066 = VST1LNdWB_fixed_Asm_32 6111 { 2067, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2067 = VST1LNdWB_fixed_Asm_8 6112 { 2068, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2068 = VST1LNdWB_register_Asm_16 6113 { 2069, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2069 = VST1LNdWB_register_Asm_32 6114 { 2070, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2070 = VST1LNdWB_register_Asm_8 6115 { 2071, 6, 0, 4, 600, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #2071 = VST1LNq16Pseudo 6116 { 2072, 8, 1, 4, 601, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #2072 = VST1LNq16Pseudo_UPD 6117 { 2073, 6, 0, 4, 600, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #2073 = VST1LNq32Pseudo 6118 { 2074, 8, 1, 4, 601, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #2074 = VST1LNq32Pseudo_UPD 6119 { 2075, 6, 0, 4, 600, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #2075 = VST1LNq8Pseudo 6120 { 2076, 8, 1, 4, 601, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #2076 = VST1LNq8Pseudo_UPD 6121 { 2077, 5, 0, 4, 581, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2077 = VST1d16 6122 { 2078, 5, 0, 4, 588, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2078 = VST1d16Q 6123 { 2079, 6, 1, 4, 589, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2079 = VST1d16Qwb_fixed 6124 { 2080, 7, 1, 4, 589, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2080 = VST1d16Qwb_register 6125 { 2081, 5, 0, 4, 585, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2081 = VST1d16T 6126 { 2082, 6, 1, 4, 586, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2082 = VST1d16Twb_fixed 6127 { 2083, 7, 1, 4, 586, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2083 = VST1d16Twb_register 6128 { 2084, 6, 1, 4, 583, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2084 = VST1d16wb_fixed 6129 { 2085, 7, 1, 4, 583, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2085 = VST1d16wb_register 6130 { 2086, 5, 0, 4, 581, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2086 = VST1d32 6131 { 2087, 5, 0, 4, 588, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2087 = VST1d32Q 6132 { 2088, 6, 1, 4, 589, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2088 = VST1d32Qwb_fixed 6133 { 2089, 7, 1, 4, 589, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2089 = VST1d32Qwb_register 6134 { 2090, 5, 0, 4, 585, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2090 = VST1d32T 6135 { 2091, 6, 1, 4, 586, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2091 = VST1d32Twb_fixed 6136 { 2092, 7, 1, 4, 586, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2092 = VST1d32Twb_register 6137 { 2093, 6, 1, 4, 583, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2093 = VST1d32wb_fixed 6138 { 2094, 7, 1, 4, 583, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2094 = VST1d32wb_register 6139 { 2095, 5, 0, 4, 581, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2095 = VST1d64 6140 { 2096, 5, 0, 4, 588, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2096 = VST1d64Q 6141 { 2097, 5, 0, 4, 588, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #2097 = VST1d64QPseudo 6142 { 2098, 6, 1, 4, 590, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245, -1 ,nullptr }, // Inst #2098 = VST1d64QPseudoWB_fixed 6143 { 2099, 7, 1, 4, 590, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #2099 = VST1d64QPseudoWB_register 6144 { 2100, 6, 1, 4, 589, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2100 = VST1d64Qwb_fixed 6145 { 2101, 7, 1, 4, 589, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2101 = VST1d64Qwb_register 6146 { 2102, 5, 0, 4, 585, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2102 = VST1d64T 6147 { 2103, 5, 0, 4, 585, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #2103 = VST1d64TPseudo 6148 { 2104, 6, 1, 4, 587, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245, -1 ,nullptr }, // Inst #2104 = VST1d64TPseudoWB_fixed 6149 { 2105, 7, 1, 4, 587, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #2105 = VST1d64TPseudoWB_register 6150 { 2106, 6, 1, 4, 586, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2106 = VST1d64Twb_fixed 6151 { 2107, 7, 1, 4, 586, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2107 = VST1d64Twb_register 6152 { 2108, 6, 1, 4, 583, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2108 = VST1d64wb_fixed 6153 { 2109, 7, 1, 4, 583, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2109 = VST1d64wb_register 6154 { 2110, 5, 0, 4, 581, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2110 = VST1d8 6155 { 2111, 5, 0, 4, 588, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2111 = VST1d8Q 6156 { 2112, 6, 1, 4, 589, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2112 = VST1d8Qwb_fixed 6157 { 2113, 7, 1, 4, 589, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2113 = VST1d8Qwb_register 6158 { 2114, 5, 0, 4, 585, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2114 = VST1d8T 6159 { 2115, 6, 1, 4, 586, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2115 = VST1d8Twb_fixed 6160 { 2116, 7, 1, 4, 586, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2116 = VST1d8Twb_register 6161 { 2117, 6, 1, 4, 583, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2117 = VST1d8wb_fixed 6162 { 2118, 7, 1, 4, 583, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2118 = VST1d8wb_register 6163 { 2119, 5, 0, 4, 582, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #2119 = VST1q16 6164 { 2120, 6, 1, 4, 584, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #2120 = VST1q16wb_fixed 6165 { 2121, 7, 1, 4, 584, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #2121 = VST1q16wb_register 6166 { 2122, 5, 0, 4, 582, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #2122 = VST1q32 6167 { 2123, 6, 1, 4, 584, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #2123 = VST1q32wb_fixed 6168 { 2124, 7, 1, 4, 584, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #2124 = VST1q32wb_register 6169 { 2125, 5, 0, 4, 582, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #2125 = VST1q64 6170 { 2126, 6, 1, 4, 584, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #2126 = VST1q64wb_fixed 6171 { 2127, 7, 1, 4, 584, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #2127 = VST1q64wb_register 6172 { 2128, 5, 0, 4, 582, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #2128 = VST1q8 6173 { 2129, 6, 1, 4, 584, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #2129 = VST1q8wb_fixed 6174 { 2130, 7, 1, 4, 584, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #2130 = VST1q8wb_register 6175 { 2131, 7, 0, 4, 602, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #2131 = VST2LNd16 6176 { 2132, 6, 0, 4, 602, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #2132 = VST2LNd16Pseudo 6177 { 2133, 8, 1, 4, 603, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #2133 = VST2LNd16Pseudo_UPD 6178 { 2134, 9, 1, 4, 603, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #2134 = VST2LNd16_UPD 6179 { 2135, 7, 0, 4, 602, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #2135 = VST2LNd32 6180 { 2136, 6, 0, 4, 602, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #2136 = VST2LNd32Pseudo 6181 { 2137, 8, 1, 4, 603, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #2137 = VST2LNd32Pseudo_UPD 6182 { 2138, 9, 1, 4, 603, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #2138 = VST2LNd32_UPD 6183 { 2139, 7, 0, 4, 602, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #2139 = VST2LNd8 6184 { 2140, 6, 0, 4, 602, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #2140 = VST2LNd8Pseudo 6185 { 2141, 8, 1, 4, 603, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #2141 = VST2LNd8Pseudo_UPD 6186 { 2142, 9, 1, 4, 603, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #2142 = VST2LNd8_UPD 6187 { 2143, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2143 = VST2LNdAsm_16 6188 { 2144, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2144 = VST2LNdAsm_32 6189 { 2145, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2145 = VST2LNdAsm_8 6190 { 2146, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2146 = VST2LNdWB_fixed_Asm_16 6191 { 2147, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2147 = VST2LNdWB_fixed_Asm_32 6192 { 2148, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2148 = VST2LNdWB_fixed_Asm_8 6193 { 2149, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2149 = VST2LNdWB_register_Asm_16 6194 { 2150, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2150 = VST2LNdWB_register_Asm_32 6195 { 2151, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2151 = VST2LNdWB_register_Asm_8 6196 { 2152, 7, 0, 4, 602, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #2152 = VST2LNq16 6197 { 2153, 6, 0, 4, 602, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #2153 = VST2LNq16Pseudo 6198 { 2154, 8, 1, 4, 603, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #2154 = VST2LNq16Pseudo_UPD 6199 { 2155, 9, 1, 4, 603, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #2155 = VST2LNq16_UPD 6200 { 2156, 7, 0, 4, 602, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #2156 = VST2LNq32 6201 { 2157, 6, 0, 4, 602, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #2157 = VST2LNq32Pseudo 6202 { 2158, 8, 1, 4, 603, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #2158 = VST2LNq32Pseudo_UPD 6203 { 2159, 9, 1, 4, 603, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #2159 = VST2LNq32_UPD 6204 { 2160, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2160 = VST2LNqAsm_16 6205 { 2161, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2161 = VST2LNqAsm_32 6206 { 2162, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2162 = VST2LNqWB_fixed_Asm_16 6207 { 2163, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2163 = VST2LNqWB_fixed_Asm_32 6208 { 2164, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2164 = VST2LNqWB_register_Asm_16 6209 { 2165, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2165 = VST2LNqWB_register_Asm_32 6210 { 2166, 5, 0, 4, 591, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #2166 = VST2b16 6211 { 2167, 6, 1, 4, 592, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #2167 = VST2b16wb_fixed 6212 { 2168, 7, 1, 4, 592, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #2168 = VST2b16wb_register 6213 { 2169, 5, 0, 4, 591, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #2169 = VST2b32 6214 { 2170, 6, 1, 4, 592, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #2170 = VST2b32wb_fixed 6215 { 2171, 7, 1, 4, 592, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #2171 = VST2b32wb_register 6216 { 2172, 5, 0, 4, 591, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #2172 = VST2b8 6217 { 2173, 6, 1, 4, 592, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #2173 = VST2b8wb_fixed 6218 { 2174, 7, 1, 4, 592, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #2174 = VST2b8wb_register 6219 { 2175, 5, 0, 4, 591, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #2175 = VST2d16 6220 { 2176, 6, 1, 4, 592, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #2176 = VST2d16wb_fixed 6221 { 2177, 7, 1, 4, 592, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #2177 = VST2d16wb_register 6222 { 2178, 5, 0, 4, 591, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #2178 = VST2d32 6223 { 2179, 6, 1, 4, 592, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #2179 = VST2d32wb_fixed 6224 { 2180, 7, 1, 4, 592, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #2180 = VST2d32wb_register 6225 { 2181, 5, 0, 4, 591, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #2181 = VST2d8 6226 { 2182, 6, 1, 4, 592, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #2182 = VST2d8wb_fixed 6227 { 2183, 7, 1, 4, 592, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #2183 = VST2d8wb_register 6228 { 2184, 5, 0, 4, 593, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2184 = VST2q16 6229 { 2185, 5, 0, 4, 593, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #2185 = VST2q16Pseudo 6230 { 2186, 6, 1, 4, 594, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245, -1 ,nullptr }, // Inst #2186 = VST2q16PseudoWB_fixed 6231 { 2187, 7, 1, 4, 594, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo254, -1 ,nullptr }, // Inst #2187 = VST2q16PseudoWB_register 6232 { 2188, 6, 1, 4, 595, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2188 = VST2q16wb_fixed 6233 { 2189, 7, 1, 4, 595, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2189 = VST2q16wb_register 6234 { 2190, 5, 0, 4, 593, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2190 = VST2q32 6235 { 2191, 5, 0, 4, 593, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #2191 = VST2q32Pseudo 6236 { 2192, 6, 1, 4, 594, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245, -1 ,nullptr }, // Inst #2192 = VST2q32PseudoWB_fixed 6237 { 2193, 7, 1, 4, 594, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo254, -1 ,nullptr }, // Inst #2193 = VST2q32PseudoWB_register 6238 { 2194, 6, 1, 4, 595, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2194 = VST2q32wb_fixed 6239 { 2195, 7, 1, 4, 595, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2195 = VST2q32wb_register 6240 { 2196, 5, 0, 4, 593, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2196 = VST2q8 6241 { 2197, 5, 0, 4, 593, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #2197 = VST2q8Pseudo 6242 { 2198, 6, 1, 4, 594, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo245, -1 ,nullptr }, // Inst #2198 = VST2q8PseudoWB_fixed 6243 { 2199, 7, 1, 4, 594, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo254, -1 ,nullptr }, // Inst #2199 = VST2q8PseudoWB_register 6244 { 2200, 6, 1, 4, 595, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242, -1 ,nullptr }, // Inst #2200 = VST2q8wb_fixed 6245 { 2201, 7, 1, 4, 595, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243, -1 ,nullptr }, // Inst #2201 = VST2q8wb_register 6246 { 2202, 8, 0, 4, 604, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr }, // Inst #2202 = VST3LNd16 6247 { 2203, 6, 0, 4, 604, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #2203 = VST3LNd16Pseudo 6248 { 2204, 8, 1, 4, 605, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #2204 = VST3LNd16Pseudo_UPD 6249 { 2205, 10, 1, 4, 605, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2205 = VST3LNd16_UPD 6250 { 2206, 8, 0, 4, 604, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr }, // Inst #2206 = VST3LNd32 6251 { 2207, 6, 0, 4, 604, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #2207 = VST3LNd32Pseudo 6252 { 2208, 8, 1, 4, 605, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #2208 = VST3LNd32Pseudo_UPD 6253 { 2209, 10, 1, 4, 605, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2209 = VST3LNd32_UPD 6254 { 2210, 8, 0, 4, 604, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr }, // Inst #2210 = VST3LNd8 6255 { 2211, 6, 0, 4, 604, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #2211 = VST3LNd8Pseudo 6256 { 2212, 8, 1, 4, 605, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #2212 = VST3LNd8Pseudo_UPD 6257 { 2213, 10, 1, 4, 605, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2213 = VST3LNd8_UPD 6258 { 2214, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2214 = VST3LNdAsm_16 6259 { 2215, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2215 = VST3LNdAsm_32 6260 { 2216, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2216 = VST3LNdAsm_8 6261 { 2217, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2217 = VST3LNdWB_fixed_Asm_16 6262 { 2218, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2218 = VST3LNdWB_fixed_Asm_32 6263 { 2219, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2219 = VST3LNdWB_fixed_Asm_8 6264 { 2220, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2220 = VST3LNdWB_register_Asm_16 6265 { 2221, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2221 = VST3LNdWB_register_Asm_32 6266 { 2222, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2222 = VST3LNdWB_register_Asm_8 6267 { 2223, 8, 0, 4, 604, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr }, // Inst #2223 = VST3LNq16 6268 { 2224, 6, 0, 4, 604, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #2224 = VST3LNq16Pseudo 6269 { 2225, 8, 1, 4, 605, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #2225 = VST3LNq16Pseudo_UPD 6270 { 2226, 10, 1, 4, 605, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2226 = VST3LNq16_UPD 6271 { 2227, 8, 0, 4, 604, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr }, // Inst #2227 = VST3LNq32 6272 { 2228, 6, 0, 4, 604, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #2228 = VST3LNq32Pseudo 6273 { 2229, 8, 1, 4, 605, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #2229 = VST3LNq32Pseudo_UPD 6274 { 2230, 10, 1, 4, 605, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2230 = VST3LNq32_UPD 6275 { 2231, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2231 = VST3LNqAsm_16 6276 { 2232, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2232 = VST3LNqAsm_32 6277 { 2233, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2233 = VST3LNqWB_fixed_Asm_16 6278 { 2234, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2234 = VST3LNqWB_fixed_Asm_32 6279 { 2235, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2235 = VST3LNqWB_register_Asm_16 6280 { 2236, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2236 = VST3LNqWB_register_Asm_32 6281 { 2237, 7, 0, 4, 596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #2237 = VST3d16 6282 { 2238, 5, 0, 4, 596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #2238 = VST3d16Pseudo 6283 { 2239, 7, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #2239 = VST3d16Pseudo_UPD 6284 { 2240, 9, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #2240 = VST3d16_UPD 6285 { 2241, 7, 0, 4, 596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #2241 = VST3d32 6286 { 2242, 5, 0, 4, 596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #2242 = VST3d32Pseudo 6287 { 2243, 7, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #2243 = VST3d32Pseudo_UPD 6288 { 2244, 9, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #2244 = VST3d32_UPD 6289 { 2245, 7, 0, 4, 596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #2245 = VST3d8 6290 { 2246, 5, 0, 4, 596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #2246 = VST3d8Pseudo 6291 { 2247, 7, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #2247 = VST3d8Pseudo_UPD 6292 { 2248, 9, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #2248 = VST3d8_UPD 6293 { 2249, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2249 = VST3dAsm_16 6294 { 2250, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2250 = VST3dAsm_32 6295 { 2251, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2251 = VST3dAsm_8 6296 { 2252, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2252 = VST3dWB_fixed_Asm_16 6297 { 2253, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2253 = VST3dWB_fixed_Asm_32 6298 { 2254, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2254 = VST3dWB_fixed_Asm_8 6299 { 2255, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2255 = VST3dWB_register_Asm_16 6300 { 2256, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2256 = VST3dWB_register_Asm_32 6301 { 2257, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2257 = VST3dWB_register_Asm_8 6302 { 2258, 7, 0, 4, 596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #2258 = VST3q16 6303 { 2259, 7, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #2259 = VST3q16Pseudo_UPD 6304 { 2260, 9, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #2260 = VST3q16_UPD 6305 { 2261, 5, 0, 4, 596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2261 = VST3q16oddPseudo 6306 { 2262, 7, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #2262 = VST3q16oddPseudo_UPD 6307 { 2263, 7, 0, 4, 596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #2263 = VST3q32 6308 { 2264, 7, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #2264 = VST3q32Pseudo_UPD 6309 { 2265, 9, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #2265 = VST3q32_UPD 6310 { 2266, 5, 0, 4, 596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2266 = VST3q32oddPseudo 6311 { 2267, 7, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #2267 = VST3q32oddPseudo_UPD 6312 { 2268, 7, 0, 4, 596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #2268 = VST3q8 6313 { 2269, 7, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #2269 = VST3q8Pseudo_UPD 6314 { 2270, 9, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #2270 = VST3q8_UPD 6315 { 2271, 5, 0, 4, 596, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2271 = VST3q8oddPseudo 6316 { 2272, 7, 1, 4, 597, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #2272 = VST3q8oddPseudo_UPD 6317 { 2273, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2273 = VST3qAsm_16 6318 { 2274, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2274 = VST3qAsm_32 6319 { 2275, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2275 = VST3qAsm_8 6320 { 2276, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2276 = VST3qWB_fixed_Asm_16 6321 { 2277, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2277 = VST3qWB_fixed_Asm_32 6322 { 2278, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2278 = VST3qWB_fixed_Asm_8 6323 { 2279, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2279 = VST3qWB_register_Asm_16 6324 { 2280, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2280 = VST3qWB_register_Asm_32 6325 { 2281, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2281 = VST3qWB_register_Asm_8 6326 { 2282, 9, 0, 4, 606, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2282 = VST4LNd16 6327 { 2283, 6, 0, 4, 606, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #2283 = VST4LNd16Pseudo 6328 { 2284, 8, 1, 4, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #2284 = VST4LNd16Pseudo_UPD 6329 { 2285, 11, 1, 4, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2285 = VST4LNd16_UPD 6330 { 2286, 9, 0, 4, 606, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2286 = VST4LNd32 6331 { 2287, 6, 0, 4, 606, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #2287 = VST4LNd32Pseudo 6332 { 2288, 8, 1, 4, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #2288 = VST4LNd32Pseudo_UPD 6333 { 2289, 11, 1, 4, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2289 = VST4LNd32_UPD 6334 { 2290, 9, 0, 4, 606, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2290 = VST4LNd8 6335 { 2291, 6, 0, 4, 606, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #2291 = VST4LNd8Pseudo 6336 { 2292, 8, 1, 4, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #2292 = VST4LNd8Pseudo_UPD 6337 { 2293, 11, 1, 4, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2293 = VST4LNd8_UPD 6338 { 2294, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2294 = VST4LNdAsm_16 6339 { 2295, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2295 = VST4LNdAsm_32 6340 { 2296, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2296 = VST4LNdAsm_8 6341 { 2297, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2297 = VST4LNdWB_fixed_Asm_16 6342 { 2298, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2298 = VST4LNdWB_fixed_Asm_32 6343 { 2299, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2299 = VST4LNdWB_fixed_Asm_8 6344 { 2300, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2300 = VST4LNdWB_register_Asm_16 6345 { 2301, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2301 = VST4LNdWB_register_Asm_32 6346 { 2302, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2302 = VST4LNdWB_register_Asm_8 6347 { 2303, 9, 0, 4, 606, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2303 = VST4LNq16 6348 { 2304, 6, 0, 4, 606, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #2304 = VST4LNq16Pseudo 6349 { 2305, 8, 1, 4, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #2305 = VST4LNq16Pseudo_UPD 6350 { 2306, 11, 1, 4, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2306 = VST4LNq16_UPD 6351 { 2307, 9, 0, 4, 606, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2307 = VST4LNq32 6352 { 2308, 6, 0, 4, 606, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #2308 = VST4LNq32Pseudo 6353 { 2309, 8, 1, 4, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #2309 = VST4LNq32Pseudo_UPD 6354 { 2310, 11, 1, 4, 607, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #2310 = VST4LNq32_UPD 6355 { 2311, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2311 = VST4LNqAsm_16 6356 { 2312, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2312 = VST4LNqAsm_32 6357 { 2313, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2313 = VST4LNqWB_fixed_Asm_16 6358 { 2314, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2314 = VST4LNqWB_fixed_Asm_32 6359 { 2315, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2315 = VST4LNqWB_register_Asm_16 6360 { 2316, 7, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2316 = VST4LNqWB_register_Asm_32 6361 { 2317, 8, 0, 4, 598, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2317 = VST4d16 6362 { 2318, 5, 0, 4, 598, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #2318 = VST4d16Pseudo 6363 { 2319, 7, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #2319 = VST4d16Pseudo_UPD 6364 { 2320, 10, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2320 = VST4d16_UPD 6365 { 2321, 8, 0, 4, 598, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2321 = VST4d32 6366 { 2322, 5, 0, 4, 598, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #2322 = VST4d32Pseudo 6367 { 2323, 7, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #2323 = VST4d32Pseudo_UPD 6368 { 2324, 10, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2324 = VST4d32_UPD 6369 { 2325, 8, 0, 4, 598, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2325 = VST4d8 6370 { 2326, 5, 0, 4, 598, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo244, -1 ,nullptr }, // Inst #2326 = VST4d8Pseudo 6371 { 2327, 7, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #2327 = VST4d8Pseudo_UPD 6372 { 2328, 10, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2328 = VST4d8_UPD 6373 { 2329, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2329 = VST4dAsm_16 6374 { 2330, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2330 = VST4dAsm_32 6375 { 2331, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2331 = VST4dAsm_8 6376 { 2332, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2332 = VST4dWB_fixed_Asm_16 6377 { 2333, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2333 = VST4dWB_fixed_Asm_32 6378 { 2334, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2334 = VST4dWB_fixed_Asm_8 6379 { 2335, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2335 = VST4dWB_register_Asm_16 6380 { 2336, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2336 = VST4dWB_register_Asm_32 6381 { 2337, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2337 = VST4dWB_register_Asm_8 6382 { 2338, 8, 0, 4, 598, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2338 = VST4q16 6383 { 2339, 7, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #2339 = VST4q16Pseudo_UPD 6384 { 2340, 10, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2340 = VST4q16_UPD 6385 { 2341, 5, 0, 4, 598, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2341 = VST4q16oddPseudo 6386 { 2342, 7, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #2342 = VST4q16oddPseudo_UPD 6387 { 2343, 8, 0, 4, 598, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2343 = VST4q32 6388 { 2344, 7, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #2344 = VST4q32Pseudo_UPD 6389 { 2345, 10, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2345 = VST4q32_UPD 6390 { 2346, 5, 0, 4, 598, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2346 = VST4q32oddPseudo 6391 { 2347, 7, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #2347 = VST4q32oddPseudo_UPD 6392 { 2348, 8, 0, 4, 598, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #2348 = VST4q8 6393 { 2349, 7, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #2349 = VST4q8Pseudo_UPD 6394 { 2350, 10, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2350 = VST4q8_UPD 6395 { 2351, 5, 0, 4, 598, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #2351 = VST4q8oddPseudo 6396 { 2352, 7, 1, 4, 599, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #2352 = VST4q8oddPseudo_UPD 6397 { 2353, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2353 = VST4qAsm_16 6398 { 2354, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2354 = VST4qAsm_32 6399 { 2355, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2355 = VST4qAsm_8 6400 { 2356, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2356 = VST4qWB_fixed_Asm_16 6401 { 2357, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2357 = VST4qWB_fixed_Asm_32 6402 { 2358, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2358 = VST4qWB_fixed_Asm_8 6403 { 2359, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2359 = VST4qWB_register_Asm_16 6404 { 2360, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2360 = VST4qWB_register_Asm_32 6405 { 2361, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2361 = VST4qWB_register_Asm_8 6406 { 2362, 5, 1, 4, 539, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2362 = VSTMDDB_UPD 6407 { 2363, 4, 0, 4, 538, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8b84ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2363 = VSTMDIA 6408 { 2364, 5, 1, 4, 539, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2364 = VSTMDIA_UPD 6409 { 2365, 4, 0, 4, 535, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18004ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #2365 = VSTMQIA 6410 { 2366, 5, 1, 4, 539, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2366 = VSTMSDB_UPD 6411 { 2367, 4, 0, 4, 538, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x18b84ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2367 = VSTMSIA 6412 { 2368, 5, 1, 4, 539, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2368 = VSTMSIA_UPD 6413 { 2369, 5, 0, 4, 532, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18b05ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2369 = VSTRD 6414 { 2370, 5, 0, 4, 232, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x18b05ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2370 = VSTRH 6415 { 2371, 5, 0, 4, 533, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18b05ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #2371 = VSTRS 6416 { 2372, 5, 1, 4, 465, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2372 = VSUBD 6417 { 2373, 5, 1, 4, 96, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8800ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #2373 = VSUBH 6418 { 2374, 5, 1, 4, 438, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #2374 = VSUBHNv2i32 6419 { 2375, 5, 1, 4, 438, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #2375 = VSUBHNv4i16 6420 { 2376, 5, 1, 4, 438, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #2376 = VSUBHNv8i8 6421 { 2377, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #2377 = VSUBLsv2i64 6422 { 2378, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #2378 = VSUBLsv4i32 6423 { 2379, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #2379 = VSUBLsv8i16 6424 { 2380, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #2380 = VSUBLuv2i64 6425 { 2381, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #2381 = VSUBLuv4i32 6426 { 2382, 5, 1, 4, 396, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #2382 = VSUBLuv8i16 6427 { 2383, 5, 1, 4, 462, 0|(1ULL<<MCID::Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #2383 = VSUBS 6428 { 2384, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #2384 = VSUBWsv2i64 6429 { 2385, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #2385 = VSUBWsv4i32 6430 { 2386, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #2386 = VSUBWsv8i16 6431 { 2387, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #2387 = VSUBWuv2i64 6432 { 2388, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #2388 = VSUBWuv4i32 6433 { 2389, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #2389 = VSUBWuv8i16 6434 { 2390, 5, 1, 4, 459, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2390 = VSUBfd 6435 { 2391, 5, 1, 4, 460, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #2391 = VSUBfq 6436 { 2392, 5, 1, 4, 88, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2392 = VSUBhd 6437 { 2393, 5, 1, 4, 89, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #2393 = VSUBhq 6438 { 2394, 5, 1, 4, 412, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #2394 = VSUBv16i8 6439 { 2395, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2395 = VSUBv1i64 6440 { 2396, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2396 = VSUBv2i32 6441 { 2397, 5, 1, 4, 412, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #2397 = VSUBv2i64 6442 { 2398, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2398 = VSUBv4i16 6443 { 2399, 5, 1, 4, 412, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #2399 = VSUBv4i32 6444 { 2400, 5, 1, 4, 412, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #2400 = VSUBv8i16 6445 { 2401, 5, 1, 4, 397, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2401 = VSUBv8i8 6446 { 2402, 6, 2, 4, 450, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2402 = VSWPd 6447 { 2403, 6, 2, 4, 450, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2403 = VSWPq 6448 { 2404, 5, 1, 4, 442, 0|(1ULL<<MCID::Predicable), 0x11480ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2404 = VTBL1 6449 { 2405, 5, 1, 4, 444, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2405 = VTBL2 6450 { 2406, 5, 1, 4, 446, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2406 = VTBL3 6451 { 2407, 5, 1, 4, 446, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2407 = VTBL3Pseudo 6452 { 2408, 5, 1, 4, 448, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2408 = VTBL4 6453 { 2409, 5, 1, 4, 448, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2409 = VTBL4Pseudo 6454 { 2410, 6, 1, 4, 443, 0|(1ULL<<MCID::Predicable), 0x11480ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #2410 = VTBX1 6455 { 2411, 6, 1, 4, 445, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2411 = VTBX2 6456 { 2412, 6, 1, 4, 447, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #2412 = VTBX3 6457 { 2413, 6, 1, 4, 447, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2413 = VTBX3Pseudo 6458 { 2414, 6, 1, 4, 449, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #2414 = VTBX4 6459 { 2415, 6, 1, 4, 449, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #2415 = VTBX4Pseudo 6460 { 2416, 5, 1, 4, 503, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2416 = VTOSHD 6461 { 2417, 5, 1, 4, 504, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2417 = VTOSHH 6462 { 2418, 5, 1, 4, 505, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2418 = VTOSHS 6463 { 2419, 4, 1, 4, 506, 0|(1ULL<<MCID::Predicable), 0x8880ULL, ImplicitList10, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2419 = VTOSIRD 6464 { 2420, 4, 1, 4, 507, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, ImplicitList10, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2420 = VTOSIRH 6465 { 2421, 4, 1, 4, 508, 0|(1ULL<<MCID::Predicable), 0x8880ULL, ImplicitList10, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2421 = VTOSIRS 6466 { 2422, 4, 1, 4, 506, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2422 = VTOSIZD 6467 { 2423, 4, 1, 4, 507, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2423 = VTOSIZH 6468 { 2424, 4, 1, 4, 508, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2424 = VTOSIZS 6469 { 2425, 5, 1, 4, 503, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2425 = VTOSLD 6470 { 2426, 5, 1, 4, 504, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2426 = VTOSLH 6471 { 2427, 5, 1, 4, 505, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2427 = VTOSLS 6472 { 2428, 5, 1, 4, 503, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2428 = VTOUHD 6473 { 2429, 5, 1, 4, 504, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2429 = VTOUHH 6474 { 2430, 5, 1, 4, 505, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2430 = VTOUHS 6475 { 2431, 4, 1, 4, 506, 0|(1ULL<<MCID::Predicable), 0x8880ULL, ImplicitList10, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2431 = VTOUIRD 6476 { 2432, 4, 1, 4, 507, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, ImplicitList10, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2432 = VTOUIRH 6477 { 2433, 4, 1, 4, 508, 0|(1ULL<<MCID::Predicable), 0x8880ULL, ImplicitList10, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2433 = VTOUIRS 6478 { 2434, 4, 1, 4, 506, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #2434 = VTOUIZD 6479 { 2435, 4, 1, 4, 507, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2435 = VTOUIZH 6480 { 2436, 4, 1, 4, 508, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2436 = VTOUIZS 6481 { 2437, 5, 1, 4, 503, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2437 = VTOULD 6482 { 2438, 5, 1, 4, 504, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2438 = VTOULH 6483 { 2439, 5, 1, 4, 505, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2439 = VTOULS 6484 { 2440, 6, 2, 4, 451, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2440 = VTRNd16 6485 { 2441, 6, 2, 4, 451, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2441 = VTRNd32 6486 { 2442, 6, 2, 4, 451, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2442 = VTRNd8 6487 { 2443, 6, 2, 4, 452, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2443 = VTRNq16 6488 { 2444, 6, 2, 4, 452, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2444 = VTRNq32 6489 { 2445, 6, 2, 4, 452, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2445 = VTRNq8 6490 { 2446, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #2446 = VTSTv16i8 6491 { 2447, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2447 = VTSTv2i32 6492 { 2448, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2448 = VTSTv4i16 6493 { 2449, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #2449 = VTSTv4i32 6494 { 2450, 5, 1, 4, 403, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #2450 = VTSTv8i16 6495 { 2451, 5, 1, 4, 404, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #2451 = VTSTv8i8 6496 { 2452, 5, 1, 4, 198, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2452 = VUHTOD 6497 { 2453, 5, 1, 4, 199, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2453 = VUHTOH 6498 { 2454, 5, 1, 4, 200, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2454 = VUHTOS 6499 { 2455, 4, 1, 4, 500, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #2455 = VUITOD 6500 { 2456, 4, 1, 4, 501, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2456 = VUITOH 6501 { 2457, 4, 1, 4, 502, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #2457 = VUITOS 6502 { 2458, 5, 1, 4, 198, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2458 = VULTOD 6503 { 2459, 5, 1, 4, 199, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2459 = VULTOH 6504 { 2460, 5, 1, 4, 200, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #2460 = VULTOS 6505 { 2461, 6, 2, 4, 451, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2461 = VUZPd16 6506 { 2462, 6, 2, 4, 451, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2462 = VUZPd8 6507 { 2463, 6, 2, 4, 453, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2463 = VUZPq16 6508 { 2464, 6, 2, 4, 453, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2464 = VUZPq32 6509 { 2465, 6, 2, 4, 453, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2465 = VUZPq8 6510 { 2466, 6, 2, 4, 451, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2466 = VZIPd16 6511 { 2467, 6, 2, 4, 451, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2467 = VZIPd8 6512 { 2468, 6, 2, 4, 453, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2468 = VZIPq16 6513 { 2469, 6, 2, 4, 453, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2469 = VZIPq32 6514 { 2470, 6, 2, 4, 453, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2470 = VZIPq8 6515 { 2471, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList11, ImplicitList12, nullptr, -1 ,nullptr }, // Inst #2471 = WIN__CHKSTK 6516 { 2472, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr }, // Inst #2472 = WIN__DBZCHK 6517 { 2473, 4, 0, 4, 367, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2473 = sysLDMDA 6518 { 2474, 5, 1, 4, 368, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2474 = sysLDMDA_UPD 6519 { 2475, 4, 0, 4, 367, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2475 = sysLDMDB 6520 { 2476, 5, 1, 4, 368, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2476 = sysLDMDB_UPD 6521 { 2477, 4, 0, 4, 367, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2477 = sysLDMIA 6522 { 2478, 5, 1, 4, 368, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2478 = sysLDMIA_UPD 6523 { 2479, 4, 0, 4, 367, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2479 = sysLDMIB 6524 { 2480, 5, 1, 4, 368, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2480 = sysLDMIB_UPD 6525 { 2481, 4, 0, 4, 388, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2481 = sysSTMDA 6526 { 2482, 5, 1, 4, 389, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2482 = sysSTMDA_UPD 6527 { 2483, 4, 0, 4, 388, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2483 = sysSTMDB 6528 { 2484, 5, 1, 4, 389, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2484 = sysSTMDB_UPD 6529 { 2485, 4, 0, 4, 388, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2485 = sysSTMIA 6530 { 2486, 5, 1, 4, 389, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2486 = sysSTMIA_UPD 6531 { 2487, 4, 0, 4, 388, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2487 = sysSTMIB 6532 { 2488, 5, 1, 4, 389, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2488 = sysSTMIB_UPD 6533 { 2489, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo273, -1 ,nullptr }, // Inst #2489 = t2ABS 6534 { 2490, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo274, -1 ,nullptr }, // Inst #2490 = t2ADCri 6535 { 2491, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo275, -1 ,nullptr }, // Inst #2491 = t2ADCrr 6536 { 2492, 7, 1, 4, 59, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo276, -1 ,nullptr }, // Inst #2492 = t2ADCrs 6537 { 2493, 5, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo277, -1 ,nullptr }, // Inst #2493 = t2ADDSri 6538 { 2494, 5, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo278, -1 ,nullptr }, // Inst #2494 = t2ADDSrr 6539 { 2495, 6, 1, 4, 252, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo279, -1 ,nullptr }, // Inst #2495 = t2ADDSrs 6540 { 2496, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #2496 = t2ADDri 6541 { 2497, 5, 1, 4, 1, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #2497 = t2ADDri12 6542 { 2498, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2498 = t2ADDrr 6543 { 2499, 7, 1, 4, 59, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2499 = t2ADDrs 6544 { 2500, 4, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2500 = t2ADR 6545 { 2501, 6, 1, 4, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #2501 = t2ANDri 6546 { 2502, 6, 1, 4, 7, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2502 = t2ANDrr 6547 { 2503, 7, 1, 4, 60, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2503 = t2ANDrs 6548 { 2504, 6, 1, 4, 51, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #2504 = t2ASRri 6549 { 2505, 6, 1, 4, 50, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2505 = t2ASRrr 6550 { 2506, 3, 0, 4, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #2506 = t2B 6551 { 2507, 5, 1, 4, 311, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2507 = t2BFC 6552 { 2508, 6, 1, 4, 312, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #2508 = t2BFI 6553 { 2509, 6, 1, 4, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #2509 = t2BICri 6554 { 2510, 6, 1, 4, 7, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2510 = t2BICrr 6555 { 2511, 7, 1, 4, 60, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2511 = t2BICrs 6556 { 2512, 3, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #2512 = t2BR_JT 6557 { 2513, 3, 0, 4, 15, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #2513 = t2BXJ 6558 { 2514, 3, 0, 4, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #2514 = t2Bcc 6559 { 2515, 8, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #2515 = t2CDP 6560 { 2516, 8, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #2516 = t2CDP2 6561 { 2517, 2, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2517 = t2CLREX 6562 { 2518, 4, 1, 4, 16, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2518 = t2CLZ 6563 { 2519, 4, 0, 4, 17, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo96, -1 ,nullptr }, // Inst #2519 = t2CMNri 6564 { 2520, 4, 0, 4, 18, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo288, -1 ,nullptr }, // Inst #2520 = t2CMNzrr 6565 { 2521, 5, 0, 4, 254, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo289, -1 ,nullptr }, // Inst #2521 = t2CMNzrs 6566 { 2522, 4, 0, 4, 255, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo96, -1 ,nullptr }, // Inst #2522 = t2CMPri 6567 { 2523, 4, 0, 4, 256, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo288, -1 ,nullptr }, // Inst #2523 = t2CMPrr 6568 { 2524, 5, 0, 4, 257, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo289, -1 ,nullptr }, // Inst #2524 = t2CMPrs 6569 { 2525, 1, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #2525 = t2CPS1p 6570 { 2526, 2, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #2526 = t2CPS2p 6571 { 2527, 3, 0, 4, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #2527 = t2CPS3p 6572 { 2528, 3, 1, 4, 0, 0, 0xc80ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2528 = t2CRC32B 6573 { 2529, 3, 1, 4, 0, 0, 0xc80ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2529 = t2CRC32CB 6574 { 2530, 3, 1, 4, 0, 0, 0xc80ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2530 = t2CRC32CH 6575 { 2531, 3, 1, 4, 0, 0, 0xc80ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2531 = t2CRC32CW 6576 { 2532, 3, 1, 4, 0, 0, 0xc80ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2532 = t2CRC32H 6577 { 2533, 3, 1, 4, 0, 0, 0xc80ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2533 = t2CRC32W 6578 { 2534, 3, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2534 = t2DBG 6579 { 2535, 2, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2535 = t2DCPS1 6580 { 2536, 2, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2536 = t2DCPS2 6581 { 2537, 2, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2537 = t2DCPS3 6582 { 2538, 3, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2538 = t2DMB 6583 { 2539, 3, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2539 = t2DSB 6584 { 2540, 6, 1, 4, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #2540 = t2EORri 6585 { 2541, 6, 1, 4, 7, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2541 = t2EORrr 6586 { 2542, 7, 1, 4, 60, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2542 = t2EORrs 6587 { 2543, 3, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2543 = t2HINT 6588 { 2544, 1, 0, 4, 10, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #2544 = t2HVC 6589 { 2545, 3, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2545 = t2ISB 6590 { 2546, 2, 0, 2, 395, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList13, OperandInfo7, -1 ,&getITDeprecationInfo }, // Inst #2546 = t2IT 6591 { 2547, 2, 0, 0, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList14, OperandInfo291, -1 ,nullptr }, // Inst #2547 = t2Int_eh_sjlj_setjmp 6592 { 2548, 2, 0, 0, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList8, OperandInfo291, -1 ,nullptr }, // Inst #2548 = t2Int_eh_sjlj_setjmp_nofp 6593 { 2549, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2549 = t2LDA 6594 { 2550, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2550 = t2LDAB 6595 { 2551, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2551 = t2LDAEX 6596 { 2552, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2552 = t2LDAEXB 6597 { 2553, 5, 2, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #2553 = t2LDAEXD 6598 { 2554, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2554 = t2LDAEXH 6599 { 2555, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2555 = t2LDAH 6600 { 2556, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2556 = t2LDC2L_OFFSET 6601 { 2557, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2557 = t2LDC2L_OPTION 6602 { 2558, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2558 = t2LDC2L_POST 6603 { 2559, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2559 = t2LDC2L_PRE 6604 { 2560, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2560 = t2LDC2_OFFSET 6605 { 2561, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2561 = t2LDC2_OPTION 6606 { 2562, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2562 = t2LDC2_POST 6607 { 2563, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2563 = t2LDC2_PRE 6608 { 2564, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2564 = t2LDCL_OFFSET 6609 { 2565, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2565 = t2LDCL_OPTION 6610 { 2566, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2566 = t2LDCL_POST 6611 { 2567, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2567 = t2LDCL_PRE 6612 { 2568, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2568 = t2LDC_OFFSET 6613 { 2569, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2569 = t2LDC_OPTION 6614 { 2570, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2570 = t2LDC_POST 6615 { 2571, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2571 = t2LDC_PRE 6616 { 2572, 4, 0, 4, 367, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2572 = t2LDMDB 6617 { 2573, 5, 1, 4, 368, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2573 = t2LDMDB_UPD 6618 { 2574, 4, 0, 4, 367, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2574 = t2LDMIA 6619 { 2575, 5, 1, 4, 369, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2575 = t2LDMIA_RET 6620 { 2576, 5, 1, 4, 368, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2576 = t2LDMIA_UPD 6621 { 2577, 5, 1, 4, 360, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2577 = t2LDRBT 6622 { 2578, 6, 2, 4, 356, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #2578 = t2LDRB_POST 6623 { 2579, 6, 2, 4, 356, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #2579 = t2LDRB_PRE 6624 { 2580, 5, 1, 4, 343, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #2580 = t2LDRBi12 6625 { 2581, 5, 1, 4, 343, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #2581 = t2LDRBi8 6626 { 2582, 4, 1, 4, 343, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2582 = t2LDRBpci 6627 { 2583, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2583 = t2LDRBpcrel 6628 { 2584, 6, 1, 4, 340, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #2584 = t2LDRBs 6629 { 2585, 7, 3, 4, 366, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #2585 = t2LDRD_POST 6630 { 2586, 7, 3, 4, 366, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #2586 = t2LDRD_PRE 6631 { 2587, 6, 2, 4, 365, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc8fULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #2587 = t2LDRDi8 6632 { 2588, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #2588 = t2LDREX 6633 { 2589, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2589 = t2LDREXB 6634 { 2590, 5, 2, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #2590 = t2LDREXD 6635 { 2591, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2591 = t2LDREXH 6636 { 2592, 5, 1, 4, 360, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2592 = t2LDRHT 6637 { 2593, 6, 2, 4, 356, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #2593 = t2LDRH_POST 6638 { 2594, 6, 2, 4, 356, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #2594 = t2LDRH_PRE 6639 { 2595, 5, 1, 4, 343, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #2595 = t2LDRHi12 6640 { 2596, 5, 1, 4, 343, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #2596 = t2LDRHi8 6641 { 2597, 4, 1, 4, 343, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2597 = t2LDRHpci 6642 { 2598, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2598 = t2LDRHpcrel 6643 { 2599, 6, 1, 4, 340, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #2599 = t2LDRHs 6644 { 2600, 5, 1, 4, 362, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2600 = t2LDRSBT 6645 { 2601, 6, 2, 4, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #2601 = t2LDRSB_POST 6646 { 2602, 6, 2, 4, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #2602 = t2LDRSB_PRE 6647 { 2603, 5, 1, 4, 351, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #2603 = t2LDRSBi12 6648 { 2604, 5, 1, 4, 351, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #2604 = t2LDRSBi8 6649 { 2605, 4, 1, 4, 351, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2605 = t2LDRSBpci 6650 { 2606, 4, 0, 0, 352, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2606 = t2LDRSBpcrel 6651 { 2607, 6, 1, 4, 353, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #2607 = t2LDRSBs 6652 { 2608, 5, 1, 4, 362, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2608 = t2LDRSHT 6653 { 2609, 6, 2, 4, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #2609 = t2LDRSH_POST 6654 { 2610, 6, 2, 4, 363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #2610 = t2LDRSH_PRE 6655 { 2611, 5, 1, 4, 351, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #2611 = t2LDRSHi12 6656 { 2612, 5, 1, 4, 351, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #2612 = t2LDRSHi8 6657 { 2613, 4, 1, 4, 351, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2613 = t2LDRSHpci 6658 { 2614, 4, 0, 0, 352, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #2614 = t2LDRSHpcrel 6659 { 2615, 6, 1, 4, 353, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #2615 = t2LDRSHs 6660 { 2616, 5, 1, 4, 361, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2616 = t2LDRT 6661 { 2617, 6, 2, 4, 359, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #2617 = t2LDR_POST 6662 { 2618, 6, 2, 4, 359, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #2618 = t2LDR_PRE 6663 { 2619, 5, 1, 4, 344, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8bULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2619 = t2LDRi12 6664 { 2620, 5, 1, 4, 344, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8cULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2620 = t2LDRi8 6665 { 2621, 4, 1, 4, 344, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #2621 = t2LDRpci 6666 { 2622, 3, 1, 0, 345, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #2622 = t2LDRpci_pic 6667 { 2623, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #2623 = t2LDRpcrel 6668 { 2624, 6, 1, 4, 346, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8dULL, nullptr, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #2624 = t2LDRs 6669 { 2625, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #2625 = t2LEApcrel 6670 { 2626, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #2626 = t2LEApcrelJT 6671 { 2627, 6, 1, 4, 51, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #2627 = t2LSLri 6672 { 2628, 6, 1, 4, 50, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2628 = t2LSLrr 6673 { 2629, 6, 1, 4, 51, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #2629 = t2LSRri 6674 { 2630, 6, 1, 4, 50, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2630 = t2LSRrr 6675 { 2631, 8, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo72, -1 ,&getMCRDeprecationInfo }, // Inst #2631 = t2MCR 6676 { 2632, 8, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #2632 = t2MCR2 6677 { 2633, 7, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #2633 = t2MCRR 6678 { 2634, 7, 0, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #2634 = t2MCRR2 6679 { 2635, 6, 1, 4, 327, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2635 = t2MLA 6680 { 2636, 6, 1, 4, 327, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2636 = t2MLS 6681 { 2637, 6, 1, 4, 261, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #2637 = t2MOVCCasr 6682 { 2638, 5, 1, 4, 41, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2638 = t2MOVCCi 6683 { 2639, 5, 1, 4, 41, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2639 = t2MOVCCi16 6684 { 2640, 5, 1, 8, 306, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #2640 = t2MOVCCi32imm 6685 { 2641, 6, 1, 4, 261, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #2641 = t2MOVCClsl 6686 { 2642, 6, 1, 4, 261, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #2642 = t2MOVCClsr 6687 { 2643, 5, 1, 4, 44, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Select)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #2643 = t2MOVCCr 6688 { 2644, 6, 1, 4, 261, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #2644 = t2MOVCCror 6689 { 2645, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #2645 = t2MOVSsi 6690 { 2646, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #2646 = t2MOVSsr 6691 { 2647, 5, 1, 4, 42, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2647 = t2MOVTi16 6692 { 2648, 4, 1, 0, 42, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #2648 = t2MOVTi16_ga_pcrel 6693 { 2649, 2, 1, 0, 308, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo310, -1 ,nullptr }, // Inst #2649 = t2MOV_ga_pcrel 6694 { 2650, 5, 1, 4, 42, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #2650 = t2MOVi 6695 { 2651, 4, 1, 4, 42, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2651 = t2MOVi16 6696 { 2652, 3, 1, 0, 309, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #2652 = t2MOVi16_ga_pcrel 6697 { 2653, 2, 1, 0, 307, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo310, -1 ,nullptr }, // Inst #2653 = t2MOVi32imm 6698 { 2654, 5, 1, 4, 49, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #2654 = t2MOVr 6699 { 2655, 5, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #2655 = t2MOVsi 6700 { 2656, 6, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #2656 = t2MOVsr 6701 { 2657, 4, 1, 4, 51, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo287, -1 ,nullptr }, // Inst #2657 = t2MOVsra_flag 6702 { 2658, 4, 1, 4, 51, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo287, -1 ,nullptr }, // Inst #2658 = t2MOVsrl_flag 6703 { 2659, 8, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #2659 = t2MRC 6704 { 2660, 8, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #2660 = t2MRC2 6705 { 2661, 7, 2, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #2661 = t2MRRC 6706 { 2662, 7, 2, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #2662 = t2MRRC2 6707 { 2663, 3, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #2663 = t2MRS_AR 6708 { 2664, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2664 = t2MRS_M 6709 { 2665, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2665 = t2MRSbanked 6710 { 2666, 3, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #2666 = t2MRSsys_AR 6711 { 2667, 4, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo314, -1 ,nullptr }, // Inst #2667 = t2MSR_AR 6712 { 2668, 4, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo314, -1 ,nullptr }, // Inst #2668 = t2MSR_M 6713 { 2669, 4, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo314, -1 ,nullptr }, // Inst #2669 = t2MSRbanked 6714 { 2670, 5, 1, 4, 324, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2670 = t2MUL 6715 { 2671, 5, 1, 4, 41, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable), 0x0ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #2671 = t2MVNCCi 6716 { 2672, 5, 1, 4, 53, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #2672 = t2MVNi 6717 { 2673, 5, 1, 4, 54, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2673 = t2MVNr 6718 { 2674, 6, 1, 4, 263, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2674 = t2MVNs 6719 { 2675, 6, 1, 4, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #2675 = t2ORNri 6720 { 2676, 6, 1, 4, 7, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2676 = t2ORNrr 6721 { 2677, 7, 1, 4, 60, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2677 = t2ORNrs 6722 { 2678, 6, 1, 4, 6, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #2678 = t2ORRri 6723 { 2679, 6, 1, 4, 7, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2679 = t2ORRrr 6724 { 2680, 7, 1, 4, 60, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2680 = t2ORRrs 6725 { 2681, 6, 1, 4, 60, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2681 = t2PKHBT 6726 { 2682, 6, 1, 4, 60, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2682 = t2PKHTB 6727 { 2683, 4, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2683 = t2PLDWi12 6728 { 2684, 4, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2684 = t2PLDWi8 6729 { 2685, 5, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr }, // Inst #2685 = t2PLDWs 6730 { 2686, 4, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2686 = t2PLDi12 6731 { 2687, 4, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2687 = t2PLDi8 6732 { 2688, 3, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2688 = t2PLDpci 6733 { 2689, 5, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr }, // Inst #2689 = t2PLDs 6734 { 2690, 4, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2690 = t2PLIi12 6735 { 2691, 4, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2691 = t2PLIi8 6736 { 2692, 3, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2692 = t2PLIpci 6737 { 2693, 5, 0, 4, 61, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr }, // Inst #2693 = t2PLIs 6738 { 2694, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2694 = t2QADD 6739 { 2695, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2695 = t2QADD16 6740 { 2696, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2696 = t2QADD8 6741 { 2697, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2697 = t2QASX 6742 { 2698, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2698 = t2QDADD 6743 { 2699, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2699 = t2QDSUB 6744 { 2700, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2700 = t2QSAX 6745 { 2701, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2701 = t2QSUB 6746 { 2702, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2702 = t2QSUB16 6747 { 2703, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2703 = t2QSUB8 6748 { 2704, 4, 1, 4, 16, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2704 = t2RBIT 6749 { 2705, 4, 1, 4, 16, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2705 = t2REV 6750 { 2706, 4, 1, 4, 16, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2706 = t2REV16 6751 { 2707, 4, 1, 4, 16, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2707 = t2REVSH 6752 { 2708, 3, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #2708 = t2RFEDB 6753 { 2709, 3, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #2709 = t2RFEDBW 6754 { 2710, 3, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #2710 = t2RFEIA 6755 { 2711, 3, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #2711 = t2RFEIAW 6756 { 2712, 6, 1, 4, 51, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #2712 = t2RORri 6757 { 2713, 6, 1, 4, 50, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2713 = t2RORrr 6758 { 2714, 5, 1, 4, 51, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, ImplicitList1, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2714 = t2RRX 6759 { 2715, 5, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo321, -1 ,nullptr }, // Inst #2715 = t2RSBSri 6760 { 2716, 6, 1, 4, 59, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo322, -1 ,nullptr }, // Inst #2716 = t2RSBSrs 6761 { 2717, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #2717 = t2RSBri 6762 { 2718, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2718 = t2RSBrr 6763 { 2719, 7, 1, 4, 264, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2719 = t2RSBrs 6764 { 2720, 5, 1, 4, 316, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2720 = t2SADD16 6765 { 2721, 5, 1, 4, 316, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2721 = t2SADD8 6766 { 2722, 5, 1, 4, 316, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2722 = t2SASX 6767 { 2723, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo274, -1 ,nullptr }, // Inst #2723 = t2SBCri 6768 { 2724, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo275, -1 ,nullptr }, // Inst #2724 = t2SBCrr 6769 { 2725, 7, 1, 4, 59, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo276, -1 ,nullptr }, // Inst #2725 = t2SBCrs 6770 { 2726, 6, 1, 4, 311, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo323, -1 ,nullptr }, // Inst #2726 = t2SBFX 6771 { 2727, 5, 1, 4, 338, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2727 = t2SDIV 6772 { 2728, 5, 1, 4, 310, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #2728 = t2SEL 6773 { 2729, 1, 0, 2, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #2729 = t2SETPAN 6774 { 2730, 2, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2730 = t2SG 6775 { 2731, 5, 1, 4, 319, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2731 = t2SHADD16 6776 { 2732, 5, 1, 4, 319, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2732 = t2SHADD8 6777 { 2733, 5, 1, 4, 319, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2733 = t2SHASX 6778 { 2734, 5, 1, 4, 319, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2734 = t2SHSAX 6779 { 2735, 5, 1, 4, 319, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2735 = t2SHSUB16 6780 { 2736, 5, 1, 4, 319, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2736 = t2SHSUB8 6781 { 2737, 3, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2737 = t2SMC 6782 { 2738, 6, 1, 4, 331, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2738 = t2SMLABB 6783 { 2739, 6, 1, 4, 331, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2739 = t2SMLABT 6784 { 2740, 6, 1, 4, 334, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2740 = t2SMLAD 6785 { 2741, 6, 1, 4, 334, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2741 = t2SMLADX 6786 { 2742, 8, 2, 4, 337, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo324, -1 ,nullptr }, // Inst #2742 = t2SMLAL 6787 { 2743, 6, 2, 4, 337, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2743 = t2SMLALBB 6788 { 2744, 6, 2, 4, 337, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2744 = t2SMLALBT 6789 { 2745, 6, 2, 4, 337, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2745 = t2SMLALD 6790 { 2746, 6, 2, 4, 337, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2746 = t2SMLALDX 6791 { 2747, 6, 2, 4, 337, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2747 = t2SMLALTB 6792 { 2748, 6, 2, 4, 337, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2748 = t2SMLALTT 6793 { 2749, 6, 1, 4, 331, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2749 = t2SMLATB 6794 { 2750, 6, 1, 4, 331, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2750 = t2SMLATT 6795 { 2751, 6, 1, 4, 331, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2751 = t2SMLAWB 6796 { 2752, 6, 1, 4, 331, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2752 = t2SMLAWT 6797 { 2753, 6, 1, 4, 332, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2753 = t2SMLSD 6798 { 2754, 6, 1, 4, 332, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2754 = t2SMLSDX 6799 { 2755, 6, 2, 4, 337, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2755 = t2SMLSLD 6800 { 2756, 6, 2, 4, 337, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2756 = t2SMLSLDX 6801 { 2757, 6, 1, 4, 327, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2757 = t2SMMLA 6802 { 2758, 6, 1, 4, 327, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2758 = t2SMMLAR 6803 { 2759, 6, 1, 4, 327, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2759 = t2SMMLS 6804 { 2760, 6, 1, 4, 327, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2760 = t2SMMLSR 6805 { 2761, 5, 1, 4, 324, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2761 = t2SMMUL 6806 { 2762, 5, 1, 4, 324, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2762 = t2SMMULR 6807 { 2763, 5, 1, 4, 329, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2763 = t2SMUAD 6808 { 2764, 5, 1, 4, 329, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2764 = t2SMUADX 6809 { 2765, 5, 1, 4, 325, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2765 = t2SMULBB 6810 { 2766, 5, 1, 4, 325, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2766 = t2SMULBT 6811 { 2767, 6, 2, 4, 336, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2767 = t2SMULL 6812 { 2768, 5, 1, 4, 325, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2768 = t2SMULTB 6813 { 2769, 5, 1, 4, 325, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2769 = t2SMULTT 6814 { 2770, 5, 1, 4, 325, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2770 = t2SMULWB 6815 { 2771, 5, 1, 4, 325, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2771 = t2SMULWT 6816 { 2772, 5, 1, 4, 326, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2772 = t2SMUSD 6817 { 2773, 5, 1, 4, 326, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2773 = t2SMUSDX 6818 { 2774, 3, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2774 = t2SRSDB 6819 { 2775, 3, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2775 = t2SRSDB_UPD 6820 { 2776, 3, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2776 = t2SRSIA 6821 { 2777, 3, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2777 = t2SRSIA_UPD 6822 { 2778, 6, 1, 4, 314, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo325, -1 ,nullptr }, // Inst #2778 = t2SSAT 6823 { 2779, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #2779 = t2SSAT16 6824 { 2780, 5, 1, 4, 316, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2780 = t2SSAX 6825 { 2781, 5, 1, 4, 316, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2781 = t2SSUB16 6826 { 2782, 5, 1, 4, 316, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2782 = t2SSUB8 6827 { 2783, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2783 = t2STC2L_OFFSET 6828 { 2784, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2784 = t2STC2L_OPTION 6829 { 2785, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2785 = t2STC2L_POST 6830 { 2786, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2786 = t2STC2L_PRE 6831 { 2787, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2787 = t2STC2_OFFSET 6832 { 2788, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2788 = t2STC2_OPTION 6833 { 2789, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2789 = t2STC2_POST 6834 { 2790, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2790 = t2STC2_PRE 6835 { 2791, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2791 = t2STCL_OFFSET 6836 { 2792, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2792 = t2STCL_OPTION 6837 { 2793, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2793 = t2STCL_POST 6838 { 2794, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2794 = t2STCL_PRE 6839 { 2795, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2795 = t2STC_OFFSET 6840 { 2796, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #2796 = t2STC_OPTION 6841 { 2797, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2797 = t2STC_POST 6842 { 2798, 6, 0, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #2798 = t2STC_PRE 6843 { 2799, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2799 = t2STL 6844 { 2800, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2800 = t2STLB 6845 { 2801, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2801 = t2STLEX 6846 { 2802, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2802 = t2STLEXB 6847 { 2803, 6, 1, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #2803 = t2STLEXD 6848 { 2804, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2804 = t2STLEXH 6849 { 2805, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #2805 = t2STLH 6850 { 2806, 4, 0, 4, 388, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2806 = t2STMDB 6851 { 2807, 5, 1, 4, 389, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2807 = t2STMDB_UPD 6852 { 2808, 4, 0, 4, 388, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2808 = t2STMIA 6853 { 2809, 5, 1, 4, 389, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2809 = t2STMIA_UPD 6854 { 2810, 5, 1, 4, 384, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2810 = t2STRBT 6855 { 2811, 6, 1, 4, 381, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2811 = t2STRB_POST 6856 { 2812, 6, 1, 4, 381, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2812 = t2STRB_PRE 6857 { 2813, 6, 1, 4, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2813 = t2STRB_preidx 6858 { 2814, 5, 0, 4, 377, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2814 = t2STRBi12 6859 { 2815, 5, 0, 4, 377, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2815 = t2STRBi8 6860 { 2816, 6, 0, 4, 374, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2816 = t2STRBs 6861 { 2817, 7, 1, 4, 387, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2817 = t2STRD_POST 6862 { 2818, 7, 1, 4, 387, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2818 = t2STRD_PRE 6863 { 2819, 6, 0, 4, 386, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc8fULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #2819 = t2STRDi8 6864 { 2820, 6, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo333, -1 ,nullptr }, // Inst #2820 = t2STREX 6865 { 2821, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2821 = t2STREXB 6866 { 2822, 6, 1, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #2822 = t2STREXD 6867 { 2823, 5, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2823 = t2STREXH 6868 { 2824, 5, 1, 4, 384, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2824 = t2STRHT 6869 { 2825, 6, 1, 4, 381, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2825 = t2STRH_POST 6870 { 2826, 6, 1, 4, 383, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2826 = t2STRH_PRE 6871 { 2827, 6, 1, 4, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2827 = t2STRH_preidx 6872 { 2828, 5, 0, 4, 377, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2828 = t2STRHi12 6873 { 2829, 5, 0, 4, 377, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2829 = t2STRHi8 6874 { 2830, 6, 0, 4, 374, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2830 = t2STRHs 6875 { 2831, 5, 1, 4, 385, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2831 = t2STRT 6876 { 2832, 6, 1, 4, 383, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, nullptr, OperandInfo334, -1 ,nullptr }, // Inst #2832 = t2STR_POST 6877 { 2833, 6, 1, 4, 383, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, nullptr, OperandInfo334, -1 ,nullptr }, // Inst #2833 = t2STR_PRE 6878 { 2834, 6, 1, 4, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2834 = t2STR_preidx 6879 { 2835, 5, 0, 4, 378, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2835 = t2STRi12 6880 { 2836, 5, 0, 4, 378, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2836 = t2STRi8 6881 { 2837, 6, 0, 4, 376, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #2837 = t2STRs 6882 { 2838, 3, 0, 4, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL, nullptr, ImplicitList4, OperandInfo49, -1 ,nullptr }, // Inst #2838 = t2SUBS_PC_LR 6883 { 2839, 5, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo277, -1 ,nullptr }, // Inst #2839 = t2SUBSri 6884 { 2840, 5, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo278, -1 ,nullptr }, // Inst #2840 = t2SUBSrr 6885 { 2841, 6, 1, 4, 252, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo279, -1 ,nullptr }, // Inst #2841 = t2SUBSrs 6886 { 2842, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #2842 = t2SUBri 6887 { 2843, 5, 1, 4, 1, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #2843 = t2SUBri12 6888 { 2844, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #2844 = t2SUBrr 6889 { 2845, 7, 1, 4, 59, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2845 = t2SUBrs 6890 { 2846, 6, 1, 4, 320, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2846 = t2SXTAB 6891 { 2847, 6, 1, 4, 320, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2847 = t2SXTAB16 6892 { 2848, 6, 1, 4, 320, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2848 = t2SXTAH 6893 { 2849, 5, 1, 4, 305, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr }, // Inst #2849 = t2SXTB 6894 { 2850, 5, 1, 4, 305, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr }, // Inst #2850 = t2SXTB16 6895 { 2851, 5, 1, 4, 305, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr }, // Inst #2851 = t2SXTH 6896 { 2852, 4, 0, 4, 14, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo335, -1 ,nullptr }, // Inst #2852 = t2TBB 6897 { 2853, 4, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #2853 = t2TBB_JT 6898 { 2854, 4, 0, 4, 14, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo335, -1 ,nullptr }, // Inst #2854 = t2TBH 6899 { 2855, 4, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #2855 = t2TBH_JT 6900 { 2856, 4, 0, 4, 269, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo96, -1 ,nullptr }, // Inst #2856 = t2TEQri 6901 { 2857, 4, 0, 4, 270, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo288, -1 ,nullptr }, // Inst #2857 = t2TEQrr 6902 { 2858, 5, 0, 4, 271, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo289, -1 ,nullptr }, // Inst #2858 = t2TEQrs 6903 { 2859, 4, 0, 4, 269, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo96, -1 ,nullptr }, // Inst #2859 = t2TSTri 6904 { 2860, 4, 0, 4, 270, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo288, -1 ,nullptr }, // Inst #2860 = t2TSTrr 6905 { 2861, 5, 0, 4, 271, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo289, -1 ,nullptr }, // Inst #2861 = t2TSTrs 6906 { 2862, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #2862 = t2TT 6907 { 2863, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #2863 = t2TTA 6908 { 2864, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #2864 = t2TTAT 6909 { 2865, 4, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #2865 = t2TTT 6910 { 2866, 5, 1, 4, 316, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2866 = t2UADD16 6911 { 2867, 5, 1, 4, 316, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2867 = t2UADD8 6912 { 2868, 5, 1, 4, 316, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2868 = t2UASX 6913 { 2869, 6, 1, 4, 311, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo323, -1 ,nullptr }, // Inst #2869 = t2UBFX 6914 { 2870, 1, 0, 4, 77, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #2870 = t2UDF 6915 { 2871, 5, 1, 4, 338, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2871 = t2UDIV 6916 { 2872, 5, 1, 4, 319, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2872 = t2UHADD16 6917 { 2873, 5, 1, 4, 319, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2873 = t2UHADD8 6918 { 2874, 5, 1, 4, 319, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2874 = t2UHASX 6919 { 2875, 5, 1, 4, 319, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2875 = t2UHSAX 6920 { 2876, 5, 1, 4, 319, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2876 = t2UHSUB16 6921 { 2877, 5, 1, 4, 319, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2877 = t2UHSUB8 6922 { 2878, 6, 2, 4, 337, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2878 = t2UMAAL 6923 { 2879, 8, 2, 4, 337, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo324, -1 ,nullptr }, // Inst #2879 = t2UMLAL 6924 { 2880, 6, 2, 4, 336, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2880 = t2UMULL 6925 { 2881, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2881 = t2UQADD16 6926 { 2882, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2882 = t2UQADD8 6927 { 2883, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2883 = t2UQASX 6928 { 2884, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2884 = t2UQSAX 6929 { 2885, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2885 = t2UQSUB16 6930 { 2886, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2886 = t2UQSUB8 6931 { 2887, 5, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2887 = t2USAD8 6932 { 2888, 6, 1, 4, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2888 = t2USADA8 6933 { 2889, 6, 1, 4, 314, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo325, -1 ,nullptr }, // Inst #2889 = t2USAT 6934 { 2890, 5, 1, 4, 314, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #2890 = t2USAT16 6935 { 2891, 5, 1, 4, 316, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2891 = t2USAX 6936 { 2892, 5, 1, 4, 316, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2892 = t2USUB16 6937 { 2893, 5, 1, 4, 316, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2893 = t2USUB8 6938 { 2894, 6, 1, 4, 320, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2894 = t2UXTAB 6939 { 2895, 6, 1, 4, 320, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2895 = t2UXTAB16 6940 { 2896, 6, 1, 4, 320, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2896 = t2UXTAH 6941 { 2897, 5, 1, 4, 305, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr }, // Inst #2897 = t2UXTB 6942 { 2898, 5, 1, 4, 305, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr }, // Inst #2898 = t2UXTB16 6943 { 2899, 5, 1, 4, 305, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr }, // Inst #2899 = t2UXTH 6944 { 2900, 6, 2, 2, 272, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, ImplicitList1, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2900 = tADC 6945 { 2901, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo338, -1 ,nullptr }, // Inst #2901 = tADDframe 6946 { 2902, 5, 1, 2, 272, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #2902 = tADDhirr 6947 { 2903, 6, 2, 2, 273, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo339, -1 ,nullptr }, // Inst #2903 = tADDi3 6948 { 2904, 6, 2, 2, 273, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr }, // Inst #2904 = tADDi8 6949 { 2905, 5, 1, 2, 272, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2905 = tADDrSP 6950 { 2906, 5, 1, 2, 273, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2906 = tADDrSPi 6951 { 2907, 6, 2, 2, 272, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2907 = tADDrr 6952 { 2908, 5, 1, 2, 273, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2908 = tADDspi 6953 { 2909, 5, 1, 2, 272, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #2909 = tADDspr 6954 { 2910, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #2910 = tADJCALLSTACKDOWN 6955 { 2911, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo8, -1 ,nullptr }, // Inst #2911 = tADJCALLSTACKUP 6956 { 2912, 4, 1, 2, 273, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo346, -1 ,nullptr }, // Inst #2912 = tADR 6957 { 2913, 6, 2, 2, 274, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2913 = tAND 6958 { 2914, 6, 2, 2, 51, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo339, -1 ,nullptr }, // Inst #2914 = tASRri 6959 { 2915, 6, 2, 2, 50, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2915 = tASRrr 6960 { 2916, 3, 0, 2, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #2916 = tB 6961 { 2917, 6, 2, 2, 274, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2917 = tBIC 6962 { 2918, 1, 0, 2, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #2918 = tBKPT 6963 { 2919, 3, 0, 4, 12, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo347, -1 ,nullptr }, // Inst #2919 = tBL 6964 { 2920, 3, 0, 2, 12, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo348, -1 ,nullptr }, // Inst #2920 = tBLXNSr 6965 { 2921, 3, 0, 4, 12, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo347, -1 ,nullptr }, // Inst #2921 = tBLXi 6966 { 2922, 3, 0, 2, 12, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo349, -1 ,nullptr }, // Inst #2922 = tBLXr 6967 { 2923, 3, 0, 2, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #2923 = tBRIND 6968 { 2924, 2, 0, 2, 14, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo350, -1 ,nullptr }, // Inst #2924 = tBR_JTr 6969 { 2925, 3, 0, 2, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #2925 = tBX 6970 { 2926, 3, 0, 2, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #2926 = tBXNS 6971 { 2927, 1, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo37, -1 ,nullptr }, // Inst #2927 = tBX_CALL 6972 { 2928, 2, 0, 2, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2928 = tBX_RET 6973 { 2929, 3, 0, 2, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo351, -1 ,nullptr }, // Inst #2929 = tBX_RET_vararg 6974 { 2930, 3, 0, 2, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #2930 = tBcc 6975 { 2931, 3, 0, 4, 14, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo36, -1 ,nullptr }, // Inst #2931 = tBfar 6976 { 2932, 2, 0, 2, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo352, -1 ,nullptr }, // Inst #2932 = tCBNZ 6977 { 2933, 2, 0, 2, 10, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo352, -1 ,nullptr }, // Inst #2933 = tCBZ 6978 { 2934, 4, 0, 2, 256, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo353, -1 ,nullptr }, // Inst #2934 = tCMNz 6979 { 2935, 4, 0, 2, 256, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr }, // Inst #2935 = tCMPhir 6980 { 2936, 4, 0, 2, 255, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo354, -1 ,nullptr }, // Inst #2936 = tCMPi8 6981 { 2937, 4, 0, 2, 256, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo353, -1 ,nullptr }, // Inst #2937 = tCMPr 6982 { 2938, 2, 0, 2, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #2938 = tCPS 6983 { 2939, 6, 2, 2, 274, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2939 = tEOR 6984 { 2940, 3, 0, 2, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2940 = tHINT 6985 { 2941, 1, 0, 2, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #2941 = tHLT 6986 { 2942, 2, 0, 0, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList6, OperandInfo13, -1 ,nullptr }, // Inst #2942 = tInt_eh_sjlj_longjmp 6987 { 2943, 2, 0, 0, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList15, OperandInfo291, -1 ,nullptr }, // Inst #2943 = tInt_eh_sjlj_setjmp 6988 { 2944, 4, 0, 2, 367, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo355, -1 ,nullptr }, // Inst #2944 = tLDMIA 6989 { 2945, 5, 1, 2, 368, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2945 = tLDMIA_UPD 6990 { 2946, 5, 1, 2, 343, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc87ULL, nullptr, nullptr, OperandInfo356, -1 ,nullptr }, // Inst #2946 = tLDRBi 6991 { 2947, 5, 1, 2, 347, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc87ULL, nullptr, nullptr, OperandInfo357, -1 ,nullptr }, // Inst #2947 = tLDRBr 6992 { 2948, 5, 1, 2, 343, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc88ULL, nullptr, nullptr, OperandInfo356, -1 ,nullptr }, // Inst #2948 = tLDRHi 6993 { 2949, 5, 1, 2, 347, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc88ULL, nullptr, nullptr, OperandInfo357, -1 ,nullptr }, // Inst #2949 = tLDRHr 6994 { 2950, 2, 1, 0, 391, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo350, -1 ,nullptr }, // Inst #2950 = tLDRLIT_ga_abs 6995 { 2951, 2, 1, 0, 392, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo350, -1 ,nullptr }, // Inst #2951 = tLDRLIT_ga_pcrel 6996 { 2952, 5, 1, 2, 354, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc87ULL, nullptr, nullptr, OperandInfo357, -1 ,nullptr }, // Inst #2952 = tLDRSB 6997 { 2953, 5, 1, 2, 354, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc88ULL, nullptr, nullptr, OperandInfo357, -1 ,nullptr }, // Inst #2953 = tLDRSH 6998 { 2954, 5, 1, 2, 344, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc89ULL, nullptr, nullptr, OperandInfo356, -1 ,nullptr }, // Inst #2954 = tLDRi 6999 { 2955, 4, 1, 2, 344, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8aULL, nullptr, nullptr, OperandInfo346, -1 ,nullptr }, // Inst #2955 = tLDRpci 7000 { 2956, 3, 1, 0, 341, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #2956 = tLDRpci_pic 7001 { 2957, 5, 1, 2, 348, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc89ULL, nullptr, nullptr, OperandInfo357, -1 ,nullptr }, // Inst #2957 = tLDRr 7002 { 2958, 5, 1, 2, 344, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8aULL, nullptr, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #2958 = tLDRspi 7003 { 2959, 4, 1, 2, 273, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #2959 = tLEApcrel 7004 { 2960, 4, 1, 2, 273, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo359, -1 ,nullptr }, // Inst #2960 = tLEApcrelJT 7005 { 2961, 6, 2, 2, 51, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo339, -1 ,nullptr }, // Inst #2961 = tLSLri 7006 { 2962, 6, 2, 2, 50, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2962 = tLSLrr 7007 { 2963, 6, 2, 2, 51, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo339, -1 ,nullptr }, // Inst #2963 = tLSRri 7008 { 2964, 6, 2, 2, 50, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2964 = tLSRrr 7009 { 2965, 5, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo360, -1 ,nullptr }, // Inst #2965 = tMOVCCr_pseudo 7010 { 2966, 2, 1, 2, 49, 0, 0xc80ULL, nullptr, ImplicitList1, OperandInfo291, -1 ,nullptr }, // Inst #2966 = tMOVSr 7011 { 2967, 5, 2, 2, 42, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo361, -1 ,nullptr }, // Inst #2967 = tMOVi8 7012 { 2968, 4, 1, 2, 49, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #2968 = tMOVr 7013 { 2969, 6, 2, 2, 52, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #2969 = tMUL 7014 { 2970, 5, 2, 2, 54, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo363, -1 ,nullptr }, // Inst #2970 = tMVN 7015 { 2971, 6, 2, 2, 274, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2971 = tORR 7016 { 2972, 3, 1, 2, 272, 0|(1ULL<<MCID::NotDuplicable), 0xc80ULL, nullptr, nullptr, OperandInfo364, -1 ,nullptr }, // Inst #2972 = tPICADD 7017 { 2973, 3, 0, 2, 370, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL, ImplicitList2, ImplicitList2, OperandInfo365, -1 ,nullptr }, // Inst #2973 = tPOP 7018 { 2974, 3, 0, 2, 371, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo365, -1 ,nullptr }, // Inst #2974 = tPOP_RET 7019 { 2975, 3, 0, 2, 390, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, ImplicitList2, ImplicitList2, OperandInfo365, -1 ,nullptr }, // Inst #2975 = tPUSH 7020 { 2976, 4, 1, 2, 16, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo353, -1 ,nullptr }, // Inst #2976 = tREV 7021 { 2977, 4, 1, 2, 16, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo353, -1 ,nullptr }, // Inst #2977 = tREV16 7022 { 2978, 4, 1, 2, 16, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo353, -1 ,nullptr }, // Inst #2978 = tREVSH 7023 { 2979, 6, 2, 2, 50, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2979 = tROR 7024 { 2980, 5, 2, 2, 273, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo363, -1 ,nullptr }, // Inst #2980 = tRSB 7025 { 2981, 6, 2, 2, 272, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, ImplicitList1, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2981 = tSBC 7026 { 2982, 1, 0, 2, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5, ARM::HasV8Ops ,nullptr }, // Inst #2982 = tSETEND 7027 { 2983, 5, 1, 2, 389, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #2983 = tSTMIA_UPD 7028 { 2984, 5, 0, 2, 377, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc87ULL, nullptr, nullptr, OperandInfo356, -1 ,nullptr }, // Inst #2984 = tSTRBi 7029 { 2985, 5, 0, 2, 373, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc87ULL, nullptr, nullptr, OperandInfo357, -1 ,nullptr }, // Inst #2985 = tSTRBr 7030 { 2986, 5, 0, 2, 377, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc88ULL, nullptr, nullptr, OperandInfo356, -1 ,nullptr }, // Inst #2986 = tSTRHi 7031 { 2987, 5, 0, 2, 373, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc88ULL, nullptr, nullptr, OperandInfo357, -1 ,nullptr }, // Inst #2987 = tSTRHr 7032 { 2988, 5, 0, 2, 378, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc89ULL, nullptr, nullptr, OperandInfo356, -1 ,nullptr }, // Inst #2988 = tSTRi 7033 { 2989, 5, 0, 2, 372, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc89ULL, nullptr, nullptr, OperandInfo357, -1 ,nullptr }, // Inst #2989 = tSTRr 7034 { 2990, 5, 0, 2, 378, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8aULL, nullptr, nullptr, OperandInfo358, -1 ,nullptr }, // Inst #2990 = tSTRspi 7035 { 2991, 6, 2, 2, 273, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo339, -1 ,nullptr }, // Inst #2991 = tSUBi3 7036 { 2992, 6, 2, 2, 273, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr }, // Inst #2992 = tSUBi8 7037 { 2993, 6, 2, 2, 272, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2993 = tSUBrr 7038 { 2994, 5, 1, 2, 273, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2994 = tSUBspi 7039 { 2995, 3, 0, 2, 10, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList2, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #2995 = tSVC 7040 { 2996, 4, 1, 2, 16, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo353, -1 ,nullptr }, // Inst #2996 = tSXTB 7041 { 2997, 4, 1, 2, 16, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo353, -1 ,nullptr }, // Inst #2997 = tSXTH 7042 { 2998, 3, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #2998 = tTAILJMPd 7043 { 2999, 3, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #2999 = tTAILJMPdND 7044 { 3000, 1, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #3000 = tTAILJMPr 7045 { 3001, 0, 0, 4, 10, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL, ImplicitList2, ImplicitList9, nullptr, -1 ,nullptr }, // Inst #3001 = tTPsoft 7046 { 3002, 0, 0, 2, 10, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #3002 = tTRAP 7047 { 3003, 4, 0, 2, 277, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo353, -1 ,nullptr }, // Inst #3003 = tTST 7048 { 3004, 1, 0, 2, 77, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #3004 = tUDF 7049 { 3005, 4, 1, 2, 16, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo353, -1 ,nullptr }, // Inst #3005 = tUXTB 7050 { 3006, 4, 1, 2, 16, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo353, -1 ,nullptr }, // Inst #3006 = tUXTH 7051}; 7052 7053static inline void InitARMMCInstrInfo(MCInstrInfo *II) { 7054 II->InitMCInstrInfo(ARMInsts, NULL, NULL, 3007); 7055} 7056 7057} // end llvm namespace 7058#endif // GET_INSTRINFO_MC_DESC 7059 7060 7061#ifdef GET_INSTRINFO_HEADER 7062#undef GET_INSTRINFO_HEADER 7063namespace llvm { 7064struct ARMGenInstrInfo : public TargetInstrInfo { 7065 explicit ARMGenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1); 7066 ~ARMGenInstrInfo() override {} 7067}; 7068} // end llvm namespace 7069#endif // GET_INSTRINFO_HEADER 7070 7071 7072#ifdef GET_INSTRINFO_OPERAND_ENUM 7073#undef GET_INSTRINFO_OPERAND_ENUM 7074namespace llvm { 7075namespace ARM { 7076namespace OpName { 7077enum { 7078OPERAND_LAST 7079}; 7080} // end namespace OpName 7081} // end namespace ARM 7082} // end namespace llvm 7083#endif //GET_INSTRINFO_OPERAND_ENUM 7084#ifdef GET_INSTRINFO_NAMED_OPS 7085#undef GET_INSTRINFO_NAMED_OPS 7086namespace llvm { 7087namespace ARM { 7088LLVM_READONLY 7089int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) { 7090 return -1; 7091} 7092} // end namespace ARM 7093} // end namespace llvm 7094#endif //GET_INSTRINFO_NAMED_OPS 7095 7096#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM 7097#undef GET_INSTRINFO_OPERAND_TYPES_ENUM 7098namespace llvm { 7099namespace ARM { 7100namespace OpTypes { 7101enum OperandType { 7102 VecListFourDByteIndexed = 0, 7103 VecListFourDHWordIndexed = 1, 7104 VecListFourDWordIndexed = 2, 7105 VecListFourQHWordIndexed = 3, 7106 VecListFourQWordIndexed = 4, 7107 VecListOneDByteIndexed = 5, 7108 VecListOneDHWordIndexed = 6, 7109 VecListOneDWordIndexed = 7, 7110 VecListThreeDByteIndexed = 8, 7111 VecListThreeDHWordIndexed = 9, 7112 VecListThreeDWordIndexed = 10, 7113 VecListThreeQHWordIndexed = 11, 7114 VecListThreeQWordIndexed = 12, 7115 VecListTwoDByteIndexed = 13, 7116 VecListTwoDHWordIndexed = 14, 7117 VecListTwoDWordIndexed = 15, 7118 VecListTwoQHWordIndexed = 16, 7119 VecListTwoQWordIndexed = 17, 7120 VectorIndex16 = 18, 7121 VectorIndex32 = 19, 7122 VectorIndex8 = 20, 7123 addr_offset_none = 21, 7124 addrmode2 = 22, 7125 addrmode3 = 23, 7126 addrmode3_pre = 24, 7127 addrmode5 = 25, 7128 addrmode5_pre = 26, 7129 addrmode5fp16 = 27, 7130 addrmode6 = 28, 7131 addrmode6align16 = 29, 7132 addrmode6align32 = 30, 7133 addrmode6align64 = 31, 7134 addrmode6align64or128 = 32, 7135 addrmode6align64or128or256 = 33, 7136 addrmode6alignNone = 34, 7137 addrmode6dup = 35, 7138 addrmode6dupalign16 = 36, 7139 addrmode6dupalign32 = 37, 7140 addrmode6dupalign64 = 38, 7141 addrmode6dupalign64or128 = 39, 7142 addrmode6dupalignNone = 40, 7143 addrmode6oneL32 = 41, 7144 addrmode_imm12 = 42, 7145 addrmode_imm12_pre = 43, 7146 addrmode_tbb = 44, 7147 addrmode_tbh = 45, 7148 addrmodepc = 46, 7149 adrlabel = 47, 7150 am2offset_imm = 48, 7151 am2offset_reg = 49, 7152 am3offset = 50, 7153 am6offset = 51, 7154 banked_reg = 52, 7155 bf_inv_mask_imm = 53, 7156 bl_target = 54, 7157 bltarget = 55, 7158 blx_target = 56, 7159 br_target = 57, 7160 brtarget = 58, 7161 c_imm = 59, 7162 cc_out = 60, 7163 cmovpred = 61, 7164 coproc_option_imm = 62, 7165 cpinst_operand = 63, 7166 dpr_reglist = 64, 7167 f32imm = 65, 7168 f64imm = 66, 7169 fbits16 = 67, 7170 fbits32 = 68, 7171 i16imm = 69, 7172 i1imm = 70, 7173 i32imm = 71, 7174 i64imm = 72, 7175 i8imm = 73, 7176 iflags_op = 74, 7177 imm0_1 = 75, 7178 imm0_15 = 76, 7179 imm0_239 = 77, 7180 imm0_255 = 78, 7181 imm0_3 = 79, 7182 imm0_31 = 80, 7183 imm0_32 = 81, 7184 imm0_4095 = 82, 7185 imm0_4095_neg = 83, 7186 imm0_63 = 84, 7187 imm0_65535 = 85, 7188 imm0_65535_expr = 86, 7189 imm0_65535_neg = 87, 7190 imm0_7 = 88, 7191 imm16 = 89, 7192 imm1_15 = 90, 7193 imm1_16 = 91, 7194 imm1_31 = 92, 7195 imm1_32 = 93, 7196 imm1_7 = 94, 7197 imm24b = 95, 7198 imm256_65535_expr = 96, 7199 imm32 = 97, 7200 imm8 = 98, 7201 imm_sr = 99, 7202 imod_op = 100, 7203 instsyncb_opt = 101, 7204 it_mask = 102, 7205 it_pred = 103, 7206 ldst_so_reg = 104, 7207 ldstm_mode = 105, 7208 memb_opt = 106, 7209 mod_imm = 107, 7210 mod_imm_neg = 108, 7211 mod_imm_not = 109, 7212 msr_mask = 110, 7213 nImmSplatI16 = 111, 7214 nImmSplatI32 = 112, 7215 nImmSplatI64 = 113, 7216 nImmSplatI8 = 114, 7217 nImmSplatNotI16 = 115, 7218 nImmSplatNotI32 = 116, 7219 nImmVMOVF32 = 117, 7220 nImmVMOVI16ByteReplicate = 118, 7221 nImmVMOVI32 = 119, 7222 nImmVMOVI32ByteReplicate = 120, 7223 nImmVMOVI32Neg = 121, 7224 nImmVMVNI16ByteReplicate = 122, 7225 nImmVMVNI32ByteReplicate = 123, 7226 nModImm = 124, 7227 neon_vcvt_imm32 = 125, 7228 nohash_imm = 126, 7229 p_imm = 127, 7230 pclabel = 128, 7231 pkh_asr_amt = 129, 7232 pkh_lsl_amt = 130, 7233 postidx_imm8 = 131, 7234 postidx_imm8s4 = 132, 7235 postidx_reg = 133, 7236 pred = 134, 7237 reglist = 135, 7238 rot_imm = 136, 7239 s_cc_out = 137, 7240 setend_op = 138, 7241 shift_imm = 139, 7242 shift_so_reg_imm = 140, 7243 shift_so_reg_reg = 141, 7244 shr_imm16 = 142, 7245 shr_imm32 = 143, 7246 shr_imm64 = 144, 7247 shr_imm8 = 145, 7248 so_reg_imm = 146, 7249 so_reg_reg = 147, 7250 spr_reglist = 148, 7251 t2_shift_imm = 149, 7252 t2_so_imm = 150, 7253 t2_so_imm_neg = 151, 7254 t2_so_imm_not = 152, 7255 t2_so_imm_notSext = 153, 7256 t2_so_reg = 154, 7257 t2addrmode_imm0_1020s4 = 155, 7258 t2addrmode_imm12 = 156, 7259 t2addrmode_imm8 = 157, 7260 t2addrmode_imm8_pre = 158, 7261 t2addrmode_imm8s4 = 159, 7262 t2addrmode_imm8s4_pre = 160, 7263 t2addrmode_negimm8 = 161, 7264 t2addrmode_posimm8 = 162, 7265 t2addrmode_so_reg = 163, 7266 t2adrlabel = 164, 7267 t2am_imm8_offset = 165, 7268 t2am_imm8s4_offset = 166, 7269 t2ldr_pcrel_imm12 = 167, 7270 t2ldrlabel = 168, 7271 t_addrmode_is1 = 169, 7272 t_addrmode_is2 = 170, 7273 t_addrmode_is4 = 171, 7274 t_addrmode_pc = 172, 7275 t_addrmode_rr = 173, 7276 t_addrmode_rrs1 = 174, 7277 t_addrmode_rrs2 = 175, 7278 t_addrmode_rrs4 = 176, 7279 t_addrmode_sp = 177, 7280 t_adrlabel = 178, 7281 t_bcctarget = 179, 7282 t_bltarget = 180, 7283 t_blxtarget = 181, 7284 t_brtarget = 182, 7285 t_cbtarget = 183, 7286 t_imm0_1020s4 = 184, 7287 t_imm0_508s4 = 185, 7288 t_imm0_508s4_neg = 186, 7289 uncondbrtarget = 187, 7290 vfp_f16imm = 188, 7291 vfp_f32imm = 189, 7292 vfp_f64imm = 190, 7293 OPERAND_TYPE_LIST_END 7294}; 7295} // end namespace OpTypes 7296} // end namespace ARM 7297} // end namespace llvm 7298#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM 7299