1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Target Register Enum Values *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10#ifdef GET_REGINFO_ENUM 11#undef GET_REGINFO_ENUM 12namespace llvm { 13 14class MCRegisterClass; 15extern const MCRegisterClass MipsMCRegisterClasses[]; 16 17namespace Mips { 18enum { 19 NoRegister, 20 AT = 1, 21 DSPCCond = 2, 22 DSPCarry = 3, 23 DSPEFI = 4, 24 DSPOutFlag = 5, 25 DSPPos = 6, 26 DSPSCount = 7, 27 FP = 8, 28 GP = 9, 29 MSAAccess = 10, 30 MSACSR = 11, 31 MSAIR = 12, 32 MSAMap = 13, 33 MSAModify = 14, 34 MSARequest = 15, 35 MSASave = 16, 36 MSAUnmap = 17, 37 PC = 18, 38 RA = 19, 39 SP = 20, 40 ZERO = 21, 41 A0 = 22, 42 A1 = 23, 43 A2 = 24, 44 A3 = 25, 45 AC0 = 26, 46 AC1 = 27, 47 AC2 = 28, 48 AC3 = 29, 49 AT_64 = 30, 50 COP00 = 31, 51 COP01 = 32, 52 COP02 = 33, 53 COP03 = 34, 54 COP04 = 35, 55 COP05 = 36, 56 COP06 = 37, 57 COP07 = 38, 58 COP08 = 39, 59 COP09 = 40, 60 COP20 = 41, 61 COP21 = 42, 62 COP22 = 43, 63 COP23 = 44, 64 COP24 = 45, 65 COP25 = 46, 66 COP26 = 47, 67 COP27 = 48, 68 COP28 = 49, 69 COP29 = 50, 70 COP30 = 51, 71 COP31 = 52, 72 COP32 = 53, 73 COP33 = 54, 74 COP34 = 55, 75 COP35 = 56, 76 COP36 = 57, 77 COP37 = 58, 78 COP38 = 59, 79 COP39 = 60, 80 COP010 = 61, 81 COP011 = 62, 82 COP012 = 63, 83 COP013 = 64, 84 COP014 = 65, 85 COP015 = 66, 86 COP016 = 67, 87 COP017 = 68, 88 COP018 = 69, 89 COP019 = 70, 90 COP020 = 71, 91 COP021 = 72, 92 COP022 = 73, 93 COP023 = 74, 94 COP024 = 75, 95 COP025 = 76, 96 COP026 = 77, 97 COP027 = 78, 98 COP028 = 79, 99 COP029 = 80, 100 COP030 = 81, 101 COP031 = 82, 102 COP210 = 83, 103 COP211 = 84, 104 COP212 = 85, 105 COP213 = 86, 106 COP214 = 87, 107 COP215 = 88, 108 COP216 = 89, 109 COP217 = 90, 110 COP218 = 91, 111 COP219 = 92, 112 COP220 = 93, 113 COP221 = 94, 114 COP222 = 95, 115 COP223 = 96, 116 COP224 = 97, 117 COP225 = 98, 118 COP226 = 99, 119 COP227 = 100, 120 COP228 = 101, 121 COP229 = 102, 122 COP230 = 103, 123 COP231 = 104, 124 COP310 = 105, 125 COP311 = 106, 126 COP312 = 107, 127 COP313 = 108, 128 COP314 = 109, 129 COP315 = 110, 130 COP316 = 111, 131 COP317 = 112, 132 COP318 = 113, 133 COP319 = 114, 134 COP320 = 115, 135 COP321 = 116, 136 COP322 = 117, 137 COP323 = 118, 138 COP324 = 119, 139 COP325 = 120, 140 COP326 = 121, 141 COP327 = 122, 142 COP328 = 123, 143 COP329 = 124, 144 COP330 = 125, 145 COP331 = 126, 146 D0 = 127, 147 D1 = 128, 148 D2 = 129, 149 D3 = 130, 150 D4 = 131, 151 D5 = 132, 152 D6 = 133, 153 D7 = 134, 154 D8 = 135, 155 D9 = 136, 156 D10 = 137, 157 D11 = 138, 158 D12 = 139, 159 D13 = 140, 160 D14 = 141, 161 D15 = 142, 162 DSPOutFlag20 = 143, 163 DSPOutFlag21 = 144, 164 DSPOutFlag22 = 145, 165 DSPOutFlag23 = 146, 166 F0 = 147, 167 F1 = 148, 168 F2 = 149, 169 F3 = 150, 170 F4 = 151, 171 F5 = 152, 172 F6 = 153, 173 F7 = 154, 174 F8 = 155, 175 F9 = 156, 176 F10 = 157, 177 F11 = 158, 178 F12 = 159, 179 F13 = 160, 180 F14 = 161, 181 F15 = 162, 182 F16 = 163, 183 F17 = 164, 184 F18 = 165, 185 F19 = 166, 186 F20 = 167, 187 F21 = 168, 188 F22 = 169, 189 F23 = 170, 190 F24 = 171, 191 F25 = 172, 192 F26 = 173, 193 F27 = 174, 194 F28 = 175, 195 F29 = 176, 196 F30 = 177, 197 F31 = 178, 198 FCC0 = 179, 199 FCC1 = 180, 200 FCC2 = 181, 201 FCC3 = 182, 202 FCC4 = 183, 203 FCC5 = 184, 204 FCC6 = 185, 205 FCC7 = 186, 206 FCR0 = 187, 207 FCR1 = 188, 208 FCR2 = 189, 209 FCR3 = 190, 210 FCR4 = 191, 211 FCR5 = 192, 212 FCR6 = 193, 213 FCR7 = 194, 214 FCR8 = 195, 215 FCR9 = 196, 216 FCR10 = 197, 217 FCR11 = 198, 218 FCR12 = 199, 219 FCR13 = 200, 220 FCR14 = 201, 221 FCR15 = 202, 222 FCR16 = 203, 223 FCR17 = 204, 224 FCR18 = 205, 225 FCR19 = 206, 226 FCR20 = 207, 227 FCR21 = 208, 228 FCR22 = 209, 229 FCR23 = 210, 230 FCR24 = 211, 231 FCR25 = 212, 232 FCR26 = 213, 233 FCR27 = 214, 234 FCR28 = 215, 235 FCR29 = 216, 236 FCR30 = 217, 237 FCR31 = 218, 238 FP_64 = 219, 239 F_HI0 = 220, 240 F_HI1 = 221, 241 F_HI2 = 222, 242 F_HI3 = 223, 243 F_HI4 = 224, 244 F_HI5 = 225, 245 F_HI6 = 226, 246 F_HI7 = 227, 247 F_HI8 = 228, 248 F_HI9 = 229, 249 F_HI10 = 230, 250 F_HI11 = 231, 251 F_HI12 = 232, 252 F_HI13 = 233, 253 F_HI14 = 234, 254 F_HI15 = 235, 255 F_HI16 = 236, 256 F_HI17 = 237, 257 F_HI18 = 238, 258 F_HI19 = 239, 259 F_HI20 = 240, 260 F_HI21 = 241, 261 F_HI22 = 242, 262 F_HI23 = 243, 263 F_HI24 = 244, 264 F_HI25 = 245, 265 F_HI26 = 246, 266 F_HI27 = 247, 267 F_HI28 = 248, 268 F_HI29 = 249, 269 F_HI30 = 250, 270 F_HI31 = 251, 271 GP_64 = 252, 272 HI0 = 253, 273 HI1 = 254, 274 HI2 = 255, 275 HI3 = 256, 276 HWR0 = 257, 277 HWR1 = 258, 278 HWR2 = 259, 279 HWR3 = 260, 280 HWR4 = 261, 281 HWR5 = 262, 282 HWR6 = 263, 283 HWR7 = 264, 284 HWR8 = 265, 285 HWR9 = 266, 286 HWR10 = 267, 287 HWR11 = 268, 288 HWR12 = 269, 289 HWR13 = 270, 290 HWR14 = 271, 291 HWR15 = 272, 292 HWR16 = 273, 293 HWR17 = 274, 294 HWR18 = 275, 295 HWR19 = 276, 296 HWR20 = 277, 297 HWR21 = 278, 298 HWR22 = 279, 299 HWR23 = 280, 300 HWR24 = 281, 301 HWR25 = 282, 302 HWR26 = 283, 303 HWR27 = 284, 304 HWR28 = 285, 305 HWR29 = 286, 306 HWR30 = 287, 307 HWR31 = 288, 308 K0 = 289, 309 K1 = 290, 310 LO0 = 291, 311 LO1 = 292, 312 LO2 = 293, 313 LO3 = 294, 314 MPL0 = 295, 315 MPL1 = 296, 316 MPL2 = 297, 317 P0 = 298, 318 P1 = 299, 319 P2 = 300, 320 RA_64 = 301, 321 S0 = 302, 322 S1 = 303, 323 S2 = 304, 324 S3 = 305, 325 S4 = 306, 326 S5 = 307, 327 S6 = 308, 328 S7 = 309, 329 SP_64 = 310, 330 T0 = 311, 331 T1 = 312, 332 T2 = 313, 333 T3 = 314, 334 T4 = 315, 335 T5 = 316, 336 T6 = 317, 337 T7 = 318, 338 T8 = 319, 339 T9 = 320, 340 V0 = 321, 341 V1 = 322, 342 W0 = 323, 343 W1 = 324, 344 W2 = 325, 345 W3 = 326, 346 W4 = 327, 347 W5 = 328, 348 W6 = 329, 349 W7 = 330, 350 W8 = 331, 351 W9 = 332, 352 W10 = 333, 353 W11 = 334, 354 W12 = 335, 355 W13 = 336, 356 W14 = 337, 357 W15 = 338, 358 W16 = 339, 359 W17 = 340, 360 W18 = 341, 361 W19 = 342, 362 W20 = 343, 363 W21 = 344, 364 W22 = 345, 365 W23 = 346, 366 W24 = 347, 367 W25 = 348, 368 W26 = 349, 369 W27 = 350, 370 W28 = 351, 371 W29 = 352, 372 W30 = 353, 373 W31 = 354, 374 ZERO_64 = 355, 375 A0_64 = 356, 376 A1_64 = 357, 377 A2_64 = 358, 378 A3_64 = 359, 379 AC0_64 = 360, 380 D0_64 = 361, 381 D1_64 = 362, 382 D2_64 = 363, 383 D3_64 = 364, 384 D4_64 = 365, 385 D5_64 = 366, 386 D6_64 = 367, 387 D7_64 = 368, 388 D8_64 = 369, 389 D9_64 = 370, 390 D10_64 = 371, 391 D11_64 = 372, 392 D12_64 = 373, 393 D13_64 = 374, 394 D14_64 = 375, 395 D15_64 = 376, 396 D16_64 = 377, 397 D17_64 = 378, 398 D18_64 = 379, 399 D19_64 = 380, 400 D20_64 = 381, 401 D21_64 = 382, 402 D22_64 = 383, 403 D23_64 = 384, 404 D24_64 = 385, 405 D25_64 = 386, 406 D26_64 = 387, 407 D27_64 = 388, 408 D28_64 = 389, 409 D29_64 = 390, 410 D30_64 = 391, 411 D31_64 = 392, 412 DSPOutFlag16_19 = 393, 413 HI0_64 = 394, 414 K0_64 = 395, 415 K1_64 = 396, 416 LO0_64 = 397, 417 S0_64 = 398, 418 S1_64 = 399, 419 S2_64 = 400, 420 S3_64 = 401, 421 S4_64 = 402, 422 S5_64 = 403, 423 S6_64 = 404, 424 S7_64 = 405, 425 T0_64 = 406, 426 T1_64 = 407, 427 T2_64 = 408, 428 T3_64 = 409, 429 T4_64 = 410, 430 T5_64 = 411, 431 T6_64 = 412, 432 T7_64 = 413, 433 T8_64 = 414, 434 T9_64 = 415, 435 V0_64 = 416, 436 V1_64 = 417, 437 NUM_TARGET_REGS // 418 438}; 439} 440 441// Register classes 442namespace Mips { 443enum { 444 OddSPRegClassID = 0, 445 CCRRegClassID = 1, 446 COP0RegClassID = 2, 447 COP2RegClassID = 3, 448 COP3RegClassID = 4, 449 DSPRRegClassID = 5, 450 FGR32RegClassID = 6, 451 FGRCCRegClassID = 7, 452 FGRH32RegClassID = 8, 453 GPR32RegClassID = 9, 454 HWRegsRegClassID = 10, 455 OddSP_with_sub_hiRegClassID = 11, 456 FGR32_and_OddSPRegClassID = 12, 457 FGRH32_and_OddSPRegClassID = 13, 458 OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID = 14, 459 CPU16RegsPlusSPRegClassID = 15, 460 CPU16RegsRegClassID = 16, 461 FCCRegClassID = 17, 462 GPRMM16RegClassID = 18, 463 GPRMM16MovePRegClassID = 19, 464 GPRMM16ZeroRegClassID = 20, 465 MSACtrlRegClassID = 21, 466 OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID = 22, 467 CPU16Regs_and_GPRMM16ZeroRegClassID = 23, 468 CPU16Regs_and_GPRMM16MovePRegClassID = 24, 469 GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 25, 470 HI32DSPRegClassID = 26, 471 LO32DSPRegClassID = 27, 472 GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 28, 473 CPURARegRegClassID = 29, 474 CPUSPRegRegClassID = 30, 475 DSPCCRegClassID = 31, 476 HI32RegClassID = 32, 477 LO32RegClassID = 33, 478 FGR64RegClassID = 34, 479 GPR64RegClassID = 35, 480 AFGR64RegClassID = 36, 481 FGR64_and_OddSPRegClassID = 37, 482 GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 38, 483 AFGR64_and_OddSPRegClassID = 39, 484 GPR64_with_sub_32_in_CPU16RegsRegClassID = 40, 485 GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 41, 486 GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 42, 487 GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 43, 488 ACC64DSPRegClassID = 44, 489 GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 45, 490 GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 46, 491 GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 47, 492 OCTEON_MPLRegClassID = 48, 493 OCTEON_PRegClassID = 49, 494 ACC64RegClassID = 50, 495 GPR64_with_sub_32_in_CPURARegRegClassID = 51, 496 GPR64_with_sub_32_in_CPUSPRegRegClassID = 52, 497 HI64RegClassID = 53, 498 LO64RegClassID = 54, 499 MSA128BRegClassID = 55, 500 MSA128DRegClassID = 56, 501 MSA128HRegClassID = 57, 502 MSA128WRegClassID = 58, 503 MSA128B_with_sub_64_in_OddSPRegClassID = 59, 504 MSA128WEvensRegClassID = 60, 505 ACC128RegClassID = 61, 506 507 }; 508} 509 510// Subregister indices 511namespace Mips { 512enum { 513 NoSubRegister, 514 sub_32, // 1 515 sub_64, // 2 516 sub_dsp16_19, // 3 517 sub_dsp20, // 4 518 sub_dsp21, // 5 519 sub_dsp22, // 6 520 sub_dsp23, // 7 521 sub_hi, // 8 522 sub_lo, // 9 523 sub_hi_then_sub_32, // 10 524 sub_32_sub_hi_then_sub_32, // 11 525 NUM_TARGET_SUBREGS 526}; 527} 528} // End llvm namespace 529#endif // GET_REGINFO_ENUM 530 531/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 532|* *| 533|* MC Register Information *| 534|* *| 535|* Automatically generated file, do not edit! *| 536|* *| 537\*===----------------------------------------------------------------------===*/ 538 539 540#ifdef GET_REGINFO_MC_DESC 541#undef GET_REGINFO_MC_DESC 542namespace llvm { 543 544extern const MCPhysReg MipsRegDiffLists[] = { 545 /* 0 */ 0, 0, 546 /* 2 */ 4, 1, 1, 1, 1, 0, 547 /* 8 */ 388, 65286, 1, 1, 1, 0, 548 /* 14 */ 20, 1, 0, 549 /* 17 */ 21, 1, 0, 550 /* 20 */ 22, 1, 0, 551 /* 23 */ 23, 1, 0, 552 /* 26 */ 24, 1, 0, 553 /* 29 */ 25, 1, 0, 554 /* 32 */ 26, 1, 0, 555 /* 35 */ 27, 1, 0, 556 /* 38 */ 28, 1, 0, 557 /* 41 */ 29, 1, 0, 558 /* 44 */ 30, 1, 0, 559 /* 47 */ 31, 1, 0, 560 /* 50 */ 32, 1, 0, 561 /* 53 */ 33, 1, 0, 562 /* 56 */ 34, 1, 0, 563 /* 59 */ 35, 1, 0, 564 /* 62 */ 65415, 1, 0, 565 /* 65 */ 65513, 1, 0, 566 /* 68 */ 3, 0, 567 /* 70 */ 4, 0, 568 /* 72 */ 6, 0, 569 /* 74 */ 11, 0, 570 /* 76 */ 12, 0, 571 /* 78 */ 22, 0, 572 /* 80 */ 23, 0, 573 /* 82 */ 29, 0, 574 /* 84 */ 30, 0, 575 /* 86 */ 65308, 72, 0, 576 /* 89 */ 65346, 72, 0, 577 /* 92 */ 38, 65322, 73, 0, 578 /* 96 */ 95, 0, 579 /* 98 */ 96, 0, 580 /* 100 */ 106, 0, 581 /* 102 */ 211, 0, 582 /* 104 */ 243, 0, 583 /* 106 */ 282, 0, 584 /* 108 */ 290, 0, 585 /* 110 */ 334, 0, 586 /* 112 */ 64983, 0, 587 /* 114 */ 65060, 0, 588 /* 116 */ 65148, 0, 589 /* 118 */ 65202, 0, 590 /* 120 */ 65205, 0, 591 /* 122 */ 65246, 0, 592 /* 124 */ 65254, 0, 593 /* 126 */ 65271, 0, 594 /* 128 */ 65293, 0, 595 /* 130 */ 37, 65430, 103, 65395, 65309, 0, 596 /* 136 */ 65325, 0, 597 /* 138 */ 65395, 0, 598 /* 140 */ 65396, 0, 599 /* 142 */ 65397, 0, 600 /* 144 */ 65398, 0, 601 /* 146 */ 65410, 0, 602 /* 148 */ 65415, 0, 603 /* 150 */ 65430, 0, 604 /* 152 */ 65440, 0, 605 /* 154 */ 65441, 0, 606 /* 156 */ 141, 65498, 0, 607 /* 159 */ 65516, 234, 65498, 0, 608 /* 163 */ 65515, 235, 65498, 0, 609 /* 167 */ 65514, 236, 65498, 0, 610 /* 171 */ 65513, 237, 65498, 0, 611 /* 175 */ 65512, 238, 65498, 0, 612 /* 179 */ 65511, 239, 65498, 0, 613 /* 183 */ 65510, 240, 65498, 0, 614 /* 187 */ 65509, 241, 65498, 0, 615 /* 191 */ 65508, 242, 65498, 0, 616 /* 195 */ 65507, 243, 65498, 0, 617 /* 199 */ 65506, 244, 65498, 0, 618 /* 203 */ 65505, 245, 65498, 0, 619 /* 207 */ 65504, 246, 65498, 0, 620 /* 211 */ 65503, 247, 65498, 0, 621 /* 215 */ 65502, 248, 65498, 0, 622 /* 219 */ 65501, 249, 65498, 0, 623 /* 223 */ 65500, 250, 65498, 0, 624 /* 227 */ 265, 65498, 0, 625 /* 230 */ 65271, 371, 65499, 0, 626 /* 234 */ 65309, 368, 65502, 0, 627 /* 238 */ 65507, 0, 628 /* 240 */ 65510, 0, 629 /* 242 */ 65511, 0, 630 /* 244 */ 65512, 0, 631 /* 246 */ 65516, 0, 632 /* 248 */ 65521, 0, 633 /* 250 */ 65522, 0, 634 /* 252 */ 65535, 0, 635}; 636 637extern const unsigned MipsLaneMaskLists[] = { 638 /* 0 */ 0x00000000, ~0u, 639 /* 2 */ 0x00000001, ~0u, 640 /* 4 */ 0x00000002, 0x00000004, 0x00000008, 0x00000010, 0x00000020, ~0u, 641 /* 10 */ 0x00000001, 0x00000040, ~0u, 642}; 643 644extern const uint16_t MipsSubRegIdxLists[] = { 645 /* 0 */ 1, 0, 646 /* 2 */ 3, 4, 5, 6, 7, 0, 647 /* 8 */ 2, 9, 8, 0, 648 /* 12 */ 9, 1, 8, 10, 11, 0, 649}; 650 651extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[] = { 652 { 65535, 65535 }, 653 { 0, 32 }, // sub_32 654 { 0, 64 }, // sub_64 655 { 16, 4 }, // sub_dsp16_19 656 { 20, 1 }, // sub_dsp20 657 { 21, 1 }, // sub_dsp21 658 { 22, 1 }, // sub_dsp22 659 { 23, 1 }, // sub_dsp23 660 { 32, 32 }, // sub_hi 661 { 0, 32 }, // sub_lo 662 { 32, 32 }, // sub_hi_then_sub_32 663 { 0, 64 }, // sub_32_sub_hi_then_sub_32 664}; 665 666extern const char MipsRegStrings[] = { 667 /* 0 */ 'C', 'O', 'P', '0', '0', 0, 668 /* 6 */ 'C', 'O', 'P', '0', '1', '0', 0, 669 /* 13 */ 'C', 'O', 'P', '2', '1', '0', 0, 670 /* 20 */ 'C', 'O', 'P', '3', '1', '0', 0, 671 /* 27 */ 'D', '1', '0', 0, 672 /* 31 */ 'F', '1', '0', 0, 673 /* 35 */ 'F', '_', 'H', 'I', '1', '0', 0, 674 /* 42 */ 'F', 'C', 'R', '1', '0', 0, 675 /* 48 */ 'H', 'W', 'R', '1', '0', 0, 676 /* 54 */ 'W', '1', '0', 0, 677 /* 58 */ 'C', 'O', 'P', '0', '2', '0', 0, 678 /* 65 */ 'C', 'O', 'P', '2', '2', '0', 0, 679 /* 72 */ 'C', 'O', 'P', '3', '2', '0', 0, 680 /* 79 */ 'F', '2', '0', 0, 681 /* 83 */ 'F', '_', 'H', 'I', '2', '0', 0, 682 /* 90 */ 'C', 'O', 'P', '2', '0', 0, 683 /* 96 */ 'F', 'C', 'R', '2', '0', 0, 684 /* 102 */ 'H', 'W', 'R', '2', '0', 0, 685 /* 108 */ 'W', '2', '0', 0, 686 /* 112 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '0', 0, 687 /* 125 */ 'C', 'O', 'P', '0', '3', '0', 0, 688 /* 132 */ 'C', 'O', 'P', '2', '3', '0', 0, 689 /* 139 */ 'C', 'O', 'P', '3', '3', '0', 0, 690 /* 146 */ 'F', '3', '0', 0, 691 /* 150 */ 'F', '_', 'H', 'I', '3', '0', 0, 692 /* 157 */ 'C', 'O', 'P', '3', '0', 0, 693 /* 163 */ 'F', 'C', 'R', '3', '0', 0, 694 /* 169 */ 'H', 'W', 'R', '3', '0', 0, 695 /* 175 */ 'W', '3', '0', 0, 696 /* 179 */ 'A', '0', 0, 697 /* 182 */ 'A', 'C', '0', 0, 698 /* 186 */ 'F', 'C', 'C', '0', 0, 699 /* 191 */ 'D', '0', 0, 700 /* 194 */ 'F', '0', 0, 701 /* 197 */ 'F', '_', 'H', 'I', '0', 0, 702 /* 203 */ 'K', '0', 0, 703 /* 206 */ 'M', 'P', 'L', '0', 0, 704 /* 211 */ 'L', 'O', '0', 0, 705 /* 215 */ 'P', '0', 0, 706 /* 218 */ 'F', 'C', 'R', '0', 0, 707 /* 223 */ 'H', 'W', 'R', '0', 0, 708 /* 228 */ 'S', '0', 0, 709 /* 231 */ 'T', '0', 0, 710 /* 234 */ 'V', '0', 0, 711 /* 237 */ 'W', '0', 0, 712 /* 240 */ 'C', 'O', 'P', '0', '1', 0, 713 /* 246 */ 'C', 'O', 'P', '0', '1', '1', 0, 714 /* 253 */ 'C', 'O', 'P', '2', '1', '1', 0, 715 /* 260 */ 'C', 'O', 'P', '3', '1', '1', 0, 716 /* 267 */ 'D', '1', '1', 0, 717 /* 271 */ 'F', '1', '1', 0, 718 /* 275 */ 'F', '_', 'H', 'I', '1', '1', 0, 719 /* 282 */ 'F', 'C', 'R', '1', '1', 0, 720 /* 288 */ 'H', 'W', 'R', '1', '1', 0, 721 /* 294 */ 'W', '1', '1', 0, 722 /* 298 */ 'C', 'O', 'P', '0', '2', '1', 0, 723 /* 305 */ 'C', 'O', 'P', '2', '2', '1', 0, 724 /* 312 */ 'C', 'O', 'P', '3', '2', '1', 0, 725 /* 319 */ 'F', '2', '1', 0, 726 /* 323 */ 'F', '_', 'H', 'I', '2', '1', 0, 727 /* 330 */ 'C', 'O', 'P', '2', '1', 0, 728 /* 336 */ 'F', 'C', 'R', '2', '1', 0, 729 /* 342 */ 'H', 'W', 'R', '2', '1', 0, 730 /* 348 */ 'W', '2', '1', 0, 731 /* 352 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '1', 0, 732 /* 365 */ 'C', 'O', 'P', '0', '3', '1', 0, 733 /* 372 */ 'C', 'O', 'P', '2', '3', '1', 0, 734 /* 379 */ 'C', 'O', 'P', '3', '3', '1', 0, 735 /* 386 */ 'F', '3', '1', 0, 736 /* 390 */ 'F', '_', 'H', 'I', '3', '1', 0, 737 /* 397 */ 'C', 'O', 'P', '3', '1', 0, 738 /* 403 */ 'F', 'C', 'R', '3', '1', 0, 739 /* 409 */ 'H', 'W', 'R', '3', '1', 0, 740 /* 415 */ 'W', '3', '1', 0, 741 /* 419 */ 'A', '1', 0, 742 /* 422 */ 'A', 'C', '1', 0, 743 /* 426 */ 'F', 'C', 'C', '1', 0, 744 /* 431 */ 'D', '1', 0, 745 /* 434 */ 'F', '1', 0, 746 /* 437 */ 'F', '_', 'H', 'I', '1', 0, 747 /* 443 */ 'K', '1', 0, 748 /* 446 */ 'M', 'P', 'L', '1', 0, 749 /* 451 */ 'L', 'O', '1', 0, 750 /* 455 */ 'P', '1', 0, 751 /* 458 */ 'F', 'C', 'R', '1', 0, 752 /* 463 */ 'H', 'W', 'R', '1', 0, 753 /* 468 */ 'S', '1', 0, 754 /* 471 */ 'T', '1', 0, 755 /* 474 */ 'V', '1', 0, 756 /* 477 */ 'W', '1', 0, 757 /* 480 */ 'C', 'O', 'P', '0', '2', 0, 758 /* 486 */ 'C', 'O', 'P', '0', '1', '2', 0, 759 /* 493 */ 'C', 'O', 'P', '2', '1', '2', 0, 760 /* 500 */ 'C', 'O', 'P', '3', '1', '2', 0, 761 /* 507 */ 'D', '1', '2', 0, 762 /* 511 */ 'F', '1', '2', 0, 763 /* 515 */ 'F', '_', 'H', 'I', '1', '2', 0, 764 /* 522 */ 'F', 'C', 'R', '1', '2', 0, 765 /* 528 */ 'H', 'W', 'R', '1', '2', 0, 766 /* 534 */ 'W', '1', '2', 0, 767 /* 538 */ 'C', 'O', 'P', '0', '2', '2', 0, 768 /* 545 */ 'C', 'O', 'P', '2', '2', '2', 0, 769 /* 552 */ 'C', 'O', 'P', '3', '2', '2', 0, 770 /* 559 */ 'F', '2', '2', 0, 771 /* 563 */ 'F', '_', 'H', 'I', '2', '2', 0, 772 /* 570 */ 'C', 'O', 'P', '2', '2', 0, 773 /* 576 */ 'F', 'C', 'R', '2', '2', 0, 774 /* 582 */ 'H', 'W', 'R', '2', '2', 0, 775 /* 588 */ 'W', '2', '2', 0, 776 /* 592 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '2', 0, 777 /* 605 */ 'C', 'O', 'P', '3', '2', 0, 778 /* 611 */ 'A', '2', 0, 779 /* 614 */ 'A', 'C', '2', 0, 780 /* 618 */ 'F', 'C', 'C', '2', 0, 781 /* 623 */ 'D', '2', 0, 782 /* 626 */ 'F', '2', 0, 783 /* 629 */ 'F', '_', 'H', 'I', '2', 0, 784 /* 635 */ 'M', 'P', 'L', '2', 0, 785 /* 640 */ 'L', 'O', '2', 0, 786 /* 644 */ 'P', '2', 0, 787 /* 647 */ 'F', 'C', 'R', '2', 0, 788 /* 652 */ 'H', 'W', 'R', '2', 0, 789 /* 657 */ 'S', '2', 0, 790 /* 660 */ 'T', '2', 0, 791 /* 663 */ 'W', '2', 0, 792 /* 666 */ 'C', 'O', 'P', '0', '3', 0, 793 /* 672 */ 'C', 'O', 'P', '0', '1', '3', 0, 794 /* 679 */ 'C', 'O', 'P', '2', '1', '3', 0, 795 /* 686 */ 'C', 'O', 'P', '3', '1', '3', 0, 796 /* 693 */ 'D', '1', '3', 0, 797 /* 697 */ 'F', '1', '3', 0, 798 /* 701 */ 'F', '_', 'H', 'I', '1', '3', 0, 799 /* 708 */ 'F', 'C', 'R', '1', '3', 0, 800 /* 714 */ 'H', 'W', 'R', '1', '3', 0, 801 /* 720 */ 'W', '1', '3', 0, 802 /* 724 */ 'C', 'O', 'P', '0', '2', '3', 0, 803 /* 731 */ 'C', 'O', 'P', '2', '2', '3', 0, 804 /* 738 */ 'C', 'O', 'P', '3', '2', '3', 0, 805 /* 745 */ 'F', '2', '3', 0, 806 /* 749 */ 'F', '_', 'H', 'I', '2', '3', 0, 807 /* 756 */ 'C', 'O', 'P', '2', '3', 0, 808 /* 762 */ 'F', 'C', 'R', '2', '3', 0, 809 /* 768 */ 'H', 'W', 'R', '2', '3', 0, 810 /* 774 */ 'W', '2', '3', 0, 811 /* 778 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '3', 0, 812 /* 791 */ 'C', 'O', 'P', '3', '3', 0, 813 /* 797 */ 'A', '3', 0, 814 /* 800 */ 'A', 'C', '3', 0, 815 /* 804 */ 'F', 'C', 'C', '3', 0, 816 /* 809 */ 'D', '3', 0, 817 /* 812 */ 'F', '3', 0, 818 /* 815 */ 'F', '_', 'H', 'I', '3', 0, 819 /* 821 */ 'L', 'O', '3', 0, 820 /* 825 */ 'F', 'C', 'R', '3', 0, 821 /* 830 */ 'H', 'W', 'R', '3', 0, 822 /* 835 */ 'S', '3', 0, 823 /* 838 */ 'T', '3', 0, 824 /* 841 */ 'W', '3', 0, 825 /* 844 */ 'C', 'O', 'P', '0', '4', 0, 826 /* 850 */ 'C', 'O', 'P', '0', '1', '4', 0, 827 /* 857 */ 'C', 'O', 'P', '2', '1', '4', 0, 828 /* 864 */ 'C', 'O', 'P', '3', '1', '4', 0, 829 /* 871 */ 'D', '1', '4', 0, 830 /* 875 */ 'F', '1', '4', 0, 831 /* 879 */ 'F', '_', 'H', 'I', '1', '4', 0, 832 /* 886 */ 'F', 'C', 'R', '1', '4', 0, 833 /* 892 */ 'H', 'W', 'R', '1', '4', 0, 834 /* 898 */ 'W', '1', '4', 0, 835 /* 902 */ 'C', 'O', 'P', '0', '2', '4', 0, 836 /* 909 */ 'C', 'O', 'P', '2', '2', '4', 0, 837 /* 916 */ 'C', 'O', 'P', '3', '2', '4', 0, 838 /* 923 */ 'F', '2', '4', 0, 839 /* 927 */ 'F', '_', 'H', 'I', '2', '4', 0, 840 /* 934 */ 'C', 'O', 'P', '2', '4', 0, 841 /* 940 */ 'F', 'C', 'R', '2', '4', 0, 842 /* 946 */ 'H', 'W', 'R', '2', '4', 0, 843 /* 952 */ 'W', '2', '4', 0, 844 /* 956 */ 'C', 'O', 'P', '3', '4', 0, 845 /* 962 */ 'D', '1', '0', '_', '6', '4', 0, 846 /* 969 */ 'D', '2', '0', '_', '6', '4', 0, 847 /* 976 */ 'D', '3', '0', '_', '6', '4', 0, 848 /* 983 */ 'A', '0', '_', '6', '4', 0, 849 /* 989 */ 'A', 'C', '0', '_', '6', '4', 0, 850 /* 996 */ 'D', '0', '_', '6', '4', 0, 851 /* 1002 */ 'H', 'I', '0', '_', '6', '4', 0, 852 /* 1009 */ 'K', '0', '_', '6', '4', 0, 853 /* 1015 */ 'L', 'O', '0', '_', '6', '4', 0, 854 /* 1022 */ 'S', '0', '_', '6', '4', 0, 855 /* 1028 */ 'T', '0', '_', '6', '4', 0, 856 /* 1034 */ 'V', '0', '_', '6', '4', 0, 857 /* 1040 */ 'D', '1', '1', '_', '6', '4', 0, 858 /* 1047 */ 'D', '2', '1', '_', '6', '4', 0, 859 /* 1054 */ 'D', '3', '1', '_', '6', '4', 0, 860 /* 1061 */ 'A', '1', '_', '6', '4', 0, 861 /* 1067 */ 'D', '1', '_', '6', '4', 0, 862 /* 1073 */ 'K', '1', '_', '6', '4', 0, 863 /* 1079 */ 'S', '1', '_', '6', '4', 0, 864 /* 1085 */ 'T', '1', '_', '6', '4', 0, 865 /* 1091 */ 'V', '1', '_', '6', '4', 0, 866 /* 1097 */ 'D', '1', '2', '_', '6', '4', 0, 867 /* 1104 */ 'D', '2', '2', '_', '6', '4', 0, 868 /* 1111 */ 'A', '2', '_', '6', '4', 0, 869 /* 1117 */ 'D', '2', '_', '6', '4', 0, 870 /* 1123 */ 'S', '2', '_', '6', '4', 0, 871 /* 1129 */ 'T', '2', '_', '6', '4', 0, 872 /* 1135 */ 'D', '1', '3', '_', '6', '4', 0, 873 /* 1142 */ 'D', '2', '3', '_', '6', '4', 0, 874 /* 1149 */ 'A', '3', '_', '6', '4', 0, 875 /* 1155 */ 'D', '3', '_', '6', '4', 0, 876 /* 1161 */ 'S', '3', '_', '6', '4', 0, 877 /* 1167 */ 'T', '3', '_', '6', '4', 0, 878 /* 1173 */ 'D', '1', '4', '_', '6', '4', 0, 879 /* 1180 */ 'D', '2', '4', '_', '6', '4', 0, 880 /* 1187 */ 'D', '4', '_', '6', '4', 0, 881 /* 1193 */ 'S', '4', '_', '6', '4', 0, 882 /* 1199 */ 'T', '4', '_', '6', '4', 0, 883 /* 1205 */ 'D', '1', '5', '_', '6', '4', 0, 884 /* 1212 */ 'D', '2', '5', '_', '6', '4', 0, 885 /* 1219 */ 'D', '5', '_', '6', '4', 0, 886 /* 1225 */ 'S', '5', '_', '6', '4', 0, 887 /* 1231 */ 'T', '5', '_', '6', '4', 0, 888 /* 1237 */ 'D', '1', '6', '_', '6', '4', 0, 889 /* 1244 */ 'D', '2', '6', '_', '6', '4', 0, 890 /* 1251 */ 'D', '6', '_', '6', '4', 0, 891 /* 1257 */ 'S', '6', '_', '6', '4', 0, 892 /* 1263 */ 'T', '6', '_', '6', '4', 0, 893 /* 1269 */ 'D', '1', '7', '_', '6', '4', 0, 894 /* 1276 */ 'D', '2', '7', '_', '6', '4', 0, 895 /* 1283 */ 'D', '7', '_', '6', '4', 0, 896 /* 1289 */ 'S', '7', '_', '6', '4', 0, 897 /* 1295 */ 'T', '7', '_', '6', '4', 0, 898 /* 1301 */ 'D', '1', '8', '_', '6', '4', 0, 899 /* 1308 */ 'D', '2', '8', '_', '6', '4', 0, 900 /* 1315 */ 'D', '8', '_', '6', '4', 0, 901 /* 1321 */ 'T', '8', '_', '6', '4', 0, 902 /* 1327 */ 'D', '1', '9', '_', '6', '4', 0, 903 /* 1334 */ 'D', '2', '9', '_', '6', '4', 0, 904 /* 1341 */ 'D', '9', '_', '6', '4', 0, 905 /* 1347 */ 'T', '9', '_', '6', '4', 0, 906 /* 1353 */ 'R', 'A', '_', '6', '4', 0, 907 /* 1359 */ 'Z', 'E', 'R', 'O', '_', '6', '4', 0, 908 /* 1367 */ 'F', 'P', '_', '6', '4', 0, 909 /* 1373 */ 'G', 'P', '_', '6', '4', 0, 910 /* 1379 */ 'S', 'P', '_', '6', '4', 0, 911 /* 1385 */ 'A', 'T', '_', '6', '4', 0, 912 /* 1391 */ 'F', 'C', 'C', '4', 0, 913 /* 1396 */ 'D', '4', 0, 914 /* 1399 */ 'F', '4', 0, 915 /* 1402 */ 'F', '_', 'H', 'I', '4', 0, 916 /* 1408 */ 'F', 'C', 'R', '4', 0, 917 /* 1413 */ 'H', 'W', 'R', '4', 0, 918 /* 1418 */ 'S', '4', 0, 919 /* 1421 */ 'T', '4', 0, 920 /* 1424 */ 'W', '4', 0, 921 /* 1427 */ 'C', 'O', 'P', '0', '5', 0, 922 /* 1433 */ 'C', 'O', 'P', '0', '1', '5', 0, 923 /* 1440 */ 'C', 'O', 'P', '2', '1', '5', 0, 924 /* 1447 */ 'C', 'O', 'P', '3', '1', '5', 0, 925 /* 1454 */ 'D', '1', '5', 0, 926 /* 1458 */ 'F', '1', '5', 0, 927 /* 1462 */ 'F', '_', 'H', 'I', '1', '5', 0, 928 /* 1469 */ 'F', 'C', 'R', '1', '5', 0, 929 /* 1475 */ 'H', 'W', 'R', '1', '5', 0, 930 /* 1481 */ 'W', '1', '5', 0, 931 /* 1485 */ 'C', 'O', 'P', '0', '2', '5', 0, 932 /* 1492 */ 'C', 'O', 'P', '2', '2', '5', 0, 933 /* 1499 */ 'C', 'O', 'P', '3', '2', '5', 0, 934 /* 1506 */ 'F', '2', '5', 0, 935 /* 1510 */ 'F', '_', 'H', 'I', '2', '5', 0, 936 /* 1517 */ 'C', 'O', 'P', '2', '5', 0, 937 /* 1523 */ 'F', 'C', 'R', '2', '5', 0, 938 /* 1529 */ 'H', 'W', 'R', '2', '5', 0, 939 /* 1535 */ 'W', '2', '5', 0, 940 /* 1539 */ 'C', 'O', 'P', '3', '5', 0, 941 /* 1545 */ 'F', 'C', 'C', '5', 0, 942 /* 1550 */ 'D', '5', 0, 943 /* 1553 */ 'F', '5', 0, 944 /* 1556 */ 'F', '_', 'H', 'I', '5', 0, 945 /* 1562 */ 'F', 'C', 'R', '5', 0, 946 /* 1567 */ 'H', 'W', 'R', '5', 0, 947 /* 1572 */ 'S', '5', 0, 948 /* 1575 */ 'T', '5', 0, 949 /* 1578 */ 'W', '5', 0, 950 /* 1581 */ 'C', 'O', 'P', '0', '6', 0, 951 /* 1587 */ 'C', 'O', 'P', '0', '1', '6', 0, 952 /* 1594 */ 'C', 'O', 'P', '2', '1', '6', 0, 953 /* 1601 */ 'C', 'O', 'P', '3', '1', '6', 0, 954 /* 1608 */ 'F', '1', '6', 0, 955 /* 1612 */ 'F', '_', 'H', 'I', '1', '6', 0, 956 /* 1619 */ 'F', 'C', 'R', '1', '6', 0, 957 /* 1625 */ 'H', 'W', 'R', '1', '6', 0, 958 /* 1631 */ 'W', '1', '6', 0, 959 /* 1635 */ 'C', 'O', 'P', '0', '2', '6', 0, 960 /* 1642 */ 'C', 'O', 'P', '2', '2', '6', 0, 961 /* 1649 */ 'C', 'O', 'P', '3', '2', '6', 0, 962 /* 1656 */ 'F', '2', '6', 0, 963 /* 1660 */ 'F', '_', 'H', 'I', '2', '6', 0, 964 /* 1667 */ 'C', 'O', 'P', '2', '6', 0, 965 /* 1673 */ 'F', 'C', 'R', '2', '6', 0, 966 /* 1679 */ 'H', 'W', 'R', '2', '6', 0, 967 /* 1685 */ 'W', '2', '6', 0, 968 /* 1689 */ 'C', 'O', 'P', '3', '6', 0, 969 /* 1695 */ 'F', 'C', 'C', '6', 0, 970 /* 1700 */ 'D', '6', 0, 971 /* 1703 */ 'F', '6', 0, 972 /* 1706 */ 'F', '_', 'H', 'I', '6', 0, 973 /* 1712 */ 'F', 'C', 'R', '6', 0, 974 /* 1717 */ 'H', 'W', 'R', '6', 0, 975 /* 1722 */ 'S', '6', 0, 976 /* 1725 */ 'T', '6', 0, 977 /* 1728 */ 'W', '6', 0, 978 /* 1731 */ 'C', 'O', 'P', '0', '7', 0, 979 /* 1737 */ 'C', 'O', 'P', '0', '1', '7', 0, 980 /* 1744 */ 'C', 'O', 'P', '2', '1', '7', 0, 981 /* 1751 */ 'C', 'O', 'P', '3', '1', '7', 0, 982 /* 1758 */ 'F', '1', '7', 0, 983 /* 1762 */ 'F', '_', 'H', 'I', '1', '7', 0, 984 /* 1769 */ 'F', 'C', 'R', '1', '7', 0, 985 /* 1775 */ 'H', 'W', 'R', '1', '7', 0, 986 /* 1781 */ 'W', '1', '7', 0, 987 /* 1785 */ 'C', 'O', 'P', '0', '2', '7', 0, 988 /* 1792 */ 'C', 'O', 'P', '2', '2', '7', 0, 989 /* 1799 */ 'C', 'O', 'P', '3', '2', '7', 0, 990 /* 1806 */ 'F', '2', '7', 0, 991 /* 1810 */ 'F', '_', 'H', 'I', '2', '7', 0, 992 /* 1817 */ 'C', 'O', 'P', '2', '7', 0, 993 /* 1823 */ 'F', 'C', 'R', '2', '7', 0, 994 /* 1829 */ 'H', 'W', 'R', '2', '7', 0, 995 /* 1835 */ 'W', '2', '7', 0, 996 /* 1839 */ 'C', 'O', 'P', '3', '7', 0, 997 /* 1845 */ 'F', 'C', 'C', '7', 0, 998 /* 1850 */ 'D', '7', 0, 999 /* 1853 */ 'F', '7', 0, 1000 /* 1856 */ 'F', '_', 'H', 'I', '7', 0, 1001 /* 1862 */ 'F', 'C', 'R', '7', 0, 1002 /* 1867 */ 'H', 'W', 'R', '7', 0, 1003 /* 1872 */ 'S', '7', 0, 1004 /* 1875 */ 'T', '7', 0, 1005 /* 1878 */ 'W', '7', 0, 1006 /* 1881 */ 'C', 'O', 'P', '0', '8', 0, 1007 /* 1887 */ 'C', 'O', 'P', '0', '1', '8', 0, 1008 /* 1894 */ 'C', 'O', 'P', '2', '1', '8', 0, 1009 /* 1901 */ 'C', 'O', 'P', '3', '1', '8', 0, 1010 /* 1908 */ 'F', '1', '8', 0, 1011 /* 1912 */ 'F', '_', 'H', 'I', '1', '8', 0, 1012 /* 1919 */ 'F', 'C', 'R', '1', '8', 0, 1013 /* 1925 */ 'H', 'W', 'R', '1', '8', 0, 1014 /* 1931 */ 'W', '1', '8', 0, 1015 /* 1935 */ 'C', 'O', 'P', '0', '2', '8', 0, 1016 /* 1942 */ 'C', 'O', 'P', '2', '2', '8', 0, 1017 /* 1949 */ 'C', 'O', 'P', '3', '2', '8', 0, 1018 /* 1956 */ 'F', '2', '8', 0, 1019 /* 1960 */ 'F', '_', 'H', 'I', '2', '8', 0, 1020 /* 1967 */ 'C', 'O', 'P', '2', '8', 0, 1021 /* 1973 */ 'F', 'C', 'R', '2', '8', 0, 1022 /* 1979 */ 'H', 'W', 'R', '2', '8', 0, 1023 /* 1985 */ 'W', '2', '8', 0, 1024 /* 1989 */ 'C', 'O', 'P', '3', '8', 0, 1025 /* 1995 */ 'D', '8', 0, 1026 /* 1998 */ 'F', '8', 0, 1027 /* 2001 */ 'F', '_', 'H', 'I', '8', 0, 1028 /* 2007 */ 'F', 'C', 'R', '8', 0, 1029 /* 2012 */ 'H', 'W', 'R', '8', 0, 1030 /* 2017 */ 'T', '8', 0, 1031 /* 2020 */ 'W', '8', 0, 1032 /* 2023 */ 'C', 'O', 'P', '0', '9', 0, 1033 /* 2029 */ 'C', 'O', 'P', '0', '1', '9', 0, 1034 /* 2036 */ 'C', 'O', 'P', '2', '1', '9', 0, 1035 /* 2043 */ 'C', 'O', 'P', '3', '1', '9', 0, 1036 /* 2050 */ 'F', '1', '9', 0, 1037 /* 2054 */ 'F', '_', 'H', 'I', '1', '9', 0, 1038 /* 2061 */ 'F', 'C', 'R', '1', '9', 0, 1039 /* 2067 */ 'H', 'W', 'R', '1', '9', 0, 1040 /* 2073 */ 'W', '1', '9', 0, 1041 /* 2077 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '1', '6', '_', '1', '9', 0, 1042 /* 2093 */ 'C', 'O', 'P', '0', '2', '9', 0, 1043 /* 2100 */ 'C', 'O', 'P', '2', '2', '9', 0, 1044 /* 2107 */ 'C', 'O', 'P', '3', '2', '9', 0, 1045 /* 2114 */ 'F', '2', '9', 0, 1046 /* 2118 */ 'F', '_', 'H', 'I', '2', '9', 0, 1047 /* 2125 */ 'C', 'O', 'P', '2', '9', 0, 1048 /* 2131 */ 'F', 'C', 'R', '2', '9', 0, 1049 /* 2137 */ 'H', 'W', 'R', '2', '9', 0, 1050 /* 2143 */ 'W', '2', '9', 0, 1051 /* 2147 */ 'C', 'O', 'P', '3', '9', 0, 1052 /* 2153 */ 'D', '9', 0, 1053 /* 2156 */ 'F', '9', 0, 1054 /* 2159 */ 'F', '_', 'H', 'I', '9', 0, 1055 /* 2165 */ 'F', 'C', 'R', '9', 0, 1056 /* 2170 */ 'H', 'W', 'R', '9', 0, 1057 /* 2175 */ 'T', '9', 0, 1058 /* 2178 */ 'W', '9', 0, 1059 /* 2181 */ 'R', 'A', 0, 1060 /* 2184 */ 'P', 'C', 0, 1061 /* 2187 */ 'D', 'S', 'P', 'E', 'F', 'I', 0, 1062 /* 2194 */ 'Z', 'E', 'R', 'O', 0, 1063 /* 2199 */ 'F', 'P', 0, 1064 /* 2202 */ 'G', 'P', 0, 1065 /* 2205 */ 'S', 'P', 0, 1066 /* 2208 */ 'M', 'S', 'A', 'I', 'R', 0, 1067 /* 2214 */ 'M', 'S', 'A', 'C', 'S', 'R', 0, 1068 /* 2221 */ 'A', 'T', 0, 1069 /* 2224 */ 'D', 'S', 'P', 'C', 'C', 'o', 'n', 'd', 0, 1070 /* 2233 */ 'M', 'S', 'A', 'S', 'a', 'v', 'e', 0, 1071 /* 2241 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', 0, 1072 /* 2252 */ 'M', 'S', 'A', 'M', 'a', 'p', 0, 1073 /* 2259 */ 'M', 'S', 'A', 'U', 'n', 'm', 'a', 'p', 0, 1074 /* 2268 */ 'D', 'S', 'P', 'P', 'o', 's', 0, 1075 /* 2275 */ 'M', 'S', 'A', 'A', 'c', 'c', 'e', 's', 's', 0, 1076 /* 2285 */ 'D', 'S', 'P', 'S', 'C', 'o', 'u', 'n', 't', 0, 1077 /* 2295 */ 'M', 'S', 'A', 'R', 'e', 'q', 'u', 'e', 's', 't', 0, 1078 /* 2306 */ 'M', 'S', 'A', 'M', 'o', 'd', 'i', 'f', 'y', 0, 1079 /* 2316 */ 'D', 'S', 'P', 'C', 'a', 'r', 'r', 'y', 0, 1080}; 1081 1082extern const MCRegisterDesc MipsRegDesc[] = { // Descriptors 1083 { 5, 0, 0, 0, 0, 0 }, 1084 { 2221, 1, 82, 1, 4033, 0 }, 1085 { 2224, 1, 1, 1, 4033, 0 }, 1086 { 2316, 1, 1, 1, 4033, 0 }, 1087 { 2187, 1, 1, 1, 4033, 0 }, 1088 { 2241, 8, 1, 2, 32, 4 }, 1089 { 2268, 1, 1, 1, 1089, 0 }, 1090 { 2285, 1, 1, 1, 1089, 0 }, 1091 { 2199, 1, 102, 1, 1089, 0 }, 1092 { 2202, 1, 104, 1, 1089, 0 }, 1093 { 2275, 1, 1, 1, 1089, 0 }, 1094 { 2214, 1, 1, 1, 1089, 0 }, 1095 { 2208, 1, 1, 1, 1089, 0 }, 1096 { 2252, 1, 1, 1, 1089, 0 }, 1097 { 2306, 1, 1, 1, 1089, 0 }, 1098 { 2295, 1, 1, 1, 1089, 0 }, 1099 { 2233, 1, 1, 1, 1089, 0 }, 1100 { 2259, 1, 1, 1, 1089, 0 }, 1101 { 2184, 1, 1, 1, 1089, 0 }, 1102 { 2181, 1, 106, 1, 1089, 0 }, 1103 { 2205, 1, 108, 1, 1089, 0 }, 1104 { 2194, 1, 110, 1, 1089, 0 }, 1105 { 179, 1, 110, 1, 1089, 0 }, 1106 { 419, 1, 110, 1, 1089, 0 }, 1107 { 611, 1, 110, 1, 1089, 0 }, 1108 { 797, 1, 110, 1, 1089, 0 }, 1109 { 182, 227, 110, 9, 1042, 10 }, 1110 { 422, 227, 1, 9, 1042, 10 }, 1111 { 614, 227, 1, 9, 1042, 10 }, 1112 { 800, 227, 1, 9, 1042, 10 }, 1113 { 1385, 238, 1, 0, 0, 2 }, 1114 { 0, 1, 1, 1, 1153, 0 }, 1115 { 240, 1, 1, 1, 1153, 0 }, 1116 { 480, 1, 1, 1, 1153, 0 }, 1117 { 666, 1, 1, 1, 1153, 0 }, 1118 { 844, 1, 1, 1, 1153, 0 }, 1119 { 1427, 1, 1, 1, 1153, 0 }, 1120 { 1581, 1, 1, 1, 1153, 0 }, 1121 { 1731, 1, 1, 1, 1153, 0 }, 1122 { 1881, 1, 1, 1, 1153, 0 }, 1123 { 2023, 1, 1, 1, 1153, 0 }, 1124 { 90, 1, 1, 1, 1153, 0 }, 1125 { 330, 1, 1, 1, 1153, 0 }, 1126 { 570, 1, 1, 1, 1153, 0 }, 1127 { 756, 1, 1, 1, 1153, 0 }, 1128 { 934, 1, 1, 1, 1153, 0 }, 1129 { 1517, 1, 1, 1, 1153, 0 }, 1130 { 1667, 1, 1, 1, 1153, 0 }, 1131 { 1817, 1, 1, 1, 1153, 0 }, 1132 { 1967, 1, 1, 1, 1153, 0 }, 1133 { 2125, 1, 1, 1, 1153, 0 }, 1134 { 157, 1, 1, 1, 1153, 0 }, 1135 { 397, 1, 1, 1, 1153, 0 }, 1136 { 605, 1, 1, 1, 1153, 0 }, 1137 { 791, 1, 1, 1, 1153, 0 }, 1138 { 956, 1, 1, 1, 1153, 0 }, 1139 { 1539, 1, 1, 1, 1153, 0 }, 1140 { 1689, 1, 1, 1, 1153, 0 }, 1141 { 1839, 1, 1, 1, 1153, 0 }, 1142 { 1989, 1, 1, 1, 1153, 0 }, 1143 { 2147, 1, 1, 1, 1153, 0 }, 1144 { 6, 1, 1, 1, 1153, 0 }, 1145 { 246, 1, 1, 1, 1153, 0 }, 1146 { 486, 1, 1, 1, 1153, 0 }, 1147 { 672, 1, 1, 1, 1153, 0 }, 1148 { 850, 1, 1, 1, 1153, 0 }, 1149 { 1433, 1, 1, 1, 1153, 0 }, 1150 { 1587, 1, 1, 1, 1153, 0 }, 1151 { 1737, 1, 1, 1, 1153, 0 }, 1152 { 1887, 1, 1, 1, 1153, 0 }, 1153 { 2029, 1, 1, 1, 1153, 0 }, 1154 { 58, 1, 1, 1, 1153, 0 }, 1155 { 298, 1, 1, 1, 1153, 0 }, 1156 { 538, 1, 1, 1, 1153, 0 }, 1157 { 724, 1, 1, 1, 1153, 0 }, 1158 { 902, 1, 1, 1, 1153, 0 }, 1159 { 1485, 1, 1, 1, 1153, 0 }, 1160 { 1635, 1, 1, 1, 1153, 0 }, 1161 { 1785, 1, 1, 1, 1153, 0 }, 1162 { 1935, 1, 1, 1, 1153, 0 }, 1163 { 2093, 1, 1, 1, 1153, 0 }, 1164 { 125, 1, 1, 1, 1153, 0 }, 1165 { 365, 1, 1, 1, 1153, 0 }, 1166 { 13, 1, 1, 1, 1153, 0 }, 1167 { 253, 1, 1, 1, 1153, 0 }, 1168 { 493, 1, 1, 1, 1153, 0 }, 1169 { 679, 1, 1, 1, 1153, 0 }, 1170 { 857, 1, 1, 1, 1153, 0 }, 1171 { 1440, 1, 1, 1, 1153, 0 }, 1172 { 1594, 1, 1, 1, 1153, 0 }, 1173 { 1744, 1, 1, 1, 1153, 0 }, 1174 { 1894, 1, 1, 1, 1153, 0 }, 1175 { 2036, 1, 1, 1, 1153, 0 }, 1176 { 65, 1, 1, 1, 1153, 0 }, 1177 { 305, 1, 1, 1, 1153, 0 }, 1178 { 545, 1, 1, 1, 1153, 0 }, 1179 { 731, 1, 1, 1, 1153, 0 }, 1180 { 909, 1, 1, 1, 1153, 0 }, 1181 { 1492, 1, 1, 1, 1153, 0 }, 1182 { 1642, 1, 1, 1, 1153, 0 }, 1183 { 1792, 1, 1, 1, 1153, 0 }, 1184 { 1942, 1, 1, 1, 1153, 0 }, 1185 { 2100, 1, 1, 1, 1153, 0 }, 1186 { 132, 1, 1, 1, 1153, 0 }, 1187 { 372, 1, 1, 1, 1153, 0 }, 1188 { 20, 1, 1, 1, 1153, 0 }, 1189 { 260, 1, 1, 1, 1153, 0 }, 1190 { 500, 1, 1, 1, 1153, 0 }, 1191 { 686, 1, 1, 1, 1153, 0 }, 1192 { 864, 1, 1, 1, 1153, 0 }, 1193 { 1447, 1, 1, 1, 1153, 0 }, 1194 { 1601, 1, 1, 1, 1153, 0 }, 1195 { 1751, 1, 1, 1, 1153, 0 }, 1196 { 1901, 1, 1, 1, 1153, 0 }, 1197 { 2043, 1, 1, 1, 1153, 0 }, 1198 { 72, 1, 1, 1, 1153, 0 }, 1199 { 312, 1, 1, 1, 1153, 0 }, 1200 { 552, 1, 1, 1, 1153, 0 }, 1201 { 738, 1, 1, 1, 1153, 0 }, 1202 { 916, 1, 1, 1, 1153, 0 }, 1203 { 1499, 1, 1, 1, 1153, 0 }, 1204 { 1649, 1, 1, 1, 1153, 0 }, 1205 { 1799, 1, 1, 1, 1153, 0 }, 1206 { 1949, 1, 1, 1, 1153, 0 }, 1207 { 2107, 1, 1, 1, 1153, 0 }, 1208 { 139, 1, 1, 1, 1153, 0 }, 1209 { 379, 1, 1, 1, 1153, 0 }, 1210 { 191, 14, 1, 9, 994, 10 }, 1211 { 431, 17, 1, 9, 994, 10 }, 1212 { 623, 20, 1, 9, 994, 10 }, 1213 { 809, 23, 1, 9, 994, 10 }, 1214 { 1396, 26, 1, 9, 994, 10 }, 1215 { 1550, 29, 1, 9, 994, 10 }, 1216 { 1700, 32, 1, 9, 994, 10 }, 1217 { 1850, 35, 1, 9, 994, 10 }, 1218 { 1995, 38, 1, 9, 994, 10 }, 1219 { 2153, 41, 1, 9, 994, 10 }, 1220 { 27, 44, 1, 9, 994, 10 }, 1221 { 267, 47, 1, 9, 994, 10 }, 1222 { 507, 50, 1, 9, 994, 10 }, 1223 { 693, 53, 1, 9, 994, 10 }, 1224 { 871, 56, 1, 9, 994, 10 }, 1225 { 1454, 59, 1, 9, 994, 10 }, 1226 { 112, 1, 144, 1, 2305, 0 }, 1227 { 352, 1, 142, 1, 2305, 0 }, 1228 { 592, 1, 140, 1, 2305, 0 }, 1229 { 778, 1, 138, 1, 2305, 0 }, 1230 { 194, 1, 159, 1, 4001, 0 }, 1231 { 434, 1, 163, 1, 4001, 0 }, 1232 { 626, 1, 163, 1, 4001, 0 }, 1233 { 812, 1, 167, 1, 4001, 0 }, 1234 { 1399, 1, 167, 1, 4001, 0 }, 1235 { 1553, 1, 171, 1, 4001, 0 }, 1236 { 1703, 1, 171, 1, 4001, 0 }, 1237 { 1853, 1, 175, 1, 4001, 0 }, 1238 { 1998, 1, 175, 1, 4001, 0 }, 1239 { 2156, 1, 179, 1, 4001, 0 }, 1240 { 31, 1, 179, 1, 4001, 0 }, 1241 { 271, 1, 183, 1, 4001, 0 }, 1242 { 511, 1, 183, 1, 4001, 0 }, 1243 { 697, 1, 187, 1, 4001, 0 }, 1244 { 875, 1, 187, 1, 4001, 0 }, 1245 { 1458, 1, 191, 1, 4001, 0 }, 1246 { 1608, 1, 191, 1, 4001, 0 }, 1247 { 1758, 1, 195, 1, 4001, 0 }, 1248 { 1908, 1, 195, 1, 4001, 0 }, 1249 { 2050, 1, 199, 1, 4001, 0 }, 1250 { 79, 1, 199, 1, 4001, 0 }, 1251 { 319, 1, 203, 1, 4001, 0 }, 1252 { 559, 1, 203, 1, 4001, 0 }, 1253 { 745, 1, 207, 1, 4001, 0 }, 1254 { 923, 1, 207, 1, 4001, 0 }, 1255 { 1506, 1, 211, 1, 4001, 0 }, 1256 { 1656, 1, 211, 1, 4001, 0 }, 1257 { 1806, 1, 215, 1, 4001, 0 }, 1258 { 1956, 1, 215, 1, 4001, 0 }, 1259 { 2114, 1, 219, 1, 4001, 0 }, 1260 { 146, 1, 219, 1, 4001, 0 }, 1261 { 386, 1, 223, 1, 4001, 0 }, 1262 { 186, 1, 1, 1, 4001, 0 }, 1263 { 426, 1, 1, 1, 4001, 0 }, 1264 { 618, 1, 1, 1, 4001, 0 }, 1265 { 804, 1, 1, 1, 4001, 0 }, 1266 { 1391, 1, 1, 1, 4001, 0 }, 1267 { 1545, 1, 1, 1, 4001, 0 }, 1268 { 1695, 1, 1, 1, 4001, 0 }, 1269 { 1845, 1, 1, 1, 4001, 0 }, 1270 { 218, 1, 1, 1, 4001, 0 }, 1271 { 458, 1, 1, 1, 4001, 0 }, 1272 { 647, 1, 1, 1, 4001, 0 }, 1273 { 825, 1, 1, 1, 4001, 0 }, 1274 { 1408, 1, 1, 1, 4001, 0 }, 1275 { 1562, 1, 1, 1, 4001, 0 }, 1276 { 1712, 1, 1, 1, 4001, 0 }, 1277 { 1862, 1, 1, 1, 4001, 0 }, 1278 { 2007, 1, 1, 1, 4001, 0 }, 1279 { 2165, 1, 1, 1, 4001, 0 }, 1280 { 42, 1, 1, 1, 4001, 0 }, 1281 { 282, 1, 1, 1, 4001, 0 }, 1282 { 522, 1, 1, 1, 4001, 0 }, 1283 { 708, 1, 1, 1, 4001, 0 }, 1284 { 886, 1, 1, 1, 4001, 0 }, 1285 { 1469, 1, 1, 1, 4001, 0 }, 1286 { 1619, 1, 1, 1, 4001, 0 }, 1287 { 1769, 1, 1, 1, 4001, 0 }, 1288 { 1919, 1, 1, 1, 4001, 0 }, 1289 { 2061, 1, 1, 1, 4001, 0 }, 1290 { 96, 1, 1, 1, 4001, 0 }, 1291 { 336, 1, 1, 1, 4001, 0 }, 1292 { 576, 1, 1, 1, 4001, 0 }, 1293 { 762, 1, 1, 1, 4001, 0 }, 1294 { 940, 1, 1, 1, 4001, 0 }, 1295 { 1523, 1, 1, 1, 4001, 0 }, 1296 { 1673, 1, 1, 1, 4001, 0 }, 1297 { 1823, 1, 1, 1, 4001, 0 }, 1298 { 1973, 1, 1, 1, 4001, 0 }, 1299 { 2131, 1, 1, 1, 4001, 0 }, 1300 { 163, 1, 1, 1, 4001, 0 }, 1301 { 403, 1, 1, 1, 4001, 0 }, 1302 { 1367, 136, 1, 0, 1184, 2 }, 1303 { 197, 1, 156, 1, 3969, 0 }, 1304 { 437, 1, 156, 1, 3969, 0 }, 1305 { 629, 1, 156, 1, 3969, 0 }, 1306 { 815, 1, 156, 1, 3969, 0 }, 1307 { 1402, 1, 156, 1, 3969, 0 }, 1308 { 1556, 1, 156, 1, 3969, 0 }, 1309 { 1706, 1, 156, 1, 3969, 0 }, 1310 { 1856, 1, 156, 1, 3969, 0 }, 1311 { 2001, 1, 156, 1, 3969, 0 }, 1312 { 2159, 1, 156, 1, 3969, 0 }, 1313 { 35, 1, 156, 1, 3969, 0 }, 1314 { 275, 1, 156, 1, 3969, 0 }, 1315 { 515, 1, 156, 1, 3969, 0 }, 1316 { 701, 1, 156, 1, 3969, 0 }, 1317 { 879, 1, 156, 1, 3969, 0 }, 1318 { 1462, 1, 156, 1, 3969, 0 }, 1319 { 1612, 1, 156, 1, 3969, 0 }, 1320 { 1762, 1, 156, 1, 3969, 0 }, 1321 { 1912, 1, 156, 1, 3969, 0 }, 1322 { 2054, 1, 156, 1, 3969, 0 }, 1323 { 83, 1, 156, 1, 3969, 0 }, 1324 { 323, 1, 156, 1, 3969, 0 }, 1325 { 563, 1, 156, 1, 3969, 0 }, 1326 { 749, 1, 156, 1, 3969, 0 }, 1327 { 927, 1, 156, 1, 3969, 0 }, 1328 { 1510, 1, 156, 1, 3969, 0 }, 1329 { 1660, 1, 156, 1, 3969, 0 }, 1330 { 1810, 1, 156, 1, 3969, 0 }, 1331 { 1960, 1, 156, 1, 3969, 0 }, 1332 { 2118, 1, 156, 1, 3969, 0 }, 1333 { 150, 1, 156, 1, 3969, 0 }, 1334 { 390, 1, 156, 1, 3969, 0 }, 1335 { 1373, 128, 1, 0, 1216, 2 }, 1336 { 199, 1, 234, 1, 1826, 0 }, 1337 { 439, 1, 134, 1, 1826, 0 }, 1338 { 631, 1, 134, 1, 1826, 0 }, 1339 { 817, 1, 134, 1, 1826, 0 }, 1340 { 223, 1, 1, 1, 3937, 0 }, 1341 { 463, 1, 1, 1, 3937, 0 }, 1342 { 652, 1, 1, 1, 3937, 0 }, 1343 { 830, 1, 1, 1, 3937, 0 }, 1344 { 1413, 1, 1, 1, 3937, 0 }, 1345 { 1567, 1, 1, 1, 3937, 0 }, 1346 { 1717, 1, 1, 1, 3937, 0 }, 1347 { 1867, 1, 1, 1, 3937, 0 }, 1348 { 2012, 1, 1, 1, 3937, 0 }, 1349 { 2170, 1, 1, 1, 3937, 0 }, 1350 { 48, 1, 1, 1, 3937, 0 }, 1351 { 288, 1, 1, 1, 3937, 0 }, 1352 { 528, 1, 1, 1, 3937, 0 }, 1353 { 714, 1, 1, 1, 3937, 0 }, 1354 { 892, 1, 1, 1, 3937, 0 }, 1355 { 1475, 1, 1, 1, 3937, 0 }, 1356 { 1625, 1, 1, 1, 3937, 0 }, 1357 { 1775, 1, 1, 1, 3937, 0 }, 1358 { 1925, 1, 1, 1, 3937, 0 }, 1359 { 2067, 1, 1, 1, 3937, 0 }, 1360 { 102, 1, 1, 1, 3937, 0 }, 1361 { 342, 1, 1, 1, 3937, 0 }, 1362 { 582, 1, 1, 1, 3937, 0 }, 1363 { 768, 1, 1, 1, 3937, 0 }, 1364 { 946, 1, 1, 1, 3937, 0 }, 1365 { 1529, 1, 1, 1, 3937, 0 }, 1366 { 1679, 1, 1, 1, 3937, 0 }, 1367 { 1829, 1, 1, 1, 3937, 0 }, 1368 { 1979, 1, 1, 1, 3937, 0 }, 1369 { 2137, 1, 1, 1, 3937, 0 }, 1370 { 169, 1, 1, 1, 3937, 0 }, 1371 { 409, 1, 1, 1, 3937, 0 }, 1372 { 203, 1, 100, 1, 3937, 0 }, 1373 { 443, 1, 100, 1, 3937, 0 }, 1374 { 211, 1, 230, 1, 1794, 0 }, 1375 { 451, 1, 126, 1, 1794, 0 }, 1376 { 640, 1, 126, 1, 1794, 0 }, 1377 { 821, 1, 126, 1, 1794, 0 }, 1378 { 206, 1, 1, 1, 3905, 0 }, 1379 { 446, 1, 1, 1, 3905, 0 }, 1380 { 635, 1, 1, 1, 3905, 0 }, 1381 { 215, 1, 1, 1, 3905, 0 }, 1382 { 455, 1, 1, 1, 3905, 0 }, 1383 { 644, 1, 1, 1, 3905, 0 }, 1384 { 1353, 124, 1, 0, 1248, 2 }, 1385 { 228, 1, 98, 1, 3873, 0 }, 1386 { 468, 1, 98, 1, 3873, 0 }, 1387 { 657, 1, 98, 1, 3873, 0 }, 1388 { 835, 1, 98, 1, 3873, 0 }, 1389 { 1418, 1, 98, 1, 3873, 0 }, 1390 { 1572, 1, 98, 1, 3873, 0 }, 1391 { 1722, 1, 98, 1, 3873, 0 }, 1392 { 1872, 1, 98, 1, 3873, 0 }, 1393 { 1379, 122, 1, 0, 1280, 2 }, 1394 { 231, 1, 96, 1, 3841, 0 }, 1395 { 471, 1, 96, 1, 3841, 0 }, 1396 { 660, 1, 96, 1, 3841, 0 }, 1397 { 838, 1, 96, 1, 3841, 0 }, 1398 { 1421, 1, 96, 1, 3841, 0 }, 1399 { 1575, 1, 96, 1, 3841, 0 }, 1400 { 1725, 1, 96, 1, 3841, 0 }, 1401 { 1875, 1, 96, 1, 3841, 0 }, 1402 { 2017, 1, 96, 1, 3841, 0 }, 1403 { 2175, 1, 96, 1, 3841, 0 }, 1404 { 234, 1, 96, 1, 3841, 0 }, 1405 { 474, 1, 96, 1, 3841, 0 }, 1406 { 237, 92, 1, 8, 1425, 10 }, 1407 { 477, 92, 1, 8, 1425, 10 }, 1408 { 663, 92, 1, 8, 1425, 10 }, 1409 { 841, 92, 1, 8, 1425, 10 }, 1410 { 1424, 92, 1, 8, 1425, 10 }, 1411 { 1578, 92, 1, 8, 1425, 10 }, 1412 { 1728, 92, 1, 8, 1425, 10 }, 1413 { 1878, 92, 1, 8, 1425, 10 }, 1414 { 2020, 92, 1, 8, 1425, 10 }, 1415 { 2178, 92, 1, 8, 1425, 10 }, 1416 { 54, 92, 1, 8, 1425, 10 }, 1417 { 294, 92, 1, 8, 1425, 10 }, 1418 { 534, 92, 1, 8, 1425, 10 }, 1419 { 720, 92, 1, 8, 1425, 10 }, 1420 { 898, 92, 1, 8, 1425, 10 }, 1421 { 1481, 92, 1, 8, 1425, 10 }, 1422 { 1631, 92, 1, 8, 1425, 10 }, 1423 { 1781, 92, 1, 8, 1425, 10 }, 1424 { 1931, 92, 1, 8, 1425, 10 }, 1425 { 2073, 92, 1, 8, 1425, 10 }, 1426 { 108, 92, 1, 8, 1425, 10 }, 1427 { 348, 92, 1, 8, 1425, 10 }, 1428 { 588, 92, 1, 8, 1425, 10 }, 1429 { 774, 92, 1, 8, 1425, 10 }, 1430 { 952, 92, 1, 8, 1425, 10 }, 1431 { 1535, 92, 1, 8, 1425, 10 }, 1432 { 1685, 92, 1, 8, 1425, 10 }, 1433 { 1835, 92, 1, 8, 1425, 10 }, 1434 { 1985, 92, 1, 8, 1425, 10 }, 1435 { 2143, 92, 1, 8, 1425, 10 }, 1436 { 175, 92, 1, 8, 1425, 10 }, 1437 { 415, 92, 1, 8, 1425, 10 }, 1438 { 1359, 118, 1, 0, 1921, 2 }, 1439 { 983, 118, 1, 0, 1921, 2 }, 1440 { 1061, 118, 1, 0, 1921, 2 }, 1441 { 1111, 118, 1, 0, 1921, 2 }, 1442 { 1149, 118, 1, 0, 1921, 2 }, 1443 { 989, 130, 1, 12, 656, 10 }, 1444 { 996, 93, 157, 9, 1377, 10 }, 1445 { 1067, 93, 157, 9, 1377, 10 }, 1446 { 1117, 93, 157, 9, 1377, 10 }, 1447 { 1155, 93, 157, 9, 1377, 10 }, 1448 { 1187, 93, 157, 9, 1377, 10 }, 1449 { 1219, 93, 157, 9, 1377, 10 }, 1450 { 1251, 93, 157, 9, 1377, 10 }, 1451 { 1283, 93, 157, 9, 1377, 10 }, 1452 { 1315, 93, 157, 9, 1377, 10 }, 1453 { 1341, 93, 157, 9, 1377, 10 }, 1454 { 962, 93, 157, 9, 1377, 10 }, 1455 { 1040, 93, 157, 9, 1377, 10 }, 1456 { 1097, 93, 157, 9, 1377, 10 }, 1457 { 1135, 93, 157, 9, 1377, 10 }, 1458 { 1173, 93, 157, 9, 1377, 10 }, 1459 { 1205, 93, 157, 9, 1377, 10 }, 1460 { 1237, 93, 157, 9, 1377, 10 }, 1461 { 1269, 93, 157, 9, 1377, 10 }, 1462 { 1301, 93, 157, 9, 1377, 10 }, 1463 { 1327, 93, 157, 9, 1377, 10 }, 1464 { 969, 93, 157, 9, 1377, 10 }, 1465 { 1047, 93, 157, 9, 1377, 10 }, 1466 { 1104, 93, 157, 9, 1377, 10 }, 1467 { 1142, 93, 157, 9, 1377, 10 }, 1468 { 1180, 93, 157, 9, 1377, 10 }, 1469 { 1212, 93, 157, 9, 1377, 10 }, 1470 { 1244, 93, 157, 9, 1377, 10 }, 1471 { 1276, 93, 157, 9, 1377, 10 }, 1472 { 1308, 93, 157, 9, 1377, 10 }, 1473 { 1334, 93, 157, 9, 1377, 10 }, 1474 { 976, 93, 157, 9, 1377, 10 }, 1475 { 1054, 93, 157, 9, 1377, 10 }, 1476 { 2077, 1, 116, 1, 1120, 0 }, 1477 { 1002, 138, 236, 0, 1344, 2 }, 1478 { 1009, 150, 1, 0, 2337, 2 }, 1479 { 1073, 150, 1, 0, 2337, 2 }, 1480 { 1015, 150, 232, 0, 1312, 2 }, 1481 { 1022, 152, 1, 0, 2369, 2 }, 1482 { 1079, 152, 1, 0, 2369, 2 }, 1483 { 1123, 152, 1, 0, 2369, 2 }, 1484 { 1161, 152, 1, 0, 2369, 2 }, 1485 { 1193, 152, 1, 0, 2369, 2 }, 1486 { 1225, 152, 1, 0, 2369, 2 }, 1487 { 1257, 152, 1, 0, 2369, 2 }, 1488 { 1289, 152, 1, 0, 2369, 2 }, 1489 { 1028, 154, 1, 0, 2369, 2 }, 1490 { 1085, 154, 1, 0, 2369, 2 }, 1491 { 1129, 154, 1, 0, 2369, 2 }, 1492 { 1167, 154, 1, 0, 2369, 2 }, 1493 { 1199, 154, 1, 0, 2369, 2 }, 1494 { 1231, 154, 1, 0, 2369, 2 }, 1495 { 1263, 154, 1, 0, 2369, 2 }, 1496 { 1295, 154, 1, 0, 2369, 2 }, 1497 { 1321, 154, 1, 0, 2369, 2 }, 1498 { 1347, 154, 1, 0, 2369, 2 }, 1499 { 1034, 154, 1, 0, 2369, 2 }, 1500 { 1091, 154, 1, 0, 2369, 2 }, 1501}; 1502 1503extern const MCPhysReg MipsRegUnitRoots[][2] = { 1504 { Mips::AT }, 1505 { Mips::DSPCCond }, 1506 { Mips::DSPCarry }, 1507 { Mips::DSPEFI }, 1508 { Mips::DSPOutFlag16_19 }, 1509 { Mips::DSPOutFlag20 }, 1510 { Mips::DSPOutFlag21 }, 1511 { Mips::DSPOutFlag22 }, 1512 { Mips::DSPOutFlag23 }, 1513 { Mips::DSPPos }, 1514 { Mips::DSPSCount }, 1515 { Mips::FP }, 1516 { Mips::GP }, 1517 { Mips::MSAAccess }, 1518 { Mips::MSACSR }, 1519 { Mips::MSAIR }, 1520 { Mips::MSAMap }, 1521 { Mips::MSAModify }, 1522 { Mips::MSARequest }, 1523 { Mips::MSASave }, 1524 { Mips::MSAUnmap }, 1525 { Mips::PC }, 1526 { Mips::RA }, 1527 { Mips::SP }, 1528 { Mips::ZERO }, 1529 { Mips::A0 }, 1530 { Mips::A1 }, 1531 { Mips::A2 }, 1532 { Mips::A3 }, 1533 { Mips::LO0 }, 1534 { Mips::HI0 }, 1535 { Mips::LO1 }, 1536 { Mips::HI1 }, 1537 { Mips::LO2 }, 1538 { Mips::HI2 }, 1539 { Mips::LO3 }, 1540 { Mips::HI3 }, 1541 { Mips::COP00 }, 1542 { Mips::COP01 }, 1543 { Mips::COP02 }, 1544 { Mips::COP03 }, 1545 { Mips::COP04 }, 1546 { Mips::COP05 }, 1547 { Mips::COP06 }, 1548 { Mips::COP07 }, 1549 { Mips::COP08 }, 1550 { Mips::COP09 }, 1551 { Mips::COP20 }, 1552 { Mips::COP21 }, 1553 { Mips::COP22 }, 1554 { Mips::COP23 }, 1555 { Mips::COP24 }, 1556 { Mips::COP25 }, 1557 { Mips::COP26 }, 1558 { Mips::COP27 }, 1559 { Mips::COP28 }, 1560 { Mips::COP29 }, 1561 { Mips::COP30 }, 1562 { Mips::COP31 }, 1563 { Mips::COP32 }, 1564 { Mips::COP33 }, 1565 { Mips::COP34 }, 1566 { Mips::COP35 }, 1567 { Mips::COP36 }, 1568 { Mips::COP37 }, 1569 { Mips::COP38 }, 1570 { Mips::COP39 }, 1571 { Mips::COP010 }, 1572 { Mips::COP011 }, 1573 { Mips::COP012 }, 1574 { Mips::COP013 }, 1575 { Mips::COP014 }, 1576 { Mips::COP015 }, 1577 { Mips::COP016 }, 1578 { Mips::COP017 }, 1579 { Mips::COP018 }, 1580 { Mips::COP019 }, 1581 { Mips::COP020 }, 1582 { Mips::COP021 }, 1583 { Mips::COP022 }, 1584 { Mips::COP023 }, 1585 { Mips::COP024 }, 1586 { Mips::COP025 }, 1587 { Mips::COP026 }, 1588 { Mips::COP027 }, 1589 { Mips::COP028 }, 1590 { Mips::COP029 }, 1591 { Mips::COP030 }, 1592 { Mips::COP031 }, 1593 { Mips::COP210 }, 1594 { Mips::COP211 }, 1595 { Mips::COP212 }, 1596 { Mips::COP213 }, 1597 { Mips::COP214 }, 1598 { Mips::COP215 }, 1599 { Mips::COP216 }, 1600 { Mips::COP217 }, 1601 { Mips::COP218 }, 1602 { Mips::COP219 }, 1603 { Mips::COP220 }, 1604 { Mips::COP221 }, 1605 { Mips::COP222 }, 1606 { Mips::COP223 }, 1607 { Mips::COP224 }, 1608 { Mips::COP225 }, 1609 { Mips::COP226 }, 1610 { Mips::COP227 }, 1611 { Mips::COP228 }, 1612 { Mips::COP229 }, 1613 { Mips::COP230 }, 1614 { Mips::COP231 }, 1615 { Mips::COP310 }, 1616 { Mips::COP311 }, 1617 { Mips::COP312 }, 1618 { Mips::COP313 }, 1619 { Mips::COP314 }, 1620 { Mips::COP315 }, 1621 { Mips::COP316 }, 1622 { Mips::COP317 }, 1623 { Mips::COP318 }, 1624 { Mips::COP319 }, 1625 { Mips::COP320 }, 1626 { Mips::COP321 }, 1627 { Mips::COP322 }, 1628 { Mips::COP323 }, 1629 { Mips::COP324 }, 1630 { Mips::COP325 }, 1631 { Mips::COP326 }, 1632 { Mips::COP327 }, 1633 { Mips::COP328 }, 1634 { Mips::COP329 }, 1635 { Mips::COP330 }, 1636 { Mips::COP331 }, 1637 { Mips::F0 }, 1638 { Mips::F1 }, 1639 { Mips::F2 }, 1640 { Mips::F3 }, 1641 { Mips::F4 }, 1642 { Mips::F5 }, 1643 { Mips::F6 }, 1644 { Mips::F7 }, 1645 { Mips::F8 }, 1646 { Mips::F9 }, 1647 { Mips::F10 }, 1648 { Mips::F11 }, 1649 { Mips::F12 }, 1650 { Mips::F13 }, 1651 { Mips::F14 }, 1652 { Mips::F15 }, 1653 { Mips::F16 }, 1654 { Mips::F17 }, 1655 { Mips::F18 }, 1656 { Mips::F19 }, 1657 { Mips::F20 }, 1658 { Mips::F21 }, 1659 { Mips::F22 }, 1660 { Mips::F23 }, 1661 { Mips::F24 }, 1662 { Mips::F25 }, 1663 { Mips::F26 }, 1664 { Mips::F27 }, 1665 { Mips::F28 }, 1666 { Mips::F29 }, 1667 { Mips::F30 }, 1668 { Mips::F31 }, 1669 { Mips::FCC0 }, 1670 { Mips::FCC1 }, 1671 { Mips::FCC2 }, 1672 { Mips::FCC3 }, 1673 { Mips::FCC4 }, 1674 { Mips::FCC5 }, 1675 { Mips::FCC6 }, 1676 { Mips::FCC7 }, 1677 { Mips::FCR0 }, 1678 { Mips::FCR1 }, 1679 { Mips::FCR2 }, 1680 { Mips::FCR3 }, 1681 { Mips::FCR4 }, 1682 { Mips::FCR5 }, 1683 { Mips::FCR6 }, 1684 { Mips::FCR7 }, 1685 { Mips::FCR8 }, 1686 { Mips::FCR9 }, 1687 { Mips::FCR10 }, 1688 { Mips::FCR11 }, 1689 { Mips::FCR12 }, 1690 { Mips::FCR13 }, 1691 { Mips::FCR14 }, 1692 { Mips::FCR15 }, 1693 { Mips::FCR16 }, 1694 { Mips::FCR17 }, 1695 { Mips::FCR18 }, 1696 { Mips::FCR19 }, 1697 { Mips::FCR20 }, 1698 { Mips::FCR21 }, 1699 { Mips::FCR22 }, 1700 { Mips::FCR23 }, 1701 { Mips::FCR24 }, 1702 { Mips::FCR25 }, 1703 { Mips::FCR26 }, 1704 { Mips::FCR27 }, 1705 { Mips::FCR28 }, 1706 { Mips::FCR29 }, 1707 { Mips::FCR30 }, 1708 { Mips::FCR31 }, 1709 { Mips::F_HI0 }, 1710 { Mips::F_HI1 }, 1711 { Mips::F_HI2 }, 1712 { Mips::F_HI3 }, 1713 { Mips::F_HI4 }, 1714 { Mips::F_HI5 }, 1715 { Mips::F_HI6 }, 1716 { Mips::F_HI7 }, 1717 { Mips::F_HI8 }, 1718 { Mips::F_HI9 }, 1719 { Mips::F_HI10 }, 1720 { Mips::F_HI11 }, 1721 { Mips::F_HI12 }, 1722 { Mips::F_HI13 }, 1723 { Mips::F_HI14 }, 1724 { Mips::F_HI15 }, 1725 { Mips::F_HI16 }, 1726 { Mips::F_HI17 }, 1727 { Mips::F_HI18 }, 1728 { Mips::F_HI19 }, 1729 { Mips::F_HI20 }, 1730 { Mips::F_HI21 }, 1731 { Mips::F_HI22 }, 1732 { Mips::F_HI23 }, 1733 { Mips::F_HI24 }, 1734 { Mips::F_HI25 }, 1735 { Mips::F_HI26 }, 1736 { Mips::F_HI27 }, 1737 { Mips::F_HI28 }, 1738 { Mips::F_HI29 }, 1739 { Mips::F_HI30 }, 1740 { Mips::F_HI31 }, 1741 { Mips::HWR0 }, 1742 { Mips::HWR1 }, 1743 { Mips::HWR2 }, 1744 { Mips::HWR3 }, 1745 { Mips::HWR4 }, 1746 { Mips::HWR5 }, 1747 { Mips::HWR6 }, 1748 { Mips::HWR7 }, 1749 { Mips::HWR8 }, 1750 { Mips::HWR9 }, 1751 { Mips::HWR10 }, 1752 { Mips::HWR11 }, 1753 { Mips::HWR12 }, 1754 { Mips::HWR13 }, 1755 { Mips::HWR14 }, 1756 { Mips::HWR15 }, 1757 { Mips::HWR16 }, 1758 { Mips::HWR17 }, 1759 { Mips::HWR18 }, 1760 { Mips::HWR19 }, 1761 { Mips::HWR20 }, 1762 { Mips::HWR21 }, 1763 { Mips::HWR22 }, 1764 { Mips::HWR23 }, 1765 { Mips::HWR24 }, 1766 { Mips::HWR25 }, 1767 { Mips::HWR26 }, 1768 { Mips::HWR27 }, 1769 { Mips::HWR28 }, 1770 { Mips::HWR29 }, 1771 { Mips::HWR30 }, 1772 { Mips::HWR31 }, 1773 { Mips::K0 }, 1774 { Mips::K1 }, 1775 { Mips::MPL0 }, 1776 { Mips::MPL1 }, 1777 { Mips::MPL2 }, 1778 { Mips::P0 }, 1779 { Mips::P1 }, 1780 { Mips::P2 }, 1781 { Mips::S0 }, 1782 { Mips::S1 }, 1783 { Mips::S2 }, 1784 { Mips::S3 }, 1785 { Mips::S4 }, 1786 { Mips::S5 }, 1787 { Mips::S6 }, 1788 { Mips::S7 }, 1789 { Mips::T0 }, 1790 { Mips::T1 }, 1791 { Mips::T2 }, 1792 { Mips::T3 }, 1793 { Mips::T4 }, 1794 { Mips::T5 }, 1795 { Mips::T6 }, 1796 { Mips::T7 }, 1797 { Mips::T8 }, 1798 { Mips::T9 }, 1799 { Mips::V0 }, 1800 { Mips::V1 }, 1801}; 1802 1803namespace { // Register classes... 1804 // OddSP Register Class... 1805 const MCPhysReg OddSP[] = { 1806 Mips::F1, Mips::F3, Mips::F5, Mips::F7, Mips::F9, Mips::F11, Mips::F13, Mips::F15, Mips::F17, Mips::F19, Mips::F21, Mips::F23, Mips::F25, Mips::F27, Mips::F29, Mips::F31, Mips::F_HI1, Mips::F_HI3, Mips::F_HI5, Mips::F_HI7, Mips::F_HI9, Mips::F_HI11, Mips::F_HI13, Mips::F_HI15, Mips::F_HI17, Mips::F_HI19, Mips::F_HI21, Mips::F_HI23, Mips::F_HI25, Mips::F_HI27, Mips::F_HI29, Mips::F_HI31, Mips::D1, Mips::D3, Mips::D5, Mips::D7, Mips::D9, Mips::D11, Mips::D13, Mips::D15, Mips::D1_64, Mips::D3_64, Mips::D5_64, Mips::D7_64, Mips::D9_64, Mips::D11_64, Mips::D13_64, Mips::D15_64, Mips::D17_64, Mips::D19_64, Mips::D21_64, Mips::D23_64, Mips::D25_64, Mips::D27_64, Mips::D29_64, Mips::D31_64, 1807 }; 1808 1809 // OddSP Bit set. 1810 const uint8_t OddSPBits[] = { 1811 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x50, 0x55, 0x55, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, 1812 }; 1813 1814 // CCR Register Class... 1815 const MCPhysReg CCR[] = { 1816 Mips::FCR0, Mips::FCR1, Mips::FCR2, Mips::FCR3, Mips::FCR4, Mips::FCR5, Mips::FCR6, Mips::FCR7, Mips::FCR8, Mips::FCR9, Mips::FCR10, Mips::FCR11, Mips::FCR12, Mips::FCR13, Mips::FCR14, Mips::FCR15, Mips::FCR16, Mips::FCR17, Mips::FCR18, Mips::FCR19, Mips::FCR20, Mips::FCR21, Mips::FCR22, Mips::FCR23, Mips::FCR24, Mips::FCR25, Mips::FCR26, Mips::FCR27, Mips::FCR28, Mips::FCR29, Mips::FCR30, Mips::FCR31, 1817 }; 1818 1819 // CCR Bit set. 1820 const uint8_t CCRBits[] = { 1821 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 1822 }; 1823 1824 // COP0 Register Class... 1825 const MCPhysReg COP0[] = { 1826 Mips::COP00, Mips::COP01, Mips::COP02, Mips::COP03, Mips::COP04, Mips::COP05, Mips::COP06, Mips::COP07, Mips::COP08, Mips::COP09, Mips::COP010, Mips::COP011, Mips::COP012, Mips::COP013, Mips::COP014, Mips::COP015, Mips::COP016, Mips::COP017, Mips::COP018, Mips::COP019, Mips::COP020, Mips::COP021, Mips::COP022, Mips::COP023, Mips::COP024, Mips::COP025, Mips::COP026, Mips::COP027, Mips::COP028, Mips::COP029, Mips::COP030, Mips::COP031, 1827 }; 1828 1829 // COP0 Bit set. 1830 const uint8_t COP0Bits[] = { 1831 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0x00, 0xe0, 0xff, 0xff, 0x07, 1832 }; 1833 1834 // COP2 Register Class... 1835 const MCPhysReg COP2[] = { 1836 Mips::COP20, Mips::COP21, Mips::COP22, Mips::COP23, Mips::COP24, Mips::COP25, Mips::COP26, Mips::COP27, Mips::COP28, Mips::COP29, Mips::COP210, Mips::COP211, Mips::COP212, Mips::COP213, Mips::COP214, Mips::COP215, Mips::COP216, Mips::COP217, Mips::COP218, Mips::COP219, Mips::COP220, Mips::COP221, Mips::COP222, Mips::COP223, Mips::COP224, Mips::COP225, Mips::COP226, Mips::COP227, Mips::COP228, Mips::COP229, Mips::COP230, Mips::COP231, 1837 }; 1838 1839 // COP2 Bit set. 1840 const uint8_t COP2Bits[] = { 1841 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01, 1842 }; 1843 1844 // COP3 Register Class... 1845 const MCPhysReg COP3[] = { 1846 Mips::COP30, Mips::COP31, Mips::COP32, Mips::COP33, Mips::COP34, Mips::COP35, Mips::COP36, Mips::COP37, Mips::COP38, Mips::COP39, Mips::COP310, Mips::COP311, Mips::COP312, Mips::COP313, Mips::COP314, Mips::COP315, Mips::COP316, Mips::COP317, Mips::COP318, Mips::COP319, Mips::COP320, Mips::COP321, Mips::COP322, Mips::COP323, Mips::COP324, Mips::COP325, Mips::COP326, Mips::COP327, Mips::COP328, Mips::COP329, Mips::COP330, Mips::COP331, 1847 }; 1848 1849 // COP3 Bit set. 1850 const uint8_t COP3Bits[] = { 1851 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x7f, 1852 }; 1853 1854 // DSPR Register Class... 1855 const MCPhysReg DSPR[] = { 1856 Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA, 1857 }; 1858 1859 // DSPR Bit set. 1860 const uint8_t DSPRBits[] = { 1861 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, 1862 }; 1863 1864 // FGR32 Register Class... 1865 const MCPhysReg FGR32[] = { 1866 Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31, 1867 }; 1868 1869 // FGR32 Bit set. 1870 const uint8_t FGR32Bits[] = { 1871 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 1872 }; 1873 1874 // FGRCC Register Class... 1875 const MCPhysReg FGRCC[] = { 1876 Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31, 1877 }; 1878 1879 // FGRCC Bit set. 1880 const uint8_t FGRCCBits[] = { 1881 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 1882 }; 1883 1884 // FGRH32 Register Class... 1885 const MCPhysReg FGRH32[] = { 1886 Mips::F_HI0, Mips::F_HI1, Mips::F_HI2, Mips::F_HI3, Mips::F_HI4, Mips::F_HI5, Mips::F_HI6, Mips::F_HI7, Mips::F_HI8, Mips::F_HI9, Mips::F_HI10, Mips::F_HI11, Mips::F_HI12, Mips::F_HI13, Mips::F_HI14, Mips::F_HI15, Mips::F_HI16, Mips::F_HI17, Mips::F_HI18, Mips::F_HI19, Mips::F_HI20, Mips::F_HI21, Mips::F_HI22, Mips::F_HI23, Mips::F_HI24, Mips::F_HI25, Mips::F_HI26, Mips::F_HI27, Mips::F_HI28, Mips::F_HI29, Mips::F_HI30, Mips::F_HI31, 1887 }; 1888 1889 // FGRH32 Bit set. 1890 const uint8_t FGRH32Bits[] = { 1891 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 1892 }; 1893 1894 // GPR32 Register Class... 1895 const MCPhysReg GPR32[] = { 1896 Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA, 1897 }; 1898 1899 // GPR32 Bit set. 1900 const uint8_t GPR32Bits[] = { 1901 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, 1902 }; 1903 1904 // HWRegs Register Class... 1905 const MCPhysReg HWRegs[] = { 1906 Mips::HWR0, Mips::HWR1, Mips::HWR2, Mips::HWR3, Mips::HWR4, Mips::HWR5, Mips::HWR6, Mips::HWR7, Mips::HWR8, Mips::HWR9, Mips::HWR10, Mips::HWR11, Mips::HWR12, Mips::HWR13, Mips::HWR14, Mips::HWR15, Mips::HWR16, Mips::HWR17, Mips::HWR18, Mips::HWR19, Mips::HWR20, Mips::HWR21, Mips::HWR22, Mips::HWR23, Mips::HWR24, Mips::HWR25, Mips::HWR26, Mips::HWR27, Mips::HWR28, Mips::HWR29, Mips::HWR30, Mips::HWR31, 1907 }; 1908 1909 // HWRegs Bit set. 1910 const uint8_t HWRegsBits[] = { 1911 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 1912 }; 1913 1914 // OddSP_with_sub_hi Register Class... 1915 const MCPhysReg OddSP_with_sub_hi[] = { 1916 Mips::D1, Mips::D3, Mips::D5, Mips::D7, Mips::D9, Mips::D11, Mips::D13, Mips::D15, Mips::D1_64, Mips::D3_64, Mips::D5_64, Mips::D7_64, Mips::D9_64, Mips::D11_64, Mips::D13_64, Mips::D15_64, Mips::D17_64, Mips::D19_64, Mips::D21_64, Mips::D23_64, Mips::D25_64, Mips::D27_64, Mips::D29_64, Mips::D31_64, 1917 }; 1918 1919 // OddSP_with_sub_hi Bit set. 1920 const uint8_t OddSP_with_sub_hiBits[] = { 1921 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, 1922 }; 1923 1924 // FGR32_and_OddSP Register Class... 1925 const MCPhysReg FGR32_and_OddSP[] = { 1926 Mips::F1, Mips::F3, Mips::F5, Mips::F7, Mips::F9, Mips::F11, Mips::F13, Mips::F15, Mips::F17, Mips::F19, Mips::F21, Mips::F23, Mips::F25, Mips::F27, Mips::F29, Mips::F31, 1927 }; 1928 1929 // FGR32_and_OddSP Bit set. 1930 const uint8_t FGR32_and_OddSPBits[] = { 1931 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, 1932 }; 1933 1934 // FGRH32_and_OddSP Register Class... 1935 const MCPhysReg FGRH32_and_OddSP[] = { 1936 Mips::F_HI1, Mips::F_HI3, Mips::F_HI5, Mips::F_HI7, Mips::F_HI9, Mips::F_HI11, Mips::F_HI13, Mips::F_HI15, Mips::F_HI17, Mips::F_HI19, Mips::F_HI21, Mips::F_HI23, Mips::F_HI25, Mips::F_HI27, Mips::F_HI29, Mips::F_HI31, 1937 }; 1938 1939 // FGRH32_and_OddSP Bit set. 1940 const uint8_t FGRH32_and_OddSPBits[] = { 1941 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, 1942 }; 1943 1944 // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Register Class... 1945 const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGRH32[] = { 1946 Mips::D1_64, Mips::D3_64, Mips::D5_64, Mips::D7_64, Mips::D9_64, Mips::D11_64, Mips::D13_64, Mips::D15_64, Mips::D17_64, Mips::D19_64, Mips::D21_64, Mips::D23_64, Mips::D25_64, Mips::D27_64, Mips::D29_64, Mips::D31_64, 1947 }; 1948 1949 // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Bit set. 1950 const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits[] = { 1951 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, 1952 }; 1953 1954 // CPU16RegsPlusSP Register Class... 1955 const MCPhysReg CPU16RegsPlusSP[] = { 1956 Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1, Mips::SP, 1957 }; 1958 1959 // CPU16RegsPlusSP Bit set. 1960 const uint8_t CPU16RegsPlusSPBits[] = { 1961 0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, 1962 }; 1963 1964 // CPU16Regs Register Class... 1965 const MCPhysReg CPU16Regs[] = { 1966 Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1, 1967 }; 1968 1969 // CPU16Regs Bit set. 1970 const uint8_t CPU16RegsBits[] = { 1971 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, 1972 }; 1973 1974 // FCC Register Class... 1975 const MCPhysReg FCC[] = { 1976 Mips::FCC0, Mips::FCC1, Mips::FCC2, Mips::FCC3, Mips::FCC4, Mips::FCC5, Mips::FCC6, Mips::FCC7, 1977 }; 1978 1979 // FCC Bit set. 1980 const uint8_t FCCBits[] = { 1981 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 1982 }; 1983 1984 // GPRMM16 Register Class... 1985 const MCPhysReg GPRMM16[] = { 1986 Mips::S0, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, 1987 }; 1988 1989 // GPRMM16 Bit set. 1990 const uint8_t GPRMM16Bits[] = { 1991 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, 1992 }; 1993 1994 // GPRMM16MoveP Register Class... 1995 const MCPhysReg GPRMM16MoveP[] = { 1996 Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4, 1997 }; 1998 1999 // GPRMM16MoveP Bit set. 2000 const uint8_t GPRMM16MovePBits[] = { 2001 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06, 2002 }; 2003 2004 // GPRMM16Zero Register Class... 2005 const MCPhysReg GPRMM16Zero[] = { 2006 Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, 2007 }; 2008 2009 // GPRMM16Zero Bit set. 2010 const uint8_t GPRMM16ZeroBits[] = { 2011 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, 2012 }; 2013 2014 // MSACtrl Register Class... 2015 const MCPhysReg MSACtrl[] = { 2016 Mips::MSAIR, Mips::MSACSR, Mips::MSAAccess, Mips::MSASave, Mips::MSAModify, Mips::MSARequest, Mips::MSAMap, Mips::MSAUnmap, 2017 }; 2018 2019 // MSACtrl Bit set. 2020 const uint8_t MSACtrlBits[] = { 2021 0x00, 0xfc, 0x03, 2022 }; 2023 2024 // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Register Class... 2025 const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGR32[] = { 2026 Mips::D1, Mips::D3, Mips::D5, Mips::D7, Mips::D9, Mips::D11, Mips::D13, Mips::D15, 2027 }; 2028 2029 // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Bit set. 2030 const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits[] = { 2031 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 2032 }; 2033 2034 // CPU16Regs_and_GPRMM16Zero Register Class... 2035 const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = { 2036 Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, 2037 }; 2038 2039 // CPU16Regs_and_GPRMM16Zero Bit set. 2040 const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = { 2041 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, 2042 }; 2043 2044 // CPU16Regs_and_GPRMM16MoveP Register Class... 2045 const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = { 2046 Mips::S1, Mips::V0, Mips::V1, Mips::S0, 2047 }; 2048 2049 // CPU16Regs_and_GPRMM16MoveP Bit set. 2050 const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = { 2051 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, 2052 }; 2053 2054 // GPRMM16MoveP_and_GPRMM16Zero Register Class... 2055 const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = { 2056 Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, 2057 }; 2058 2059 // GPRMM16MoveP_and_GPRMM16Zero Bit set. 2060 const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = { 2061 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, 2062 }; 2063 2064 // HI32DSP Register Class... 2065 const MCPhysReg HI32DSP[] = { 2066 Mips::HI0, Mips::HI1, Mips::HI2, Mips::HI3, 2067 }; 2068 2069 // HI32DSP Bit set. 2070 const uint8_t HI32DSPBits[] = { 2071 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 2072 }; 2073 2074 // LO32DSP Register Class... 2075 const MCPhysReg LO32DSP[] = { 2076 Mips::LO0, Mips::LO1, Mips::LO2, Mips::LO3, 2077 }; 2078 2079 // LO32DSP Bit set. 2080 const uint8_t LO32DSPBits[] = { 2081 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 2082 }; 2083 2084 // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class... 2085 const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { 2086 Mips::S1, Mips::V0, Mips::V1, 2087 }; 2088 2089 // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. 2090 const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { 2091 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, 2092 }; 2093 2094 // CPURAReg Register Class... 2095 const MCPhysReg CPURAReg[] = { 2096 Mips::RA, 2097 }; 2098 2099 // CPURAReg Bit set. 2100 const uint8_t CPURARegBits[] = { 2101 0x00, 0x00, 0x08, 2102 }; 2103 2104 // CPUSPReg Register Class... 2105 const MCPhysReg CPUSPReg[] = { 2106 Mips::SP, 2107 }; 2108 2109 // CPUSPReg Bit set. 2110 const uint8_t CPUSPRegBits[] = { 2111 0x00, 0x00, 0x10, 2112 }; 2113 2114 // DSPCC Register Class... 2115 const MCPhysReg DSPCC[] = { 2116 Mips::DSPCCond, 2117 }; 2118 2119 // DSPCC Bit set. 2120 const uint8_t DSPCCBits[] = { 2121 0x04, 2122 }; 2123 2124 // HI32 Register Class... 2125 const MCPhysReg HI32[] = { 2126 Mips::HI0, 2127 }; 2128 2129 // HI32 Bit set. 2130 const uint8_t HI32Bits[] = { 2131 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 2132 }; 2133 2134 // LO32 Register Class... 2135 const MCPhysReg LO32[] = { 2136 Mips::LO0, 2137 }; 2138 2139 // LO32 Bit set. 2140 const uint8_t LO32Bits[] = { 2141 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 2142 }; 2143 2144 // FGR64 Register Class... 2145 const MCPhysReg FGR64[] = { 2146 Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64, Mips::D20_64, Mips::D21_64, Mips::D22_64, Mips::D23_64, Mips::D24_64, Mips::D25_64, Mips::D26_64, Mips::D27_64, Mips::D28_64, Mips::D29_64, Mips::D30_64, Mips::D31_64, 2147 }; 2148 2149 // FGR64 Bit set. 2150 const uint8_t FGR64Bits[] = { 2151 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 2152 }; 2153 2154 // GPR64 Register Class... 2155 const MCPhysReg GPR64[] = { 2156 Mips::ZERO_64, Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64, 2157 }; 2158 2159 // GPR64 Bit set. 2160 const uint8_t GPR64Bits[] = { 2161 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, 2162 }; 2163 2164 // AFGR64 Register Class... 2165 const MCPhysReg AFGR64[] = { 2166 Mips::D0, Mips::D1, Mips::D2, Mips::D3, Mips::D4, Mips::D5, Mips::D6, Mips::D7, Mips::D8, Mips::D9, Mips::D10, Mips::D11, Mips::D12, Mips::D13, Mips::D14, Mips::D15, 2167 }; 2168 2169 // AFGR64 Bit set. 2170 const uint8_t AFGR64Bits[] = { 2171 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 2172 }; 2173 2174 // FGR64_and_OddSP Register Class... 2175 const MCPhysReg FGR64_and_OddSP[] = { 2176 Mips::D1_64, Mips::D3_64, Mips::D5_64, Mips::D7_64, Mips::D9_64, Mips::D11_64, Mips::D13_64, Mips::D15_64, Mips::D17_64, Mips::D19_64, Mips::D21_64, Mips::D23_64, Mips::D25_64, Mips::D27_64, Mips::D29_64, Mips::D31_64, 2177 }; 2178 2179 // FGR64_and_OddSP Bit set. 2180 const uint8_t FGR64_and_OddSPBits[] = { 2181 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, 2182 }; 2183 2184 // GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class... 2185 const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = { 2186 Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64, Mips::SP_64, 2187 }; 2188 2189 // GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set. 2190 const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = { 2191 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, 2192 }; 2193 2194 // AFGR64_and_OddSP Register Class... 2195 const MCPhysReg AFGR64_and_OddSP[] = { 2196 Mips::D1, Mips::D3, Mips::D5, Mips::D7, Mips::D9, Mips::D11, Mips::D13, Mips::D15, 2197 }; 2198 2199 // AFGR64_and_OddSP Bit set. 2200 const uint8_t AFGR64_and_OddSPBits[] = { 2201 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 2202 }; 2203 2204 // GPR64_with_sub_32_in_CPU16Regs Register Class... 2205 const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = { 2206 Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64, 2207 }; 2208 2209 // GPR64_with_sub_32_in_CPU16Regs Bit set. 2210 const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = { 2211 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, 2212 }; 2213 2214 // GPR64_with_sub_32_in_GPRMM16MoveP Register Class... 2215 const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = { 2216 Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, 2217 }; 2218 2219 // GPR64_with_sub_32_in_GPRMM16MoveP Bit set. 2220 const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = { 2221 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03, 2222 }; 2223 2224 // GPR64_with_sub_32_in_GPRMM16Zero Register Class... 2225 const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = { 2226 Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64, 2227 }; 2228 2229 // GPR64_with_sub_32_in_GPRMM16Zero Bit set. 2230 const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = { 2231 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, 2232 }; 2233 2234 // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class... 2235 const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = { 2236 Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64, 2237 }; 2238 2239 // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set. 2240 const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = { 2241 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, 2242 }; 2243 2244 // ACC64DSP Register Class... 2245 const MCPhysReg ACC64DSP[] = { 2246 Mips::AC0, Mips::AC1, Mips::AC2, Mips::AC3, 2247 }; 2248 2249 // ACC64DSP Bit set. 2250 const uint8_t ACC64DSPBits[] = { 2251 0x00, 0x00, 0x00, 0x3c, 2252 }; 2253 2254 // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class... 2255 const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = { 2256 Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, 2257 }; 2258 2259 // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set. 2260 const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = { 2261 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, 2262 }; 2263 2264 // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class... 2265 const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = { 2266 Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S1_64, 2267 }; 2268 2269 // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set. 2270 const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = { 2271 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, 2272 }; 2273 2274 // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class... 2275 const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { 2276 Mips::V0_64, Mips::V1_64, Mips::S1_64, 2277 }; 2278 2279 // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. 2280 const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { 2281 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, 2282 }; 2283 2284 // OCTEON_MPL Register Class... 2285 const MCPhysReg OCTEON_MPL[] = { 2286 Mips::MPL0, Mips::MPL1, Mips::MPL2, 2287 }; 2288 2289 // OCTEON_MPL Bit set. 2290 const uint8_t OCTEON_MPLBits[] = { 2291 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, 2292 }; 2293 2294 // OCTEON_P Register Class... 2295 const MCPhysReg OCTEON_P[] = { 2296 Mips::P0, Mips::P1, Mips::P2, 2297 }; 2298 2299 // OCTEON_P Bit set. 2300 const uint8_t OCTEON_PBits[] = { 2301 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 2302 }; 2303 2304 // ACC64 Register Class... 2305 const MCPhysReg ACC64[] = { 2306 Mips::AC0, 2307 }; 2308 2309 // ACC64 Bit set. 2310 const uint8_t ACC64Bits[] = { 2311 0x00, 0x00, 0x00, 0x04, 2312 }; 2313 2314 // GPR64_with_sub_32_in_CPURAReg Register Class... 2315 const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = { 2316 Mips::RA_64, 2317 }; 2318 2319 // GPR64_with_sub_32_in_CPURAReg Bit set. 2320 const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = { 2321 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 2322 }; 2323 2324 // GPR64_with_sub_32_in_CPUSPReg Register Class... 2325 const MCPhysReg GPR64_with_sub_32_in_CPUSPReg[] = { 2326 Mips::SP_64, 2327 }; 2328 2329 // GPR64_with_sub_32_in_CPUSPReg Bit set. 2330 const uint8_t GPR64_with_sub_32_in_CPUSPRegBits[] = { 2331 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 2332 }; 2333 2334 // HI64 Register Class... 2335 const MCPhysReg HI64[] = { 2336 Mips::HI0_64, 2337 }; 2338 2339 // HI64 Bit set. 2340 const uint8_t HI64Bits[] = { 2341 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 2342 }; 2343 2344 // LO64 Register Class... 2345 const MCPhysReg LO64[] = { 2346 Mips::LO0_64, 2347 }; 2348 2349 // LO64 Bit set. 2350 const uint8_t LO64Bits[] = { 2351 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 2352 }; 2353 2354 // MSA128B Register Class... 2355 const MCPhysReg MSA128B[] = { 2356 Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31, 2357 }; 2358 2359 // MSA128B Bit set. 2360 const uint8_t MSA128BBits[] = { 2361 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 2362 }; 2363 2364 // MSA128D Register Class... 2365 const MCPhysReg MSA128D[] = { 2366 Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31, 2367 }; 2368 2369 // MSA128D Bit set. 2370 const uint8_t MSA128DBits[] = { 2371 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 2372 }; 2373 2374 // MSA128H Register Class... 2375 const MCPhysReg MSA128H[] = { 2376 Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31, 2377 }; 2378 2379 // MSA128H Bit set. 2380 const uint8_t MSA128HBits[] = { 2381 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 2382 }; 2383 2384 // MSA128W Register Class... 2385 const MCPhysReg MSA128W[] = { 2386 Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31, 2387 }; 2388 2389 // MSA128W Bit set. 2390 const uint8_t MSA128WBits[] = { 2391 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 2392 }; 2393 2394 // MSA128B_with_sub_64_in_OddSP Register Class... 2395 const MCPhysReg MSA128B_with_sub_64_in_OddSP[] = { 2396 Mips::W1, Mips::W3, Mips::W5, Mips::W7, Mips::W9, Mips::W11, Mips::W13, Mips::W15, Mips::W17, Mips::W19, Mips::W21, Mips::W23, Mips::W25, Mips::W27, Mips::W29, Mips::W31, 2397 }; 2398 2399 // MSA128B_with_sub_64_in_OddSP Bit set. 2400 const uint8_t MSA128B_with_sub_64_in_OddSPBits[] = { 2401 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, 2402 }; 2403 2404 // MSA128WEvens Register Class... 2405 const MCPhysReg MSA128WEvens[] = { 2406 Mips::W0, Mips::W2, Mips::W4, Mips::W6, Mips::W8, Mips::W10, Mips::W12, Mips::W14, Mips::W16, Mips::W18, Mips::W20, Mips::W22, Mips::W24, Mips::W26, Mips::W28, Mips::W30, 2407 }; 2408 2409 // MSA128WEvens Bit set. 2410 const uint8_t MSA128WEvensBits[] = { 2411 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02, 2412 }; 2413 2414 // ACC128 Register Class... 2415 const MCPhysReg ACC128[] = { 2416 Mips::AC0_64, 2417 }; 2418 2419 // ACC128 Bit set. 2420 const uint8_t ACC128Bits[] = { 2421 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 2422 }; 2423 2424} 2425 2426extern const char MipsRegClassStrings[] = { 2427 /* 0 */ 'C', 'O', 'P', '0', 0, 2428 /* 5 */ 'O', 'd', 'd', 'S', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'i', 'n', '_', 'F', 'G', 'R', 'H', '3', '2', 0, 2429 /* 45 */ 'H', 'I', '3', '2', 0, 2430 /* 50 */ 'L', 'O', '3', '2', 0, 2431 /* 55 */ 'O', 'd', 'd', 'S', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'i', 'n', '_', 'F', 'G', 'R', '3', '2', 0, 2432 /* 94 */ 'G', 'P', 'R', '3', '2', 0, 2433 /* 100 */ 'C', 'O', 'P', '2', 0, 2434 /* 105 */ 'C', 'O', 'P', '3', 0, 2435 /* 110 */ 'A', 'C', 'C', '6', '4', 0, 2436 /* 116 */ 'H', 'I', '6', '4', 0, 2437 /* 121 */ 'L', 'O', '6', '4', 0, 2438 /* 126 */ 'A', 'F', 'G', 'R', '6', '4', 0, 2439 /* 133 */ 'G', 'P', 'R', '6', '4', 0, 2440 /* 139 */ 'G', 'P', 'R', 'M', 'M', '1', '6', 0, 2441 /* 147 */ 'A', 'C', 'C', '1', '2', '8', 0, 2442 /* 154 */ 'M', 'S', 'A', '1', '2', '8', 'B', 0, 2443 /* 162 */ 'F', 'C', 'C', 0, 2444 /* 166 */ 'D', 'S', 'P', 'C', 'C', 0, 2445 /* 172 */ 'F', 'G', 'R', 'C', 'C', 0, 2446 /* 178 */ 'M', 'S', 'A', '1', '2', '8', 'D', 0, 2447 /* 186 */ 'M', 'S', 'A', '1', '2', '8', 'H', 0, 2448 /* 194 */ 'O', 'C', 'T', 'E', 'O', 'N', '_', 'M', 'P', 'L', 0, 2449 /* 205 */ 'H', 'I', '3', '2', 'D', 'S', 'P', 0, 2450 /* 213 */ 'L', 'O', '3', '2', 'D', 'S', 'P', 0, 2451 /* 221 */ 'A', 'C', 'C', '6', '4', 'D', 'S', 'P', 0, 2452 /* 230 */ 'F', 'G', 'R', 'H', '3', '2', '_', 'a', 'n', 'd', '_', 'O', 'd', 'd', 'S', 'P', 0, 2453 /* 247 */ 'F', 'G', 'R', '3', '2', '_', 'a', 'n', 'd', '_', 'O', 'd', 'd', 'S', 'P', 0, 2454 /* 263 */ 'A', 'F', 'G', 'R', '6', '4', '_', 'a', 'n', 'd', '_', 'O', 'd', 'd', 'S', 'P', 0, 2455 /* 280 */ 'M', 'S', 'A', '1', '2', '8', 'B', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '6', '4', '_', 'i', 'n', '_', 'O', 'd', 'd', 'S', 'P', 0, 2456 /* 309 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', 'P', 'l', 'u', 's', 'S', 'P', 0, 2457 /* 346 */ 'O', 'C', 'T', 'E', 'O', 'N', '_', 'P', 0, 2458 /* 355 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0, 2459 /* 403 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0, 2460 /* 437 */ 'C', 'C', 'R', 0, 2461 /* 441 */ 'D', 'S', 'P', 'R', 0, 2462 /* 446 */ 'M', 'S', 'A', '1', '2', '8', 'W', 0, 2463 /* 454 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', 'R', 'A', 'R', 'e', 'g', 0, 2464 /* 484 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', 'S', 'P', 'R', 'e', 'g', 0, 2465 /* 514 */ 'O', 'd', 'd', 'S', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', 0, 2466 /* 532 */ 'M', 'S', 'A', 'C', 't', 'r', 'l', 0, 2467 /* 540 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0, 2468 /* 590 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', '_', 'a', 'n', 'd', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0, 2469 /* 654 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0, 2470 /* 701 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0, 2471 /* 734 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', 0, 2472 /* 765 */ 'H', 'W', 'R', 'e', 'g', 's', 0, 2473 /* 772 */ 'M', 'S', 'A', '1', '2', '8', 'W', 'E', 'v', 'e', 'n', 's', 0, 2474}; 2475 2476extern const MCRegisterClass MipsMCRegisterClasses[] = { 2477 { OddSP, OddSPBits, 241, 56, sizeof(OddSPBits), Mips::OddSPRegClassID, 4, 4, 1, 0 }, 2478 { CCR, CCRBits, 437, 32, sizeof(CCRBits), Mips::CCRRegClassID, 4, 4, 1, 0 }, 2479 { COP0, COP0Bits, 0, 32, sizeof(COP0Bits), Mips::COP0RegClassID, 4, 4, 1, 0 }, 2480 { COP2, COP2Bits, 100, 32, sizeof(COP2Bits), Mips::COP2RegClassID, 4, 4, 1, 0 }, 2481 { COP3, COP3Bits, 105, 32, sizeof(COP3Bits), Mips::COP3RegClassID, 4, 4, 1, 0 }, 2482 { DSPR, DSPRBits, 441, 32, sizeof(DSPRBits), Mips::DSPRRegClassID, 4, 4, 1, 1 }, 2483 { FGR32, FGR32Bits, 88, 32, sizeof(FGR32Bits), Mips::FGR32RegClassID, 4, 4, 1, 1 }, 2484 { FGRCC, FGRCCBits, 172, 32, sizeof(FGRCCBits), Mips::FGRCCRegClassID, 4, 4, 1, 1 }, 2485 { FGRH32, FGRH32Bits, 38, 32, sizeof(FGRH32Bits), Mips::FGRH32RegClassID, 4, 4, 1, 0 }, 2486 { GPR32, GPR32Bits, 94, 32, sizeof(GPR32Bits), Mips::GPR32RegClassID, 4, 4, 1, 1 }, 2487 { HWRegs, HWRegsBits, 765, 32, sizeof(HWRegsBits), Mips::HWRegsRegClassID, 4, 4, 1, 0 }, 2488 { OddSP_with_sub_hi, OddSP_with_sub_hiBits, 514, 24, sizeof(OddSP_with_sub_hiBits), Mips::OddSP_with_sub_hiRegClassID, 4, 4, 1, 0 }, 2489 { FGR32_and_OddSP, FGR32_and_OddSPBits, 247, 16, sizeof(FGR32_and_OddSPBits), Mips::FGR32_and_OddSPRegClassID, 4, 4, 1, 1 }, 2490 { FGRH32_and_OddSP, FGRH32_and_OddSPBits, 230, 16, sizeof(FGRH32_and_OddSPBits), Mips::FGRH32_and_OddSPRegClassID, 4, 4, 1, 0 }, 2491 { OddSP_with_sub_hi_with_sub_hi_in_FGRH32, OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits, 5, 16, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits), Mips::OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID, 4, 4, 1, 0 }, 2492 { CPU16RegsPlusSP, CPU16RegsPlusSPBits, 330, 9, sizeof(CPU16RegsPlusSPBits), Mips::CPU16RegsPlusSPRegClassID, 4, 4, 1, 1 }, 2493 { CPU16Regs, CPU16RegsBits, 755, 8, sizeof(CPU16RegsBits), Mips::CPU16RegsRegClassID, 4, 4, 1, 1 }, 2494 { FCC, FCCBits, 162, 8, sizeof(FCCBits), Mips::FCCRegClassID, 4, 4, 1, 0 }, 2495 { GPRMM16, GPRMM16Bits, 139, 8, sizeof(GPRMM16Bits), Mips::GPRMM16RegClassID, 4, 4, 1, 1 }, 2496 { GPRMM16MoveP, GPRMM16MovePBits, 390, 8, sizeof(GPRMM16MovePBits), Mips::GPRMM16MovePRegClassID, 4, 4, 1, 1 }, 2497 { GPRMM16Zero, GPRMM16ZeroBits, 578, 8, sizeof(GPRMM16ZeroBits), Mips::GPRMM16ZeroRegClassID, 4, 4, 1, 1 }, 2498 { MSACtrl, MSACtrlBits, 532, 8, sizeof(MSACtrlBits), Mips::MSACtrlRegClassID, 4, 4, 1, 1 }, 2499 { OddSP_with_sub_hi_with_sub_hi_in_FGR32, OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits, 55, 8, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits), Mips::OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID, 4, 4, 1, 0 }, 2500 { CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, 628, 7, sizeof(CPU16Regs_and_GPRMM16ZeroBits), Mips::CPU16Regs_and_GPRMM16ZeroRegClassID, 4, 4, 1, 1 }, 2501 { CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, 376, 4, sizeof(CPU16Regs_and_GPRMM16MovePBits), Mips::CPU16Regs_and_GPRMM16MovePRegClassID, 4, 4, 1, 1 }, 2502 { GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, 561, 4, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 4, 4, 1, 1 }, 2503 { HI32DSP, HI32DSPBits, 205, 4, sizeof(HI32DSPBits), Mips::HI32DSPRegClassID, 4, 4, 1, 1 }, 2504 { LO32DSP, LO32DSPBits, 213, 4, sizeof(LO32DSPBits), Mips::LO32DSPRegClassID, 4, 4, 1, 1 }, 2505 { GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 611, 3, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 4, 4, 1, 1 }, 2506 { CPURAReg, CPURARegBits, 475, 1, sizeof(CPURARegBits), Mips::CPURARegRegClassID, 4, 4, 1, 0 }, 2507 { CPUSPReg, CPUSPRegBits, 505, 1, sizeof(CPUSPRegBits), Mips::CPUSPRegRegClassID, 4, 4, 1, 0 }, 2508 { DSPCC, DSPCCBits, 166, 1, sizeof(DSPCCBits), Mips::DSPCCRegClassID, 4, 4, 1, 1 }, 2509 { HI32, HI32Bits, 45, 1, sizeof(HI32Bits), Mips::HI32RegClassID, 4, 4, 1, 1 }, 2510 { LO32, LO32Bits, 50, 1, sizeof(LO32Bits), Mips::LO32RegClassID, 4, 4, 1, 1 }, 2511 { FGR64, FGR64Bits, 127, 32, sizeof(FGR64Bits), Mips::FGR64RegClassID, 8, 8, 1, 1 }, 2512 { GPR64, GPR64Bits, 133, 32, sizeof(GPR64Bits), Mips::GPR64RegClassID, 8, 8, 1, 1 }, 2513 { AFGR64, AFGR64Bits, 126, 16, sizeof(AFGR64Bits), Mips::AFGR64RegClassID, 8, 8, 1, 1 }, 2514 { FGR64_and_OddSP, FGR64_and_OddSPBits, 264, 16, sizeof(FGR64_and_OddSPBits), Mips::FGR64_and_OddSPRegClassID, 8, 8, 1, 1 }, 2515 { GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, 309, 9, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits), Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID, 8, 8, 1, 1 }, 2516 { AFGR64_and_OddSP, AFGR64_and_OddSPBits, 263, 8, sizeof(AFGR64_and_OddSPBits), Mips::AFGR64_and_OddSPRegClassID, 8, 8, 1, 1 }, 2517 { GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, 734, 8, sizeof(GPR64_with_sub_32_in_CPU16RegsBits), Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID, 8, 8, 1, 1 }, 2518 { GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, 403, 8, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID, 8, 8, 1, 1 }, 2519 { GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, 701, 8, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID, 8, 8, 1, 1 }, 2520 { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, 654, 7, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID, 8, 8, 1, 1 }, 2521 { ACC64DSP, ACC64DSPBits, 221, 4, sizeof(ACC64DSPBits), Mips::ACC64DSPRegClassID, 8, 8, 1, 1 }, 2522 { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, 355, 4, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID, 8, 8, 1, 1 }, 2523 { GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, 540, 4, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 8, 8, 1, 1 }, 2524 { GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 590, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 8, 8, 1, 1 }, 2525 { OCTEON_MPL, OCTEON_MPLBits, 194, 3, sizeof(OCTEON_MPLBits), Mips::OCTEON_MPLRegClassID, 8, 8, 1, 0 }, 2526 { OCTEON_P, OCTEON_PBits, 346, 3, sizeof(OCTEON_PBits), Mips::OCTEON_PRegClassID, 8, 8, 1, 0 }, 2527 { ACC64, ACC64Bits, 110, 1, sizeof(ACC64Bits), Mips::ACC64RegClassID, 8, 8, 1, 1 }, 2528 { GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, 454, 1, sizeof(GPR64_with_sub_32_in_CPURARegBits), Mips::GPR64_with_sub_32_in_CPURARegRegClassID, 8, 8, 1, 1 }, 2529 { GPR64_with_sub_32_in_CPUSPReg, GPR64_with_sub_32_in_CPUSPRegBits, 484, 1, sizeof(GPR64_with_sub_32_in_CPUSPRegBits), Mips::GPR64_with_sub_32_in_CPUSPRegRegClassID, 8, 8, 1, 1 }, 2530 { HI64, HI64Bits, 116, 1, sizeof(HI64Bits), Mips::HI64RegClassID, 8, 8, 1, 1 }, 2531 { LO64, LO64Bits, 121, 1, sizeof(LO64Bits), Mips::LO64RegClassID, 8, 8, 1, 1 }, 2532 { MSA128B, MSA128BBits, 154, 32, sizeof(MSA128BBits), Mips::MSA128BRegClassID, 16, 16, 1, 1 }, 2533 { MSA128D, MSA128DBits, 178, 32, sizeof(MSA128DBits), Mips::MSA128DRegClassID, 16, 16, 1, 1 }, 2534 { MSA128H, MSA128HBits, 186, 32, sizeof(MSA128HBits), Mips::MSA128HRegClassID, 16, 16, 1, 1 }, 2535 { MSA128W, MSA128WBits, 446, 32, sizeof(MSA128WBits), Mips::MSA128WRegClassID, 16, 16, 1, 1 }, 2536 { MSA128B_with_sub_64_in_OddSP, MSA128B_with_sub_64_in_OddSPBits, 280, 16, sizeof(MSA128B_with_sub_64_in_OddSPBits), Mips::MSA128B_with_sub_64_in_OddSPRegClassID, 16, 16, 1, 1 }, 2537 { MSA128WEvens, MSA128WEvensBits, 772, 16, sizeof(MSA128WEvensBits), Mips::MSA128WEvensRegClassID, 16, 16, 1, 1 }, 2538 { ACC128, ACC128Bits, 147, 1, sizeof(ACC128Bits), Mips::ACC128RegClassID, 16, 16, 1, 1 }, 2539}; 2540 2541// Mips Dwarf<->LLVM register mappings. 2542extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[] = { 2543 { 0U, Mips::ZERO_64 }, 2544 { 1U, Mips::AT_64 }, 2545 { 2U, Mips::V0_64 }, 2546 { 3U, Mips::V1_64 }, 2547 { 4U, Mips::A0_64 }, 2548 { 5U, Mips::A1_64 }, 2549 { 6U, Mips::A2_64 }, 2550 { 7U, Mips::A3_64 }, 2551 { 8U, Mips::T0_64 }, 2552 { 9U, Mips::T1_64 }, 2553 { 10U, Mips::T2_64 }, 2554 { 11U, Mips::T3_64 }, 2555 { 12U, Mips::T4_64 }, 2556 { 13U, Mips::T5_64 }, 2557 { 14U, Mips::T6_64 }, 2558 { 15U, Mips::T7_64 }, 2559 { 16U, Mips::S0_64 }, 2560 { 17U, Mips::S1_64 }, 2561 { 18U, Mips::S2_64 }, 2562 { 19U, Mips::S3_64 }, 2563 { 20U, Mips::S4_64 }, 2564 { 21U, Mips::S5_64 }, 2565 { 22U, Mips::S6_64 }, 2566 { 23U, Mips::S7_64 }, 2567 { 24U, Mips::T8_64 }, 2568 { 25U, Mips::T9_64 }, 2569 { 26U, Mips::K0_64 }, 2570 { 27U, Mips::K1_64 }, 2571 { 28U, Mips::GP_64 }, 2572 { 29U, Mips::SP_64 }, 2573 { 30U, Mips::FP_64 }, 2574 { 31U, Mips::RA_64 }, 2575 { 32U, Mips::D0_64 }, 2576 { 33U, Mips::D1_64 }, 2577 { 34U, Mips::D2_64 }, 2578 { 35U, Mips::D3_64 }, 2579 { 36U, Mips::D4_64 }, 2580 { 37U, Mips::D5_64 }, 2581 { 38U, Mips::D6_64 }, 2582 { 39U, Mips::D7_64 }, 2583 { 40U, Mips::D8_64 }, 2584 { 41U, Mips::D9_64 }, 2585 { 42U, Mips::D10_64 }, 2586 { 43U, Mips::D11_64 }, 2587 { 44U, Mips::D12_64 }, 2588 { 45U, Mips::D13_64 }, 2589 { 46U, Mips::D14_64 }, 2590 { 47U, Mips::D15_64 }, 2591 { 48U, Mips::D16_64 }, 2592 { 49U, Mips::D17_64 }, 2593 { 50U, Mips::D18_64 }, 2594 { 51U, Mips::D19_64 }, 2595 { 52U, Mips::D20_64 }, 2596 { 53U, Mips::D21_64 }, 2597 { 54U, Mips::D22_64 }, 2598 { 55U, Mips::D23_64 }, 2599 { 56U, Mips::D24_64 }, 2600 { 57U, Mips::D25_64 }, 2601 { 58U, Mips::D26_64 }, 2602 { 59U, Mips::D27_64 }, 2603 { 60U, Mips::D28_64 }, 2604 { 61U, Mips::D29_64 }, 2605 { 62U, Mips::D30_64 }, 2606 { 63U, Mips::D31_64 }, 2607 { 64U, Mips::HI0 }, 2608 { 65U, Mips::LO0 }, 2609 { 176U, Mips::HI1 }, 2610 { 177U, Mips::LO1 }, 2611 { 178U, Mips::HI2 }, 2612 { 179U, Mips::LO2 }, 2613 { 180U, Mips::HI3 }, 2614 { 181U, Mips::LO3 }, 2615}; 2616extern const unsigned MipsDwarfFlavour0Dwarf2LSize = array_lengthof(MipsDwarfFlavour0Dwarf2L); 2617 2618extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[] = { 2619 { 0U, Mips::ZERO_64 }, 2620 { 1U, Mips::AT_64 }, 2621 { 2U, Mips::V0_64 }, 2622 { 3U, Mips::V1_64 }, 2623 { 4U, Mips::A0_64 }, 2624 { 5U, Mips::A1_64 }, 2625 { 6U, Mips::A2_64 }, 2626 { 7U, Mips::A3_64 }, 2627 { 8U, Mips::T0_64 }, 2628 { 9U, Mips::T1_64 }, 2629 { 10U, Mips::T2_64 }, 2630 { 11U, Mips::T3_64 }, 2631 { 12U, Mips::T4_64 }, 2632 { 13U, Mips::T5_64 }, 2633 { 14U, Mips::T6_64 }, 2634 { 15U, Mips::T7_64 }, 2635 { 16U, Mips::S0_64 }, 2636 { 17U, Mips::S1_64 }, 2637 { 18U, Mips::S2_64 }, 2638 { 19U, Mips::S3_64 }, 2639 { 20U, Mips::S4_64 }, 2640 { 21U, Mips::S5_64 }, 2641 { 22U, Mips::S6_64 }, 2642 { 23U, Mips::S7_64 }, 2643 { 24U, Mips::T8_64 }, 2644 { 25U, Mips::T9_64 }, 2645 { 26U, Mips::K0_64 }, 2646 { 27U, Mips::K1_64 }, 2647 { 28U, Mips::GP_64 }, 2648 { 29U, Mips::SP_64 }, 2649 { 30U, Mips::FP_64 }, 2650 { 31U, Mips::RA_64 }, 2651 { 32U, Mips::D0_64 }, 2652 { 33U, Mips::D1_64 }, 2653 { 34U, Mips::D2_64 }, 2654 { 35U, Mips::D3_64 }, 2655 { 36U, Mips::D4_64 }, 2656 { 37U, Mips::D5_64 }, 2657 { 38U, Mips::D6_64 }, 2658 { 39U, Mips::D7_64 }, 2659 { 40U, Mips::D8_64 }, 2660 { 41U, Mips::D9_64 }, 2661 { 42U, Mips::D10_64 }, 2662 { 43U, Mips::D11_64 }, 2663 { 44U, Mips::D12_64 }, 2664 { 45U, Mips::D13_64 }, 2665 { 46U, Mips::D14_64 }, 2666 { 47U, Mips::D15_64 }, 2667 { 48U, Mips::D16_64 }, 2668 { 49U, Mips::D17_64 }, 2669 { 50U, Mips::D18_64 }, 2670 { 51U, Mips::D19_64 }, 2671 { 52U, Mips::D20_64 }, 2672 { 53U, Mips::D21_64 }, 2673 { 54U, Mips::D22_64 }, 2674 { 55U, Mips::D23_64 }, 2675 { 56U, Mips::D24_64 }, 2676 { 57U, Mips::D25_64 }, 2677 { 58U, Mips::D26_64 }, 2678 { 59U, Mips::D27_64 }, 2679 { 60U, Mips::D28_64 }, 2680 { 61U, Mips::D29_64 }, 2681 { 62U, Mips::D30_64 }, 2682 { 63U, Mips::D31_64 }, 2683 { 64U, Mips::HI0 }, 2684 { 65U, Mips::LO0 }, 2685 { 176U, Mips::HI1 }, 2686 { 177U, Mips::LO1 }, 2687 { 178U, Mips::HI2 }, 2688 { 179U, Mips::LO2 }, 2689 { 180U, Mips::HI3 }, 2690 { 181U, Mips::LO3 }, 2691}; 2692extern const unsigned MipsEHFlavour0Dwarf2LSize = array_lengthof(MipsEHFlavour0Dwarf2L); 2693 2694extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[] = { 2695 { Mips::AT, 1U }, 2696 { Mips::FP, 30U }, 2697 { Mips::GP, 28U }, 2698 { Mips::RA, 31U }, 2699 { Mips::SP, 29U }, 2700 { Mips::ZERO, 0U }, 2701 { Mips::A0, 4U }, 2702 { Mips::A1, 5U }, 2703 { Mips::A2, 6U }, 2704 { Mips::A3, 7U }, 2705 { Mips::AT_64, 1U }, 2706 { Mips::F0, 32U }, 2707 { Mips::F1, 33U }, 2708 { Mips::F2, 34U }, 2709 { Mips::F3, 35U }, 2710 { Mips::F4, 36U }, 2711 { Mips::F5, 37U }, 2712 { Mips::F6, 38U }, 2713 { Mips::F7, 39U }, 2714 { Mips::F8, 40U }, 2715 { Mips::F9, 41U }, 2716 { Mips::F10, 42U }, 2717 { Mips::F11, 43U }, 2718 { Mips::F12, 44U }, 2719 { Mips::F13, 45U }, 2720 { Mips::F14, 46U }, 2721 { Mips::F15, 47U }, 2722 { Mips::F16, 48U }, 2723 { Mips::F17, 49U }, 2724 { Mips::F18, 50U }, 2725 { Mips::F19, 51U }, 2726 { Mips::F20, 52U }, 2727 { Mips::F21, 53U }, 2728 { Mips::F22, 54U }, 2729 { Mips::F23, 55U }, 2730 { Mips::F24, 56U }, 2731 { Mips::F25, 57U }, 2732 { Mips::F26, 58U }, 2733 { Mips::F27, 59U }, 2734 { Mips::F28, 60U }, 2735 { Mips::F29, 61U }, 2736 { Mips::F30, 62U }, 2737 { Mips::F31, 63U }, 2738 { Mips::FP_64, 30U }, 2739 { Mips::F_HI0, 32U }, 2740 { Mips::F_HI1, 33U }, 2741 { Mips::F_HI2, 34U }, 2742 { Mips::F_HI3, 35U }, 2743 { Mips::F_HI4, 36U }, 2744 { Mips::F_HI5, 37U }, 2745 { Mips::F_HI6, 38U }, 2746 { Mips::F_HI7, 39U }, 2747 { Mips::F_HI8, 40U }, 2748 { Mips::F_HI9, 41U }, 2749 { Mips::F_HI10, 42U }, 2750 { Mips::F_HI11, 43U }, 2751 { Mips::F_HI12, 44U }, 2752 { Mips::F_HI13, 45U }, 2753 { Mips::F_HI14, 46U }, 2754 { Mips::F_HI15, 47U }, 2755 { Mips::F_HI16, 48U }, 2756 { Mips::F_HI17, 49U }, 2757 { Mips::F_HI18, 50U }, 2758 { Mips::F_HI19, 51U }, 2759 { Mips::F_HI20, 52U }, 2760 { Mips::F_HI21, 53U }, 2761 { Mips::F_HI22, 54U }, 2762 { Mips::F_HI23, 55U }, 2763 { Mips::F_HI24, 56U }, 2764 { Mips::F_HI25, 57U }, 2765 { Mips::F_HI26, 58U }, 2766 { Mips::F_HI27, 59U }, 2767 { Mips::F_HI28, 60U }, 2768 { Mips::F_HI29, 61U }, 2769 { Mips::F_HI30, 62U }, 2770 { Mips::F_HI31, 63U }, 2771 { Mips::GP_64, 28U }, 2772 { Mips::HI0, 64U }, 2773 { Mips::HI1, 176U }, 2774 { Mips::HI2, 178U }, 2775 { Mips::HI3, 180U }, 2776 { Mips::K0, 26U }, 2777 { Mips::K1, 27U }, 2778 { Mips::LO0, 65U }, 2779 { Mips::LO1, 177U }, 2780 { Mips::LO2, 179U }, 2781 { Mips::LO3, 181U }, 2782 { Mips::RA_64, 31U }, 2783 { Mips::S0, 16U }, 2784 { Mips::S1, 17U }, 2785 { Mips::S2, 18U }, 2786 { Mips::S3, 19U }, 2787 { Mips::S4, 20U }, 2788 { Mips::S5, 21U }, 2789 { Mips::S6, 22U }, 2790 { Mips::S7, 23U }, 2791 { Mips::SP_64, 29U }, 2792 { Mips::T0, 8U }, 2793 { Mips::T1, 9U }, 2794 { Mips::T2, 10U }, 2795 { Mips::T3, 11U }, 2796 { Mips::T4, 12U }, 2797 { Mips::T5, 13U }, 2798 { Mips::T6, 14U }, 2799 { Mips::T7, 15U }, 2800 { Mips::T8, 24U }, 2801 { Mips::T9, 25U }, 2802 { Mips::V0, 2U }, 2803 { Mips::V1, 3U }, 2804 { Mips::W0, 32U }, 2805 { Mips::W1, 33U }, 2806 { Mips::W2, 34U }, 2807 { Mips::W3, 35U }, 2808 { Mips::W4, 36U }, 2809 { Mips::W5, 37U }, 2810 { Mips::W6, 38U }, 2811 { Mips::W7, 39U }, 2812 { Mips::W8, 40U }, 2813 { Mips::W9, 41U }, 2814 { Mips::W10, 42U }, 2815 { Mips::W11, 43U }, 2816 { Mips::W12, 44U }, 2817 { Mips::W13, 45U }, 2818 { Mips::W14, 46U }, 2819 { Mips::W15, 47U }, 2820 { Mips::W16, 48U }, 2821 { Mips::W17, 49U }, 2822 { Mips::W18, 50U }, 2823 { Mips::W19, 51U }, 2824 { Mips::W20, 52U }, 2825 { Mips::W21, 53U }, 2826 { Mips::W22, 54U }, 2827 { Mips::W23, 55U }, 2828 { Mips::W24, 56U }, 2829 { Mips::W25, 57U }, 2830 { Mips::W26, 58U }, 2831 { Mips::W27, 59U }, 2832 { Mips::W28, 60U }, 2833 { Mips::W29, 61U }, 2834 { Mips::W30, 62U }, 2835 { Mips::W31, 63U }, 2836 { Mips::ZERO_64, 0U }, 2837 { Mips::A0_64, 4U }, 2838 { Mips::A1_64, 5U }, 2839 { Mips::A2_64, 6U }, 2840 { Mips::A3_64, 7U }, 2841 { Mips::D0_64, 32U }, 2842 { Mips::D1_64, 33U }, 2843 { Mips::D2_64, 34U }, 2844 { Mips::D3_64, 35U }, 2845 { Mips::D4_64, 36U }, 2846 { Mips::D5_64, 37U }, 2847 { Mips::D6_64, 38U }, 2848 { Mips::D7_64, 39U }, 2849 { Mips::D8_64, 40U }, 2850 { Mips::D9_64, 41U }, 2851 { Mips::D10_64, 42U }, 2852 { Mips::D11_64, 43U }, 2853 { Mips::D12_64, 44U }, 2854 { Mips::D13_64, 45U }, 2855 { Mips::D14_64, 46U }, 2856 { Mips::D15_64, 47U }, 2857 { Mips::D16_64, 48U }, 2858 { Mips::D17_64, 49U }, 2859 { Mips::D18_64, 50U }, 2860 { Mips::D19_64, 51U }, 2861 { Mips::D20_64, 52U }, 2862 { Mips::D21_64, 53U }, 2863 { Mips::D22_64, 54U }, 2864 { Mips::D23_64, 55U }, 2865 { Mips::D24_64, 56U }, 2866 { Mips::D25_64, 57U }, 2867 { Mips::D26_64, 58U }, 2868 { Mips::D27_64, 59U }, 2869 { Mips::D28_64, 60U }, 2870 { Mips::D29_64, 61U }, 2871 { Mips::D30_64, 62U }, 2872 { Mips::D31_64, 63U }, 2873 { Mips::K0_64, 26U }, 2874 { Mips::K1_64, 27U }, 2875 { Mips::S0_64, 16U }, 2876 { Mips::S1_64, 17U }, 2877 { Mips::S2_64, 18U }, 2878 { Mips::S3_64, 19U }, 2879 { Mips::S4_64, 20U }, 2880 { Mips::S5_64, 21U }, 2881 { Mips::S6_64, 22U }, 2882 { Mips::S7_64, 23U }, 2883 { Mips::T0_64, 8U }, 2884 { Mips::T1_64, 9U }, 2885 { Mips::T2_64, 10U }, 2886 { Mips::T3_64, 11U }, 2887 { Mips::T4_64, 12U }, 2888 { Mips::T5_64, 13U }, 2889 { Mips::T6_64, 14U }, 2890 { Mips::T7_64, 15U }, 2891 { Mips::T8_64, 24U }, 2892 { Mips::T9_64, 25U }, 2893 { Mips::V0_64, 2U }, 2894 { Mips::V1_64, 3U }, 2895}; 2896extern const unsigned MipsDwarfFlavour0L2DwarfSize = array_lengthof(MipsDwarfFlavour0L2Dwarf); 2897 2898extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[] = { 2899 { Mips::AT, 1U }, 2900 { Mips::FP, 30U }, 2901 { Mips::GP, 28U }, 2902 { Mips::RA, 31U }, 2903 { Mips::SP, 29U }, 2904 { Mips::ZERO, 0U }, 2905 { Mips::A0, 4U }, 2906 { Mips::A1, 5U }, 2907 { Mips::A2, 6U }, 2908 { Mips::A3, 7U }, 2909 { Mips::AT_64, 1U }, 2910 { Mips::F0, 32U }, 2911 { Mips::F1, 33U }, 2912 { Mips::F2, 34U }, 2913 { Mips::F3, 35U }, 2914 { Mips::F4, 36U }, 2915 { Mips::F5, 37U }, 2916 { Mips::F6, 38U }, 2917 { Mips::F7, 39U }, 2918 { Mips::F8, 40U }, 2919 { Mips::F9, 41U }, 2920 { Mips::F10, 42U }, 2921 { Mips::F11, 43U }, 2922 { Mips::F12, 44U }, 2923 { Mips::F13, 45U }, 2924 { Mips::F14, 46U }, 2925 { Mips::F15, 47U }, 2926 { Mips::F16, 48U }, 2927 { Mips::F17, 49U }, 2928 { Mips::F18, 50U }, 2929 { Mips::F19, 51U }, 2930 { Mips::F20, 52U }, 2931 { Mips::F21, 53U }, 2932 { Mips::F22, 54U }, 2933 { Mips::F23, 55U }, 2934 { Mips::F24, 56U }, 2935 { Mips::F25, 57U }, 2936 { Mips::F26, 58U }, 2937 { Mips::F27, 59U }, 2938 { Mips::F28, 60U }, 2939 { Mips::F29, 61U }, 2940 { Mips::F30, 62U }, 2941 { Mips::F31, 63U }, 2942 { Mips::FP_64, 30U }, 2943 { Mips::F_HI0, 32U }, 2944 { Mips::F_HI1, 33U }, 2945 { Mips::F_HI2, 34U }, 2946 { Mips::F_HI3, 35U }, 2947 { Mips::F_HI4, 36U }, 2948 { Mips::F_HI5, 37U }, 2949 { Mips::F_HI6, 38U }, 2950 { Mips::F_HI7, 39U }, 2951 { Mips::F_HI8, 40U }, 2952 { Mips::F_HI9, 41U }, 2953 { Mips::F_HI10, 42U }, 2954 { Mips::F_HI11, 43U }, 2955 { Mips::F_HI12, 44U }, 2956 { Mips::F_HI13, 45U }, 2957 { Mips::F_HI14, 46U }, 2958 { Mips::F_HI15, 47U }, 2959 { Mips::F_HI16, 48U }, 2960 { Mips::F_HI17, 49U }, 2961 { Mips::F_HI18, 50U }, 2962 { Mips::F_HI19, 51U }, 2963 { Mips::F_HI20, 52U }, 2964 { Mips::F_HI21, 53U }, 2965 { Mips::F_HI22, 54U }, 2966 { Mips::F_HI23, 55U }, 2967 { Mips::F_HI24, 56U }, 2968 { Mips::F_HI25, 57U }, 2969 { Mips::F_HI26, 58U }, 2970 { Mips::F_HI27, 59U }, 2971 { Mips::F_HI28, 60U }, 2972 { Mips::F_HI29, 61U }, 2973 { Mips::F_HI30, 62U }, 2974 { Mips::F_HI31, 63U }, 2975 { Mips::GP_64, 28U }, 2976 { Mips::HI0, 64U }, 2977 { Mips::HI1, 176U }, 2978 { Mips::HI2, 178U }, 2979 { Mips::HI3, 180U }, 2980 { Mips::K0, 26U }, 2981 { Mips::K1, 27U }, 2982 { Mips::LO0, 65U }, 2983 { Mips::LO1, 177U }, 2984 { Mips::LO2, 179U }, 2985 { Mips::LO3, 181U }, 2986 { Mips::RA_64, 31U }, 2987 { Mips::S0, 16U }, 2988 { Mips::S1, 17U }, 2989 { Mips::S2, 18U }, 2990 { Mips::S3, 19U }, 2991 { Mips::S4, 20U }, 2992 { Mips::S5, 21U }, 2993 { Mips::S6, 22U }, 2994 { Mips::S7, 23U }, 2995 { Mips::SP_64, 29U }, 2996 { Mips::T0, 8U }, 2997 { Mips::T1, 9U }, 2998 { Mips::T2, 10U }, 2999 { Mips::T3, 11U }, 3000 { Mips::T4, 12U }, 3001 { Mips::T5, 13U }, 3002 { Mips::T6, 14U }, 3003 { Mips::T7, 15U }, 3004 { Mips::T8, 24U }, 3005 { Mips::T9, 25U }, 3006 { Mips::V0, 2U }, 3007 { Mips::V1, 3U }, 3008 { Mips::W0, 32U }, 3009 { Mips::W1, 33U }, 3010 { Mips::W2, 34U }, 3011 { Mips::W3, 35U }, 3012 { Mips::W4, 36U }, 3013 { Mips::W5, 37U }, 3014 { Mips::W6, 38U }, 3015 { Mips::W7, 39U }, 3016 { Mips::W8, 40U }, 3017 { Mips::W9, 41U }, 3018 { Mips::W10, 42U }, 3019 { Mips::W11, 43U }, 3020 { Mips::W12, 44U }, 3021 { Mips::W13, 45U }, 3022 { Mips::W14, 46U }, 3023 { Mips::W15, 47U }, 3024 { Mips::W16, 48U }, 3025 { Mips::W17, 49U }, 3026 { Mips::W18, 50U }, 3027 { Mips::W19, 51U }, 3028 { Mips::W20, 52U }, 3029 { Mips::W21, 53U }, 3030 { Mips::W22, 54U }, 3031 { Mips::W23, 55U }, 3032 { Mips::W24, 56U }, 3033 { Mips::W25, 57U }, 3034 { Mips::W26, 58U }, 3035 { Mips::W27, 59U }, 3036 { Mips::W28, 60U }, 3037 { Mips::W29, 61U }, 3038 { Mips::W30, 62U }, 3039 { Mips::W31, 63U }, 3040 { Mips::ZERO_64, 0U }, 3041 { Mips::A0_64, 4U }, 3042 { Mips::A1_64, 5U }, 3043 { Mips::A2_64, 6U }, 3044 { Mips::A3_64, 7U }, 3045 { Mips::D0_64, 32U }, 3046 { Mips::D1_64, 33U }, 3047 { Mips::D2_64, 34U }, 3048 { Mips::D3_64, 35U }, 3049 { Mips::D4_64, 36U }, 3050 { Mips::D5_64, 37U }, 3051 { Mips::D6_64, 38U }, 3052 { Mips::D7_64, 39U }, 3053 { Mips::D8_64, 40U }, 3054 { Mips::D9_64, 41U }, 3055 { Mips::D10_64, 42U }, 3056 { Mips::D11_64, 43U }, 3057 { Mips::D12_64, 44U }, 3058 { Mips::D13_64, 45U }, 3059 { Mips::D14_64, 46U }, 3060 { Mips::D15_64, 47U }, 3061 { Mips::D16_64, 48U }, 3062 { Mips::D17_64, 49U }, 3063 { Mips::D18_64, 50U }, 3064 { Mips::D19_64, 51U }, 3065 { Mips::D20_64, 52U }, 3066 { Mips::D21_64, 53U }, 3067 { Mips::D22_64, 54U }, 3068 { Mips::D23_64, 55U }, 3069 { Mips::D24_64, 56U }, 3070 { Mips::D25_64, 57U }, 3071 { Mips::D26_64, 58U }, 3072 { Mips::D27_64, 59U }, 3073 { Mips::D28_64, 60U }, 3074 { Mips::D29_64, 61U }, 3075 { Mips::D30_64, 62U }, 3076 { Mips::D31_64, 63U }, 3077 { Mips::K0_64, 26U }, 3078 { Mips::K1_64, 27U }, 3079 { Mips::S0_64, 16U }, 3080 { Mips::S1_64, 17U }, 3081 { Mips::S2_64, 18U }, 3082 { Mips::S3_64, 19U }, 3083 { Mips::S4_64, 20U }, 3084 { Mips::S5_64, 21U }, 3085 { Mips::S6_64, 22U }, 3086 { Mips::S7_64, 23U }, 3087 { Mips::T0_64, 8U }, 3088 { Mips::T1_64, 9U }, 3089 { Mips::T2_64, 10U }, 3090 { Mips::T3_64, 11U }, 3091 { Mips::T4_64, 12U }, 3092 { Mips::T5_64, 13U }, 3093 { Mips::T6_64, 14U }, 3094 { Mips::T7_64, 15U }, 3095 { Mips::T8_64, 24U }, 3096 { Mips::T9_64, 25U }, 3097 { Mips::V0_64, 2U }, 3098 { Mips::V1_64, 3U }, 3099}; 3100extern const unsigned MipsEHFlavour0L2DwarfSize = array_lengthof(MipsEHFlavour0L2Dwarf); 3101 3102extern const uint16_t MipsRegEncodingTable[] = { 3103 0, 3104 1, 3105 0, 3106 0, 3107 0, 3108 0, 3109 0, 3110 0, 3111 30, 3112 28, 3113 2, 3114 1, 3115 0, 3116 6, 3117 4, 3118 5, 3119 3, 3120 7, 3121 0, 3122 31, 3123 29, 3124 0, 3125 4, 3126 5, 3127 6, 3128 7, 3129 0, 3130 1, 3131 2, 3132 3, 3133 1, 3134 0, 3135 1, 3136 2, 3137 3, 3138 4, 3139 5, 3140 6, 3141 7, 3142 8, 3143 9, 3144 0, 3145 1, 3146 2, 3147 3, 3148 4, 3149 5, 3150 6, 3151 7, 3152 8, 3153 9, 3154 0, 3155 1, 3156 2, 3157 3, 3158 4, 3159 5, 3160 6, 3161 7, 3162 8, 3163 9, 3164 10, 3165 11, 3166 12, 3167 13, 3168 14, 3169 15, 3170 16, 3171 17, 3172 18, 3173 19, 3174 20, 3175 21, 3176 22, 3177 23, 3178 24, 3179 25, 3180 26, 3181 27, 3182 28, 3183 29, 3184 30, 3185 31, 3186 10, 3187 11, 3188 12, 3189 13, 3190 14, 3191 15, 3192 16, 3193 17, 3194 18, 3195 19, 3196 20, 3197 21, 3198 22, 3199 23, 3200 24, 3201 25, 3202 26, 3203 27, 3204 28, 3205 29, 3206 30, 3207 31, 3208 10, 3209 11, 3210 12, 3211 13, 3212 14, 3213 15, 3214 16, 3215 17, 3216 18, 3217 19, 3218 20, 3219 21, 3220 22, 3221 23, 3222 24, 3223 25, 3224 26, 3225 27, 3226 28, 3227 29, 3228 30, 3229 31, 3230 0, 3231 2, 3232 4, 3233 6, 3234 8, 3235 10, 3236 12, 3237 14, 3238 16, 3239 18, 3240 20, 3241 22, 3242 24, 3243 26, 3244 28, 3245 30, 3246 0, 3247 0, 3248 0, 3249 0, 3250 0, 3251 1, 3252 2, 3253 3, 3254 4, 3255 5, 3256 6, 3257 7, 3258 8, 3259 9, 3260 10, 3261 11, 3262 12, 3263 13, 3264 14, 3265 15, 3266 16, 3267 17, 3268 18, 3269 19, 3270 20, 3271 21, 3272 22, 3273 23, 3274 24, 3275 25, 3276 26, 3277 27, 3278 28, 3279 29, 3280 30, 3281 31, 3282 0, 3283 1, 3284 2, 3285 3, 3286 4, 3287 5, 3288 6, 3289 7, 3290 0, 3291 1, 3292 2, 3293 3, 3294 4, 3295 5, 3296 6, 3297 7, 3298 8, 3299 9, 3300 10, 3301 11, 3302 12, 3303 13, 3304 14, 3305 15, 3306 16, 3307 17, 3308 18, 3309 19, 3310 20, 3311 21, 3312 22, 3313 23, 3314 24, 3315 25, 3316 26, 3317 27, 3318 28, 3319 29, 3320 30, 3321 31, 3322 30, 3323 0, 3324 1, 3325 2, 3326 3, 3327 4, 3328 5, 3329 6, 3330 7, 3331 8, 3332 9, 3333 10, 3334 11, 3335 12, 3336 13, 3337 14, 3338 15, 3339 16, 3340 17, 3341 18, 3342 19, 3343 20, 3344 21, 3345 22, 3346 23, 3347 24, 3348 25, 3349 26, 3350 27, 3351 28, 3352 29, 3353 30, 3354 31, 3355 28, 3356 0, 3357 1, 3358 2, 3359 3, 3360 0, 3361 1, 3362 2, 3363 3, 3364 4, 3365 5, 3366 6, 3367 7, 3368 8, 3369 9, 3370 10, 3371 11, 3372 12, 3373 13, 3374 14, 3375 15, 3376 16, 3377 17, 3378 18, 3379 19, 3380 20, 3381 21, 3382 22, 3383 23, 3384 24, 3385 25, 3386 26, 3387 27, 3388 28, 3389 29, 3390 30, 3391 31, 3392 26, 3393 27, 3394 0, 3395 1, 3396 2, 3397 3, 3398 0, 3399 1, 3400 2, 3401 0, 3402 1, 3403 2, 3404 31, 3405 16, 3406 17, 3407 18, 3408 19, 3409 20, 3410 21, 3411 22, 3412 23, 3413 29, 3414 8, 3415 9, 3416 10, 3417 11, 3418 12, 3419 13, 3420 14, 3421 15, 3422 24, 3423 25, 3424 2, 3425 3, 3426 0, 3427 1, 3428 2, 3429 3, 3430 4, 3431 5, 3432 6, 3433 7, 3434 8, 3435 9, 3436 10, 3437 11, 3438 12, 3439 13, 3440 14, 3441 15, 3442 16, 3443 17, 3444 18, 3445 19, 3446 20, 3447 21, 3448 22, 3449 23, 3450 24, 3451 25, 3452 26, 3453 27, 3454 28, 3455 29, 3456 30, 3457 31, 3458 0, 3459 4, 3460 5, 3461 6, 3462 7, 3463 0, 3464 0, 3465 1, 3466 2, 3467 3, 3468 4, 3469 5, 3470 6, 3471 7, 3472 8, 3473 9, 3474 10, 3475 11, 3476 12, 3477 13, 3478 14, 3479 15, 3480 16, 3481 17, 3482 18, 3483 19, 3484 20, 3485 21, 3486 22, 3487 23, 3488 24, 3489 25, 3490 26, 3491 27, 3492 28, 3493 29, 3494 30, 3495 31, 3496 0, 3497 0, 3498 26, 3499 27, 3500 0, 3501 16, 3502 17, 3503 18, 3504 19, 3505 20, 3506 21, 3507 22, 3508 23, 3509 8, 3510 9, 3511 10, 3512 11, 3513 12, 3514 13, 3515 14, 3516 15, 3517 24, 3518 25, 3519 2, 3520 3, 3521}; 3522static inline void InitMipsMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) { 3523 RI->InitMCRegisterInfo(MipsRegDesc, 418, RA, PC, MipsMCRegisterClasses, 62, MipsRegUnitRoots, 297, MipsRegDiffLists, MipsLaneMaskLists, MipsRegStrings, MipsRegClassStrings, MipsSubRegIdxLists, 12, 3524MipsSubRegIdxRanges, MipsRegEncodingTable); 3525 3526 switch (DwarfFlavour) { 3527 default: 3528 llvm_unreachable("Unknown DWARF flavour"); 3529 case 0: 3530 RI->mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false); 3531 break; 3532 } 3533 switch (EHFlavour) { 3534 default: 3535 llvm_unreachable("Unknown DWARF flavour"); 3536 case 0: 3537 RI->mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true); 3538 break; 3539 } 3540 switch (DwarfFlavour) { 3541 default: 3542 llvm_unreachable("Unknown DWARF flavour"); 3543 case 0: 3544 RI->mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false); 3545 break; 3546 } 3547 switch (EHFlavour) { 3548 default: 3549 llvm_unreachable("Unknown DWARF flavour"); 3550 case 0: 3551 RI->mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true); 3552 break; 3553 } 3554} 3555 3556} // End llvm namespace 3557#endif // GET_REGINFO_MC_DESC 3558