1 /* Definitions dealing with TriCore/PCP opcodes and core registers. 2 Copyright (C) 1998-2003 Free Software Foundation, Inc. 3 Contributed by Michael Schumacher (mike@hightec-rt.com). 4 5 This file is part of GDB, GAS, and the GNU binutils. 6 7 GDB, GAS, and the GNU binutils are free software; you can redistribute 8 them and/or modify them under the terms of the GNU General Public 9 License as published by the Free Software Foundation; either version 10 1, or (at your option) any later version. 11 12 GDB, GAS, and the GNU binutils are distributed in the hope that they 13 will be useful, but WITHOUT ANY WARRANTY; without even the implied 14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 15 the GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this file; see the file COPYING. If not, write to the Free 19 Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 20 02110-1335 USA 21 */ 22 23 /* Supported TriCore and PCP instruction set architectures. */ 24 25 typedef enum _tricore_opcode_arch_val 26 { 27 TRICORE_GENERIC = 0x00000000, 28 TRICORE_RIDER_A = 0x00000001, 29 TRICORE_RIDER_B = 0x00000002, 30 TRICORE_RIDER_D = TRICORE_RIDER_B, 31 TRICORE_V2 = 0x00000004, 32 TRICORE_PCP = 0x00000010, 33 TRICORE_PCP2 = 0x00000020 34 } tricore_isa; 35 36 37 #define bfd_mach_rider_a 0x0001 38 #define bfd_mach_rider_b 0x0002 39 #define bfd_mach_rider_c 0x0003 40 #define bfd_mach_rider_2 0x0004 41 #define bfd_mach_rider_d 0x0002 42 #define bfd_mach_rider_mask 0x000f 43 44 #define SEC_ARCH_BIT_0 0x008 45 /* Some handy definitions for upward/downward compatibility of insns. */ 46 47 #define TRICORE_V2_UP TRICORE_V2 48 #define TRICORE_RIDER_D_UP (TRICORE_RIDER_D | TRICORE_V2_UP) 49 #define TRICORE_RIDER_B_UP (TRICORE_RIDER_B | TRICORE_RIDER_D_UP) 50 51 #define TRICORE_RIDER_B_DN TRICORE_RIDER_B 52 #define TRICORE_RIDER_D_DN (TRICORE_RIDER_D | TRICORE_RIDER_B_DN) 53 #define TRICORE_V2_DN (TRICORE_V2 | TRICORE_RIDER_D_DN) 54 55 /* The various instruction formats of the TriCore architecture. */ 56 57 typedef enum _tricore_fmt 58 { 59 /* 32-bit formats */ 60 61 TRICORE_FMT_ABS, 62 TRICORE_FMT_ABSB, 63 TRICORE_FMT_B, 64 TRICORE_FMT_BIT, 65 TRICORE_FMT_BO, 66 TRICORE_FMT_BOL, 67 TRICORE_FMT_BRC, 68 TRICORE_FMT_BRN, 69 TRICORE_FMT_BRR, 70 TRICORE_FMT_RC, 71 TRICORE_FMT_RCPW, 72 TRICORE_FMT_RCR, 73 TRICORE_FMT_RCRR, 74 TRICORE_FMT_RCRW, 75 TRICORE_FMT_RLC, 76 TRICORE_FMT_RR, 77 TRICORE_FMT_RR1, 78 TRICORE_FMT_RR2, 79 TRICORE_FMT_RRPW, 80 TRICORE_FMT_RRR, 81 TRICORE_FMT_RRR1, 82 TRICORE_FMT_RRR2, 83 TRICORE_FMT_RRRR, 84 TRICORE_FMT_RRRW, 85 TRICORE_FMT_SYS, 86 87 /* 16-bit formats */ 88 89 TRICORE_FMT_SB, 90 TRICORE_FMT_SBC, 91 TRICORE_FMT_SBR, 92 TRICORE_FMT_SBRN, 93 TRICORE_FMT_SC, 94 TRICORE_FMT_SLR, 95 TRICORE_FMT_SLRO, 96 TRICORE_FMT_SR, 97 TRICORE_FMT_SRC, 98 TRICORE_FMT_SRO, 99 TRICORE_FMT_SRR, 100 TRICORE_FMT_SRRS, 101 TRICORE_FMT_SSR, 102 TRICORE_FMT_SSRO, 103 TRICORE_FMT_MAX /* Sentinel. */ 104 } tricore_fmt; 105 106 #if defined(__STDC__) || defined(ALMOST_STDC) 107 # define F(x) TRICORE_FMT_ ## x 108 #elif defined(_MSC_VER) 109 # define F(x) TRICORE_FMT_ ## x 110 #else 111 # define F(x) TRICORE_FMT_/**/x 112 #endif 113 114 /* Opcode masks for the instruction formats above. */ 115 116 extern unsigned long tricore_mask_abs; 117 extern unsigned long tricore_mask_absb; 118 extern unsigned long tricore_mask_b; 119 extern unsigned long tricore_mask_bit; 120 extern unsigned long tricore_mask_bo; 121 extern unsigned long tricore_mask_bol; 122 extern unsigned long tricore_mask_brc; 123 extern unsigned long tricore_mask_brn; 124 extern unsigned long tricore_mask_brr; 125 extern unsigned long tricore_mask_rc; 126 extern unsigned long tricore_mask_rcpw; 127 extern unsigned long tricore_mask_rcr; 128 extern unsigned long tricore_mask_rcrr; 129 extern unsigned long tricore_mask_rcrw; 130 extern unsigned long tricore_mask_rlc; 131 extern unsigned long tricore_mask_rr; 132 extern unsigned long tricore_mask_rr1; 133 extern unsigned long tricore_mask_rr2; 134 extern unsigned long tricore_mask_rrpw; 135 extern unsigned long tricore_mask_rrr; 136 extern unsigned long tricore_mask_rrr1; 137 extern unsigned long tricore_mask_rrr2; 138 extern unsigned long tricore_mask_rrrr; 139 extern unsigned long tricore_mask_rrrw; 140 extern unsigned long tricore_mask_sys; 141 extern unsigned long tricore_mask_sb; 142 extern unsigned long tricore_mask_sbc; 143 extern unsigned long tricore_mask_sbr; 144 extern unsigned long tricore_mask_sbrn; 145 extern unsigned long tricore_mask_sc; 146 extern unsigned long tricore_mask_slr; 147 extern unsigned long tricore_mask_slro; 148 extern unsigned long tricore_mask_sr; 149 extern unsigned long tricore_mask_src; 150 extern unsigned long tricore_mask_sro; 151 extern unsigned long tricore_mask_srr; 152 extern unsigned long tricore_mask_srrs; 153 extern unsigned long tricore_mask_ssr; 154 extern unsigned long tricore_mask_ssro; 155 extern unsigned long tricore_opmask[]; 156 157 extern void tricore_init_arch_vars PARAMS ((unsigned long)); 158 159 /* This structure describes TriCore opcodes. */ 160 161 struct tricore_opcode 162 { 163 const char *name; /* The opcode's mnemonic name. */ 164 const int len32; /* 1 if it's a 32-bit insn. */ 165 const unsigned long opcode; /* The binary code of this opcode. */ 166 const unsigned long lose; /* Mask for bits that must not be set. */ 167 const tricore_fmt format; /* The instruction format. */ 168 const int nr_operands; /* The number of operands. */ 169 const char *args; /* Kinds of operands (see below). */ 170 const char *fields; /* Where to put the operands (see below). */ 171 const tricore_isa isa; /* Instruction set architecture. */ 172 int insind; /* The insn's index (computed at runtime). */ 173 int inslast; /* Index of last insn w/ that name (dito). */ 174 }; 175 176 extern struct tricore_opcode tricore_opcodes[]; 177 extern const int tricore_numopcodes; 178 extern unsigned long tricore_opmask[]; 179 180 /* This structure describes PCP/PCP2 opcodes. */ 181 182 struct pcp_opcode 183 { 184 const char *name; /* The opcode's mnemonic name. */ 185 const int len32; /* 1 if it's a 32-bit insn. */ 186 const unsigned long opcode; /* The binary code of this opcode. */ 187 const unsigned long lose; /* Mask for bits that must not be set. */ 188 const int fmt_group; /* The group ID of the instruction format. */ 189 const int ooo; /* 1 if operands may be given out of order. */ 190 const int nr_operands; /* The number of operands. */ 191 const char *args; /* Kinds of operands (see below), */ 192 const tricore_isa isa; /* PCP instruction set architecture. */ 193 int insind; /* The insn's index (computed at runtime). */ 194 int inslast; /* Index of last insn w/ that name (dito). */ 195 }; 196 197 extern struct pcp_opcode pcp_opcodes[]; 198 extern const int pcp_numopcodes; 199 200 /* This structure describes TriCore core registers (SFRs). */ 201 202 struct tricore_core_register 203 { 204 const char *name; /* The name of the register ($-prepended). */ 205 const unsigned long addr; /* The memory address of the register. */ 206 const tricore_isa isa; /* Instruction set architecture. */ 207 }; 208 209 extern const struct tricore_core_register tricore_sfrs[]; 210 extern const int tricore_numsfrs; 211 212 /* Kinds of operands for TriCore instructions: 213 d A simple data register (%d0-%d15). 214 g A simple data register with an 'l' suffix. 215 G A simple data register with an 'u' suffix. 216 - A simple data register with an 'll' suffix. 217 + A simple data register with an 'uu' suffix. 218 l A simple data register with an 'lu' suffix. 219 L A simple data register with an 'ul' suffix. 220 D An extended data register (d-register pair; %e0, %e2, ..., %e14). 221 i Implicit data register %d15. 222 a A simple address register (%a0-%a15). 223 A An extended address register (a-register pair; %a0, %a2, ..., %a14). 224 I Implicit address register %a15. 225 P Implicit stack register %a10. 226 c A core register ($psw, $pc etc.). 227 1 A 1-bit zero-extended constant. 228 2 A 2-bit zero-extended constant. 229 3 A 3-bit zero-extended constant. 230 4 A 4-bit sign-extended constant. 231 f A 4-bit zero-extended constant. 232 5 A 5-bit zero-extended constant. 233 F A 5-bit sign-extended constant. 234 v A 5-bit zero-extended constant with bit 0 == 0 (=> 4bit/2). 235 6 A 6-bit zero-extended constant with bits 0,1 == 0 (=> 4bit/4). 236 8 A 8-bit zero-extended constant. 237 9 A 9-bit sign-extended constant. 238 n A 9-bit zero-extended constant. 239 k A 10-bit zero-extended constant with bits 0,1 == 0 (=> 8bit/4). 240 0 A 10-bit sign-extended constant. 241 q A 15-bit zero-extended constant. 242 w A 16-bit sign-extended constant. 243 W A 16-bit zero-extended constant. 244 M A 32-bit memory address. 245 m A 4-bit PC-relative offset (zero-extended, /2). 246 r A 4-bit PC-relative offset (one-extended, /2). 247 x A 5-bit PC-relative offset (zero-extended, /2). 248 R A 8-bit PC-relative offset (sign-extended, /2). 249 o A 15-bit PC-relative offset (sign-extended, /2). 250 O A 24-bit PC-relative offset (sign-extended, /2). 251 t A 18-bit absolute memory address (segmented). 252 T A 24-bit absolute memory address (segmented, /2). 253 U A symbol whose value isn't known yet. 254 @ Register indirect ([%an]). 255 & SP indirect ([%sp] or [%a10]). 256 < Pre-incremented register indirect ([+%an]). 257 > Post-incremented register indirect ([%an+]). 258 * Circular address mode ([%An+c]). 259 # Bitreverse address mode ([%An+r]). 260 ? Indexed address mode ([%An+i]). 261 S Implicit base ([%a15]). 262 */ 263 264 /* The instruction fields where operands are stored. */ 265 266 #define FMT_ABS_NONE '0' 267 #define FMT_ABS_OFF18 '1' 268 #define FMT_ABS_S1_D '2' 269 #define FMT_ABSB_NONE '0' 270 #define FMT_ABSB_OFF18 '1' 271 #define FMT_ABSB_B '2' 272 #define FMT_ABSB_BPOS3 '3' 273 #define FMT_B_NONE '0' 274 #define FMT_B_DISP24 '1' 275 #define FMT_BIT_NONE '0' 276 #define FMT_BIT_D '1' 277 #define FMT_BIT_P2 '2' 278 #define FMT_BIT_P1 '3' 279 #define FMT_BIT_S2 '4' 280 #define FMT_BIT_S1 '5' 281 #define FMT_BO_NONE '0' 282 #define FMT_BO_OFF10 '1' 283 #define FMT_BO_S2 '2' 284 #define FMT_BO_S1_D '3' 285 #define FMT_BOL_NONE '0' 286 #define FMT_BOL_OFF16 '1' 287 #define FMT_BOL_S2 '2' 288 #define FMT_BOL_S1_D '3' 289 #define FMT_BRC_NONE '0' 290 #define FMT_BRC_DISP15 '1' 291 #define FMT_BRC_CONST4 '2' 292 #define FMT_BRC_S1 '3' 293 #define FMT_BRN_NONE '0' 294 #define FMT_BRN_DISP15 '1' 295 #define FMT_BRN_N '2' 296 #define FMT_BRN_S1 '3' 297 #define FMT_BRR_NONE '0' 298 #define FMT_BRR_DISP15 '1' 299 #define FMT_BRR_S2 '2' 300 #define FMT_BRR_S1 '3' 301 #define FMT_RC_NONE '0' 302 #define FMT_RC_D '1' 303 #define FMT_RC_CONST9 '2' 304 #define FMT_RC_S1 '3' 305 #define FMT_RCPW_NONE '0' 306 #define FMT_RCPW_D '1' 307 #define FMT_RCPW_P '2' 308 #define FMT_RCPW_W '3' 309 #define FMT_RCPW_CONST4 '4' 310 #define FMT_RCPW_S1 '5' 311 #define FMT_RCR_NONE '0' 312 #define FMT_RCR_D '1' 313 #define FMT_RCR_S3 '2' 314 #define FMT_RCR_CONST9 '3' 315 #define FMT_RCR_S1 '4' 316 #define FMT_RCRR_NONE '0' 317 #define FMT_RCRR_D '1' 318 #define FMT_RCRR_S3 '2' 319 #define FMT_RCRR_CONST4 '3' 320 #define FMT_RCRR_S1 '4' 321 #define FMT_RCRW_NONE '0' 322 #define FMT_RCRW_D '1' 323 #define FMT_RCRW_S3 '2' 324 #define FMT_RCRW_W '3' 325 #define FMT_RCRW_CONST4 '4' 326 #define FMT_RCRW_S1 '5' 327 #define FMT_RLC_NONE '0' 328 #define FMT_RLC_D '1' 329 #define FMT_RLC_CONST16 '2' 330 #define FMT_RLC_S1 '3' 331 #define FMT_RR_NONE '0' 332 #define FMT_RR_D '1' 333 #define FMT_RR_N '2' 334 #define FMT_RR_S2 '3' 335 #define FMT_RR_S1 '4' 336 #define FMT_RR1_NONE '0' 337 #define FMT_RR1_D '1' 338 #define FMT_RR1_N '2' 339 #define FMT_RR1_S2 '3' 340 #define FMT_RR1_S1 '4' 341 #define FMT_RR2_NONE '0' 342 #define FMT_RR2_D '1' 343 #define FMT_RR2_S2 '2' 344 #define FMT_RR2_S1 '3' 345 #define FMT_RRPW_NONE '0' 346 #define FMT_RRPW_D '1' 347 #define FMT_RRPW_P '2' 348 #define FMT_RRPW_W '3' 349 #define FMT_RRPW_S2 '4' 350 #define FMT_RRPW_S1 '5' 351 #define FMT_RRR_NONE '0' 352 #define FMT_RRR_D '1' 353 #define FMT_RRR_S3 '2' 354 #define FMT_RRR_N '3' 355 #define FMT_RRR_S2 '4' 356 #define FMT_RRR_S1 '5' 357 #define FMT_RRR1_NONE '0' 358 #define FMT_RRR1_D '1' 359 #define FMT_RRR1_S3 '2' 360 #define FMT_RRR1_N '3' 361 #define FMT_RRR1_S2 '4' 362 #define FMT_RRR1_S1 '5' 363 #define FMT_RRR2_NONE '0' 364 #define FMT_RRR2_D '1' 365 #define FMT_RRR2_S3 '2' 366 #define FMT_RRR2_S2 '3' 367 #define FMT_RRR2_S1 '4' 368 #define FMT_RRRR_NONE '0' 369 #define FMT_RRRR_D '1' 370 #define FMT_RRRR_S3 '2' 371 #define FMT_RRRR_S2 '3' 372 #define FMT_RRRR_S1 '4' 373 #define FMT_RRRW_NONE '0' 374 #define FMT_RRRW_D '1' 375 #define FMT_RRRW_S3 '2' 376 #define FMT_RRRW_W '3' 377 #define FMT_RRRW_S2 '4' 378 #define FMT_RRRW_S1 '5' 379 #define FMT_SYS_NONE '0' 380 #define FMT_SYS_S1_D '1' 381 #define FMT_SB_NONE '0' 382 #define FMT_SB_DISP8 '1' 383 #define FMT_SBC_NONE '0' 384 #define FMT_SBC_CONST4 '1' 385 #define FMT_SBC_DISP4 '2' 386 #define FMT_SBR_NONE '0' 387 #define FMT_SBR_S2 '1' 388 #define FMT_SBR_DISP4 '2' 389 #define FMT_SBRN_NONE '0' 390 #define FMT_SBRN_N '1' 391 #define FMT_SBRN_DISP4 '2' 392 #define FMT_SC_NONE '0' 393 #define FMT_SC_CONST8 '1' 394 #define FMT_SLR_NONE '0' 395 #define FMT_SLR_S2 '1' 396 #define FMT_SLR_D '2' 397 #define FMT_SLRO_NONE '0' 398 #define FMT_SLRO_OFF4 '1' 399 #define FMT_SLRO_D '2' 400 #define FMT_SR_NONE '0' 401 #define FMT_SR_S1_D '1' 402 #define FMT_SRC_NONE '0' 403 #define FMT_SRC_CONST4 '1' 404 #define FMT_SRC_S1_D '2' 405 #define FMT_SRO_NONE '0' 406 #define FMT_SRO_S2 '1' 407 #define FMT_SRO_OFF4 '2' 408 #define FMT_SRR_NONE '0' 409 #define FMT_SRR_S2 '1' 410 #define FMT_SRR_S1_D '2' 411 #define FMT_SRRS_NONE '0' 412 #define FMT_SRRS_S2 '1' 413 #define FMT_SRRS_S1_D '2' 414 #define FMT_SRRS_N '3' 415 #define FMT_SSR_NONE '0' 416 #define FMT_SSR_S2 '1' 417 #define FMT_SSR_S1 '2' 418 #define FMT_SSRO_NONE '0' 419 #define FMT_SSRO_OFF4 '1' 420 #define FMT_SSRO_S1 '2' 421 422 /* Kinds of operands for PCP instructions: 423 a Condition code 0-7 (CONDCA). 424 b Condition code 8-15 (CONDCB). 425 c CNC=[0,1,2]. 426 d DST{+,-}. 427 e A constant expression. 428 E An indirect constant expression. 429 f SIZE=[8,16,32]. 430 g ST=[0,1]. 431 h EC=[0,1]. 432 i INT=[0,1]. 433 j EP=[0,1]. 434 k SET (const value 1). 435 l CLR (const value 0). 436 m DAC=[0,1]. 437 n CNT0=[1..8] for COPY, or [2,4,8] for BCOPY. 438 o RTA=[0,1]. 439 p EDA=[0,1]. 440 q SDB=[0,1]. 441 r A direct register (R0-R7). 442 R An indirect register ([R0]-[R7]). 443 s SRC{+,-}. 444 u A direct symbol whose value isn't known yet. 445 U An indirect symbol whose value isn't known yet. 446 */ 447 448 /* End of tricore.h. */ 449