1 //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9
10 /* Capstone Disassembly Engine */
11 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
12
13 #ifdef CAPSTONE_HAS_POWERPC
14
15 #include <stdio.h> // DEBUG
16 #include <stdlib.h>
17 #include <string.h>
18
19 #include "../../cs_priv.h"
20 #include "../../utils.h"
21
22 #include "../../MCInst.h"
23 #include "../../MCInstrDesc.h"
24 #include "../../MCFixedLenDisassembler.h"
25 #include "../../MCRegisterInfo.h"
26 #include "../../MCDisassembler.h"
27 #include "../../MathExtras.h"
28
29 #define GET_REGINFO_ENUM
30 #include "PPCGenRegisterInfo.inc"
31
32
33 // FIXME: These can be generated by TableGen from the existing register
34 // encoding values!
35
36 static const unsigned CRRegs[] = {
37 PPC_CR0, PPC_CR1, PPC_CR2, PPC_CR3,
38 PPC_CR4, PPC_CR5, PPC_CR6, PPC_CR7
39 };
40
41 static const unsigned CRBITRegs[] = {
42 PPC_CR0LT, PPC_CR0GT, PPC_CR0EQ, PPC_CR0UN,
43 PPC_CR1LT, PPC_CR1GT, PPC_CR1EQ, PPC_CR1UN,
44 PPC_CR2LT, PPC_CR2GT, PPC_CR2EQ, PPC_CR2UN,
45 PPC_CR3LT, PPC_CR3GT, PPC_CR3EQ, PPC_CR3UN,
46 PPC_CR4LT, PPC_CR4GT, PPC_CR4EQ, PPC_CR4UN,
47 PPC_CR5LT, PPC_CR5GT, PPC_CR5EQ, PPC_CR5UN,
48 PPC_CR6LT, PPC_CR6GT, PPC_CR6EQ, PPC_CR6UN,
49 PPC_CR7LT, PPC_CR7GT, PPC_CR7EQ, PPC_CR7UN
50 };
51
52 static const unsigned FRegs[] = {
53 PPC_F0, PPC_F1, PPC_F2, PPC_F3,
54 PPC_F4, PPC_F5, PPC_F6, PPC_F7,
55 PPC_F8, PPC_F9, PPC_F10, PPC_F11,
56 PPC_F12, PPC_F13, PPC_F14, PPC_F15,
57 PPC_F16, PPC_F17, PPC_F18, PPC_F19,
58 PPC_F20, PPC_F21, PPC_F22, PPC_F23,
59 PPC_F24, PPC_F25, PPC_F26, PPC_F27,
60 PPC_F28, PPC_F29, PPC_F30, PPC_F31
61 };
62
63 static const unsigned VRegs[] = {
64 PPC_V0, PPC_V1, PPC_V2, PPC_V3,
65 PPC_V4, PPC_V5, PPC_V6, PPC_V7,
66 PPC_V8, PPC_V9, PPC_V10, PPC_V11,
67 PPC_V12, PPC_V13, PPC_V14, PPC_V15,
68 PPC_V16, PPC_V17, PPC_V18, PPC_V19,
69 PPC_V20, PPC_V21, PPC_V22, PPC_V23,
70 PPC_V24, PPC_V25, PPC_V26, PPC_V27,
71 PPC_V28, PPC_V29, PPC_V30, PPC_V31
72 };
73
74 static const unsigned VSRegs[] = {
75 PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3,
76 PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7,
77 PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11,
78 PPC_VSL12, PPC_VSL13, PPC_VSL14, PPC_VSL15,
79 PPC_VSL16, PPC_VSL17, PPC_VSL18, PPC_VSL19,
80 PPC_VSL20, PPC_VSL21, PPC_VSL22, PPC_VSL23,
81 PPC_VSL24, PPC_VSL25, PPC_VSL26, PPC_VSL27,
82 PPC_VSL28, PPC_VSL29, PPC_VSL30, PPC_VSL31,
83
84 PPC_VSH0, PPC_VSH1, PPC_VSH2, PPC_VSH3,
85 PPC_VSH4, PPC_VSH5, PPC_VSH6, PPC_VSH7,
86 PPC_VSH8, PPC_VSH9, PPC_VSH10, PPC_VSH11,
87 PPC_VSH12, PPC_VSH13, PPC_VSH14, PPC_VSH15,
88 PPC_VSH16, PPC_VSH17, PPC_VSH18, PPC_VSH19,
89 PPC_VSH20, PPC_VSH21, PPC_VSH22, PPC_VSH23,
90 PPC_VSH24, PPC_VSH25, PPC_VSH26, PPC_VSH27,
91 PPC_VSH28, PPC_VSH29, PPC_VSH30, PPC_VSH31
92 };
93
94 static const unsigned VSFRegs[] = {
95 PPC_F0, PPC_F1, PPC_F2, PPC_F3,
96 PPC_F4, PPC_F5, PPC_F6, PPC_F7,
97 PPC_F8, PPC_F9, PPC_F10, PPC_F11,
98 PPC_F12, PPC_F13, PPC_F14, PPC_F15,
99 PPC_F16, PPC_F17, PPC_F18, PPC_F19,
100 PPC_F20, PPC_F21, PPC_F22, PPC_F23,
101 PPC_F24, PPC_F25, PPC_F26, PPC_F27,
102 PPC_F28, PPC_F29, PPC_F30, PPC_F31,
103
104 PPC_VF0, PPC_VF1, PPC_VF2, PPC_VF3,
105 PPC_VF4, PPC_VF5, PPC_VF6, PPC_VF7,
106 PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11,
107 PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15,
108 PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19,
109 PPC_VF20, PPC_VF21, PPC_VF22, PPC_VF23,
110 PPC_VF24, PPC_VF25, PPC_VF26, PPC_VF27,
111 PPC_VF28, PPC_VF29, PPC_VF30, PPC_VF31
112 };
113
114 static const unsigned GPRegs[] = {
115 PPC_R0, PPC_R1, PPC_R2, PPC_R3,
116 PPC_R4, PPC_R5, PPC_R6, PPC_R7,
117 PPC_R8, PPC_R9, PPC_R10, PPC_R11,
118 PPC_R12, PPC_R13, PPC_R14, PPC_R15,
119 PPC_R16, PPC_R17, PPC_R18, PPC_R19,
120 PPC_R20, PPC_R21, PPC_R22, PPC_R23,
121 PPC_R24, PPC_R25, PPC_R26, PPC_R27,
122 PPC_R28, PPC_R29, PPC_R30, PPC_R31
123 };
124
125 static const unsigned GP0Regs[] = {
126 PPC_ZERO, PPC_R1, PPC_R2, PPC_R3,
127 PPC_R4, PPC_R5, PPC_R6, PPC_R7,
128 PPC_R8, PPC_R9, PPC_R10, PPC_R11,
129 PPC_R12, PPC_R13, PPC_R14, PPC_R15,
130 PPC_R16, PPC_R17, PPC_R18, PPC_R19,
131 PPC_R20, PPC_R21, PPC_R22, PPC_R23,
132 PPC_R24, PPC_R25, PPC_R26, PPC_R27,
133 PPC_R28, PPC_R29, PPC_R30, PPC_R31
134 };
135
136 static const unsigned G8Regs[] = {
137 PPC_X0, PPC_X1, PPC_X2, PPC_X3,
138 PPC_X4, PPC_X5, PPC_X6, PPC_X7,
139 PPC_X8, PPC_X9, PPC_X10, PPC_X11,
140 PPC_X12, PPC_X13, PPC_X14, PPC_X15,
141 PPC_X16, PPC_X17, PPC_X18, PPC_X19,
142 PPC_X20, PPC_X21, PPC_X22, PPC_X23,
143 PPC_X24, PPC_X25, PPC_X26, PPC_X27,
144 PPC_X28, PPC_X29, PPC_X30, PPC_X31
145 };
146
147 static const unsigned QFRegs[] = {
148 PPC_QF0, PPC_QF1, PPC_QF2, PPC_QF3,
149 PPC_QF4, PPC_QF5, PPC_QF6, PPC_QF7,
150 PPC_QF8, PPC_QF9, PPC_QF10, PPC_QF11,
151 PPC_QF12, PPC_QF13, PPC_QF14, PPC_QF15,
152 PPC_QF16, PPC_QF17, PPC_QF18, PPC_QF19,
153 PPC_QF20, PPC_QF21, PPC_QF22, PPC_QF23,
154 PPC_QF24, PPC_QF25, PPC_QF26, PPC_QF27,
155 PPC_QF28, PPC_QF29, PPC_QF30, PPC_QF31
156 };
157
getFeatureBits(int feature)158 static uint64_t getFeatureBits(int feature)
159 {
160 // enable all features
161 return (uint64_t)-1;
162 }
163
decodeRegisterClass(MCInst * Inst,uint64_t RegNo,const unsigned * Regs)164 static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo,
165 const unsigned *Regs)
166 {
167 // assert(RegNo < N && "Invalid register number");
168 MCOperand_CreateReg0(Inst, Regs[RegNo]);
169 return MCDisassembler_Success;
170 }
171
DecodeCRRCRegisterClass(MCInst * Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)172 static DecodeStatus DecodeCRRCRegisterClass(MCInst *Inst, uint64_t RegNo,
173 uint64_t Address,
174 const void *Decoder)
175 {
176 return decodeRegisterClass(Inst, RegNo, CRRegs);
177 }
178
DecodeCRBITRCRegisterClass(MCInst * Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)179 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst *Inst, uint64_t RegNo,
180 uint64_t Address,
181 const void *Decoder)
182 {
183 return decodeRegisterClass(Inst, RegNo, CRBITRegs);
184 }
185
DecodeF4RCRegisterClass(MCInst * Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)186 static DecodeStatus DecodeF4RCRegisterClass(MCInst *Inst, uint64_t RegNo,
187 uint64_t Address,
188 const void *Decoder)
189 {
190 return decodeRegisterClass(Inst, RegNo, FRegs);
191 }
192
DecodeF8RCRegisterClass(MCInst * Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)193 static DecodeStatus DecodeF8RCRegisterClass(MCInst *Inst, uint64_t RegNo,
194 uint64_t Address,
195 const void *Decoder)
196 {
197 return decodeRegisterClass(Inst, RegNo, FRegs);
198 }
199
DecodeVRRCRegisterClass(MCInst * Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)200 static DecodeStatus DecodeVRRCRegisterClass(MCInst *Inst, uint64_t RegNo,
201 uint64_t Address,
202 const void *Decoder)
203 {
204 return decodeRegisterClass(Inst, RegNo, VRegs);
205 }
206
DecodeVSRCRegisterClass(MCInst * Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)207 static DecodeStatus DecodeVSRCRegisterClass(MCInst *Inst, uint64_t RegNo,
208 uint64_t Address,
209 const void *Decoder)
210 {
211 return decodeRegisterClass(Inst, RegNo, VSRegs);
212 }
213
DecodeVSFRCRegisterClass(MCInst * Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)214 static DecodeStatus DecodeVSFRCRegisterClass(MCInst *Inst, uint64_t RegNo,
215 uint64_t Address,
216 const void *Decoder)
217 {
218 return decodeRegisterClass(Inst, RegNo, VSFRegs);
219 }
220
DecodeGPRCRegisterClass(MCInst * Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)221 static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, uint64_t RegNo,
222 uint64_t Address,
223 const void *Decoder)
224 {
225 return decodeRegisterClass(Inst, RegNo, GPRegs);
226 }
227
DecodeGPRC_NOR0RegisterClass(MCInst * Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)228 static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst *Inst, uint64_t RegNo,
229 uint64_t Address,
230 const void *Decoder)
231 {
232 return decodeRegisterClass(Inst, RegNo, GP0Regs);
233 }
234
DecodeG8RCRegisterClass(MCInst * Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)235 static DecodeStatus DecodeG8RCRegisterClass(MCInst *Inst, uint64_t RegNo,
236 uint64_t Address,
237 const void *Decoder)
238 {
239 return decodeRegisterClass(Inst, RegNo, G8Regs);
240 }
241
242 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
243 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
244
DecodeQFRCRegisterClass(MCInst * Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)245 static DecodeStatus DecodeQFRCRegisterClass(MCInst *Inst, uint64_t RegNo,
246 uint64_t Address,
247 const void *Decoder)
248 {
249 return decodeRegisterClass(Inst, RegNo, QFRegs);
250 }
251
252 #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass
253 #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass
254
decodeUImmOperand(MCInst * Inst,uint64_t Imm,int64_t Address,const void * Decoder,unsigned N)255 static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm,
256 int64_t Address, const void *Decoder, unsigned N)
257 {
258 //assert(isUInt<N>(Imm) && "Invalid immediate");
259 MCOperand_CreateImm0(Inst, Imm);
260 return MCDisassembler_Success;
261 }
262
decodeSImmOperand(MCInst * Inst,uint64_t Imm,int64_t Address,const void * Decoder,unsigned N)263 static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm,
264 int64_t Address, const void *Decoder, unsigned N)
265 {
266 // assert(isUInt<N>(Imm) && "Invalid immediate");
267 MCOperand_CreateImm0(Inst, SignExtend64(Imm, N));
268 return MCDisassembler_Success;
269 }
270
271
272 #define GET_INSTRINFO_ENUM
273 #include "PPCGenInstrInfo.inc"
274
decodeMemRIOperands(MCInst * Inst,uint64_t Imm,int64_t Address,const void * Decoder)275 static DecodeStatus decodeMemRIOperands(MCInst *Inst, uint64_t Imm,
276 int64_t Address, const void *Decoder)
277 {
278 // Decode the memri field (imm, reg), which has the low 16-bits as the
279 // displacement and the next 5 bits as the register #.
280
281 uint64_t Base = Imm >> 16;
282 uint64_t Disp = Imm & 0xFFFF;
283
284 // assert(Base < 32 && "Invalid base register");
285 if (Base >= 32)
286 return MCDisassembler_Fail;
287
288 switch (MCInst_getOpcode(Inst)) {
289 default: break;
290 case PPC_LBZU:
291 case PPC_LHAU:
292 case PPC_LHZU:
293 case PPC_LWZU:
294 case PPC_LFSU:
295 case PPC_LFDU:
296 // Add the tied output operand.
297 MCOperand_CreateReg0(Inst, GP0Regs[Base]);
298 break;
299 case PPC_STBU:
300 case PPC_STHU:
301 case PPC_STWU:
302 case PPC_STFSU:
303 case PPC_STFDU:
304 MCInst_insert0(Inst, 0, MCOperand_CreateReg1(Inst, GP0Regs[Base]));
305 break;
306 }
307
308 MCOperand_CreateImm0(Inst, SignExtend64(Disp, 16));
309 MCOperand_CreateReg0(Inst, GP0Regs[Base]);
310 return MCDisassembler_Success;
311 }
312
decodeMemRIXOperands(MCInst * Inst,uint64_t Imm,int64_t Address,const void * Decoder)313 static DecodeStatus decodeMemRIXOperands(MCInst *Inst, uint64_t Imm,
314 int64_t Address, const void *Decoder)
315 {
316 // Decode the memrix field (imm, reg), which has the low 14-bits as the
317 // displacement and the next 5 bits as the register #.
318
319 uint64_t Base = Imm >> 14;
320 uint64_t Disp = Imm & 0x3FFF;
321
322 // assert(Base < 32 && "Invalid base register");
323
324 if (MCInst_getOpcode(Inst) == PPC_LDU)
325 // Add the tied output operand.
326 MCOperand_CreateReg0(Inst, GP0Regs[Base]);
327 else if (MCInst_getOpcode(Inst) == PPC_STDU)
328 MCInst_insert0(Inst, 0, MCOperand_CreateReg1(Inst, GP0Regs[Base]));
329
330 MCOperand_CreateImm0(Inst, SignExtend64(Disp << 2, 16));
331 MCOperand_CreateReg0(Inst, GP0Regs[Base]);
332 return MCDisassembler_Success;
333 }
334
decodeCRBitMOperand(MCInst * Inst,uint64_t Imm,int64_t Address,const void * Decoder)335 static DecodeStatus decodeCRBitMOperand(MCInst *Inst, uint64_t Imm,
336 int64_t Address, const void *Decoder)
337 {
338 // The cr bit encoding is 0x80 >> cr_reg_num.
339
340 unsigned Zeros = CountTrailingZeros_64(Imm);
341 // assert(Zeros < 8 && "Invalid CR bit value");
342 if (Zeros >=8)
343 return MCDisassembler_Fail;
344
345 MCOperand_CreateReg0(Inst, CRRegs[7 - Zeros]);
346 return MCDisassembler_Success;
347 }
348
349 #include "PPCGenDisassemblerTables.inc"
350
getInstruction(MCInst * MI,const uint8_t * code,size_t code_len,uint16_t * Size,uint64_t Address,MCRegisterInfo * MRI)351 static DecodeStatus getInstruction(MCInst *MI,
352 const uint8_t *code, size_t code_len,
353 uint16_t *Size,
354 uint64_t Address, MCRegisterInfo *MRI)
355 {
356 uint32_t insn;
357 DecodeStatus result;
358 // Get the four bytes of the instruction.
359 if (code_len < 4) {
360 // not enough data
361 *Size = 0;
362 return MCDisassembler_Fail;
363 }
364
365 // The instruction is big-endian encoded.
366 if (MODE_IS_BIG_ENDIAN(MI->csh->mode))
367 insn = ((uint32_t) code[0] << 24) | (code[1] << 16) |
368 (code[2] << 8) | (code[3] << 0);
369 else
370 insn = ((uint32_t) code[3] << 24) | (code[2] << 16) |
371 (code[1] << 8) | (code[0] << 0);
372
373 if (MI->flat_insn->detail) {
374 memset(MI->flat_insn->detail, 0, offsetof(cs_detail, ppc)+sizeof(cs_ppc));
375 }
376
377 if (MI->csh->mode & CS_MODE_QPX) {
378 result = decodeInstruction_4(DecoderTableQPX32, MI, insn, Address, 4);
379 if (result != MCDisassembler_Fail) {
380 *Size = 4;
381 return result;
382 }
383
384 MCInst_clear(MI);
385 }
386
387 result = decodeInstruction_4(DecoderTable32, MI, insn, Address, 4);
388 if (result != MCDisassembler_Fail) {
389 *Size = 4;
390 return result;
391 }
392
393 // report error
394 MCInst_clear(MI);
395 *Size = 0;
396 return MCDisassembler_Fail;
397 }
398
PPC_getInstruction(csh ud,const uint8_t * code,size_t code_len,MCInst * instr,uint16_t * size,uint64_t address,void * info)399 bool PPC_getInstruction(csh ud, const uint8_t *code, size_t code_len,
400 MCInst *instr, uint16_t *size, uint64_t address, void *info)
401 {
402 DecodeStatus status = getInstruction(instr,
403 code, code_len,
404 size,
405 address, (MCRegisterInfo *)info);
406
407 return status == MCDisassembler_Success;
408 }
409
410 #define GET_REGINFO_MC_DESC
411 #include "PPCGenRegisterInfo.inc"
PPC_init(MCRegisterInfo * MRI)412 void PPC_init(MCRegisterInfo *MRI)
413 {
414 /*
415 InitMCRegisterInfo(PPCRegDesc, 310, RA, PC,
416 PPCMCRegisterClasses, 23,
417 PPCRegUnitRoots,
418 138,
419 PPCRegDiffLists,
420 PPCLaneMaskLists,
421 PPCRegStrings,
422 PPCRegClassStrings,
423 PPCSubRegIdxLists,
424 8,
425 PPCSubRegIdxRanges,
426 PPCRegEncodingTable);
427 */
428
429
430 MCRegisterInfo_InitMCRegisterInfo(MRI, PPCRegDesc, 310,
431 0, 0,
432 PPCMCRegisterClasses, 23,
433 0, 0,
434 PPCRegDiffLists,
435 0,
436 PPCSubRegIdxLists, 8,
437 0);
438 }
439
440 #endif
441