1;; Constraint definitions for Adaptiva epiphany
2;; Copyright (C) 2007-2018 Free Software Foundation, Inc.
3;; Contributed by Embecosm on behalf of Adapteva, Inc.
4
5;; This file is part of GCC.
6
7;; GCC is free software; you can redistribute it and/or modify
8;; it under the terms of the GNU General Public License as published by
9;; the Free Software Foundation; either version 3, or (at your option)
10;; any later version.
11
12;; GCC is distributed in the hope that it will be useful,
13;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15;; GNU General Public License for more details.
16
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3.  If not see
19;; <http://www.gnu.org/licenses/>.
20
21;; Integer constraints
22
23(define_constraint "U16"
24  "An unsigned 16-bit constant."
25  (ior (and (match_code "const_int")
26	    (match_test "IMM16 (ival)"))
27       (and (match_code "symbol_ref,label_ref,const")
28	    (match_test "epiphany_small16 (op)"))))
29
30(define_constraint "K"
31  "An unsigned 5-bit constant."
32  (and (match_code "const_int")
33       (match_test "IMM5 (ival)")))
34
35;; This could also accept symbol_ref, label_ref or const if we introduce
36;; a small area and/or attribute that satisfies the 11-bit signed range.
37(define_constraint "L"
38  "A signed 11-bit constant."
39  (and (match_code "const_int")
40       (match_test "SIMM11 (ival)")))
41
42(define_constraint "CnL"
43  "A negated signed 11-bit constant."
44  (and (match_code "const_int")
45       (match_test "SIMM11 (-ival)")))
46
47(define_constraint "Cm1"
48  "A signed 11-bit constant added to -1"
49  (and (match_code "const_int")
50       (match_test "SIMM11 (ival+1)")
51       (match_test "epiphany_m1reg >= 0")))
52
53(define_constraint "Cl1"
54  "Left-shift of -1"
55  (and (match_code "const_int")
56       (match_test "ival == (ival | ~(ival-1))")
57       (match_test "epiphany_m1reg >= 0")))
58
59(define_constraint "Cr1"
60  "Right-shift of -1"
61  (and (match_code "const_int")
62       (match_test "ival == (ival & ~(ival+1))")
63       (match_test "epiphany_m1reg >= 0")))
64
65(define_constraint "Cal"
66  "Constant for arithmetic/logical operations"
67  (match_test "(flag_pic
68		? nonsymbolic_immediate_operand (op, VOIDmode)
69		: immediate_operand (op, VOIDmode))"))
70
71(define_constraint "Csy"
72  "Symbolic constant for call/jump instruction"
73  (match_test "symbolic_operand (op, VOIDmode)"))
74
75;; Register constraints
76;; proper register constraints define a register class and can thus
77;; drive register allocation and reload.  OTOH sometimes we want to
78;; avoid just that.
79
80;; The register class usable in short insns.
81;; Subject to TARGET_PREFER_SHORT_INSN_REGS.
82(define_register_constraint "Rcs" "SHORT_INSN_REGS"
83  "short insn register class.")
84
85; The registers that can be used to hold a sibcall call address.
86; This must not conflict with any callee-saved registers.
87(define_register_constraint "Rsc" "SIBCALL_REGS"
88  "sibcall register class")
89
90; The registers that can be used to hold a status value
91(define_register_constraint "Rct" "CORE_CONTROL_REGS"
92  "Core control register class")
93
94;; The register group usable in short insns.
95(define_constraint "Rgs"
96  "short insn register group."
97  (and (match_code "reg")
98       (match_test "REGNO (op) >= FIRST_PSEUDO_REGISTER || REGNO (op) <= 7")))
99
100;; Constant suitable for the addsi3_r pattern.
101(define_constraint "Car"
102  "addsi3_r constant."
103  (and (match_code "const_int")
104       (ior (match_test "RTX_OK_FOR_OFFSET_P (SImode, op)")
105	    (match_test "RTX_OK_FOR_OFFSET_P (HImode, op)")
106	    (match_test "RTX_OK_FOR_OFFSET_P (QImode, op)"))))
107
108;; The return address if it can be replaced with GPR_LR.
109(define_constraint "Rra"
110  "return address constraint - register variant"
111  (and (match_code "unspec")
112       (match_test "XINT (op, 1) == UNSPEC_RETURN_ADDR")
113       (match_test "!MACHINE_FUNCTION (cfun)->lr_clobbered")))
114
115(define_constraint "Rcc"
116  "integer condition code"
117  (and (match_code "reg")
118       (match_test "REGNO (op) == CC_REGNUM")))
119
120;; The return address, which might be a stack slot.  */
121(define_constraint "Sra"
122  "return address constraint - memory variant"
123  (and (match_code "unspec")
124       (match_test "XINT (op, 1) == UNSPEC_RETURN_ADDR")))
125
126(define_constraint "Cfm"
127  "control register values to switch fp mode"
128  (and (match_code "const")
129       (match_test "GET_CODE (XEXP (op, 0)) == UNSPEC")
130       (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_FP_MODE")))
131