1 /* Definitions of target machine for GNU compiler, for Sun SPARC. 2 Copyright (C) 1987-2018 Free Software Foundation, Inc. 3 Contributed by Michael Tiemann (tiemann@cygnus.com). 4 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, 5 at Cygnus Support. 6 7 This file is part of GCC. 8 9 GCC is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 GCC is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GCC; see the file COPYING3. If not see 21 <http://www.gnu.org/licenses/>. */ 22 23 #include "config/vxworks-dummy.h" 24 25 /* Note that some other tm.h files include this one and then override 26 whatever definitions are necessary. */ 27 28 #define TARGET_CPU_CPP_BUILTINS() sparc_target_macros () 29 30 /* Specify this in a cover file to provide bi-architecture (32/64) support. */ 31 /* #define SPARC_BI_ARCH */ 32 33 /* Macro used later in this file to determine default architecture. */ 34 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0) 35 36 /* TARGET_ARCH{32,64} are the main macros to decide which of the two 37 architectures to compile for. We allow targets to choose compile time or 38 runtime selection. */ 39 #ifdef IN_LIBGCC2 40 #if defined(__sparcv9) || defined(__arch64__) 41 #define TARGET_ARCH32 0 42 #else 43 #define TARGET_ARCH32 1 44 #endif /* sparc64 */ 45 #else 46 #ifdef SPARC_BI_ARCH 47 #define TARGET_ARCH32 (!TARGET_64BIT) 48 #else 49 #define TARGET_ARCH32 (DEFAULT_ARCH32_P) 50 #endif /* SPARC_BI_ARCH */ 51 #endif /* IN_LIBGCC2 */ 52 #define TARGET_ARCH64 (!TARGET_ARCH32) 53 54 /* Code model selection in 64-bit environment. 55 56 The machine mode used for addresses is 32-bit wide: 57 58 TARGET_CM_32: 32-bit address space. 59 It is the code model used when generating 32-bit code. 60 61 The machine mode used for addresses is 64-bit wide: 62 63 TARGET_CM_MEDLOW: 32-bit address space. 64 The executable must be in the low 32 bits of memory. 65 This avoids generating %uhi and %ulo terms. Programs 66 can be statically or dynamically linked. 67 68 TARGET_CM_MEDMID: 44-bit address space. 69 The executable must be in the low 44 bits of memory, 70 and the %[hml]44 terms are used. The text and data 71 segments have a maximum size of 2GB (31-bit span). 72 The maximum offset from any instruction to the label 73 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). 74 75 TARGET_CM_MEDANY: 64-bit address space. 76 The text and data segments have a maximum size of 2GB 77 (31-bit span) and may be located anywhere in memory. 78 The maximum offset from any instruction to the label 79 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). 80 81 TARGET_CM_EMBMEDANY: 64-bit address space. 82 The text and data segments have a maximum size of 2GB 83 (31-bit span) and may be located anywhere in memory. 84 The global register %g4 contains the start address of 85 the data segment. Programs are statically linked and 86 PIC is not supported. 87 88 Different code models are not supported in 32-bit environment. */ 89 90 enum cmodel { 91 CM_32, 92 CM_MEDLOW, 93 CM_MEDMID, 94 CM_MEDANY, 95 CM_EMBMEDANY 96 }; 97 98 /* One of CM_FOO. */ 99 extern enum cmodel sparc_cmodel; 100 101 /* V9 code model selection. */ 102 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW) 103 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID) 104 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY) 105 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY) 106 107 #define SPARC_DEFAULT_CMODEL CM_32 108 109 /* Do not use the .note.GNU-stack convention by default. */ 110 #define NEED_INDICATE_EXEC_STACK 0 111 112 /* This is call-clobbered in the normal ABI, but is reserved in the 113 home grown (aka upward compatible) embedded ABI. */ 114 #define EMBMEDANY_BASE_REG "%g4" 115 116 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile, 117 and specified by the user via --with-cpu=foo. 118 This specifies the cpu implementation, not the architecture size. */ 119 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit 120 capable cpu's. */ 121 #define TARGET_CPU_sparc 0 122 #define TARGET_CPU_v7 0 /* alias */ 123 #define TARGET_CPU_cypress 0 /* alias */ 124 #define TARGET_CPU_v8 1 /* generic v8 implementation */ 125 #define TARGET_CPU_supersparc 2 126 #define TARGET_CPU_hypersparc 3 127 #define TARGET_CPU_leon 4 128 #define TARGET_CPU_leon3 5 129 #define TARGET_CPU_leon3v7 6 130 #define TARGET_CPU_sparclite 7 131 #define TARGET_CPU_f930 7 /* alias */ 132 #define TARGET_CPU_f934 7 /* alias */ 133 #define TARGET_CPU_sparclite86x 8 134 #define TARGET_CPU_sparclet 9 135 #define TARGET_CPU_tsc701 9 /* alias */ 136 #define TARGET_CPU_v9 10 /* generic v9 implementation */ 137 #define TARGET_CPU_sparcv9 10 /* alias */ 138 #define TARGET_CPU_sparc64 10 /* alias */ 139 #define TARGET_CPU_ultrasparc 11 140 #define TARGET_CPU_ultrasparc3 12 141 #define TARGET_CPU_niagara 13 142 #define TARGET_CPU_niagara2 14 143 #define TARGET_CPU_niagara3 15 144 #define TARGET_CPU_niagara4 16 145 #define TARGET_CPU_niagara7 19 146 #define TARGET_CPU_m8 20 147 148 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ 149 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ 150 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \ 151 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \ 152 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 \ 153 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 \ 154 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 \ 155 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara7 \ 156 || TARGET_CPU_DEFAULT == TARGET_CPU_m8 157 158 #define CPP_CPU32_DEFAULT_SPEC "" 159 #define ASM_CPU32_DEFAULT_SPEC "" 160 161 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 162 /* ??? What does Sun's CC pass? */ 163 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 164 /* ??? It's not clear how other assemblers will handle this, so by default 165 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case 166 is handled in sol2.h. */ 167 #define ASM_CPU64_DEFAULT_SPEC "-Av9" 168 #endif 169 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc 170 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 171 #define ASM_CPU64_DEFAULT_SPEC "-Av9a" 172 #endif 173 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 174 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 175 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" 176 #endif 177 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara 178 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 179 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" 180 #endif 181 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 182 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 183 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" 184 #endif 185 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 186 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 187 #define ASM_CPU64_DEFAULT_SPEC "-Av9" AS_NIAGARA3_FLAG 188 #endif 189 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 190 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 191 #define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA4_FLAG 192 #endif 193 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara7 194 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 195 #define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA7_FLAG 196 #endif 197 #if TARGET_CPU_DEFAULT == TARGET_CPU_m8 198 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 199 #define ASM_CPU64_DEFAULT_SPEC AS_M8_FLAG 200 #endif 201 202 #else 203 204 #define CPP_CPU64_DEFAULT_SPEC "" 205 #define ASM_CPU64_DEFAULT_SPEC "" 206 207 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \ 208 || TARGET_CPU_DEFAULT == TARGET_CPU_v8 209 #define CPP_CPU32_DEFAULT_SPEC "" 210 #define ASM_CPU32_DEFAULT_SPEC "" 211 #endif 212 213 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet 214 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__" 215 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet" 216 #endif 217 218 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite 219 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__" 220 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" 221 #endif 222 223 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x 224 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__" 225 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" 226 #endif 227 228 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc 229 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__" 230 #define ASM_CPU32_DEFAULT_SPEC "" 231 #endif 232 233 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc 234 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__" 235 #define ASM_CPU32_DEFAULT_SPEC "" 236 #endif 237 238 #if TARGET_CPU_DEFAULT == TARGET_CPU_leon \ 239 || TARGET_CPU_DEFAULT == TARGET_CPU_leon3 240 #define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D__sparc_v8__" 241 #define ASM_CPU32_DEFAULT_SPEC AS_LEON_FLAG 242 #endif 243 244 #if TARGET_CPU_DEFAULT == TARGET_CPU_leon3v7 245 #define CPP_CPU32_DEFAULT_SPEC "-D__leon__" 246 #define ASM_CPU32_DEFAULT_SPEC AS_LEONV7_FLAG 247 #endif 248 249 #endif 250 251 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC) 252 #error Unrecognized value in TARGET_CPU_DEFAULT. 253 #endif 254 255 #ifdef SPARC_BI_ARCH 256 257 #define CPP_CPU_DEFAULT_SPEC \ 258 (DEFAULT_ARCH32_P ? "\ 259 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \ 260 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \ 261 " : "\ 262 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \ 263 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \ 264 ") 265 #define ASM_CPU_DEFAULT_SPEC \ 266 (DEFAULT_ARCH32_P ? "\ 267 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \ 268 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \ 269 " : "\ 270 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \ 271 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \ 272 ") 273 274 #else /* !SPARC_BI_ARCH */ 275 276 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC) 277 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC) 278 279 #endif /* !SPARC_BI_ARCH */ 280 281 /* Define macros to distinguish architectures. */ 282 283 /* Common CPP definitions used by CPP_SPEC amongst the various targets 284 for handling -mcpu=xxx switches. */ 285 #define CPP_CPU_SPEC "\ 286 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \ 287 %{mcpu=sparclite:-D__sparclite__} \ 288 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \ 289 %{mcpu=sparclite86x:-D__sparclite86x__} \ 290 %{mcpu=v8:-D__sparc_v8__} \ 291 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \ 292 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \ 293 %{mcpu=leon:-D__leon__ -D__sparc_v8__} \ 294 %{mcpu=leon3:-D__leon__ -D__sparc_v8__} \ 295 %{mcpu=leon3v7:-D__leon__} \ 296 %{mcpu=v9:-D__sparc_v9__} \ 297 %{mcpu=ultrasparc:-D__sparc_v9__} \ 298 %{mcpu=ultrasparc3:-D__sparc_v9__} \ 299 %{mcpu=niagara:-D__sparc_v9__} \ 300 %{mcpu=niagara2:-D__sparc_v9__} \ 301 %{mcpu=niagara3:-D__sparc_v9__} \ 302 %{mcpu=niagara4:-D__sparc_v9__} \ 303 %{mcpu=niagara7:-D__sparc_v9__} \ 304 %{mcpu=m8:-D__sparc_v9__} \ 305 %{!mcpu*:%(cpp_cpu_default)} \ 306 " 307 #define CPP_ARCH32_SPEC "" 308 #define CPP_ARCH64_SPEC "-D__arch64__" 309 310 #define CPP_ARCH_DEFAULT_SPEC \ 311 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC) 312 313 #define CPP_ARCH_SPEC "\ 314 %{m32:%(cpp_arch32)} \ 315 %{m64:%(cpp_arch64)} \ 316 %{!m32:%{!m64:%(cpp_arch_default)}} \ 317 " 318 319 /* Macros to distinguish the endianness, window model and FP support. */ 320 #define CPP_OTHER_SPEC "\ 321 %{mflat:-D_FLAT} \ 322 %{msoft-float:-D_SOFT_FLOAT} \ 323 " 324 325 /* Macros to distinguish the particular subtarget. */ 326 #define CPP_SUBTARGET_SPEC "" 327 328 #define CPP_SPEC \ 329 "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_other) %(cpp_subtarget)" 330 331 /* This used to translate -dalign to -malign, but that is no good 332 because it can't turn off the usual meaning of making debugging dumps. */ 333 334 #define CC1_SPEC "" 335 336 /* Override in target specific files. */ 337 #define ASM_CPU_SPEC "\ 338 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \ 339 %{mcpu=sparclite:-Asparclite} \ 340 %{mcpu=sparclite86x:-Asparclite} \ 341 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \ 342 %{mcpu=v8:-Av8} \ 343 %{mcpu=supersparc:-Av8} \ 344 %{mcpu=hypersparc:-Av8} \ 345 %{mcpu=leon:" AS_LEON_FLAG "} \ 346 %{mcpu=leon3:" AS_LEON_FLAG "} \ 347 %{mcpu=leon3v7:" AS_LEONV7_FLAG "} \ 348 %{mv8plus:-Av8plus} \ 349 %{mcpu=v9:-Av9} \ 350 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \ 351 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \ 352 %{mcpu=niagara:%{!mv8plus:-Av9b}} \ 353 %{mcpu=niagara2:%{!mv8plus:-Av9b}} \ 354 %{mcpu=niagara3:%{!mv8plus:-Av9" AS_NIAGARA3_FLAG "}} \ 355 %{mcpu=niagara4:%{!mv8plus:" AS_NIAGARA4_FLAG "}} \ 356 %{mcpu=niagara7:%{!mv8plus:" AS_NIAGARA7_FLAG "}} \ 357 %{mcpu=m8:%{!mv8plus:" AS_M8_FLAG "}} \ 358 %{!mcpu*:%(asm_cpu_default)} \ 359 " 360 361 /* Word size selection, among other things. 362 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */ 363 364 #define ASM_ARCH32_SPEC "-32" 365 #ifdef HAVE_AS_REGISTER_PSEUDO_OP 366 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs" 367 #else 368 #define ASM_ARCH64_SPEC "-64" 369 #endif 370 #define ASM_ARCH_DEFAULT_SPEC \ 371 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC) 372 373 #define ASM_ARCH_SPEC "\ 374 %{m32:%(asm_arch32)} \ 375 %{m64:%(asm_arch64)} \ 376 %{!m32:%{!m64:%(asm_arch_default)}} \ 377 " 378 379 #ifdef HAVE_AS_RELAX_OPTION 380 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}" 381 #else 382 #define ASM_RELAX_SPEC "" 383 #endif 384 385 /* Special flags to the Sun-4 assembler when using pipe for input. */ 386 387 #define ASM_SPEC "\ 388 %{!pg:%{!p:%{" FPIE_OR_FPIC_SPEC ":-k}}} %{keep-local-as-symbols:-L} \ 389 %(asm_cpu) %(asm_relax)" 390 391 /* This macro defines names of additional specifications to put in the specs 392 that can be used in various specifications like CC1_SPEC. Its definition 393 is an initializer with a subgrouping for each command option. 394 395 Each subgrouping contains a string constant, that defines the 396 specification name, and a string constant that used by the GCC driver 397 program. 398 399 Do not define this macro if it does not need to do anything. */ 400 401 #define EXTRA_SPECS \ 402 { "cpp_cpu", CPP_CPU_SPEC }, \ 403 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ 404 { "cpp_arch32", CPP_ARCH32_SPEC }, \ 405 { "cpp_arch64", CPP_ARCH64_SPEC }, \ 406 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\ 407 { "cpp_arch", CPP_ARCH_SPEC }, \ 408 { "cpp_other", CPP_OTHER_SPEC }, \ 409 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \ 410 { "asm_cpu", ASM_CPU_SPEC }, \ 411 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \ 412 { "asm_arch32", ASM_ARCH32_SPEC }, \ 413 { "asm_arch64", ASM_ARCH64_SPEC }, \ 414 { "asm_relax", ASM_RELAX_SPEC }, \ 415 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\ 416 { "asm_arch", ASM_ARCH_SPEC }, \ 417 SUBTARGET_EXTRA_SPECS 418 419 #define SUBTARGET_EXTRA_SPECS 420 421 /* Because libgcc can generate references back to libc (via .umul etc.) we have 422 to list libc again after the second libgcc. */ 423 #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L" 424 425 426 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int") 427 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int") 428 429 /* ??? This should be 32 bits for v9 but what can we do? */ 430 #define WCHAR_TYPE "short unsigned int" 431 #define WCHAR_TYPE_SIZE 16 432 433 /* Mask of all CPU selection flags. */ 434 #define MASK_ISA \ 435 (MASK_SPARCLITE + MASK_SPARCLET + MASK_LEON + MASK_LEON3 \ 436 + MASK_V8 + MASK_V9 + MASK_DEPRECATED_V8_INSNS) 437 438 /* Mask of all CPU feature flags. */ 439 #define MASK_FEATURES \ 440 (MASK_FPU + MASK_HARD_QUAD + MASK_VIS + MASK_VIS2 + MASK_VIS3 \ 441 + MASK_VIS4 + MASK_CBCOND + MASK_FMAF + MASK_FSMULD \ 442 + MASK_POPC + MASK_SUBXC) 443 444 /* TARGET_HARD_MUL: Use 32-bit hardware multiply instructions but not %y. */ 445 #define TARGET_HARD_MUL \ 446 (TARGET_SPARCLITE || TARGET_SPARCLET \ 447 || TARGET_V8 || TARGET_DEPRECATED_V8_INSNS) 448 449 /* TARGET_HARD_MUL32: Use 32-bit hardware multiply instructions with %y 450 to get high 32 bits. False in 64-bit or V8+ because multiply stores 451 a 64-bit result in a register. */ 452 #define TARGET_HARD_MUL32 \ 453 (TARGET_HARD_MUL && TARGET_ARCH32 && !TARGET_V8PLUS) 454 455 /* MASK_APP_REGS must always be the default because that's what 456 FIXED_REGISTERS is set to and -ffixed- is processed before 457 TARGET_CONDITIONAL_REGISTER_USAGE is called (where we process 458 -mno-app-regs). */ 459 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU) 460 461 /* Recast the cpu class to be the cpu attribute. 462 Every file includes us, but not every file includes insn-attr.h. */ 463 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu) 464 465 /* Support for a compile-time default CPU, et cetera. The rules are: 466 --with-cpu is ignored if -mcpu is specified. 467 --with-tune is ignored if -mtune is specified. 468 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu 469 are specified. */ 470 #define OPTION_DEFAULT_SPECS \ 471 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \ 472 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ 473 {"float", "%{!msoft-float:%{!mhard-float:%{!mfpu:%{!mno-fpu:-m%(VALUE)-float}}}}" } 474 475 /* target machine storage layout */ 476 477 /* Define this if most significant bit is lowest numbered 478 in instructions that operate on numbered bit-fields. */ 479 #define BITS_BIG_ENDIAN 1 480 481 /* Define this if most significant byte of a word is the lowest numbered. */ 482 #define BYTES_BIG_ENDIAN 1 483 484 /* Define this if most significant word of a multiword number is the lowest 485 numbered. */ 486 #define WORDS_BIG_ENDIAN 1 487 488 #define MAX_BITS_PER_WORD 64 489 490 /* Width of a word, in units (bytes). */ 491 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4) 492 #ifdef IN_LIBGCC2 493 #define MIN_UNITS_PER_WORD UNITS_PER_WORD 494 #else 495 #define MIN_UNITS_PER_WORD 4 496 #endif 497 498 /* Now define the sizes of the C data types. */ 499 #define SHORT_TYPE_SIZE 16 500 #define INT_TYPE_SIZE 32 501 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32) 502 #define LONG_LONG_TYPE_SIZE 64 503 #define FLOAT_TYPE_SIZE 32 504 #define DOUBLE_TYPE_SIZE 64 505 506 /* LONG_DOUBLE_TYPE_SIZE is defined per OS even though the 507 SPARC ABI says that it is 128-bit wide. */ 508 /* #define LONG_DOUBLE_TYPE_SIZE 128 */ 509 510 /* The widest floating-point format really supported by the hardware. */ 511 #define WIDEST_HARDWARE_FP_SIZE 64 512 513 /* Width in bits of a pointer. This is the size of ptr_mode. */ 514 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32) 515 516 /* This is the machine mode used for addresses. */ 517 #define Pmode (TARGET_ARCH64 ? DImode : SImode) 518 519 /* If we have to extend pointers (only when TARGET_ARCH64 and not 520 TARGET_PTR64), we want to do it unsigned. This macro does nothing 521 if ptr_mode and Pmode are the same. */ 522 #define POINTERS_EXTEND_UNSIGNED 1 523 524 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 525 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32) 526 527 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 528 /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because 529 then %sp+2047 is 128-bit aligned so %sp is really only byte-aligned. */ 530 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64) 531 532 /* Temporary hack until the FIXME above is fixed. */ 533 #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS) 534 535 /* ALIGN FRAMES on double word boundaries */ 536 #define SPARC_STACK_ALIGN(LOC) ROUND_UP ((LOC), UNITS_PER_WORD * 2) 537 538 /* Allocation boundary (in *bits*) for the code of a function. */ 539 #define FUNCTION_BOUNDARY 32 540 541 /* Alignment of field after `int : 0' in a structure. */ 542 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32) 543 544 /* Every structure's size must be a multiple of this. */ 545 #define STRUCTURE_SIZE_BOUNDARY 8 546 547 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 548 #define PCC_BITFIELD_TYPE_MATTERS 1 549 550 /* No data type wants to be aligned rounder than this. */ 551 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64) 552 553 /* The best alignment to use in cases where we have a choice. */ 554 #define FASTEST_ALIGNMENT 64 555 556 /* Define this macro as an expression for the alignment of a structure 557 (given by STRUCT as a tree node) if the alignment computed in the 558 usual way is COMPUTED and the alignment explicitly specified was 559 SPECIFIED. 560 561 The default is to use SPECIFIED if it is larger; otherwise, use 562 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */ 563 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \ 564 (TARGET_FASTER_STRUCTS ? \ 565 ((TREE_CODE (STRUCT) == RECORD_TYPE \ 566 || TREE_CODE (STRUCT) == UNION_TYPE \ 567 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \ 568 && TYPE_FIELDS (STRUCT) != 0 \ 569 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \ 570 : MAX ((COMPUTED), (SPECIFIED))) \ 571 : MAX ((COMPUTED), (SPECIFIED))) 572 573 /* An integer expression for the size in bits of the largest integer machine 574 mode that should actually be used. We allow pairs of registers. */ 575 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_ARCH64 ? TImode : DImode) 576 577 /* We need 2 words, so we can save the stack pointer and the return register 578 of the function containing a non-local goto target. */ 579 #define STACK_SAVEAREA_MODE(LEVEL) \ 580 ((LEVEL) == SAVE_NONLOCAL ? (TARGET_ARCH64 ? TImode : DImode) : Pmode) 581 582 /* Make arrays of chars word-aligned for the same reasons. */ 583 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 584 (TREE_CODE (TYPE) == ARRAY_TYPE \ 585 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 586 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 587 588 /* Make local arrays of chars word-aligned for the same reasons. */ 589 #define LOCAL_ALIGNMENT(TYPE, ALIGN) DATA_ALIGNMENT (TYPE, ALIGN) 590 591 /* Set this nonzero if move instructions will actually fail to work 592 when given unaligned data. */ 593 #define STRICT_ALIGNMENT 1 594 595 /* Things that must be doubleword aligned cannot go in the text section, 596 because the linker fails to align the text section enough! 597 Put them in the data section. This macro is only used in this file. */ 598 #define MAX_TEXT_ALIGN 32 599 600 /* Standard register usage. */ 601 602 /* Number of actual hardware registers. 603 The hardware registers are assigned numbers for the compiler 604 from 0 to just below FIRST_PSEUDO_REGISTER. 605 All registers that the compiler knows about must be given numbers, 606 even those that are not normally considered general registers. 607 608 SPARC has 32 integer registers and 32 floating point registers. 609 64-bit SPARC has 32 additional fp regs, but the odd numbered ones are not 610 accessible. We still account for them to simplify register computations 611 (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so 612 32+32+32+4 == 100. 613 Register 100 is used as the integer condition code register. 614 Register 101 is used as the soft frame pointer register. 615 Register 102 is used as the general status register by VIS instructions. */ 616 617 #define FIRST_PSEUDO_REGISTER 103 618 619 #define SPARC_FIRST_INT_REG 0 620 #define SPARC_LAST_INT_REG 31 621 #define SPARC_FIRST_FP_REG 32 622 /* Additional V9 fp regs. */ 623 #define SPARC_FIRST_V9_FP_REG 64 624 #define SPARC_LAST_V9_FP_REG 95 625 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */ 626 #define SPARC_FIRST_V9_FCC_REG 96 627 #define SPARC_LAST_V9_FCC_REG 99 628 /* V8 fcc reg. */ 629 #define SPARC_FCC_REG 96 630 /* Integer CC reg. We don't distinguish %icc from %xcc. */ 631 #define SPARC_ICC_REG 100 632 #define SPARC_GSR_REG 102 633 634 /* Nonzero if REGNO is an fp reg. */ 635 #define SPARC_FP_REG_P(REGNO) \ 636 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG) 637 638 /* Nonzero if REGNO is an int reg. */ 639 #define SPARC_INT_REG_P(REGNO) \ 640 (((unsigned) (REGNO)) <= SPARC_LAST_INT_REG) 641 642 /* Argument passing regs. */ 643 #define SPARC_OUTGOING_INT_ARG_FIRST 8 644 #define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24) 645 #define SPARC_FP_ARG_FIRST 32 646 647 /* 1 for registers that have pervasive standard uses 648 and are not available for the register allocator. 649 650 On non-v9 systems: 651 g1 is free to use as temporary. 652 g2-g4 are reserved for applications. Gcc normally uses them as 653 temporaries, but this can be disabled via the -mno-app-regs option. 654 g5 through g7 are reserved for the operating system. 655 656 On v9 systems: 657 g1,g5 are free to use as temporaries, and are free to use between calls 658 if the call is to an external function via the PLT. 659 g4 is free to use as a temporary in the non-embedded case. 660 g4 is reserved in the embedded case. 661 g2-g3 are reserved for applications. Gcc normally uses them as 662 temporaries, but this can be disabled via the -mno-app-regs option. 663 g6-g7 are reserved for the operating system (or application in 664 embedded case). 665 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must 666 currently be a fixed register until this pattern is rewritten. 667 Register 1 is also used when restoring call-preserved registers in large 668 stack frames. 669 670 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in 671 TARGET_CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-. 672 */ 673 674 #define FIXED_REGISTERS \ 675 {1, 0, 2, 2, 2, 2, 1, 1, \ 676 0, 0, 0, 0, 0, 0, 1, 0, \ 677 0, 0, 0, 0, 0, 0, 0, 0, \ 678 0, 0, 0, 0, 0, 0, 0, 1, \ 679 \ 680 0, 0, 0, 0, 0, 0, 0, 0, \ 681 0, 0, 0, 0, 0, 0, 0, 0, \ 682 0, 0, 0, 0, 0, 0, 0, 0, \ 683 0, 0, 0, 0, 0, 0, 0, 0, \ 684 \ 685 0, 0, 0, 0, 0, 0, 0, 0, \ 686 0, 0, 0, 0, 0, 0, 0, 0, \ 687 0, 0, 0, 0, 0, 0, 0, 0, \ 688 0, 0, 0, 0, 0, 0, 0, 0, \ 689 \ 690 0, 0, 0, 0, 1, 1, 1} 691 692 /* 1 for registers not available across function calls. 693 These must include the FIXED_REGISTERS and also any 694 registers that can be used without being saved. 695 The latter must include the registers where values are returned 696 and the register where structure-value addresses are passed. 697 Aside from that, you can include as many other registers as you like. */ 698 699 #define CALL_USED_REGISTERS \ 700 {1, 1, 1, 1, 1, 1, 1, 1, \ 701 1, 1, 1, 1, 1, 1, 1, 1, \ 702 0, 0, 0, 0, 0, 0, 0, 0, \ 703 0, 0, 0, 0, 0, 0, 0, 1, \ 704 \ 705 1, 1, 1, 1, 1, 1, 1, 1, \ 706 1, 1, 1, 1, 1, 1, 1, 1, \ 707 1, 1, 1, 1, 1, 1, 1, 1, \ 708 1, 1, 1, 1, 1, 1, 1, 1, \ 709 \ 710 1, 1, 1, 1, 1, 1, 1, 1, \ 711 1, 1, 1, 1, 1, 1, 1, 1, \ 712 1, 1, 1, 1, 1, 1, 1, 1, \ 713 1, 1, 1, 1, 1, 1, 1, 1, \ 714 \ 715 1, 1, 1, 1, 1, 1, 1} 716 717 /* 1 for registers not available across function calls. 718 Unlike the above, this need not include the FIXED_REGISTERS, but any 719 registers that can be used without being saved. 720 The latter must include the registers where values are returned 721 and the register where structure-value addresses are passed. 722 Aside from that, you can include as many other registers as you like. */ 723 724 #define CALL_REALLY_USED_REGISTERS \ 725 {1, 1, 1, 1, 1, 1, 1, 1, \ 726 1, 1, 1, 1, 1, 1, 1, 1, \ 727 0, 0, 0, 0, 0, 0, 0, 0, \ 728 0, 0, 0, 0, 0, 0, 0, 0, \ 729 \ 730 1, 1, 1, 1, 1, 1, 1, 1, \ 731 1, 1, 1, 1, 1, 1, 1, 1, \ 732 1, 1, 1, 1, 1, 1, 1, 1, \ 733 1, 1, 1, 1, 1, 1, 1, 1, \ 734 \ 735 1, 1, 1, 1, 1, 1, 1, 1, \ 736 1, 1, 1, 1, 1, 1, 1, 1, \ 737 1, 1, 1, 1, 1, 1, 1, 1, \ 738 1, 1, 1, 1, 1, 1, 1, 1, \ 739 \ 740 1, 1, 1, 1, 1, 1, 1} 741 742 /* Due to the ARCH64 discrepancy above we must override this next 743 macro too. */ 744 #define REGMODE_NATURAL_SIZE(MODE) sparc_regmode_natural_size (MODE) 745 746 /* Value is 1 if it is OK to rename a hard register FROM to another hard 747 register TO. We cannot rename %g1 as it may be used before the save 748 register window instruction in the prologue. */ 749 #define HARD_REGNO_RENAME_OK(FROM, TO) ((FROM) != 1) 750 751 /* Select a register mode required for caller save of hard regno REGNO. 752 Contrary to what is documented, the default is not the smallest suitable 753 mode but the largest suitable mode for the given (REGNO, NREGS) pair and 754 it quickly creates paradoxical subregs that can be problematic. */ 755 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 756 ((MODE) == VOIDmode ? choose_hard_reg_mode (REGNO, NREGS, false) : (MODE)) 757 758 /* Specify the registers used for certain standard purposes. 759 The values of these macros are register numbers. */ 760 761 /* Register to use for pushing function arguments. */ 762 #define STACK_POINTER_REGNUM 14 763 764 /* The stack bias (amount by which the hardware register is offset by). */ 765 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0) 766 767 /* Actual top-of-stack address is 92/176 greater than the contents of the 768 stack pointer register for !v9/v9. That is: 769 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return 770 address, and 6*4 bytes for the 6 register parameters. 771 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer 772 parameter regs. */ 773 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS) 774 775 /* Base register for access to local variables of the function. */ 776 #define HARD_FRAME_POINTER_REGNUM 30 777 778 /* The soft frame pointer does not have the stack bias applied. */ 779 #define FRAME_POINTER_REGNUM 101 780 781 #define INIT_EXPANDERS \ 782 do { \ 783 if (crtl->emit.regno_pointer_align) \ 784 { \ 785 /* The biased stack pointer is only aligned on BITS_PER_UNIT. */\ 786 if (SPARC_STACK_BIAS) \ 787 { \ 788 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) \ 789 = BITS_PER_UNIT; \ 790 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) \ 791 = BITS_PER_UNIT; \ 792 } \ 793 \ 794 /* In 32-bit mode, not everything is double-word aligned. */ \ 795 if (TARGET_ARCH32) \ 796 { \ 797 REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) \ 798 = BITS_PER_WORD; \ 799 REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) \ 800 = BITS_PER_WORD; \ 801 REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) \ 802 = BITS_PER_WORD; \ 803 } \ 804 } \ 805 } while (0) 806 807 /* Base register for access to arguments of the function. */ 808 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM 809 810 /* Register in which static-chain is passed to a function. This must 811 not be a register used by the prologue. */ 812 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2) 813 814 /* Register which holds the global offset table, if any. */ 815 #define GLOBAL_OFFSET_TABLE_REGNUM 23 816 817 /* Register which holds offset table for position-independent data references. 818 The original SPARC ABI imposes no requirement on the choice of the register 819 so we use a pseudo-register to make sure it is properly saved and restored 820 around calls to setjmp. Now the ABI of VxWorks RTP makes it live on entry 821 to PLT entries so we use the canonical GOT register in this case. */ 822 #define PIC_OFFSET_TABLE_REGNUM \ 823 (TARGET_VXWORKS_RTP && flag_pic ? GLOBAL_OFFSET_TABLE_REGNUM : INVALID_REGNUM) 824 825 /* Pick a default value we can notice from override_options: 826 !v9: Default is on. 827 v9: Default is off. 828 Originally it was -1, but later on the container of options changed to 829 unsigned byte, so we decided to pick 127 as default value, which does 830 reflect an undefined default value in case of 0/1. */ 831 #define DEFAULT_PCC_STRUCT_RETURN 127 832 833 /* Functions which return large structures get the address 834 to place the wanted value at offset 64 from the frame. 835 Must reserve 64 bytes for the in and local registers. 836 v9: Functions which return large structures get the address to place the 837 wanted value from an invisible first argument. */ 838 #define STRUCT_VALUE_OFFSET 64 839 840 /* Define the classes of registers for register constraints in the 841 machine description. Also define ranges of constants. 842 843 One of the classes must always be named ALL_REGS and include all hard regs. 844 If there is more than one class, another class must be named NO_REGS 845 and contain no registers. 846 847 The name GENERAL_REGS must be the name of a class (or an alias for 848 another name such as ALL_REGS). This is the class of registers 849 that is allowed by "g" or "r" in a register constraint. 850 Also, registers outside this class are allocated only when 851 instructions express preferences for them. 852 853 The classes must be numbered in nondecreasing order; that is, 854 a larger-numbered class must never be contained completely 855 in a smaller-numbered class. 856 857 For any two classes, it is very desirable that there be another 858 class that represents their union. */ 859 860 /* The SPARC has various kinds of registers: general, floating point, 861 and condition codes [well, it has others as well, but none that we 862 care directly about]. 863 864 For v9 we must distinguish between the upper and lower floating point 865 registers because the upper ones can't hold SFmode values. 866 TARGET_HARD_REGNO_MODE_OK won't help here because reload assumes that 867 register(s) satisfying a group need for a class will also satisfy a 868 single need for that class. EXTRA_FP_REGS is a bit of a misnomer as 869 it covers all 64 fp regs. 870 871 It is important that one class contains all the general and all the standard 872 fp regs. Otherwise find_reg() won't properly allocate int regs for moves, 873 because reg_class_record() will bias the selection in favor of fp regs, 874 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS, 875 because FP_REGS > GENERAL_REGS. 876 877 It is also important that one class contain all the general and all 878 the fp regs. Otherwise when spilling a DFmode reg, it may be from 879 EXTRA_FP_REGS but find_reloads() may use class 880 GENERAL_OR_FP_REGS. This will cause allocate_reload_reg() to die 881 because the compiler thinks it doesn't have a spill reg when in 882 fact it does. 883 884 v9 also has 4 floating point condition code registers. Since we don't 885 have a class that is the union of FPCC_REGS with either of the others, 886 it is important that it appear first. Otherwise the compiler will die 887 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its 888 constraints. */ 889 890 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS, 891 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, 892 ALL_REGS, LIM_REG_CLASSES }; 893 894 #define N_REG_CLASSES (int) LIM_REG_CLASSES 895 896 /* Give names of register classes as strings for dump file. */ 897 898 #define REG_CLASS_NAMES \ 899 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \ 900 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \ 901 "ALL_REGS" } 902 903 /* Define which registers fit in which classes. 904 This is an initializer for a vector of HARD_REG_SET 905 of length N_REG_CLASSES. */ 906 907 #define REG_CLASS_CONTENTS \ 908 {{0, 0, 0, 0}, /* NO_REGS */ \ 909 {0, 0, 0, 0xf}, /* FPCC_REGS */ \ 910 {0xffff, 0, 0, 0}, /* I64_REGS */ \ 911 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \ 912 {0, -1, 0, 0}, /* FP_REGS */ \ 913 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \ 914 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \ 915 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \ 916 {-1, -1, -1, 0x7f}} /* ALL_REGS */ 917 918 /* The same information, inverted: 919 Return the class number of the smallest class containing 920 reg number REGNO. This could be a conditional expression 921 or could index an array. */ 922 923 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; 924 925 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] 926 927 /* This is the order in which to allocate registers normally. 928 929 We put %f0-%f7 last among the float registers, so as to make it more 930 likely that a pseudo-register which dies in the float return register 931 area will get allocated to the float return register, thus saving a move 932 instruction at the end of the function. 933 934 Similarly for integer return value registers. 935 936 We know in this case that we will not end up with a leaf function. 937 938 The register allocator is given the global and out registers first 939 because these registers are call clobbered and thus less useful to 940 global register allocation. 941 942 Next we list the local and in registers. They are not call clobbered 943 and thus very useful for global register allocation. We list the input 944 registers before the locals so that it is more likely the incoming 945 arguments received in those registers can just stay there and not be 946 reloaded. */ 947 948 #define REG_ALLOC_ORDER \ 949 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ 950 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ 951 15, /* %o7 */ \ 952 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ 953 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\ 954 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ 955 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ 956 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ 957 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ 958 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ 959 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ 960 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ 961 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ 962 96, 97, 98, 99, /* %fcc0-3 */ \ 963 100, 0, 14, 30, 101, 102 } /* %icc, %g0, %o6, %i6, %sfp, %gsr */ 964 965 /* This is the order in which to allocate registers for 966 leaf functions. If all registers can fit in the global and 967 output registers, then we have the possibility of having a leaf 968 function. 969 970 The macro actually mentioned the input registers first, 971 because they get renumbered into the output registers once 972 we know really do have a leaf function. 973 974 To be more precise, this register allocation order is used 975 when %o7 is found to not be clobbered right before register 976 allocation. Normally, the reason %o7 would be clobbered is 977 due to a call which could not be transformed into a sibling 978 call. 979 980 As a consequence, it is possible to use the leaf register 981 allocation order and not end up with a leaf function. We will 982 not get suboptimal register allocation in that case because by 983 definition of being potentially leaf, there were no function 984 calls. Therefore, allocation order within the local register 985 window is not critical like it is when we do have function calls. */ 986 987 #define REG_LEAF_ALLOC_ORDER \ 988 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ 989 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \ 990 15, /* %o7 */ \ 991 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ 992 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ 993 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ 994 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ 995 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ 996 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ 997 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ 998 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ 999 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ 1000 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ 1001 96, 97, 98, 99, /* %fcc0-3 */ \ 1002 100, 0, 14, 30, 31, 101, 102 } /* %icc, %g0, %o6, %i6, %i7, %sfp, %gsr */ 1003 1004 #define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc () 1005 1006 extern char sparc_leaf_regs[]; 1007 #define LEAF_REGISTERS sparc_leaf_regs 1008 1009 extern char leaf_reg_remap[]; 1010 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) 1011 1012 /* The class value for index registers, and the one for base regs. */ 1013 #define INDEX_REG_CLASS GENERAL_REGS 1014 #define BASE_REG_CLASS GENERAL_REGS 1015 1016 /* Local macro to handle the two v9 classes of FP regs. */ 1017 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS) 1018 1019 /* Predicate for 2-bit and 5-bit unsigned constants. */ 1020 #define SPARC_IMM2_P(X) (((unsigned HOST_WIDE_INT) (X) & ~0x3) == 0) 1021 #define SPARC_IMM5_P(X) (((unsigned HOST_WIDE_INT) (X) & ~0x1F) == 0) 1022 1023 /* Predicates for 5-bit, 10-bit, 11-bit and 13-bit signed constants. */ 1024 #define SPARC_SIMM5_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x10 < 0x20) 1025 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400) 1026 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800) 1027 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000) 1028 1029 /* 10- and 11-bit immediates are only used for a few specific insns. 1030 SMALL_INT is used throughout the port so we continue to use it. */ 1031 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X))) 1032 1033 /* Predicate for constants that can be loaded with a sethi instruction. 1034 This is the general, 64-bit aware, bitwise version that ensures that 1035 only constants whose representation fits in the mask 1036 1037 0x00000000fffffc00 1038 1039 are accepted. It will reject, for example, negative SImode constants 1040 on 64-bit hosts, so correct handling is to mask the value beforehand 1041 according to the mode of the instruction. */ 1042 #define SPARC_SETHI_P(X) \ 1043 (((unsigned HOST_WIDE_INT) (X) \ 1044 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0) 1045 1046 /* Version of the above predicate for SImode constants and below. */ 1047 #define SPARC_SETHI32_P(X) \ 1048 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode))) 1049 1050 /* Return the maximum number of consecutive registers 1051 needed to represent mode MODE in a register of class CLASS. */ 1052 /* On SPARC, this is the size of MODE in words. */ 1053 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1054 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \ 1055 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1056 1057 /* Stack layout; function entry, exit and calling. */ 1058 1059 /* Define this if pushing a word on the stack 1060 makes the stack pointer a smaller address. */ 1061 #define STACK_GROWS_DOWNWARD 1 1062 1063 /* Define this to nonzero if the nominal address of the stack frame 1064 is at the high-address end of the local variables; 1065 that is, each additional local variable allocated 1066 goes at a more negative offset in the frame. */ 1067 #define FRAME_GROWS_DOWNWARD 1 1068 1069 /* Offset of first parameter from the argument pointer register value. 1070 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg 1071 even if this function isn't going to use it. 1072 v9: This is 128 for the ins and locals. */ 1073 #define FIRST_PARM_OFFSET(FNDECL) \ 1074 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD) 1075 1076 /* Offset from the argument pointer register value to the CFA. 1077 This is different from FIRST_PARM_OFFSET because the register window 1078 comes between the CFA and the arguments. */ 1079 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 1080 1081 /* When a parameter is passed in a register, stack space is still 1082 allocated for it. 1083 !v9: All 6 possible integer registers have backing store allocated. 1084 v9: Only space for the arguments passed is allocated. */ 1085 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special 1086 meaning to the backend. Further, we need to be able to detect if a 1087 varargs/unprototyped function is called, as they may want to spill more 1088 registers than we've provided space. Ugly, ugly. So for now we retain 1089 all 6 slots even for v9. */ 1090 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD) 1091 1092 /* Definitions for register elimination. */ 1093 1094 #define ELIMINABLE_REGS \ 1095 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1096 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} } 1097 1098 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1099 do \ 1100 { \ 1101 (OFFSET) = sparc_initial_elimination_offset ((TO)); \ 1102 } \ 1103 while (0) 1104 1105 /* Keep the stack pointer constant throughout the function. 1106 This is both an optimization and a necessity: longjmp 1107 doesn't behave itself when the stack pointer moves within 1108 the function! */ 1109 #define ACCUMULATE_OUTGOING_ARGS 1 1110 1111 /* Define this macro if the target machine has "register windows". This 1112 C expression returns the register number as seen by the called function 1113 corresponding to register number OUT as seen by the calling function. 1114 Return OUT if register number OUT is not an outbound register. */ 1115 1116 #define INCOMING_REGNO(OUT) \ 1117 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16) 1118 1119 /* Define this macro if the target machine has "register windows". This 1120 C expression returns the register number as seen by the calling function 1121 corresponding to register number IN as seen by the called function. 1122 Return IN if register number IN is not an inbound register. */ 1123 1124 #define OUTGOING_REGNO(IN) \ 1125 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16) 1126 1127 /* Define this macro if the target machine has register windows. This 1128 C expression returns true if the register is call-saved but is in the 1129 register window. */ 1130 1131 #define LOCAL_REGNO(REGNO) \ 1132 (!TARGET_FLAT && (REGNO) >= 16 && (REGNO) <= 31) 1133 1134 /* Define the size of space to allocate for the return value of an 1135 untyped_call. */ 1136 1137 #define APPLY_RESULT_SIZE (TARGET_ARCH64 ? 24 : 16) 1138 1139 /* 1 if N is a possible register number for function argument passing. 1140 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */ 1141 1142 #define FUNCTION_ARG_REGNO_P(N) \ 1143 (((N) >= 8 && (N) <= 13) \ 1144 || (TARGET_ARCH64 && TARGET_FPU && (N) >= 32 && (N) <= 63)) 1145 1146 /* Define a data type for recording info about an argument list 1147 during the scan of that argument list. This data type should 1148 hold all necessary information about the function itself 1149 and about the args processed so far, enough to enable macros 1150 such as FUNCTION_ARG to determine where the next arg should go. 1151 1152 On SPARC (!v9), this is a single integer, which is a number of words 1153 of arguments scanned so far (including the invisible argument, 1154 if any, which holds the structure-value-address). 1155 Thus 7 or more means all following args should go on the stack. 1156 1157 For v9, we also need to know whether a prototype is present. */ 1158 1159 struct sparc_args { 1160 int words; /* number of words passed so far */ 1161 int prototype_p; /* nonzero if a prototype is present */ 1162 int libcall_p; /* nonzero if a library call */ 1163 }; 1164 #define CUMULATIVE_ARGS struct sparc_args 1165 1166 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1167 for a call to a function whose data type is FNTYPE. 1168 For a library call, FNTYPE is 0. */ 1169 1170 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1171 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL)); 1172 1173 1174 /* Generate the special assembly code needed to tell the assembler whatever 1175 it might need to know about the return value of a function. 1176 1177 For SPARC assemblers, we need to output a .proc pseudo-op which conveys 1178 information to the assembler relating to peephole optimization (done in 1179 the assembler). */ 1180 1181 #define ASM_DECLARE_RESULT(FILE, RESULT) \ 1182 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT))) 1183 1184 /* Output the special assembly code needed to tell the assembler some 1185 register is used as global register variable. 1186 1187 SPARC 64bit psABI declares registers %g2 and %g3 as application 1188 registers and %g6 and %g7 as OS registers. Any object using them 1189 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them 1190 and how they are used (scratch or some global variable). 1191 Linker will then refuse to link together objects which use those 1192 registers incompatibly. 1193 1194 Unless the registers are used for scratch, two different global 1195 registers cannot be declared to the same name, so in the unlikely 1196 case of a global register variable occupying more than one register 1197 we prefix the second and following registers with .gnu.part1. etc. */ 1198 1199 extern GTY(()) char sparc_hard_reg_printed[8]; 1200 1201 #ifdef HAVE_AS_REGISTER_PSEUDO_OP 1202 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \ 1203 do { \ 1204 if (TARGET_ARCH64) \ 1205 { \ 1206 int end = end_hard_regno (DECL_MODE (decl), REGNO); \ 1207 int reg; \ 1208 for (reg = (REGNO); reg < 8 && reg < end; reg++) \ 1209 if ((reg & ~1) == 2 || (reg & ~1) == 6) \ 1210 { \ 1211 if (reg == (REGNO)) \ 1212 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \ 1213 else \ 1214 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \ 1215 reg, reg - (REGNO), (NAME)); \ 1216 sparc_hard_reg_printed[reg] = 1; \ 1217 } \ 1218 } \ 1219 } while (0) 1220 #endif 1221 1222 1223 /* Emit rtl for profiling. */ 1224 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL) 1225 1226 /* All the work done in PROFILE_HOOK, but still required. */ 1227 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0) 1228 1229 /* Set the name of the mcount function for the system. */ 1230 #define MCOUNT_FUNCTION "*mcount" 1231 1232 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1233 the stack pointer does not matter. The value is tested only in 1234 functions that have frame pointers. */ 1235 #define EXIT_IGNORE_STACK 1 1236 1237 /* Length in units of the trampoline for entering a nested function. */ 1238 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16) 1239 1240 /* Alignment required for trampolines, in bits. */ 1241 #define TRAMPOLINE_ALIGNMENT 128 1242 1243 /* Generate RTL to flush the register windows so as to make arbitrary frames 1244 available. */ 1245 #define SETUP_FRAME_ADDRESSES() \ 1246 do { \ 1247 if (!TARGET_FLAT) \ 1248 emit_insn (gen_flush_register_windows ());\ 1249 } while (0) 1250 1251 /* Given an rtx for the address of a frame, 1252 return an rtx for the address of the word in the frame 1253 that holds the dynamic chain--the previous frame's address. */ 1254 #define DYNAMIC_CHAIN_ADDRESS(frame) \ 1255 plus_constant (Pmode, frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS) 1256 1257 /* Given an rtx for the frame pointer, 1258 return an rtx for the address of the frame. */ 1259 #define FRAME_ADDR_RTX(frame) plus_constant (Pmode, frame, SPARC_STACK_BIAS) 1260 1261 /* The return address isn't on the stack, it is in a register, so we can't 1262 access it from the current frame pointer. We can access it from the 1263 previous frame pointer though by reading a value from the register window 1264 save area. */ 1265 #define RETURN_ADDR_IN_PREVIOUS_FRAME 1 1266 1267 /* This is the offset of the return address to the true next instruction to be 1268 executed for the current function. */ 1269 #define RETURN_ADDR_OFFSET \ 1270 (8 + 4 * (! TARGET_ARCH64 && cfun->returns_struct)) 1271 1272 /* The current return address is in %i7. The return address of anything 1273 farther back is in the register window save area at [%fp+60]. */ 1274 /* ??? This ignores the fact that the actual return address is +8 for normal 1275 returns, and +12 for structure returns. */ 1276 #define RETURN_ADDR_REGNUM 31 1277 #define RETURN_ADDR_RTX(count, frame) \ 1278 ((count == -1) \ 1279 ? gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) \ 1280 : gen_rtx_MEM (Pmode, \ 1281 memory_address (Pmode, plus_constant (Pmode, frame, \ 1282 15 * UNITS_PER_WORD \ 1283 + SPARC_STACK_BIAS)))) 1284 1285 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's 1286 +12, but always using +8 is close enough for frame unwind purposes. 1287 Actually, just using %o7 is close enough for unwinding, but %o7+8 1288 is something you can return to. */ 1289 #define INCOMING_RETURN_ADDR_REGNUM 15 1290 #define INCOMING_RETURN_ADDR_RTX \ 1291 plus_constant (word_mode, \ 1292 gen_rtx_REG (word_mode, INCOMING_RETURN_ADDR_REGNUM), 8) 1293 #define DWARF_FRAME_RETURN_COLUMN \ 1294 DWARF_FRAME_REGNUM (INCOMING_RETURN_ADDR_REGNUM) 1295 1296 /* The offset from the incoming value of %sp to the top of the stack frame 1297 for the current function. On sparc64, we have to account for the stack 1298 bias if present. */ 1299 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS 1300 1301 /* Describe how we implement __builtin_eh_return. */ 1302 #define EH_RETURN_REGNUM 1 1303 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM) 1304 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_REGNUM) 1305 1306 /* Define registers used by the epilogue and return instruction. */ 1307 #define EPILOGUE_USES(REGNO) \ 1308 ((REGNO) == RETURN_ADDR_REGNUM \ 1309 || (TARGET_FLAT \ 1310 && epilogue_completed \ 1311 && (REGNO) == INCOMING_RETURN_ADDR_REGNUM) \ 1312 || (crtl->calls_eh_return && (REGNO) == EH_RETURN_REGNUM)) 1313 1314 /* Select a format to encode pointers in exception handling data. CODE 1315 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 1316 true if the symbol may be affected by dynamic relocations. 1317 1318 If assembler and linker properly support .uaword %r_disp32(foo), 1319 then use PC relative 32-bit relocations instead of absolute relocs 1320 for shared libraries. On sparc64, use pc relative 32-bit relocs even 1321 for binaries, to save memory. 1322 1323 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the 1324 symbol %r_disp32() is against was not local, but .hidden. In that 1325 case, we have to use DW_EH_PE_absptr for pic personality. */ 1326 #ifdef HAVE_AS_SPARC_UA_PCREL 1327 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN 1328 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 1329 (flag_pic \ 1330 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ 1331 : ((TARGET_ARCH64 && ! GLOBAL) \ 1332 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 1333 : DW_EH_PE_absptr)) 1334 #else 1335 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 1336 (flag_pic \ 1337 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \ 1338 : ((TARGET_ARCH64 && ! GLOBAL) \ 1339 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 1340 : DW_EH_PE_absptr)) 1341 #endif 1342 1343 /* Emit a PC-relative relocation. */ 1344 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ 1345 do { \ 1346 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 1347 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \ 1348 assemble_name (FILE, LABEL); \ 1349 fputc (')', FILE); \ 1350 } while (0) 1351 #endif 1352 1353 /* Addressing modes, and classification of registers for them. */ 1354 1355 /* Macros to check register numbers against specific register classes. */ 1356 1357 /* These assume that REGNO is a hard or pseudo reg number. 1358 They give nonzero only if REGNO is a hard reg of the suitable class 1359 or a pseudo reg currently allocated to a suitable hard reg. 1360 Since they use reg_renumber, they are safe only once reg_renumber 1361 has been allocated, which happens in reginfo.c during register 1362 allocation. */ 1363 1364 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1365 (SPARC_INT_REG_P (REGNO) || SPARC_INT_REG_P (reg_renumber[REGNO]) \ 1366 || (REGNO) == FRAME_POINTER_REGNUM \ 1367 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM) 1368 1369 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) 1370 1371 #define REGNO_OK_FOR_FP_P(REGNO) \ 1372 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \ 1373 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32))) 1374 1375 #define REGNO_OK_FOR_CCFP_P(REGNO) \ 1376 (TARGET_V9 \ 1377 && (((unsigned) (REGNO) - 96 < (unsigned)4) \ 1378 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4))) 1379 1380 /* Maximum number of registers that can appear in a valid memory address. */ 1381 1382 #define MAX_REGS_PER_ADDRESS 2 1383 1384 /* Recognize any constant value that is a valid address. 1385 When PIC, we do not accept an address that would require a scratch reg 1386 to load into a register. */ 1387 1388 #define CONSTANT_ADDRESS_P(X) constant_address_p (X) 1389 1390 /* Define this, so that when PIC, reload won't try to reload invalid 1391 addresses which require two reload registers. */ 1392 1393 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 1394 1395 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */ 1396 1397 #ifdef HAVE_AS_OFFSETABLE_LO10 1398 #define USE_AS_OFFSETABLE_LO10 1 1399 #else 1400 #define USE_AS_OFFSETABLE_LO10 0 1401 #endif 1402 1403 /* Try a machine-dependent way of reloading an illegitimate address 1404 operand. If we find one, push the reload and jump to WIN. This 1405 macro is used in only one place: `find_reloads_address' in reload.c. */ 1406 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 1407 do { \ 1408 int win; \ 1409 (X) = sparc_legitimize_reload_address ((X), (MODE), (OPNUM), \ 1410 (int)(TYPE), (IND_LEVELS), &win); \ 1411 if (win) \ 1412 goto WIN; \ 1413 } while (0) 1414 1415 /* Specify the machine mode that this machine uses 1416 for the index in the tablejump instruction. */ 1417 /* If we ever implement any of the full models (such as CM_FULLANY), 1418 this has to be DImode in that case */ 1419 #ifdef HAVE_GAS_SUBSECTION_ORDERING 1420 #define CASE_VECTOR_MODE \ 1421 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode) 1422 #else 1423 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise 1424 we have to sign extend which slows things down. */ 1425 #define CASE_VECTOR_MODE \ 1426 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode) 1427 #endif 1428 1429 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1430 #define DEFAULT_SIGNED_CHAR 1 1431 1432 /* Max number of bytes we can move from memory to memory 1433 in one reasonably fast instruction. */ 1434 #define MOVE_MAX 8 1435 1436 /* If a memory-to-memory move would take MOVE_RATIO or more simple 1437 move-instruction pairs, we will do a movmem or libcall instead. */ 1438 1439 #define MOVE_RATIO(speed) ((speed) ? 8 : 3) 1440 1441 /* Define if operations between registers always perform the operation 1442 on the full register even if a narrower mode is specified. */ 1443 #define WORD_REGISTER_OPERATIONS 1 1444 1445 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1446 will either zero-extend or sign-extend. The value of this macro should 1447 be the code that says which one of the two operations is implicitly 1448 done, UNKNOWN if none. */ 1449 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1450 1451 /* Nonzero if access to memory by bytes is slow and undesirable. 1452 For RISC chips, it means that access to memory by bytes is no 1453 better than access by words when possible, so grab a whole word 1454 and maybe make use of that. */ 1455 #define SLOW_BYTE_ACCESS 1 1456 1457 /* Define this to be nonzero if shift instructions ignore all but the low-order 1458 few bits. */ 1459 #define SHIFT_COUNT_TRUNCATED 1 1460 1461 /* For SImode, we make sure the top 32-bits of the register are clear and 1462 then we subtract 32 from the lzd instruction result. */ 1463 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1464 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1) 1465 1466 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 1467 return the mode to be used for the comparison. For floating-point, 1468 CCFP[E]mode is used. CCNZmode should be used when the first operand 1469 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special 1470 processing is needed. */ 1471 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y)) 1472 1473 /* Return nonzero if MODE implies a floating point inequality can be 1474 reversed. For SPARC this is always true because we have a full 1475 compliment of ordered and unordered comparisons, but until generic 1476 code knows how to reverse it correctly we keep the old definition. */ 1477 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode) 1478 1479 /* A function address in a call instruction for indexing purposes. */ 1480 #define FUNCTION_MODE Pmode 1481 1482 /* Define this if addresses of constant functions 1483 shouldn't be put through pseudo regs where they can be cse'd. 1484 Desirable on machines where ordinary constants are expensive 1485 but a CALL with constant address is cheap. */ 1486 #define NO_FUNCTION_CSE 1 1487 1488 /* The _Q_* comparison libcalls return booleans. */ 1489 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode) 1490 1491 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such 1492 that the inputs are fully consumed before the output memory is clobbered. */ 1493 1494 #define TARGET_BUGGY_QP_LIB 0 1495 1496 /* Assume by default that we do not have the Solaris-specific conversion 1497 routines nor 64-bit integer multiply and divide routines. */ 1498 1499 #define SUN_CONVERSION_LIBFUNCS 0 1500 #define DITF_CONVERSION_LIBFUNCS 0 1501 #define SUN_INTEGER_MULTIPLY_64 0 1502 1503 /* Provide the cost of a branch. For pre-v9 processors we use 1504 a value of 3 to take into account the potential annulling of 1505 the delay slot (which ends up being a bubble in the pipeline slot) 1506 plus a cycle to take into consideration the instruction cache 1507 effects. 1508 1509 On v9 and later, which have branch prediction facilities, we set 1510 it to the depth of the pipeline as that is the cost of a 1511 mispredicted branch. 1512 1513 On Niagara, normal branches insert 3 bubbles into the pipe 1514 and annulled branches insert 4 bubbles. 1515 1516 On Niagara-2 and Niagara-3, a not-taken branch costs 1 cycle whereas 1517 a taken branch costs 6 cycles. 1518 1519 The T4 Supplement specifies the branch latency at 2 cycles. 1520 The M7 Supplement specifies the branch latency at 1 cycle. */ 1521 1522 #define BRANCH_COST(speed_p, predictable_p) \ 1523 ((sparc_cpu == PROCESSOR_V9 \ 1524 || sparc_cpu == PROCESSOR_ULTRASPARC) \ 1525 ? 7 \ 1526 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \ 1527 ? 9 \ 1528 : (sparc_cpu == PROCESSOR_NIAGARA \ 1529 ? 4 \ 1530 : ((sparc_cpu == PROCESSOR_NIAGARA2 \ 1531 || sparc_cpu == PROCESSOR_NIAGARA3) \ 1532 ? 5 \ 1533 : (sparc_cpu == PROCESSOR_NIAGARA4 \ 1534 ? 2 \ 1535 : (sparc_cpu == PROCESSOR_NIAGARA7 \ 1536 ? 1 \ 1537 : 3)))))) 1538 1539 /* Control the assembler format that we output. */ 1540 1541 /* A C string constant describing how to begin a comment in the target 1542 assembler language. The compiler assumes that the comment will end at 1543 the end of the line. */ 1544 1545 #define ASM_COMMENT_START "!" 1546 1547 /* Output to assembler file text saying following lines 1548 may contain character constants, extra white space, comments, etc. */ 1549 1550 #define ASM_APP_ON "" 1551 1552 /* Output to assembler file text saying following lines 1553 no longer contain unusual constructs. */ 1554 1555 #define ASM_APP_OFF "" 1556 1557 /* How to refer to registers in assembler output. 1558 This sequence is indexed by compiler's hard-register-number (see above). */ 1559 1560 #define REGISTER_NAMES \ 1561 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ 1562 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ 1563 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ 1564 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ 1565 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ 1566 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ 1567 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ 1568 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \ 1569 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \ 1570 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \ 1571 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \ 1572 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \ 1573 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp", "%gsr" } 1574 1575 /* Define additional names for use in asm clobbers and asm declarations. */ 1576 1577 #define ADDITIONAL_REGISTER_NAMES \ 1578 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}} 1579 1580 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length 1581 can run past this up to a continuation point. Once we used 1500, but 1582 a single entry in C++ can run more than 500 bytes, due to the length of 1583 mangled symbol names. dbxout.c should really be fixed to do 1584 continuations when they are actually needed instead of trying to 1585 guess... */ 1586 #define DBX_CONTIN_LENGTH 1000 1587 1588 /* This is how to output a command to make the user-level label named NAME 1589 defined for reference from other files. */ 1590 1591 /* Globalizing directive for a label. */ 1592 #define GLOBAL_ASM_OP "\t.global " 1593 1594 /* The prefix to add to user-visible assembler symbols. */ 1595 1596 #define USER_LABEL_PREFIX "_" 1597 1598 /* This is how to store into the string LABEL 1599 the symbol_ref name of an internal numbered label where 1600 PREFIX is the class of label and NUM is the number within the class. 1601 This is suitable for output with `assemble_name'. */ 1602 1603 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 1604 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM)) 1605 1606 /* This is how we hook in and defer the case-vector until the end of 1607 the function. */ 1608 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \ 1609 sparc_defer_case_vector ((LAB),(VEC), 0) 1610 1611 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \ 1612 sparc_defer_case_vector ((LAB),(VEC), 1) 1613 1614 /* This is how to output an element of a case-vector that is absolute. */ 1615 1616 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1617 do { \ 1618 char label[30]; \ 1619 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 1620 if (CASE_VECTOR_MODE == SImode) \ 1621 fprintf (FILE, "\t.word\t"); \ 1622 else \ 1623 fprintf (FILE, "\t.xword\t"); \ 1624 assemble_name (FILE, label); \ 1625 fputc ('\n', FILE); \ 1626 } while (0) 1627 1628 /* This is how to output an element of a case-vector that is relative. 1629 (SPARC uses such vectors only when generating PIC.) */ 1630 1631 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1632 do { \ 1633 char label[30]; \ 1634 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \ 1635 if (CASE_VECTOR_MODE == SImode) \ 1636 fprintf (FILE, "\t.word\t"); \ 1637 else \ 1638 fprintf (FILE, "\t.xword\t"); \ 1639 assemble_name (FILE, label); \ 1640 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \ 1641 fputc ('-', FILE); \ 1642 assemble_name (FILE, label); \ 1643 fputc ('\n', FILE); \ 1644 } while (0) 1645 1646 /* This is what to output before and after case-vector (both 1647 relative and absolute). If .subsection -1 works, we put case-vectors 1648 at the beginning of the current section. */ 1649 1650 #ifdef HAVE_GAS_SUBSECTION_ORDERING 1651 1652 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \ 1653 fprintf(FILE, "\t.subsection\t-1\n") 1654 1655 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \ 1656 fprintf(FILE, "\t.previous\n") 1657 1658 #endif 1659 1660 /* This is how to output an assembler line 1661 that says to advance the location counter 1662 to a multiple of 2**LOG bytes. */ 1663 1664 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1665 if ((LOG) != 0) \ 1666 fprintf (FILE, "\t.align %d\n", (1<<(LOG))) 1667 1668 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1669 fprintf (FILE, "\t.skip " HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) 1670 1671 /* This says how to output an assembler line 1672 to define a global common symbol. */ 1673 1674 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1675 ( fputs ("\t.common ", (FILE)), \ 1676 assemble_name ((FILE), (NAME)), \ 1677 fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE))) 1678 1679 /* This says how to output an assembler line to define a local common 1680 symbol. */ 1681 1682 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \ 1683 ( fputs ("\t.reserve ", (FILE)), \ 1684 assemble_name ((FILE), (NAME)), \ 1685 fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \ 1686 (SIZE), ((ALIGNED) / BITS_PER_UNIT))) 1687 1688 /* A C statement (sans semicolon) to output to the stdio stream 1689 FILE the assembler definition of uninitialized global DECL named 1690 NAME whose size is SIZE bytes and alignment is ALIGN bytes. 1691 Try to use asm_output_aligned_bss to implement this macro. */ 1692 1693 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 1694 do { \ 1695 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ 1696 } while (0) 1697 1698 /* Output #ident as a .ident. */ 1699 1700 #undef TARGET_ASM_OUTPUT_IDENT 1701 #define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive 1702 1703 /* Prettify the assembly. */ 1704 1705 extern int sparc_indent_opcode; 1706 1707 #define ASM_OUTPUT_OPCODE(FILE, PTR) \ 1708 do { \ 1709 if (sparc_indent_opcode) \ 1710 { \ 1711 putc (' ', FILE); \ 1712 sparc_indent_opcode = 0; \ 1713 } \ 1714 } while (0) 1715 1716 /* TLS support defaulting to original Sun flavor. GNU extensions 1717 must be activated in separate configuration files. */ 1718 #ifdef HAVE_AS_TLS 1719 #define TARGET_TLS 1 1720 #else 1721 #define TARGET_TLS 0 1722 #endif 1723 1724 #define TARGET_SUN_TLS TARGET_TLS 1725 #define TARGET_GNU_TLS 0 1726 1727 #ifdef HAVE_AS_FMAF_HPC_VIS3 1728 #define AS_NIAGARA3_FLAG "d" 1729 #else 1730 #define AS_NIAGARA3_FLAG "b" 1731 #endif 1732 1733 #ifdef HAVE_AS_SPARC4 1734 #define AS_NIAGARA4_FLAG "-xarch=sparc4" 1735 #else 1736 #define AS_NIAGARA4_FLAG "-Av9" AS_NIAGARA3_FLAG 1737 #endif 1738 1739 #ifdef HAVE_AS_SPARC5_VIS4 1740 #define AS_NIAGARA7_FLAG "-xarch=sparc5" 1741 #else 1742 #define AS_NIAGARA7_FLAG AS_NIAGARA4_FLAG 1743 #endif 1744 1745 #ifdef HAVE_AS_SPARC6 1746 #define AS_M8_FLAG "-xarch=sparc6" 1747 #else 1748 #define AS_M8_FLAG AS_NIAGARA7_FLAG 1749 #endif 1750 1751 #ifdef HAVE_AS_LEON 1752 #define AS_LEON_FLAG "-Aleon" 1753 #define AS_LEONV7_FLAG "-Aleon" 1754 #else 1755 #define AS_LEON_FLAG "-Av8" 1756 #define AS_LEONV7_FLAG "-Av7" 1757 #endif 1758 1759 /* We use gcc _mcount for profiling. */ 1760 #define NO_PROFILE_COUNTERS 0 1761 1762 /* Debug support */ 1763 #define MASK_DEBUG_OPTIONS 0x01 /* debug option handling */ 1764 #define MASK_DEBUG_ALL MASK_DEBUG_OPTIONS 1765 1766 #define TARGET_DEBUG_OPTIONS (sparc_debug & MASK_DEBUG_OPTIONS) 1767 1768 /* By default, use the weakest memory model for the cpu. */ 1769 #ifndef SUBTARGET_DEFAULT_MEMORY_MODEL 1770 #define SUBTARGET_DEFAULT_MEMORY_MODEL SMM_DEFAULT 1771 #endif 1772 1773 /* Define this to 1 if the FE_EXCEPT values defined in fenv.h start at 1. */ 1774 #define SPARC_LOW_FE_EXCEPT_VALUES 0 1775 1776 #define TARGET_SUPPORTS_WIDE_INT 1 1777