1 /* { dg-do compile { target { powerpc*-*-* } } } */
2 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
3 /* { dg-require-effective-target lp64 } */
4 /* { dg-require-effective-target powerpc_p9vector_ok } */
5 /* { dg-options "-O2 -mcpu=power9" } */
6
7 #include <altivec.h>
8
9 vector unsigned int
rlmi_test_1(vector unsigned int x,vector unsigned int y,vector unsigned int z)10 rlmi_test_1 (vector unsigned int x, vector unsigned int y,
11 vector unsigned int z)
12 {
13 return vec_rlmi (x, y, z);
14 }
15
16 vector unsigned long long
rlmi_test_2(vector unsigned long long x,vector unsigned long long y,vector unsigned long long z)17 rlmi_test_2 (vector unsigned long long x, vector unsigned long long y,
18 vector unsigned long long z)
19 {
20 return vec_rlmi (x, y, z);
21 }
22
23 vector unsigned int
vrlnm_test_1(vector unsigned int x,vector unsigned int y)24 vrlnm_test_1 (vector unsigned int x, vector unsigned int y)
25 {
26 return vec_vrlnm (x, y);
27 }
28
29 vector unsigned long long
vrlnm_test_2(vector unsigned long long x,vector unsigned long long y)30 vrlnm_test_2 (vector unsigned long long x, vector unsigned long long y)
31 {
32 return vec_vrlnm (x, y);
33 }
34
35 vector unsigned int
rlnm_test_1(vector unsigned int x,vector unsigned int y,vector unsigned int z)36 rlnm_test_1 (vector unsigned int x, vector unsigned int y,
37 vector unsigned int z)
38 {
39 return vec_rlnm (x, y, z);
40 }
41
42 vector unsigned long long
rlnm_test_2(vector unsigned long long x,vector unsigned long long y,vector unsigned long long z)43 rlnm_test_2 (vector unsigned long long x, vector unsigned long long y,
44 vector unsigned long long z)
45 {
46 return vec_rlnm (x, y, z);
47 }
48
49 /* Expected code generation for rlmi_test_1 is vrlwmi.
50 Expected code generation for rlmi_test_2 is vrldmi.
51 Expected code generation for vrlnm_test_1 is vrlwnm.
52 Expected code generation for vrlnm_test_2 is vrldnm.
53 Expected code generation for the others is more complex, because
54 the second and third arguments are combined by a shift and OR,
55 and because there is no splat-immediate doubleword.
56 - For rlnm_test_1: vspltisw, vslw, xxlor, vrlwnm.
57 - For rlnm_test_2: xxspltib, vextsb2d, vsld, xxlor, vrldnm.
58 There is a choice of splat instructions in both cases, so we
59 just check for "splt". */
60
61 /* { dg-final { scan-assembler-times "vrlwmi" 1 } } */
62 /* { dg-final { scan-assembler-times "vrldmi" 1 } } */
63 /* { dg-final { scan-assembler-times "splt" 2 } } */
64 /* { dg-final { scan-assembler-times "vextsb2d" 1 } } */
65 /* { dg-final { scan-assembler-times "vslw" 1 } } */
66 /* { dg-final { scan-assembler-times "vsld" 1 } } */
67 /* { dg-final { scan-assembler-times "xxlor" 2 } } */
68 /* { dg-final { scan-assembler-times "vrlwnm" 2 } } */
69 /* { dg-final { scan-assembler-times "vrldnm" 2 } } */
70