1 /* SPDX-License-Identifier: MIT
2 *
3 * Permission is hereby granted, free of charge, to any person
4 * obtaining a copy of this software and associated documentation
5 * files (the "Software"), to deal in the Software without
6 * restriction, including without limitation the rights to use, copy,
7 * modify, merge, publish, distribute, sublicense, and/or sell copies
8 * of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be
12 * included in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
18 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
19 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Copyright:
24 * 2020 Evan Nemerson <evan@nemerson.com>
25 * 2020 Sean Maher <seanptmaher@gmail.com> (Copyright owned by Google, LLC)
26 */
27
28 #if !defined(SIMDE_ARM_NEON_UZP_H) && !defined(SIMDE_BUG_INTEL_857088)
29 #define SIMDE_ARM_NEON_UZP_H
30
31 #include "types.h"
32 #include "uzp1.h"
33 #include "uzp2.h"
34
35 HEDLEY_DIAGNOSTIC_PUSH
36 SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
37 SIMDE_BEGIN_DECLS_
38
39 SIMDE_FUNCTION_ATTRIBUTES
40 simde_float32x2x2_t
simde_vuzp_f32(simde_float32x2_t a,simde_float32x2_t b)41 simde_vuzp_f32(simde_float32x2_t a, simde_float32x2_t b) {
42 #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
43 return vuzp_f32(a, b);
44 #else
45 simde_float32x2x2_t r = { { simde_vuzp1_f32(a, b), simde_vuzp2_f32(a, b) } };
46 return r;
47 #endif
48 }
49 #if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
50 #undef vuzp_f32
51 #define vuzp_f32(a, b) simde_vuzp_f32((a), (b))
52 #endif
53
54 SIMDE_FUNCTION_ATTRIBUTES
55 simde_int8x8x2_t
simde_vuzp_s8(simde_int8x8_t a,simde_int8x8_t b)56 simde_vuzp_s8(simde_int8x8_t a, simde_int8x8_t b) {
57 #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
58 return vuzp_s8(a, b);
59 #else
60 simde_int8x8x2_t r = { { simde_vuzp1_s8(a, b), simde_vuzp2_s8(a, b) } };
61 return r;
62 #endif
63 }
64 #if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
65 #undef vuzp_s8
66 #define vuzp_s8(a, b) simde_vuzp_s8((a), (b))
67 #endif
68
69 SIMDE_FUNCTION_ATTRIBUTES
70 simde_int16x4x2_t
simde_vuzp_s16(simde_int16x4_t a,simde_int16x4_t b)71 simde_vuzp_s16(simde_int16x4_t a, simde_int16x4_t b) {
72 #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
73 return vuzp_s16(a, b);
74 #else
75 simde_int16x4x2_t r = { { simde_vuzp1_s16(a, b), simde_vuzp2_s16(a, b) } };
76 return r;
77 #endif
78 }
79 #if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
80 #undef vuzp_s16
81 #define vuzp_s16(a, b) simde_vuzp_s16((a), (b))
82 #endif
83
84 SIMDE_FUNCTION_ATTRIBUTES
85 simde_int32x2x2_t
simde_vuzp_s32(simde_int32x2_t a,simde_int32x2_t b)86 simde_vuzp_s32(simde_int32x2_t a, simde_int32x2_t b) {
87 #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
88 return vuzp_s32(a, b);
89 #else
90 simde_int32x2x2_t r = { { simde_vuzp1_s32(a, b), simde_vuzp2_s32(a, b) } };
91 return r;
92 #endif
93 }
94 #if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
95 #undef vuzp_s32
96 #define vuzp_s32(a, b) simde_vuzp_s32((a), (b))
97 #endif
98
99 SIMDE_FUNCTION_ATTRIBUTES
100 simde_uint8x8x2_t
simde_vuzp_u8(simde_uint8x8_t a,simde_uint8x8_t b)101 simde_vuzp_u8(simde_uint8x8_t a, simde_uint8x8_t b) {
102 #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
103 return vuzp_u8(a, b);
104 #else
105 simde_uint8x8x2_t r = { { simde_vuzp1_u8(a, b), simde_vuzp2_u8(a, b) } };
106 return r;
107 #endif
108 }
109 #if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
110 #undef vuzp_u8
111 #define vuzp_u8(a, b) simde_vuzp_u8((a), (b))
112 #endif
113
114 SIMDE_FUNCTION_ATTRIBUTES
115 simde_uint16x4x2_t
simde_vuzp_u16(simde_uint16x4_t a,simde_uint16x4_t b)116 simde_vuzp_u16(simde_uint16x4_t a, simde_uint16x4_t b) {
117 #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
118 return vuzp_u16(a, b);
119 #else
120 simde_uint16x4x2_t r = { { simde_vuzp1_u16(a, b), simde_vuzp2_u16(a, b) } };
121 return r;
122 #endif
123 }
124 #if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
125 #undef vuzp_u16
126 #define vuzp_u16(a, b) simde_vuzp_u16((a), (b))
127 #endif
128
129 SIMDE_FUNCTION_ATTRIBUTES
130 simde_uint32x2x2_t
simde_vuzp_u32(simde_uint32x2_t a,simde_uint32x2_t b)131 simde_vuzp_u32(simde_uint32x2_t a, simde_uint32x2_t b) {
132 #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
133 return vuzp_u32(a, b);
134 #else
135 simde_uint32x2x2_t r = { { simde_vuzp1_u32(a, b), simde_vuzp2_u32(a, b) } };
136 return r;
137 #endif
138 }
139 #if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
140 #undef vuzp_u32
141 #define vuzp_u32(a, b) simde_vuzp_u32((a), (b))
142 #endif
143
144 SIMDE_FUNCTION_ATTRIBUTES
145 simde_float32x4x2_t
simde_vuzpq_f32(simde_float32x4_t a,simde_float32x4_t b)146 simde_vuzpq_f32(simde_float32x4_t a, simde_float32x4_t b) {
147 #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
148 return vuzpq_f32(a, b);
149 #else
150 simde_float32x4x2_t r = { { simde_vuzp1q_f32(a, b), simde_vuzp2q_f32(a, b) } };
151 return r;
152 #endif
153 }
154 #if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
155 #undef vuzpq_f32
156 #define vuzpq_f32(a, b) simde_vuzpq_f32((a), (b))
157 #endif
158
159 SIMDE_FUNCTION_ATTRIBUTES
160 simde_int8x16x2_t
simde_vuzpq_s8(simde_int8x16_t a,simde_int8x16_t b)161 simde_vuzpq_s8(simde_int8x16_t a, simde_int8x16_t b) {
162 #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
163 return vuzpq_s8(a, b);
164 #else
165 simde_int8x16x2_t r = { { simde_vuzp1q_s8(a, b), simde_vuzp2q_s8(a, b) } };
166 return r;
167 #endif
168 }
169 #if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
170 #undef vuzpq_s8
171 #define vuzpq_s8(a, b) simde_vuzpq_s8((a), (b))
172 #endif
173
174 SIMDE_FUNCTION_ATTRIBUTES
175 simde_int16x8x2_t
simde_vuzpq_s16(simde_int16x8_t a,simde_int16x8_t b)176 simde_vuzpq_s16(simde_int16x8_t a, simde_int16x8_t b) {
177 #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
178 return vuzpq_s16(a, b);
179 #else
180 simde_int16x8x2_t r = { { simde_vuzp1q_s16(a, b), simde_vuzp2q_s16(a, b) } };
181 return r;
182 #endif
183 }
184 #if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
185 #undef vuzpq_s16
186 #define vuzpq_s16(a, b) simde_vuzpq_s16((a), (b))
187 #endif
188
189 SIMDE_FUNCTION_ATTRIBUTES
190 simde_int32x4x2_t
simde_vuzpq_s32(simde_int32x4_t a,simde_int32x4_t b)191 simde_vuzpq_s32(simde_int32x4_t a, simde_int32x4_t b) {
192 #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
193 return vuzpq_s32(a, b);
194 #else
195 simde_int32x4x2_t r = { { simde_vuzp1q_s32(a, b), simde_vuzp2q_s32(a, b) } };
196 return r;
197 #endif
198 }
199 #if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
200 #undef vuzpq_s32
201 #define vuzpq_s32(a, b) simde_vuzpq_s32((a), (b))
202 #endif
203
204 SIMDE_FUNCTION_ATTRIBUTES
205 simde_uint8x16x2_t
simde_vuzpq_u8(simde_uint8x16_t a,simde_uint8x16_t b)206 simde_vuzpq_u8(simde_uint8x16_t a, simde_uint8x16_t b) {
207 #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
208 return vuzpq_u8(a, b);
209 #else
210 simde_uint8x16x2_t r = { { simde_vuzp1q_u8(a, b), simde_vuzp2q_u8(a, b) } };
211 return r;
212 #endif
213 }
214 #if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
215 #undef vuzpq_u8
216 #define vuzpq_u8(a, b) simde_vuzpq_u8((a), (b))
217 #endif
218
219 SIMDE_FUNCTION_ATTRIBUTES
220 simde_uint16x8x2_t
simde_vuzpq_u16(simde_uint16x8_t a,simde_uint16x8_t b)221 simde_vuzpq_u16(simde_uint16x8_t a, simde_uint16x8_t b) {
222 #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
223 return vuzpq_u16(a, b);
224 #else
225 simde_uint16x8x2_t r = { { simde_vuzp1q_u16(a, b), simde_vuzp2q_u16(a, b) } };
226 return r;
227 #endif
228 }
229 #if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
230 #undef vuzpq_u16
231 #define vuzpq_u16(a, b) simde_vuzpq_u16((a), (b))
232 #endif
233
234 SIMDE_FUNCTION_ATTRIBUTES
235 simde_uint32x4x2_t
simde_vuzpq_u32(simde_uint32x4_t a,simde_uint32x4_t b)236 simde_vuzpq_u32(simde_uint32x4_t a, simde_uint32x4_t b) {
237 #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
238 return vuzpq_u32(a, b);
239 #else
240 simde_uint32x4x2_t r = { { simde_vuzp1q_u32(a, b), simde_vuzp2q_u32(a, b) } };
241 return r;
242 #endif
243 }
244 #if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
245 #undef vuzpq_u32
246 #define vuzpq_u32(a, b) simde_vuzpq_u32((a), (b))
247 #endif
248
249 SIMDE_END_DECLS_
250 HEDLEY_DIAGNOSTIC_POP
251
252 #endif /* !defined(SIMDE_ARM_NEON_UZP_H) */
253