1; CRIS CPU description. -*- Scheme -*- 2; 3; Copyright 2003, 2004 Free Software Foundation, Inc. 4; 5; Contributed by Axis Communications AB. 6; 7; This file is part of the GNU Binutils. 8; 9; This program is free software; you can redistribute it and/or modify 10; it under the terms of the GNU General Public License as published by 11; the Free Software Foundation; either version 2 of the License, or 12; (at your option) any later version. 13; 14; This program is distributed in the hope that it will be useful, 15; but WITHOUT ANY WARRANTY; without even the implied warranty of 16; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17; GNU General Public License for more details. 18; 19; You should have received a copy of the GNU General Public License 20; along with this program; if not, write to the Free Software 21; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 22 23(include "simplify.inc") 24 25;;;;;;;;;;;;;;;;;; -pmacro (generic ones) 26 27(define-pmacro (.car2 l) (.apply (.pmacro (a b) a) l)) 28(define-pmacro (.cadr2 l) (.apply (.pmacro (a b) b) l)) 29(define-pmacro (SI-ext x) "How to sign-extend a dword to dword (a nop)" x) 30(define-pmacro (HI-ext x) "How to sign-extend a word to dword" (ext SI x)) 31(define-pmacro (QI-ext x) "How to sign-extend a byte to dword" (ext SI x)) 32(define-pmacro (SI-zext x) "How to zero-extend a dword to dword (a nop)" x) 33(define-pmacro (HI-zext x) "How to zero-extend a word to dword" (zext SI x)) 34(define-pmacro (QI-zext x) "How to zero-extend a byte to dword" (zext SI x)) 35(define-pmacro 36 (define-pmacro-map x) 37 "On a list ((x0 y0) .. (xN yN)), 0 <= m <= N, (define-pmacro xm ym)" 38 (.splice 39 begin 40 (.unsplice 41 (.map 42 (.pmacro (l) (.apply (.pmacro (xm ym) (define-pmacro xm ym)) l)) x))) 43) 44 45;;;;;;;;;;;;;;;;;; -arch -isa -cpu -model 46 47(define-arch 48 (name cris) 49 (comment "Axis Communications CRIS") 50 (default-alignment unaligned) 51 (insn-lsb0? #t) 52 (machs crisv0 crisv3 crisv8 crisv10 crisv32) 53 (isas cris) 54) 55 56(define-isa 57 (name cris) 58 (base-insn-bitsize 16) 59 (liw-insns 1) 60 (parallel-insns 1) 61) 62 63(define-pmacro 64 (define-cpu-cris x-suffix x-comment) 65 "Define a CRIS CPU family" 66 (define-cpu 67 (name (.sym cris x-suffix f)) 68 (comment x-comment) 69 (endian little) 70 ; CGEN-FIXME: Should be deduced from the default? 71 (word-bitsize 32) 72 (file-transform (.str x-suffix)) 73 ) 74) 75 76; Useful when there's a need to iterate over all models. 77(define-pmacro (cris-cpu-model-numbers) 78 "List of CRIS CPU model numbers (version register contents)" 79 (0 3 8 10 32) 80) 81 82(define-pmacro (cris-cpu-models) 83 "List of CRIS CPU model names" 84 (.map (.pmacro (n) (.sym v n)) (cris-cpu-model-numbers)) 85) 86 87; Mapping from model name to number. 88(define-pmacro-map 89 (.map (.pmacro (n) ((.sym v n -number) n)) 90 (cris-cpu-model-numbers))) 91 92; FIXME: Rationalize these rules. 93; CPU names must be distinct from the architecture name and machine names. 94; The "b" suffix stands for "base" and is the convention. 95; The "f" suffix stands for "family" and is the convention. 96; We ignore the "b" convention, partly because v0 isn't really a "base", at 97; least not for some aspects of v32. 98(define-cpu-cris v0 "CRIS base family") 99(define-cpu-cris v3 "CRIS v3 family") 100(define-cpu-cris v8 "CRIS v8 family") 101(define-cpu-cris v10 "CRIS v10 family") 102(define-cpu-cris v32 "CRIS v32 family") 103 104(define-pmacro MACH-PRE-V32 (MACH crisv0,crisv3,crisv8,crisv10)) 105(define-pmacro MACH-V3-UP (MACH crisv3,crisv8,crisv10,crisv32)) 106(define-pmacro MACH-V32 (MACH crisv32)) 107(define-pmacro MACH-PC MACH-PRE-V32) 108(define-pmacro MACH-ACR MACH-V32) 109(define-pmacro MACH-BRANCH-OFFSET-AT-INSN MACH-V32) 110(define-pmacro MACH-BRANCH-OFFSET-AFTER-INSN MACH-PRE-V32) 111 112(define-pmacro 113 current-mach-is-v32 114 "Whether the generated code is for V32. See comment at h-v32." 115 (reg h-v32) 116) 117 118(define-pmacro (define-mach-cris x-suffix x-comment x-name) 119 "Define a CRIS mach" 120 (define-mach 121 (name (.sym cris x-suffix)) 122 ; They're all called "cris" in bfd. Watch out for breakages for some 123 ; uses. 124 (bfd-name x-name) 125 (comment x-comment) 126 (cpu (.sym cris x-suffix f))) 127) 128 129(define-mach-cris v0 "Generic CRIS v0 CPU, ETRAX 1 .. 3" "cris") 130(define-mach-cris v3 "Generic CRIS v3 CPU, ETRAX 4" "cris") 131(define-mach-cris v8 "Generic CRIS v8 CPU, ETRAX 100" "cris") 132(define-mach-cris v10 "Generic CRIS v10 CPU, ETRAX 100 LX" "cris") 133(define-mach-cris v32 "Generic CRIS v32 CPU, ETRAX FS" "crisv32") 134 135(define-pmacro (define-model-simplecris x-name x-comment) 136 "Define a simple CRIS model" 137 (define-model 138 (name (.sym cris x-name)) 139 (comment x-comment) 140 (mach (.sym cris x-name)) 141 142 (unit u-exec "Execution Unit" () 1 1 () () () ()) 143 (unit u-mem "Memory Unit" () 1 1 () () () ()) 144 145 (unit u-const16 "Fetch 16-bit operand" () 1 1 () () () ()) 146 (unit u-const32 "Fetch 32-bit operand" () 1 1 147 () () () ()) 148 ; Used in special-case insn, for example arithmetic with PC destination. 149 (unit u-stall "Stall unit" () 1 1 () () () ()) 150 (unit u-skip4 "Skip 4 bytes" () 1 1 () () () ()) 151 (unit u-multiply "Multiply Unit" () 1 1 ((MACH crisv10)) () () ()) 152 (unit u-movem "Movem Unit" () 1 1 () 153 ((Rd INT -1)) 154 () ())) 155) 156 157(define-model-simplecris v0 "Model of CRIS v0, ETRAX 1 .. 3") 158(define-model-simplecris v3 "Model of CRIS v3, ETRAX 4") 159(define-model-simplecris v8 "Model of CRIS v8, ETRAX 100") 160(define-model-simplecris v10 "Model of CRIS v10, ETRAX 100 LX") 161 162; For some reason, we get an error: 163; Generating arch.h ... 164; ERROR: In procedure vector-ref: 165; ERROR: Wrong type argument in position 1: () 166; if we include timings for machs that we don't generate sims for. 167; Last checked: CVS as of 2004-11-18. 168; CGEN-FIXME: Looks like another CGEN bug. When it's fixed (or when 169; generating sims for v0, v3 or v8), add 0, 3 and 8 to 170; simplecris-timing-models. But before that, simplecris-timing-x has to 171; be rewritten to work on a multiple-element-list, not assume a single 172; element. (A change which seems likely to depend on lexical scoping for 173; macros to be introduced: try the obvious implementation.) 174(define-pmacro simplecris-timing-models (10)) 175(define-pmacro (simplecris-common-timing x-units) 176 "Make timing models, using x-units for all simplecris-timing-models" 177 ; CGEN-FIXME: Another CGEN bug: the part (.unsplice (10)) will remain 178 ; unexpanded in (.sym crisv (.unsplice (10)) if we write this as 179 ; ((.splice (.sym crisv (.unsplice simplecris-timing-models)) 180 ; (.unsplice x-units))) 181 ((.splice (.sym crisv (.apply (.pmacro (x) x) simplecris-timing-models)) 182 (.unsplice x-units))) 183) 184 185(define-pmacro-map 186 ( 187 ; Timing for memory instructions running on a simple cris model. 188 ((simplecris-mem-timing) (simplecris-common-timing 189 ((unit u-mem) (unit u-exec)))) 190 ; Timing for movem instructions running on a simple cris model. 191 ((simplecris-movem-timing) (simplecris-common-timing 192 ((unit u-movem) (unit u-exec)))) 193 ; Similar, for an 8- or 16-bit constant ([PC+]) operand. 194 ((simplecris-const-timing-HI) 195 (simplecris-common-timing 196 ((unit u-const16) (unit u-exec)))) 197 ; Similar, for a 32-bit constant ([PC+]) operand. 198 ((simplecris-const-timing-SI) 199 (simplecris-common-timing 200 ((unit u-const32) (unit u-exec)))) 201 ; Similar, no particular operand. 202 ((simplecris-timing) (simplecris-common-timing 203 ((unit u-exec))))) 204) 205 206(define-model 207 (name crisv32) 208 (comment "Model of CRISv32") 209 (mach crisv32) 210 211 (state 212 ; Bitmask of h-gr register (0..15) and h-sr register (17..31) 213 ; modified by 3rd previous insn, updated by the u-exec unit. 214 ; Because there's no need to mark writes to special registers BZ and 215 ; WZ, bit 16 is for jump mark and bit 20 for memory-write mark. 216 (prev-prev-prev-modf-regs UINT) 217 218 ; Ditto for the 2nd previous insn. 219 (prev-prev-modf-regs UINT) 220 221 ; Ditto for the previous insn. 222 (prev-modf-regs UINT) 223 224 ; Bit-mask for regs modified by the current insn, propagated to 225 ; prev-modf-regs. 226 (modf-regs UINT) 227 228 ; Registers loaded by movem are not forwarded to the execution 229 ; stage, so we need to insert stall-cycles for ordinary insns 230 ; accessing such registers. In addition to the *modf-regs 231 ; above, these are set to tell *ordinary* insns which registers 232 ; are inaccessible. 233 234 (prev-prev-prev-movem-dest-regs UINT) 235 236 ; Ditto for the 2nd previous insn. 237 (prev-prev-movem-dest-regs UINT) 238 239 ; Ditto for the previous insn. 240 (prev-movem-dest-regs UINT) 241 242 ; Bit-mask for regs modified by the current insn, propagated to 243 ; prev-movem-dest-regs. 244 (movem-dest-regs UINT)) 245 246 ; It seems this pipeline description isn't used at all; this is just 247 ; for show. 248 ; Noteworthy is the placement of the memory stage before the execute stage. 249 (pipeline all "" () ((fetch) (decode) (memory) (execute) (writeback))) 250 251 ; Units that contribute only a constant pipeline delay are not included. 252 (unit u-mem "Memory Unit" () 1 1 () 253 ((Rs INT -1)) 254 () ()) 255 256 ; Artificial units for read/write-related hazard accounting. 257 (unit u-mem-r "Memory Unit Read" () 1 1 () () () ()) 258 (unit u-mem-w "Memory Unit Write" () 1 1 () () () ()) 259 260 (unit u-movem-rtom "Movem-to-memory Unit" () 1 1 () 261 ((Rs INT -1) (Rd INT -1)) 262 () ()) 263 (unit u-movem-mtor "Movem-to-register Unit" () 1 1 () 264 ((Rs INT -1) (Rd INT -1)) 265 () ()) 266 (unit u-multiply "Multiply Unit" () 1 1 () 267 ((Rs INT -1) (Rd INT -1)) 268 () ()) 269 (unit u-branch "Branch Unit" () 1 1 () 270 () 271 () ()) 272 (unit u-jump-r "Jump-to-register Unit" () 1 1 () 273 ((Rs INT -1)) 274 () ()) 275 (unit u-jump-sr "Jump-to-special-register Unit" () 1 1 () 276 ((Ps INT -1)) 277 () ()) 278 (unit u-jump "JAS/BAS Unit, saving PC" () 1 1 () 279 () 280 ((Pd INT -1)) ()) 281 282 ; To keep track of PC; not really functional units. 283 (unit u-const16 "Fetch 16-bit operand" () 1 1 () () () ()) 284 (unit u-const32 "Fetch 32-bit operand" () 1 1 () () () ()) 285 (unit u-skip4 "Skip 4 bytes" () 1 1 () () () ()) 286 287 ; For v32, we need to keep track of inputs (for movem destination 288 ; cycle penalties) and output (for e.g. memory source and jump 289 ; source cycle penalties). 290 (unit u-exec "Execution Unit" () 1 1 () 291 ((Rd INT -1) (Rs INT -1)) 292 ((Rd INT -1)) 293 ()) 294 295 ; Special case of u-exec for movem: don't treat Rd as an incoming 296 ; parameter. 297 (unit u-exec-movem "Execution Unit" () 1 1 () 298 ((Rs INT -1)) 299 ((Rd INT -1)) 300 ()) 301 302 ; Special case of u-exec when the destination is a special 303 ; register. 304 (unit u-exec-to-sr "Execution Unit" () 1 1 () 305 ((Rs INT -1)) 306 ((Pd INT -1)) ()) 307) 308 309(define-pmacro (crisv32-timing-destreg d) 310 "Timing for instructions running on a crisv32 model" 311 ((crisv32 312 (.splice unit u-exec (.unsplice d)))) 313) 314(define-pmacro (crisv32-timing) (crisv32-timing-destreg ())) 315 316(define-pmacro (cris-timing-Rd-sfield) 317 (crisv32-timing-destreg ((out Rd Rd-sfield))) 318) 319 320(define-pmacro (crisv32-timing-c-HI) 321 ((crisv32 (unit u-const16) (unit u-exec))) 322) 323 324(define-pmacro-map 325 ((crisv32-timing-c-QI crisv32-timing-c-HI) 326 ((crisv32-timing-c-SI) ((crisv32 (unit u-const32) (unit u-exec)))) 327 ((crisv32-timing-c-sr-SI) ((crisv32 (unit u-const32) (unit u-exec-to-sr)))) 328 ((crisv32-reg-sr-timing) ((crisv32 (unit u-exec-to-sr)))) 329 ((crisv32-mem-sr-timing) 330 ((crisv32 (unit u-mem) (unit u-mem-r) (unit u-exec-to-sr)))) 331 ((crisv32-mem-timing) ((crisv32 (unit u-mem) (unit u-mem-r) (unit u-exec)))) 332 ((crisv32-mem-write-timing) ((crisv32 (unit u-mem) (unit u-exec) (unit u-mem-w))))) 333) 334 335(define-pmacro-map 336 ( 337 ; Timing for instructions using memory operands. 338 ((cris-mem-timing) (.splice (.unsplice (simplecris-mem-timing)) 339 (.unsplice (crisv32-mem-timing)))) 340 ; Timing for instructions using memory operands. 341 ((cris-mem-write-timing) (.splice 342 (.unsplice (simplecris-mem-timing)) 343 (.unsplice (crisv32-mem-write-timing)))) 344 ; Timing for moves from general register to special register. 345 ((cris-reg-sr-timing) (.splice (.unsplice (simplecris-timing)) 346 (.unsplice (crisv32-reg-sr-timing)))) 347 ; Timing for moves from memory to special register. 348 ((cris-mem-sr-timing) (.splice (.unsplice (simplecris-mem-timing)) 349 (.unsplice (crisv32-mem-sr-timing)))) 350 ; Timing for non-mul, non-memory, non-special-register, 16-bit instructions. 351 ((cris-timing) (.splice (.unsplice (simplecris-timing)) 352 (.unsplice (crisv32-timing)))) 353 ; Timing for instructions with 8- or 16-bit constant operand ([PC+]). 354 ((cris-timing-const-HI) (.splice 355 (.unsplice (simplecris-const-timing-HI)) 356 (.unsplice (crisv32-timing-c-HI)))) 357 ; Timing for instructions with a 32-bit constant operand ([PC+]). 358 ((cris-timing-const-SI) (.splice 359 (.unsplice (simplecris-const-timing-SI)) 360 (.unsplice (crisv32-timing-c-SI)))) 361 ; Like cris-timing-const-SI, but destination special register. 362 ((cris-timing-const-sr-SI) (.splice 363 (.unsplice (simplecris-const-timing-SI)) 364 (.unsplice (crisv32-timing-c-sr-SI)))) 365 ; Like cris-timing-const-HI, but destination special register. 366 ((cris-timing-const-sr-HI) (.splice 367 (.unsplice (simplecris-const-timing-HI)) 368 (.unsplice (crisv32-timing-c-sr-SI))))) 369) 370 371(define-pmacro cris-timing-const-QI cris-timing-const-HI) 372(define-pmacro cris-timing-const-sr-QI cris-timing-const-sr-HI) 373 374(define-pmacro (simplecris-common-specregs) 375 "The common special registers in pre-v32 models." 376 ((QI 0) (QI 1) (HI 4) (HI 5) 377 (SI 8) (SI 9) (SI 10) (SI 11) (SI 12) (SI 13)) 378) 379 380(define-pmacro (cris-implemented-specregs-v0) 381 "Special registers in v0 and their sizes" 382 (.splice (.unsplice (simplecris-common-specregs)) (HI 6) (HI 7)) 383) 384(define-pmacro 385 cris-implemented-specregs-const-v0 386 cris-implemented-specregs-v0 387) 388 389(define-pmacro (cris-implemented-specregs-v3) 390 "Special registers in v3 and their sizes" 391 (.splice (.unsplice (cris-implemented-specregs-v0)) (SI 14)) 392) 393(define-pmacro 394 cris-implemented-specregs-const-v3 395 cris-implemented-specregs-v3 396) 397 398(define-pmacro (cris-implemented-specregs-v8) 399 "Special registers in v8 and their sizes" 400 (.splice (.unsplice (simplecris-common-specregs)) (SI 14)) 401) 402(define-pmacro 403 cris-implemented-specregs-const-v8 404 cris-implemented-specregs-v8 405) 406 407(define-pmacro (cris-implemented-specregs-v10) 408 "Special registers in v10 and their sizes" 409 (.splice (.unsplice (simplecris-common-specregs)) (SI 7) (SI 14) (SI 15)) 410) 411(define-pmacro 412 cris-implemented-specregs-const-v10 413 cris-implemented-specregs-v10 414) 415 416(define-pmacro (cris-implemented-specregs-v32) 417 "Special registers in v32 and their sizes" 418 ((QI 0) (QI 1) (QI 2) (QI 3) (HI 4) 419 (SI 5) (SI 6) (SI 7) (SI 8) (SI 9) 420 (SI 10) (SI 11) (SI 12) (SI 13) (SI 14) (SI 15)) 421) 422; For v32, all special register operations on constants (that is, 423; move) take 32-bit operands, not the real size of the register, as in 424; other move operations. 425(define-pmacro (cris-implemented-specregs-const-v32) 426 (.map (.pmacro (regno) (SI regno)) (.iota 16)) 427) 428 429(define-pmacro cris-swap-codes 430 "CRIS Swap codes in numeric order (no zero)" 431 ( r b br w wr wb wbr 432 n nr nb nbr nw nwr nwb nwbr) 433) 434 435(define-pmacro cris-flagnames 436 "CRIS flag field values, dest and src fields concatenated" 437 (c v z n x i u p) ; ... b m for pre-v32 438) 439 440(define-pmacro-map 441 ; Bitnumber for each respective flag. 442 (.map (.pmacro (x num) ((.sym x -bitnumber) num)) 443 cris-flagnames (.iota 8)) 444) 445 446; I give up. Here's a perl-script to get the values I want for this macro 447; (not working along list principles, though). You can run this region. 448; perl -e '$x = "cvznxiup"; for ($i = 0; $i < 256; $i++) { $s = ""; 449; for ($j = 0; $j < 8; $j++) { if ($i & (1 << $j)) { 450; $s .= substr ($x, $j, 1);}} 451; printf ("%s%s", $s eq "" ? "_" : $s, (($i + 1) % 8) == 0 ? "\n " : " "); }' 452(define-pmacro cris-flag-combinations 453 "Combinations of flags in numeric order" 454 (_ c v cv z cz vz cvz 455 n cn vn cvn zn czn vzn cvzn 456 x cx vx cvx zx czx vzx cvzx 457 nx cnx vnx cvnx znx cznx vznx cvznx 458 i ci vi cvi zi czi vzi cvzi 459 ni cni vni cvni zni czni vzni cvzni 460 xi cxi vxi cvxi zxi czxi vzxi cvzxi 461 nxi cnxi vnxi cvnxi znxi cznxi vznxi cvznxi 462 u cu vu cvu zu czu vzu cvzu 463 nu cnu vnu cvnu znu cznu vznu cvznu 464 xu cxu vxu cvxu zxu czxu vzxu cvzxu 465 nxu cnxu vnxu cvnxu znxu cznxu vznxu cvznxu 466 iu ciu viu cviu ziu cziu vziu cvziu 467 niu cniu vniu cvniu zniu czniu vzniu cvzniu 468 xiu cxiu vxiu cvxiu zxiu czxiu vzxiu cvzxiu 469 nxiu cnxiu vnxiu cvnxiu znxiu cznxiu vznxiu cvznxiu 470 p cp vp cvp zp czp vzp cvzp 471 np cnp vnp cvnp znp cznp vznp cvznp 472 xp cxp vxp cvxp zxp czxp vzxp cvzxp 473 nxp cnxp vnxp cvnxp znxp cznxp vznxp cvznxp 474 ip cip vip cvip zip czip vzip cvzip 475 nip cnip vnip cvnip znip cznip vznip cvznip 476 xip cxip vxip cvxip zxip czxip vzxip cvzxip 477 nxip cnxip vnxip cvnxip znxip cznxip vznxip cvznxip 478 up cup vup cvup zup czup vzup cvzup 479 nup cnup vnup cvnup znup cznup vznup cvznup 480 xup cxup vxup cvxup zxup czxup vzxup cvzxup 481 nxup cnxup vnxup cvnxup znxup cznxup vznxup cvznxup 482 iup ciup viup cviup ziup cziup vziup cvziup 483 niup cniup vniup cvniup zniup czniup vzniup cvzniup 484 xiup cxiup vxiup cvxiup zxiup czxiup vzxiup cvzxiup 485 nxiup cnxiup vnxiup cvnxiup znxiup cznxiup vznxiup cvznxiup 486 ) 487) 488 489(define-pmacro cc-condition (not cbit)) 490(define-pmacro cs-condition cbit) 491(define-pmacro ne-condition (not zbit)) 492(define-pmacro eq-condition zbit) 493(define-pmacro vc-condition (not vbit)) 494(define-pmacro vs-condition vbit) 495(define-pmacro pl-condition (not nbit)) 496(define-pmacro mi-condition nbit) 497(define-pmacro ls-condition (or cbit zbit)) 498(define-pmacro hi-condition (not (or cbit zbit))) 499(define-pmacro ge-condition (not (xor vbit nbit))) 500(define-pmacro lt-condition (xor vbit nbit)) 501(define-pmacro gt-condition (not (or (xor vbit nbit) zbit))) 502(define-pmacro le-condition (or (xor vbit nbit) zbit)) 503(define-pmacro a-condition 1) 504 505; FIXME: define this properly for v10 and pre-v10. 506(define-pmacro wf-condition pbit) 507 508(define-pmacro (cris-condition condno) 509 "Return condition state for condition number CONDNO" 510 (sequence 511 BI 512 ((SI tmpcond) (BI condres)) 513 (set tmpcond condno) 514 (.splice 515 cond 516 (.unsplice 517 (.map 518 (.pmacro 519 (condn condc) 520 ((eq tmpcond condn) (set condres (.sym condc -condition)))) 521 (.iota 16) 522 cris-condition-codes))) 523 condres) 524) 525 526;;;;;;;;;;;;;;;;;; -keyword 527 528; General registers. 529(define-pmacro (cris-general-gregs) 530 (.splice (SP 14) (.unsplice (.map (.pmacro (n) ((.sym R n) n)) (.iota 15)))) 531) 532 533; Can't keep more than one gr-names definition at the same time; 534; generated enum declarations in sim/cris/cris-desc.h will collide. 535; FIXME: (include "different-mach-parts") 536 537(define-keyword 538 (name gr-names-pcreg) 539 (attrs MACH-PC) 540 (print-name h-gr-real-pc) 541 ; Put PC first so it is preferred over r15. 542 (.splice values (PC 15) (.unsplice (cris-general-gregs))) 543) 544 545(define-keyword 546 (name gr-names-acr) 547 (attrs MACH-ACR) 548 ; The print-name directive will control the enum prefix. With the 549 ; arguably more appropriate h-gr-v32 or h-gr-acr, we'd get names like 550 ; H_GR_ACR_R0 instead of H_GR_R0. Since we have to choose something for 551 ; unprefixed names, we use the CRISv32 names. FIXME: All users should 552 ; change to use H_GR_V32_R0 (etc.), then change this to h-gr-v32. 553 (print-name h-gr) 554 ; Put ACR first so it is preferred over r15. 555 (.splice values (ACR 15) (.unsplice (cris-general-gregs))) 556) 557 558(define-keyword 559 (name gr-names-v32) 560 (attrs MACH-V32) 561 ; In preparation for implementing the FIXME above. 562 (print-name h-gr-v32) 563 ; Put ACR first so it is preferred over r15. 564 (.splice values (ACR 15) (.unsplice (cris-general-gregs))) 565) 566 567; Special registers with names common to all. 568(define-pmacro (cris-general-pregs) 569 (.splice 570 (VR 1) 571 (SRP 11) 572 (.unsplice (.map (.pmacro (n) ((.sym P n) n)) (.iota 15)))) 573) 574 575(define-keyword 576 (name p-names-v10) 577 (attrs MACH-PRE-V32) 578 (print-name h-sr-pre-v32) 579 (.splice 580 values 581 (CCR 5) 582 (MOF 7) 583 (IBR 9) 584 (IRP 10) 585 (BAR 12) 586 (DCCR 13) 587 (BRP 14) 588 (USP 15) 589 (.unsplice (cris-general-pregs))) 590) 591 592(define-keyword 593 (name p-names-v32) 594 (attrs MACH-V32) 595 ; See comment for gr-names-acr. 596 (print-name h-sr) 597 (.splice 598 values 599 (BZ 0) 600 (PID 2) 601 (SRS 3) 602 (WZ 4) 603 (EXS 5) 604 (EDA 6) 605 (MOF 7) 606 (DZ 8) 607 (EBP 9) 608 (ERP 10) 609 (NRP 12) 610 (CCS 13) 611 (USP 14) 612 (SPC 15) 613 (.unsplice (cris-general-pregs))) 614) 615 616; Similarly as for h-gr-v32, in preparation. 617(define-keyword 618 (name p-names-v32-x) 619 (attrs MACH-V32) 620 ; See comment for gr-names-acr. 621 (print-name h-sr-v32) 622 (.splice 623 values 624 (BZ 0) 625 (PID 2) 626 (SRS 3) 627 (WZ 4) 628 (EXS 5) 629 (EDA 6) 630 (MOF 7) 631 (DZ 8) 632 (EBP 9) 633 (ERP 10) 634 (NRP 12) 635 (CCS 13) 636 (USP 14) 637 (SPC 15) 638 (.unsplice (cris-general-pregs))) 639) 640 641(define-pmacro p0 (reg h-sr 0)) 642(define-pmacro vr (reg h-sr 1)) 643(define-pmacro pid (reg h-sr 2)) 644(define-pmacro srs (reg h-sr 3)) 645(define-pmacro p4 (reg h-sr 4)) 646(define-pmacro ccr (reg h-sr 5)) 647(define-pmacro mof (reg h-sr 7)) 648(define-pmacro p8 (reg h-sr 8)) 649(define-pmacro ibr (reg h-sr 9)) 650(define-pmacro ebp (reg h-sr 9)) 651(define-pmacro erp (reg h-sr 10)) 652(define-pmacro srp (reg h-sr 11)) 653(define-pmacro ccs (reg h-sr 13)) 654(define-pmacro dccr (reg h-sr 13)) 655(define-pmacro usp (reg h-sr 14)) 656(define-pmacro spc (reg h-sr 15)) 657 658(define-pmacro sp (reg h-gr 14)) 659(define-pmacro acr (reg h-gr 15)) 660 661(define-pmacro cris-condition-codes 662 "CRIS condition codes in numeric order" 663 (cc cs ne eq vc vs pl mi ls hi ge lt gt le a wf) 664) 665 666; No use having different lists; this is the only CC that 667; differs between v10 and v32, and mostly in the name. 668(define-pmacro sb wf) 669 670 671;;;;;;;;;;;;;;;;;; -hardware 672 673;; Various constant generators. 674 675(define-hardware 676 (name h-inc) 677 (comment "autoincrement-bit syntax specifier") 678 (type immediate (UINT 1)) 679 (values keyword "" (("" 0) ("+" 1))) 680) 681 682(define-hardware 683 (name h-ccode) 684 (comment "Condition code specifier") 685 (type immediate (UINT 4)) 686 (values keyword "" 687 (.map (.pmacro (x y) ((.str x) y)) 688 cris-condition-codes (.iota 16))) 689) 690 691(define-hardware 692 (name h-swap) 693 (comment "Swap option specifier") 694 (type immediate (UINT 4)) 695 (values 696 keyword "" 697 (.splice 698 (" " 0) 699 (.unsplice 700 (.map 701 (.pmacro (x y) ((.str x) y)) cris-swap-codes (.iota 15 1))))) 702) 703 704(define-hardware 705 (name h-flagbits) 706 (comment "Flag bits specifier") 707 (type immediate (UINT 8)) 708 (values 709 keyword "" 710 (.map (.pmacro (x y) ((.str x) y)) cris-flag-combinations (.iota 256))) 711) 712 713; Apparently, the semantic-name isn't used for accessors, so external 714; users like the sim glue and SID sees the -v32 and -pre-v32 munged names. 715; Defining "dispatchers"; virtual registers whose getter and setter works 716; on the "real" mach variants, seems to help. CGEN-FIXME: Make 717; semantic-name set the generated names. 718(define-pmacro (cris-d-hwreg x-name x-type) 719 (define-hardware 720 (name x-name) 721 (comment (.str "Dispatcher for " x-name)) 722 (attrs VIRTUAL) 723 (type register x-type) 724 (get () (reg (.sym x-name -x))) 725 (set (val) (set (reg (.sym x-name -x)) val))) 726) 727(define-pmacro (cris-d-hwregf-a x-name x-type x-n x-attrs) 728 (define-hardware 729 (name x-name) 730 (comment (.str "Dispatcher for " x-name)) 731 (.splice attrs VIRTUAL (.unsplice x-attrs)) 732 (type register x-type (x-n)) 733 (get (index) (reg (.sym x-name -x) index)) 734 (set (index val) (set-quiet (reg (.sym x-name -x) index) val))) 735) 736(define-pmacro (cris-d-hwregf x-name x-type x-n) 737 (cris-d-hwregf-a x-name x-type x-n ()) 738) 739(define-pmacro (cris-d-hwregf-p x-name x-type x-n) 740 (cris-d-hwregf-a x-name x-type x-n (PROFILE)) 741) 742 743; At first glance we could use (eq-attr (current-mach) ...) for 744; everything, but that seems sometimes (always?) to yield false. For 745; ifields, it causes noncompilable C-code. For the insn semantics code, 746; it causes tests movei.ms and mulv32.ms to fail, apparently because the 747; current-mach-is-v32 usage in flags setting is miscompiled as 0 (or 748; rather, misgenerated). Instead we use different definitions of a 749; MACH-tagged virtual register yielding a constant, together with a 750; pmacro. CGEN-FIXME: If eq-attr is someday fixed, we could just remove 751; these h-v32 virtual register definitions and change the pmacro 752; definition for current-mach-is-v32. 753(define-hardware 754 (semantic-name h-v32) 755 (name h-v32-v32) 756 (attrs MACH-V32 VIRTUAL) 757 (type register BI) 758 (get () (const BI 1)) 759 (set (val) (error "Can't set h-v32")) 760) 761(define-hardware 762 (semantic-name h-v32) 763 (name h-v32-non-v32) 764 (attrs MACH-PRE-V32 VIRTUAL) 765 (type register BI) 766 (get () (const BI 0)) 767 (set (val) (error "Can't set h-v32")) 768) 769 770;; "Real" hardware. 771 772(define-hardware 773 (name h-pc) 774 (comment "program counter") 775 (attrs PC PROFILE) 776 (type pc) 777 ; There's no bit 0 in PC, so just ignore it when jumping etc. 778 (set (val) (set (raw-reg h-pc) (and val (inv 1)))) 779) 780 781; Note that setting register 15 isn't handled here, but in each insn, so 782; the proper "jump" attributes and other special stuff for speedy 783; execution can be present. 784(cris-d-hwregf-p h-gr SI 16) 785(define-hardware 786 (semantic-name h-gr-x) 787 (name h-gr-pc) 788 (attrs MACH-PC VIRTUAL) 789 (comment "General purpose registers, aborting on PC access") 790 (type register SI (16)) 791 (indices extern-keyword gr-names-pcreg) 792 (get 793 (index) 794 (if SI (eq index 15) 795 (error SI "General register read of PC is not implemented.") 796 (reg SI h-gr-real-pc index))) 797 (set 798 (index val) 799 (sequence 800 () 801 (if (eq index 15) 802 (error "General register write to PC is not implemented.")) 803 (set (reg SI h-gr-real-pc index) val))) 804) 805(define-hardware 806 (name h-gr-real-pc) 807 (attrs MACH-PC) 808 (comment "General purpose registers") 809 (type register SI (16)) 810 (indices extern-keyword gr-names-pcreg) 811) 812 813; We have to use a virtual register trick to get the "raw", unaccounted 814; contents of the global register; the raw-reg RTX only works for 815; non-virtual register files. 816(define-hardware 817 (semantic-name h-raw-gr) 818 (name h-raw-gr-pc) 819 (attrs MACH-PC VIRTUAL) 820 (comment "Unaccounted version of general purpose registers") 821 (type register SI (16)) 822 (get (index) (raw-reg h-gr-real-pc index)) 823 (set (index val) (set-quiet (raw-reg h-gr-real-pc index) val)) 824) 825(define-hardware 826 (semantic-name h-gr-x) 827 (name h-gr-acr) 828 (attrs MACH-ACR) 829 (comment "General purpose registers") 830 (type register SI (16)) 831 (indices extern-keyword gr-names-acr) 832) 833(define-hardware 834 (semantic-name h-raw-gr) 835 (name h-raw-gr-acr) 836 (attrs MACH-ACR VIRTUAL) 837 (comment "Unaccounted version of general purpose registers") 838 (type register SI (16)) 839 (get (index) (raw-reg h-gr-x index)) 840 (set (index val) (set-quiet (raw-reg h-gr-x index) val)) 841) 842 843; FIXME: get and set semantics? Unknown how to split semantics best; with 844; get/set semantics or within the insn specification. Doing the former for 845; now. Should use different names for pre-v10. 846; FIXME: No dccr for v0 and v3. Different high flag bits. 847(cris-d-hwregf-p h-sr SI 16) 848(define-pmacro 849 (cris-h-sr machver) 850 (define-hardware 851 (semantic-name h-sr-x) 852 (name (.sym h-sr-v machver)) 853 (attrs (MACH (.sym crisv machver))) 854 (comment (.str "Special registers for v" machver)) 855 (type register SI (16)) 856 (indices extern-keyword p-names-v10) 857 (get 858 (index) 859 (cond 860 SI 861 ((orif (orif (eq index (regno p0)) (eq index (regno p4))) 862 (eq index (regno p8))) 0) 863 ((eq index (regno vr)) machver) 864 ((orif (eq index (regno ccr)) 865 (eq index (regno dccr))) 866 ; Return "P U I X N Z V C" for the low 8 bits. 867 ; FIXME: More bits. 868 (or SI 869 (and SI (raw-reg SI h-sr-x (regno ccr)) #xffffff00) 870 (or 871 (zext SI (reg BI h-cbit)) 872 (or 873 (sll (zext SI (reg BI h-vbit)) 1) 874 (or 875 (sll (zext SI (reg BI h-zbit)) 2) 876 (or 877 (sll (zext SI (reg BI h-nbit)) 3) 878 (or 879 (sll (zext SI (reg BI h-xbit)) 4) 880 (or 881 (sll (zext SI (reg BI h-ibit)) 5) 882 (or 883 (sll (zext SI (reg BI h-ubit)) 6) 884 (or 885 (sll (zext SI (reg BI h-pbit)) 7) 886 0)))))))))) 887 (else (raw-reg SI h-sr-x index)))) 888 (set 889 (index val) 890 (cond 891 ((orif (orif (eq index (regno p0)) (eq index (regno p4))) 892 (orif (eq index (regno p8)) (eq index (regno vr)))) 893 (nop)) 894 ((orif (eq index (regno ccr)) (eq index (regno dccr))) 895 (sequence 896 () 897 (set (reg BI h-cbit) (if BI (ne SI (and val (sll 1 0)) 0) 1 0)) 898 (set (reg BI h-vbit) (if BI (ne SI (and val (sll 1 1)) 0) 1 0)) 899 (set (reg BI h-zbit) (if BI (ne SI (and val (sll 1 2)) 0) 1 0)) 900 (set (reg BI h-nbit) (if BI (ne SI (and val (sll 1 3)) 0) 1 0)) 901 (set (reg BI h-xbit) (if BI (ne SI (and val (sll 1 4)) 0) 1 0)) 902 (set (reg BI h-ibit) (if BI (ne SI (and val (sll 1 5)) 0) 1 0)) 903 (set (reg BI h-ubit) (if BI (ne SI (and val (sll 1 6)) 0) 1 0)) 904 (set (reg BI h-pbit) (if BI (ne SI (and val (sll 1 7)) 0) 1 0)) 905 (set-quiet (raw-reg SI h-sr-x (regno ccr)) val) 906 (set-quiet (raw-reg SI h-sr-x (regno dccr)) val))) 907 (else (set-quiet (raw-reg SI h-sr-x index) val))))) 908) 909 910(cris-h-sr 0) 911(cris-h-sr 3) 912(cris-h-sr 8) 913(cris-h-sr 10) 914 915(define-hardware 916 (semantic-name h-sr-x) 917 (name h-sr-v32) 918 (attrs MACH-V32) 919 (comment "Special registers for v32") 920 (type register SI (16)) 921 (indices extern-keyword p-names-v32) 922 923 (get 924 (index) 925 (cond 926 SI 927 ((orif (orif (eq index (regno p0)) (eq index (regno p4))) 928 (eq index (regno p8))) 0) 929 ((eq index (regno vr)) 32) 930 ((eq index (regno ccs)) 931 ; Return "S R P U I X N Z V C" for the low 10 bits. 932 (or SI 933 (and SI (raw-reg SI h-sr-x (regno ccs)) #x3ffffc00) 934 (or 935 (zext SI (reg BI h-cbit)) 936 (or 937 (sll (zext SI (reg BI h-vbit)) 1) 938 (or 939 (sll (zext SI (reg BI h-zbit)) 2) 940 (or 941 (sll (zext SI (reg BI h-nbit)) 3) 942 (or 943 (sll (zext SI (reg BI h-xbit)) 4) 944 (or 945 (sll (zext SI (reg BI h-ibit)) 5) 946 (or 947 (sll (zext SI (reg BI h-ubit)) 6) 948 (or 949 (sll (zext SI (reg BI h-pbit)) 7) 950 (or 951 (sll (zext SI (reg BI h-rbit)) 8) 952 (or 953 (sll (zext SI (reg BI h-sbit)) 9) 954 (or 955 (sll (zext SI (reg BI h-mbit)) 30) 956 (or 957 (sll (zext SI (reg BI h-qbit)) 31) 958 0)))))))))))))) 959 ((eq index (regno usp)) 960 ; In user mode, return general stack pointer. 961 (if BI (reg BI h-ubit) 962 (raw-reg SI h-gr-x (regno sp)) 963 (raw-reg SI h-sr-x (regno usp)))) 964 (else (raw-reg SI h-sr-x index)))) 965 966 (set 967 (index val) 968 (cond 969 ((orif (orif (eq index (regno p0)) (eq index (regno p4))) 970 (orif (eq index (regno p8)) (eq index (regno vr)))) 971 (nop)) 972 ((eq index (regno ccs)) 973 (sequence 974 () 975 ; Protected bits are handled as such in the respective setter function. 976 (set (reg BI h-cbit) (if BI (ne SI (and val (sll 1 0)) 0) 1 0)) 977 (set (reg BI h-vbit) (if BI (ne SI (and val (sll 1 1)) 0) 1 0)) 978 (set (reg BI h-zbit) (if BI (ne SI (and val (sll 1 2)) 0) 1 0)) 979 (set (reg BI h-nbit) (if BI (ne SI (and val (sll 1 3)) 0) 1 0)) 980 (set (reg BI h-xbit) (if BI (ne SI (and val (sll 1 4)) 0) 1 0)) 981 (set (reg BI h-ibit) (if BI (ne SI (and val (sll 1 5)) 0) 1 0)) 982 (set (reg BI h-sbit) (if BI (ne SI (and val (sll 1 9)) 0) 1 0)) 983 (set (reg BI h-mbit) (if BI (ne SI (and val (sll 1 30)) 0) 1 0)) 984 (set (reg BI h-pbit) (if BI (ne SI (and val (sll 1 7)) 0) 1 0)) 985 (set (reg BI h-rbit) (if BI (ne SI (and val (sll 1 8)) 0) 1 0)) 986 (set (reg BI h-qbit) (if BI (ne SI (and val (sll 1 31)) 0) 1 0)) 987 ; Set the U bit last, so the setter functions for the other bits 988 ; don't see it as set from this operation. It is not cleared from 989 ; this operation, so we don't have to handle that; it's only 990 ; cleared "manually" from within simulator-specific context-switch 991 ; machinery. 992 (set (reg BI h-ubit) (if BI (ne SI (and val (sll 1 6)) 0) 1 0)) 993 (set-quiet (raw-reg SI h-sr-x index) val))) 994 ((eq index (regno usp)) 995 ; In user mode, set general register 14 too, whenever setting USP. 996 (sequence 997 () 998 (if (reg BI h-ubit) (set (raw-reg SI h-gr-x (regno sp)) val)) 999 (set (raw-reg SI h-sr-x (regno usp)) val))) 1000 ((eq index (regno srs)) 1001 (if (not (reg BI h-ubit)) (set (raw-reg h-sr-x (regno srs)) val))) 1002 ((eq index (regno ebp)) 1003 (if (not (reg BI h-ubit)) (set (raw-reg h-sr-x (regno ebp)) val))) 1004 ((eq index (regno pid)) 1005 (if (not (reg BI h-ubit)) 1006 (sequence 1007 () 1008 (c-call VOID "@cpu@_write_pid_handler" val) 1009 (set (raw-reg h-sr-x (regno pid)) val)))) 1010 ((eq index (regno spc)) 1011 (if (not (reg BI h-ubit)) (set (raw-reg h-sr-x (regno spc)) val))) 1012 (else (set-quiet (raw-reg SI h-sr-x index) val)))) 1013) 1014 1015(define-hardware 1016 (name h-supr) 1017 (attrs MACH-V32 VIRTUAL) 1018 (comment "Support registers") 1019 (type register SI (16)) 1020 (values keyword "" (.map (.pmacro (y) ((.str S y) y)) (.iota 16))) 1021 (get (index) (c-call SI "@cpu@_read_supr" index)) 1022 (set (index val) (c-call VOID "@cpu@_write_supr" index val)) 1023) 1024 1025(define-pmacro (cris-dsh semantic-name name comment attrs type) 1026 "Like dsh, but the semantic-name is separate" 1027 (define-full-hardware 1028 name comment attrs semantic-name type () () () () () ()) 1029) 1030 1031; We define the condition codes that hold arithmetic flags separately 1032; and "or" them in, in the get and set methods of the special 1033; registers. We define arithmetic flags as any of C V Z N X. They 1034; thankfully have that order (zero-based) in all processor versions. 1035 1036; To avoid having two variants of most move-type instructions because V32 1037; doesn't set C and V (and N and Z), we fake the setting to virtual 1038; registers which have two different implementations. 1039(define-pmacro (cris-move-flag f f-name f-whence) 1040 "Flag set differently in pre-v32 and v32 in some cases" 1041 (begin 1042 (dsh (.sym h- f bit) (.str f-name " bit") () (register BI)) 1043 (cris-d-hwreg (.sym h- f bit-move) BI) 1044 (define-hardware 1045 (semantic-name (.sym h- f bit-move-x)) 1046 (name (.sym h- f bit-move-v32)) 1047 (comment (.str f-name " bit set in " f-whence " instructions, ignored")) 1048 (attrs MACH-V32 VIRTUAL) 1049 (type register BI) 1050 (get 1051 () 1052 (sequence BI () 1053 (error (.str "Can't get h-" f "bit-move on CRISv32")) 0)) 1054 (set (val) (nop))) 1055 (define-hardware 1056 (semantic-name (.sym h- f bit-move-x)) 1057 (name (.sym h- f bit-move-pre-v32)) 1058 (comment 1059 (.str 1060 f-name " bit set in " f-whence " instructions, same as " f "bit")) 1061 (attrs MACH-PRE-V32 VIRTUAL) 1062 (type register BI) 1063 (get () (reg (.sym h- f bit))) 1064 (set (val) (set (reg (.sym h- f bit)) val)))) 1065) 1066 1067(cris-move-flag c "carry" "move-type") 1068(cris-move-flag v "overflow" "move-type") 1069(cris-move-flag z "zero" "moveq") 1070(cris-move-flag n "sign" "moveq") 1071 1072(dsh h-xbit "extended-arithmetic bit" () (register BI)) 1073(cris-d-hwreg h-ibit BI) 1074(cris-dsh h-ibit-x h-ibit-pre-v32 1075 "interrupt-enable bit" (MACH-PRE-V32) (register BI)) 1076(dsh h-pbit "sequence-broken bit" ((MACH crisv10,crisv32)) (register BI)) 1077(dsh h-rbit "carry bit for MCP+restore-p bit" (MACH-V32) (register BI)) 1078(cris-d-hwreg h-ubit BI) 1079(cris-dsh h-ubit-x h-ubit-pre-v32 1080 "user mode bit" ((MACH crisv10)) (register BI)) 1081(dsh h-gbit "guru mode bit" (MACH-V32) (register BI)) 1082 1083; When doing a transition from kernel to user mode on V32, we save the 1084; stack pointer in an internal register and copy USP to R14, so we don't 1085; need non-trivial handlers for general registers. 1086(dsh 1087 h-kernel-sp 1088 "Kernel stack pointer during user mode" 1089 (MACH-V32) 1090 (register SI) 1091) 1092 1093(define-hardware 1094 (semantic-name h-ubit-x) 1095 (name h-ubit-v32) 1096 (comment "User mode bit") 1097 (attrs MACH-V32) 1098 (type register BI) 1099 (set 1100 (val) 1101 (sequence 1102 () 1103 (if (andif val (not (raw-reg BI h-ubit-x))) 1104 (sequence 1105 () 1106 (set (reg SI h-kernel-sp) (raw-reg h-gr-x (regno sp))) 1107 (set (raw-reg h-gr-x (regno sp)) (raw-reg h-sr-x (regno usp))) 1108 (set (raw-reg BI h-ubit-x) val) 1109 (c-call VOID "@cpu@_usermode_enabled"))))) 1110) 1111 1112(define-hardware 1113 (semantic-name h-ibit-x) 1114 (name h-ibit-v32) 1115 (comment "Interrupt-enable bit") 1116 (attrs MACH-V32) 1117 (type register BI) 1118 (set 1119 (val) 1120 (sequence 1121 () 1122 (if (not (reg BI h-ubit)) 1123 (sequence 1124 ((BI enabled)) 1125 (set enabled (andif val (not (raw-reg BI h-ibit-x)))) 1126 (set (raw-reg BI h-ibit-x) val) 1127 ; Call handler when enabling. 1128 (if enabled (c-call VOID "@cpu@_interrupts_enabled")))))) 1129) 1130 1131(define-hardware 1132 (name h-mbit) 1133 (comment "NMI enable bit") 1134 (attrs MACH-V32) 1135 (type register BI) 1136 (set 1137 (val) 1138 (sequence 1139 () 1140 ; Don't allow clearing (through this handler) when once set. 1141 (if (andif val (andif (not (raw-reg BI h-mbit)) (not (reg BI h-ubit)))) 1142 (sequence 1143 () 1144 (set (raw-reg BI h-mbit) 1) 1145 ; Call handler when enabling. 1146 (c-call VOID "@cpu@_nmi_enabled"))))) 1147) 1148 1149(define-pmacro 1150 (dsh-cond-bit-v32 x-name x-comment x-cond) 1151 "dsh bit for MACH-V32, with bit only changeable when X-COND" 1152 (define-hardware 1153 (name x-name) 1154 (comment x-comment) 1155 (attrs MACH-V32) 1156 (type register BI) 1157 (set (val) (sequence () (if x-cond (set (raw-reg BI x-name) val))))) 1158) 1159(define-pmacro 1160 (dsh-protected-bit-v32 x-name x-comment) 1161 "dsh bit for MACH-V32, with bit only changeable in kernel mode" 1162 (dsh-cond-bit-v32 x-name x-comment (not (reg BI h-ubit))) 1163) 1164(dsh-protected-bit-v32 h-qbit "Pending single-step bit") 1165 1166(define-hardware 1167 (name h-sbit) 1168 (comment "Cause single step exception on ... [see CRISv32 ref] bit") 1169 (attrs MACH-V32) 1170 (type register BI) 1171 (set 1172 (val) 1173 (sequence 1174 () 1175 (if (not (reg BI h-ubit)) 1176 (sequence 1177 ((BI enabled)) 1178 (set enabled (andif val (not (raw-reg BI h-sbit)))) 1179 (set (raw-reg BI h-sbit) val) 1180 ; Call handler when enabling. 1181 (if enabled (c-call VOID "@cpu@_single_step_enabled")))))) 1182) 1183 1184(dnop cbit "" (SEM-ONLY) h-cbit f-nil) 1185(dnop cbit-move 1186 "cbit for pre-V32, nothing for newer" (SEM-ONLY) h-cbit-move f-nil) 1187(dnop vbit "" (SEM-ONLY) h-vbit f-nil) 1188(dnop vbit-move 1189 "vbit for pre-V32, nothing for newer" (SEM-ONLY) h-vbit-move f-nil) 1190(dnop zbit "" (SEM-ONLY) h-zbit f-nil) 1191(dnop zbit-move 1192 "zbit for pre-V32, nothing for newer" (SEM-ONLY) h-zbit-move f-nil) 1193(dnop nbit "" (SEM-ONLY) h-nbit f-nil) 1194(dnop nbit-move 1195 "nbit for pre-V32, nothing for newer" (SEM-ONLY) h-nbit-move f-nil) 1196(dnop xbit "" (SEM-ONLY) h-xbit f-nil) 1197(dnop ibit "" (SEM-ONLY) h-ibit f-nil) 1198(dnop ubit "" (SEM-ONLY (MACH crisv10,crisv32)) h-ubit f-nil) 1199(dnop pbit "" (SEM-ONLY (MACH crisv10,crisv32)) h-pbit f-nil) 1200(dnop 1201 rbit "carry bit for MCP+restore-P flag bit" (SEM-ONLY MACH-V32) h-rbit f-nil) 1202(dnop sbit "" (SEM-ONLY MACH-V32) h-sbit f-nil) 1203(dnop mbit "" (SEM-ONLY MACH-V32) h-mbit f-nil) 1204(dnop qbit "" (SEM-ONLY MACH-V32) h-qbit f-nil) 1205 1206(cris-d-hwreg h-insn-prefixed-p BI) 1207(cris-dsh 1208 h-insn-prefixed-p-x 1209 h-insn-prefixed-p-pre-v32 1210 "instruction-is-prefixed bit" 1211 (MACH-PRE-V32) 1212 (register BI) 1213) 1214 1215; CRISv32 has no prefixing on memory accesses. CGEN-FIXME: [Once (eq-attr 1216; (current-mach) ...) works]: can we change andif and/or orif so it 1217; doesn't look too close at short-circuited operands and avoid defining an 1218; operand that doesn't apply to a certain mach? 1219(define-hardware 1220 (semantic-name h-insn-prefixed-p-x) 1221 (name h-insn-prefixed-p-v32) 1222 (attrs MACH-V32 VIRTUAL) 1223 (comment "instruction-is-prefixed bit") 1224 (type register BI) 1225 (get () (const BI 0)) 1226 (set (val) (nop)) 1227) 1228(dnop 1229 prefix-set 1230 "Instruction-prefixed flag" 1231 (SEM-ONLY) 1232 h-insn-prefixed-p 1233 f-nil 1234) 1235 1236(cris-dsh 1237 h-prefixreg h-prefixreg-pre-v32 1238 "Prefix-address register" (MACH-PRE-V32) (register SI)) 1239(define-hardware 1240 (semantic-name h-prefixreg) 1241 (name h-prefixreg-v32) 1242 (comment "Prefix-address register, redirecting to ACR") 1243 (attrs MACH-V32 VIRTUAL) 1244 (type register SI) 1245 ; Why can't we have just a "acr" a.k.a "(reg h-gr 15)" here? 1246 (get () acr) 1247 (set (value) (set acr value)) 1248) 1249 1250(dnop 1251 prefixreg 1252 "Prefix address" 1253 (SEM-ONLY) 1254 h-prefixreg 1255 f-nil 1256) 1257 1258;;;;;;;;;;;;;;;;;; -ifield 1259 1260; 15 0 1261; +-----------+-----+-----------+-----+-----------+ 1262; | Operand2 | Mode| Opcode | Size| Operand1 | 1263; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ 1264; 1265; Figure 5. General instruction format. 1266; 1267; Some deviations from this format exist, [see below]. 1268 1269; Field specifiers in CGEN specify the highest numbered bit followed by 1270; the number of bits. 1271 1272(dnf f-operand1 "Operand1" () 3 4) 1273(dnf f-size "Size" () 5 2) 1274(dnf f-opcode "Opcode" () 9 4) 1275(dnf f-mode "Mode" () 11 2) 1276(dnf f-operand2 "Operand2" () 15 4) 1277 1278; Subfields. FIXME: unfortunately there's some limitation in CGEN so we 1279; can't (as would be somewhat intuitive) make f-mode a multi-ifield 1280; consisting of these two, concatenated. 1281(dnf f-memmode "Indirect of autoincrement" () 10 1) 1282(dnf f-membit "Memory specifier" () 11 1) 1283 1284(dnf f-b5 "Bit 5 (zero for some quick operands)" () 5 1) 1285 1286; When the addressing mode is quick immediate, the low bits are 1287; part of the operand. 1288(dnf f-opcode-hi "Opcode field, high bits" () 9 2) 1289 1290; Common synonyms for those fields. 1291(define-pmacro f-source f-operand1) 1292(define-pmacro f-dest f-operand2) 1293 1294(dnmf 1295 f-dstsrc "Dest and source fields concatenated" () UINT 1296 (f-dest f-source) 1297 ; Insert-code. 1298 (sequence 1299 ((SI tmpval)) 1300 (set tmpval (ifield f-dstsrc)) 1301 (set (ifield f-dest) (and (srl tmpval 4) #xf)) 1302 (set (ifield f-source) (and tmpval #xf))) 1303 ; Extract-code. 1304 (set 1305 (ifield f-dstsrc) 1306 (and (or (ifield f-source) (sll (ifield f-dest) 4)) #xff)) 1307) 1308 1309;The 6-bit value may be sign or zero extended depending on the instruction. 1310; 1311; 15 0 1312; +-----------+-----+-----------+-----+-----------+ 1313; | Operand2 | Mode| Opcode | Immediate value | 1314; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ 1315; 1316; Figure 6. Quick immediate addressing mode instruction format. 1317 1318(dnf f-u6 "Quick immediate unsigned 6-bit" () 5 6) 1319(df f-s6 "Quick signed 6-bit" () 5 6 INT #f #f) 1320 1321; There's also a variant used with shift insns, with one bit larger opcode 1322; and one bit smaller immediate value, though it doesn't have a general 1323; graphic description. 1324(dnf f-u5 "Quick unsigned 5-bit" () 4 5) 1325 1326; Similarly, a four-bit immediate field. 1327(dnf f-u4 "Quick unsigned 4-bit" () 3 4) 1328 1329; An 8-bit signed value, which doesn't have a general graphic description. 1330(df f-s8 "Source signed byte" () 7 8 INT #f #f) 1331 1332; The 9-bit branch offset, with bit 0 in the field being bit 8 in the 1333; offset, and bit 0 in the offset always 0. 1334(df f-disp9-hi "PC-relative 9-bit offset, sign bit" () 0 1 INT #f #f) 1335(dnf f-disp9-lo "PC-relative 9-bit offset, low bits" () 7 7) 1336 1337; It would work to have this in two mach-specific variants, but 1338; considering that current-mach-is-v32 is a compile-time constant, we 1339; don't win any simulator performance. 1340(dnmf 1341 f-disp9 "PC-relative 9-bit offset" 1342 (PCREL-ADDR) 1343 INT 1344 (f-disp9-hi f-disp9-lo) 1345 ; Insert-code. 1346 (sequence 1347 ((SI absval)) 1348 (set absval (srl (sub (sub SI (ifield f-disp9) pc) 1349 (if SI current-mach-is-v32 0 2)) 1)) 1350 (set (ifield f-disp9-hi) (if (lt absval 0) 1 0)) 1351 (set (ifield f-disp9-lo) (and absval) #x7f)) 1352 ; Extract-code. 1353 (sequence 1354 ((SI abslo) (SI absval)) 1355 (set abslo (sll (ifield f-disp9-lo) 1)) 1356 (set absval 1357 (or (if SI (ne (ifield f-disp9-hi) 0) 1358 (inv SI #xff) 1359 0) 1360 abslo)) 1361 (set (ifield f-disp9) 1362 (add SI (add SI pc absval) (if SI current-mach-is-v32 0 2)))) 1363) 1364 1365; The operand of LAPCQ is PC-relative, similar to f-disp9 but unsigned, 1366; and only four bits. 1367(df 1368 f-qo 1369 "PC-relative 4-bit unsigned offset, counted from start of insn" 1370 (MACH-V32 PCREL-ADDR) 1371 3 4 1372 UINT 1373 ; Insert-code. 1374 ((value pc) (srl SI (sub SI value pc) 1)) 1375 ; Extract-code. 1376 ((value pc) (add SI pc (sll SI value 1))) 1377) 1378 1379; 8-bit, 16-bit and 32-bit immediates. The 8-bit values are constructed 1380; through encoding/decoding functions, since the PC increment is by a 1381; word. 1382(define-pmacro (dcrisf x-name x-comment x-attrs x-word-offset x-word-length 1383 x-start x-length x-mode x-encode x-decode) 1384 (define-ifield 1385 (name x-name) 1386 (comment x-comment) 1387 (.splice attrs (.unsplice x-attrs)) 1388 (word-offset x-word-offset) 1389 (word-length x-word-length) 1390 (start x-start) 1391 (length x-length) 1392 (mode x-mode) 1393 (.splice encode (.unsplice x-encode)) 1394 (.splice decode (.unsplice x-decode)) 1395 ) 1396) 1397 1398(dcrisf 1399 f-indir-pc+-byte "[PC+] 8-bit field" (SIGN-OPT) 1400 16 16 1401 15 16 ; CGEN-FIXME: Should be 7 8 1402 INT (#f) (#f) 1403) 1404 1405(dcrisf 1406 f-indir-pc+-word "[PC+] 16-bit field" (SIGN-OPT) 1407 16 16 15 16 INT (#f) (#f) 1408) 1409 1410; CGEN-FIXME: I shouldn't have to use trunc here, should I? 1411; Sign-extension should be implicit through use of SI (as opposed to USI) 1412; and additionally through SIGN-OPT. The ext isn't actually needed, but 1413; having it there rather than implicit makes more sense than to just have 1414; the trunc. 1415(dcrisf 1416 f-indir-pc+-word-pcrel "[PC+] PC-relative 16-bit field" 1417 (PCREL-ADDR SIGN-OPT) 1418 16 16 15 16 SI 1419 ((value pc) (sub SI value (add SI pc (if SI current-mach-is-v32 0 4)))) 1420 ((value pc) (add SI (ext SI (trunc HI value)) (add SI pc (if SI current-mach-is-v32 0 4)))) 1421) 1422 1423(dcrisf 1424 f-indir-pc+-dword "PC autoincrement - 32-bit field" (SIGN-OPT) 1425 16 32 31 32 INT (#f) (#f) 1426) 1427 1428(dcrisf 1429 f-indir-pc+-dword-pcrel 1430 "[PC+] PC-relative 32-bit field, counted from start of insn" 1431 (SIGN-OPT MACH-V32 PCREL-ADDR) 1432 16 32 31 32 INT 1433 ((value pc) (sub SI value pc)) 1434 ((value pc) (add SI pc value)) 1435) 1436 1437;;;;;;;;;;;;;;;;;; -insn-enum -normal-operand -normal-derived-operand 1438 1439;; How different fields are transformed into something we put in insns. 1440 1441; m := size modifier, byte (00), word (01) or dword (10) 1442; z := size modifier, byte (0) or word (1) 1443; (For the latter, the "higher" bit is always 0, mapping trivially on m.) 1444 1445(define-normal-insn-enum 1446 insn-size 1447 "Standard instruction operand size" 1448 () 1449 SIZE_ 1450 f-size 1451 ("BYTE" "WORD" "DWORD" "FIXED") 1452) 1453 1454; The mode field for insns with "s" operand (perhaps with a partial set of 1455; operand types). 1456(define-normal-insn-enum 1457 insn-mode 1458 "Standard instruction addressing modes" 1459 () 1460 MODE_ 1461 f-mode 1462 ("QUICK_IMMEDIATE" "REGISTER" "INDIRECT" "AUTOINCREMENT") 1463) 1464 1465(define-normal-insn-enum 1466 insn-memoryness-mode 1467 "Whether the operand is indirect" 1468 () 1469 MODEMEMP_ 1470 f-membit 1471 ("NO" "YES") 1472) 1473 1474; FIXME: Needed? 1475(define-normal-insn-enum 1476 insn-memincness-mode 1477 "Whether the indirect operand is autoincrement" 1478 () 1479 MODEINCP_ 1480 f-memmode 1481 ("NO" "YES") 1482) 1483 1484; Special semantics for multiply. 1485(define-pmacro MODE_MULU MODE_INDIRECT) 1486(define-pmacro MODE_MULS MODE_AUTOINCREMENT) 1487 1488(define-normal-insn-enum 1489 insn-signed-size 1490 "Signed instruction operand size" 1491 () 1492 SIGNED_ 1493 f-size 1494 ("UNDEF_SIZE_0" "UNDEF_SIZE_1" "BYTE" "WORD") 1495) 1496 1497(define-normal-insn-enum 1498 insn-unsigned-size 1499 "Unsigned instruction operand size" 1500 () 1501 UNSIGNED_ 1502 f-size 1503 ("BYTE" "WORD" "UNDEF_SIZE_2" "UNDEF_SIZE_3") 1504) 1505 1506; Rs := source operand, register addressing mode 1507(dnop Rs "Source general register" () h-gr f-source) 1508 1509; [Rs] := source operand, indirect addressing mode 1510; = MODE_INDIRECT Rs 1511 1512; [Rs+] := source operand, autoincrement addressing mode (see note!) 1513; = MODE_AUTOINCREMENT Rs 1514 1515; The union of [Rs] and [Rs(+)] 1516; = MODEMEMP_YES Rs 1517 1518; Whether an indirect operand is increment can be obtained as an operand by 1519; = inc 1520(dnop inc "Incrementness of indirect operand" () h-inc f-memmode) 1521 1522; or as an affirmative specifier 1523; = MODEINCP_YES 1524; (or MODEINCP_NO) 1525 1526; s := source operand, any of the modes Rs, [Rs] or [Rs+] 1527; No common operand; each are handled separately, using the above definitions. 1528 1529; Ps := source operand, special register 1530; It's in the field usually used for the destination. 1531(dnop Ps "Source special register" () h-sr f-dest) 1532 1533; Ss := source operand, support register 1534; It's in the field usually used for the destination. 1535(dnop Ss "Source support register" (MACH-V32) h-supr f-dest) 1536 1537; Sd := source operand, support register 1538(dnop Sd "Destination support register" (MACH-V32) h-supr f-dest) 1539 1540; i := 6-bit signed immediate operand 1541(dnop i "Quick signed 6-bit" () h-sint f-s6) 1542 1543; j := 6-bit unsigned immediate operand 1544(dnop j "Quick unsigned 6-bit" () h-uint f-u6) 1545 1546; c := 5-bit immediate shift value 1547(dnop c "Quick unsigned 5-bit" () h-uint f-u5) 1548 1549; qo := 4-bit unsigned immediate operand 1550(dnop qo "Quick unsigned 4-bit, PC-relative" (MACH-V32) h-addr f-qo) 1551 1552; Rd := destination operand, register addressing mode 1553(dnop Rd "Destination general register" () h-gr f-dest) 1554(define-pmacro Rd-sfield Rs) 1555(define-pmacro Rs-dfield Rd) 1556 1557; [Rd] := destination operand, indirect addressing mode 1558; = MODE_INDIRECT Rd 1559 1560; [Rd+] := destination operand, autoincrement addressing mode 1561; = MODE_AUTOINCREMENT Rd 1562 1563; [PC+] := destination operand PC, autoincrement addressing mode 1564; = MODE_AUTOINCREMENT (f-dest 15) X 1565; where X is one of sconst8, uconst8, sconst16, uconst16 or const32. 1566(dnop sconst8 "Signed byte [PC+]" () h-sint f-indir-pc+-byte) 1567(dnop uconst8 "Unsigned byte [PC+]" () h-uint f-indir-pc+-byte) 1568(dnop sconst16 "Signed word [PC+]" () h-sint f-indir-pc+-word) 1569(dnop uconst16 "Unsigned word [PC+]" () h-uint f-indir-pc+-word) 1570(dnop const32 "Dword [PC+]" () h-uint f-indir-pc+-dword) 1571(dnop const32-pcrel "Dword [PC+]" () h-addr f-indir-pc+-dword-pcrel) 1572 1573; d := destination operand, any of the modes Rd, [Rd] or [Rd+] 1574; No common operand; each are handled separately, using the above definitions. 1575 1576; Pd := destination operand, special register 1577(dnop Pd "Destination special register" () h-sr f-dest) 1578 1579; o := 8-bit immediate offset value 1580(dnop o "Signed 8-bit" () h-sint f-s8) 1581 1582; The division of operand semantics and insn fields in the CRIS 1583; instruction set reference doesn't permit a simple mapping to a 1584; simulator description, and the division of insn fields and 1585; semantics in CGEN is not between the define-normal-ifield 1586; vs. define-normal-operand. For example, the "o" operand is 1587; PC-relative for branch insns, as described by the CGEN f-disp9 1588; field. 1589; See comment at f-disp9; thankfully the mach 1590; attribute works here to have two different definitions by the 1591; same name. 1592(dnop o-pcrel "9-bit signed immediate PC-rel" 1593 () 1594 h-iaddr f-disp9) 1595 1596(dnop o-word-pcrel "16-bit signed immediate PC-rel" 1597 () 1598 h-iaddr f-indir-pc+-word-pcrel) 1599 1600; cc := condition code 1601(dnop cc "Condition codes" () h-ccode f-dest) 1602 1603; n := 4 bit breakpoint exception vector index 1604(dnop n "Quick unsigned 4-bit" () h-uint f-u4) 1605 1606; The "option" in the SWAP insn. 1607(dnop swapoption "Swap option" () h-swap f-dest) 1608 1609(dnop list-of-flags "Flag bits as operand" () h-flagbits f-dstsrc) 1610 1611; Enumerations for insn codes, for use in insn definitions 1612; instead of raw numbers. See it as operand definitions for the 1613; opcode field. 1614 1615(define-normal-insn-enum 1616 insn-qi-opc 1617 "Insns for MODE_QUICK_IMMEDIATE" 1618 () 1619 Q_ 1620 f-opcode 1621 ("BCC_0" "BCC_1" "BCC_2" "BCC_3" 1622 "BDAP_0" "BDAP_1" "BDAP_2" "BDAP_3" 1623 "ADDQ" "MOVEQ" "SUBQ" "CMPQ" 1624 "ANDQ" "ORQ" "ASHQ" "LSHQ") 1625) 1626 1627(define-normal-insn-enum 1628 insn-qihi-opc 1629 "Same as insn-qi-opc, though using only the high two bits of the opcode" 1630 () 1631 QHI_ 1632 f-opcode-hi 1633 ("BCC" "BDAP" "OTHER2" "OTHER3") 1634) 1635(define-pmacro QHI_ADDOQ QHI_BDAP) 1636 1637(define-normal-insn-enum 1638 insn-r-opc 1639 "Insns for MODE_REGISTER and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD" 1640 () 1641 R_ 1642 f-opcode 1643 ("ADDX" "MOVX" "SUBX" "LSL" 1644 "ADDI" "BIAP" "NEG" "BOUND" 1645 "ADD" "MOVE" "SUB" "CMP" 1646 "AND" "OR" "ASR" "LSR") 1647) 1648(define-pmacro R_ADDI_ACR R_BIAP) 1649 1650(define-normal-insn-enum 1651 insn-rfix-opc 1652 "Insns for MODE_REGISTER and SIZE_FIXED" 1653 () 1654 RFIX_ 1655 f-opcode 1656 ("ADDX" "MOVX" "SUBX" "BTST" 1657 "SCC" "ADDC" "SETF" "CLEARF" 1658 "MOVE_R_S" "MOVE_S_R" "ABS" "DSTEP" 1659 "LZ" "SWAP" "XOR" "MSTEP") 1660) 1661(define-pmacro RFIX_MCP RFIX_MSTEP) 1662 1663(define-normal-insn-enum 1664 insn-indir-opc 1665 "Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and either SIZE_BYTE, SIZE_WORD or SIZE_DWORD" 1666 () 1667 INDIR_ 1668 f-opcode 1669 ("ADDX" "MOVX" "SUBX" "CMPX" 1670 "MUL" "BDAP_M" "ADDC" "BOUND" 1671 "ADD" "MOVE_M_R" "SUB" "CMP" 1672 "AND" "OR" "TEST" "MOVE_R_M") 1673) 1674(define-pmacro INDIR_ADDO INDIR_BDAP_M) 1675 1676(define-normal-insn-enum 1677 insn-infix-opc 1678 "Insns for (MODE_INDIRECT or MODE_AUTOINCREMENT) and SIZE_FIXED" 1679 () 1680 INFIX_ 1681 f-opcode 1682 ("ADDX" "MOVX" "SUBX" "CMPX" 1683 "JUMP_M" "DIP" "JUMP_R" "BCC_M" 1684 "MOVE_M_S" "MOVE_S_M" "BMOD" "BSTORE" 1685 "RBF" "SBFS" "MOVEM_M_R" "MOVEM_R_M") 1686) 1687 1688(define-pmacro INFIX_MOVE_SS INFIX_SBFS) 1689(define-pmacro INFIX_LAPC INFIX_DIP) 1690(define-pmacro INFIX_RFE INFIX_JUMP_M) 1691(define-pmacro INFIX_RFN INFIX_JUMP_M) 1692(define-pmacro INFIX_HALT INFIX_JUMP_M) 1693(define-pmacro INFIX_SFE INFIX_JUMP_M) 1694(define-pmacro INFIX_RFG INFIX_JUMP_M) 1695(define-pmacro INFIX_JAS_R INFIX_JUMP_R) 1696(define-pmacro INFIX_JAS_M INFIX_JUMP_R) 1697(define-pmacro INFIX_JASC INFIX_RBF) 1698(define-pmacro INFIX_JUMP_P INFIX_BCC_M) 1699(define-pmacro INFIX_BAS INFIX_BMOD) 1700(define-pmacro INFIX_BASC INFIX_BSTORE) 1701(define-pmacro INFIX_BREAK INFIX_JUMP_M) 1702(define-pmacro INFIX_FIDXI INFIX_JUMP_M) 1703(define-pmacro INFIX_FIDXD INFIX_BAS) 1704(define-pmacro INFIX_FTAGI INFIX_JUMP_M) 1705(define-pmacro INFIX_FTAGD INFIX_BAS) 1706 1707; Classes of insns: 1708; Move-to-register, move-to-memory, move-to/from-other-register, 1709; logical, arithmetic, branch. 1710; Classes of operands: 1711; quick, register, memory-indirect, memory-postinc. 1712 1713 1714;;;;;;;;;;;;;;;;;; -normal-insn 1715 1716(define-pmacro (dni-bwd-attr name comment attr syntax fmt fsem timing) 1717 (begin 1718 (dni (.sym name .b) (.str "byte " comment) attr (.str name ".b " syntax) 1719 (.splice (.unsplice fmt) SIZE_BYTE) 1720 (fsem QI) 1721 timing) 1722 (dni (.sym name .w) (.str "word " comment) attr (.str name ".w " syntax) 1723 (.splice (.unsplice fmt) SIZE_WORD) 1724 (fsem HI) 1725 timing) 1726 (dni (.sym name .d) (.str "dword " comment) attr (.str name ".d " syntax) 1727 (.splice (.unsplice fmt) SIZE_DWORD) 1728 (fsem SI) 1729 timing)) 1730) 1731 1732(define-pmacro (dni-cdt-attr name comment attr syntax fmt semantics) 1733 "dni without specifying timing" 1734 (dni name comment attr syntax fmt semantics (cris-timing)) 1735) 1736 1737(define-pmacro (dni-cdt-bwd-attr name comment attr syntax fmt fsem) 1738 (begin 1739 (dni-cdt-attr (.sym name .b-r) (.str "byte " comment) attr (.str name ".b " syntax) 1740 (.splice (.unsplice fmt) SIZE_BYTE) 1741 (fsem QI)) 1742 (dni-cdt-attr (.sym name .w-r) (.str "word " comment) attr (.str name ".w " syntax) 1743 (.splice (.unsplice fmt) SIZE_WORD) 1744 (fsem HI)) 1745 (dni-cdt-attr (.sym name .d-r) (.str "dword " comment) attr (.str name ".d " syntax) 1746 (.splice (.unsplice fmt) SIZE_DWORD) 1747 (fsem SI))) 1748) 1749 1750; Some convenience macros based on the above ones. 1751(define-pmacro (dni-cdt-bwd name comment syntax fmt fsem) 1752 (dni-cdt-bwd-attr name comment () syntax fmt fsem) 1753) 1754 1755(define-pmacro (dni-bwd name comment syntax fmt fsem timing) 1756 (dni-bwd-attr comment () syntax fmt fsem timing) 1757) 1758 1759(define-pmacro-map 1760 (((dni-cdt name comment syntax fmt semantics) 1761 (dni-cdt-attr name comment () syntax fmt semantics)) 1762 ((dni-c-QI-attr name comment attr syntax fmt fsem) 1763 (dni name comment attr syntax fmt fsem (cris-timing-const-QI))) 1764 ((dni-c-HI-attr name comment attr syntax fmt fsem) 1765 (dni name comment attr syntax fmt fsem (cris-timing-const-HI))) 1766 ((dni-c-SI-attr name comment attr syntax fmt fsem) 1767 (dni name comment attr syntax fmt fsem (cris-timing-const-SI)))) 1768) 1769 1770(define-pmacro-map 1771 (((dni-c-QI name comment syntax fmt fsem) 1772 (dni-c-QI-attr name comment () syntax fmt fsem)) 1773 ((dni-c-HI name comment syntax fmt fsem) 1774 (dni-c-HI-attr name comment () syntax fmt fsem)) 1775 ((dni-c-SI name comment syntax fmt fsem) 1776 (dni-c-SI-attr name comment () syntax fmt fsem))) 1777) 1778 1779; These flags are both cleared by all insns except prefixes (before 1780; CRISv32) and "setf x", so we put them in a handy macro. 1781(define-pmacro 1782 (reset-x-p) 1783 (sequence 1784 () 1785 (set xbit 0) 1786 (set prefix-set 0)) 1787) 1788 1789; NOP | 0 0 0 0| 0 1| 0 1 0 0| 0 0| 1 1 1 1| 1790; (For V32, "SETF" (no flags) is used.) 1791(dni-cdt-attr 1792 nop "nop" (MACH-PC) "nop" 1793 (+ (f-operand2 0) R_ADDI MODE_REGISTER SIZE_BYTE (f-operand1 15)) 1794 (reset-x-p) 1795) 1796 1797; Pre- and v32+ variants MOVE insns set flags differently. These two 1798; macros for flag settings are meant to be used in all MOVE insns. 1799(define-pmacro (setf-moveq value) 1800 (sequence 1801 () 1802 (set-quiet nbit-move (lt SI value 0)) 1803 (set-quiet zbit-move (andif BI (eq SI value 0) (if BI xbit zbit 1))) 1804 (set-quiet cbit-move 0) 1805 (set-quiet vbit-move 0) 1806 (reset-x-p)) 1807) 1808 1809(define-pmacro (setf-move size value) 1810 (sequence 1811 () 1812 (set nbit (lt size value 0)) 1813 (set zbit (andif BI (eq size value 0) (if BI xbit zbit 1))) 1814 (set-quiet cbit-move 0) 1815 (set-quiet vbit-move 0) 1816 (reset-x-p)) 1817) 1818; The CGEN binop-with-bit operations are not documented well enough that I 1819; trust their semantics to remain stable. Better define local ones: the 1820; semantics become explicit. 1821(define-pmacro-map 1822 (((add-overflow size R D S carry) 1823 (orif BI (andif BI (andif BI (lt size S 0) (lt size D 0)) (ge size R 0)) 1824 (andif BI (andif BI (ge size S 0) (ge size D 0)) (lt size R 0)))) 1825 ((add-carry size R D S carry) 1826 (orif BI (andif BI (lt size S 0) (lt size D 0)) 1827 (orif BI (andif BI (lt size D 0) (ge size R 0)) 1828 (andif BI (lt size S 0) (ge size R 0))))) 1829 ((sub-overflow size R D S carry) 1830 (orif BI (andif BI (andif BI (ge size S 0) (lt size D 0)) (ge size R 0)) 1831 (andif BI (andif BI (lt size S 0) (ge size D 0)) (lt size R 0)))) 1832 ((sub-carry size R D S carry) 1833 (orif BI (andif BI (lt size S 0) (ge size D 0)) 1834 (orif BI (andif BI (ge size D 0) (lt size R 0)) 1835 (andif BI (lt size S 0) (lt size R 0))))) 1836 ; Only valid for size := DI 1837 ((mulu-overflow size R D S carry) 1838 (ne DI R (zext DI (trunc SI R)))) 1839 ((mulu-carry size R D S carry) 1840 (andif current-mach-is-v32 carry)) 1841 ((muls-overflow size R D S carry) 1842 (ne DI R (ext DI (trunc SI R)))) 1843 ((muls-carry size R D S carry) 1844 (andif current-mach-is-v32 carry))) 1845) 1846 1847(define-pmacro (setf-arit2 size op source1 source2 result carryin carryout) 1848 "Set no-prefix, x=0, carryout, v, z and n according to operation OP in size SIZE" 1849 (sequence 1850 () 1851 (set carryout ((.sym op -carry) size result source1 source2 carryin)) 1852 (set nbit (lt size result 0)) 1853 (set zbit (andif BI (eq size result 0) (orif BI zbit (not BI xbit)))) 1854 (set vbit ((.sym op -overflow) size result source1 source2 carryin)) 1855 (reset-x-p)) 1856) 1857(define-pmacro (setf-arit size op source1 source2 result carry) 1858 "Set no-prefix, x=0, c, v, z and n according to operation OP in size SIZE" 1859 (setf-arit2 size op source1 source2 result carry cbit) 1860) 1861 1862; Let's have convienence macros for arithmetic, including evaluation of the 1863; operation, destination modification, flag setting and carry propagation. 1864(define-pmacro 1865 (cris-arit6-int arit size fdest fdest_op srcop1 srcop2 carryout carryin) 1866 "Core for performing some three-operand arithmetic with carry as parameter" 1867 (sequence 1868 ((size tmpopd) (size tmpops) (BI carry) (size newval)) 1869 (set tmpops srcop2) 1870 (set tmpopd srcop1) 1871 (set carry carryin) 1872 (set newval ((.sym arit c) tmpopd tmpops (if BI (eq xbit 0) 0 carry))) 1873 (fdest size fdest_op newval) 1874 (setf-arit2 size arit tmpopd tmpops newval carry carryout)) 1875) 1876 1877(define-pmacro 1878 (cris-arit5-int arit size destregno srcop1 srcop2 carryout carryin) 1879 "As cris-arit6-int, but to set a part of a general register" 1880 (cris-arit6-int 1881 arit 1882 size 1883 (.pmacro (sz regno val) (set-subreg-gr sz regno val)) 1884 destregno 1885 srcop1 1886 srcop2 1887 carryout 1888 carryin) 1889) 1890 1891(define-pmacro (cris-arit5 arit size destreg srcop1 srcop2 carryout carryin) 1892 "As cris-arit5-int, but takes a register as parameter, not register number" 1893 (cris-arit5-int arit size (regno destreg) srcop1 srcop2 carryout carryin) 1894) 1895(define-pmacro (cris-arit3-int arit size destregno srcop1 srcop2) 1896 "As cris-arit5-int, but with carry-in same as carry-out" 1897 (cris-arit5-int arit size destregno srcop1 srcop2 cbit cbit) 1898) 1899(define-pmacro (cris-arit3 arit size destreg srcop1 srcop2) 1900 "As cris-arit3-int, but takes a register as parameter, not register number" 1901 (cris-arit3-int arit size (regno destreg) srcop1 srcop2) 1902) 1903(define-pmacro (cris-arit arit size destreg srcop) 1904 "As cris-arit3, but with destination same as srcop1" 1905 (cris-arit3 arit size destreg destreg srcop) 1906) 1907(define-pmacro (cris-arit-3op arit size destsrcop2 srcop1 dest-3op) 1908 "Similar to cris-arit3-int, but for prefixed operand only" 1909 (cris-arit3-int arit size 1910 (if SI (andif prefix-set (not inc)) 1911 (regno dest-3op) 1912 (regno destsrcop2)) 1913 destsrcop2 srcop1) 1914) 1915 1916; Convenience macros to select a part of a value and its complement, for 1917; the <op>.b, <op>.w and <op>.d operations. 1918(define-pmacro (QI-part val) (and SI val #xff)) 1919(define-pmacro (non-QI-part val) (and SI val #xffffff00)) 1920(define-pmacro (HI-part val) (and SI val #xffff)) 1921(define-pmacro (non-HI-part val) (and SI val #xffff0000)) 1922(define-pmacro (SI-part val) val) 1923(define-pmacro (non-SI-part val) 0) 1924(define-pmacro 1925 (set-subreg-gr-bw BWD gregno newval) 1926 "Set a byte or word part or full dword of a general register" 1927 (sequence 1928 ((SI oldregval)) 1929 (set oldregval (reg h-raw-gr gregno)) 1930 (set (reg h-gr gregno) 1931 (or SI ((.sym BWD -part) newval) ((.sym non- BWD -part) oldregval)))) 1932) 1933(define-pmacro (set-subreg-gr BWD gregno newval) 1934 ((.sym set-subreg-gr- BWD) BWD gregno newval) 1935) 1936(define-pmacro (set-subreg-gr-SI SI gregno newval) 1937 (set (reg h-gr gregno) newval) 1938) 1939(define-pmacro set-subreg-gr-HI set-subreg-gr-bw) 1940(define-pmacro set-subreg-gr-QI set-subreg-gr-bw) 1941 1942; MOVE.m Rs,Rd [ Rd | 011001mm | Rs ] 1943(dni-cdt-bwd 1944 move "move.m r,R" 1945 "move.m ${Rs},${Rd}" 1946 (+ Rd MODE_REGISTER R_MOVE Rs) 1947 (.pmacro 1948 (BWD) 1949 (sequence 1950 ((BWD newval)) 1951 (set newval Rs) 1952 (set-subreg-gr BWD (regno Rd) newval) 1953 (setf-move BWD newval))) 1954) 1955 1956; MOVE.D PC,Rd [ Rd | 01100110 | 1111 ] 1957; This insn is used in PIC code to find out the code address. It's an 1958; exception to the (guarded) non-implementation of PC operands in this 1959; file. 1960(dni-cdt-attr 1961 movepcr "move.d PC,R" 1962 (MACH-PC UNCOND-CTI) 1963 "move.d PC,${Rd}" 1964 (+ Rd MODE_REGISTER R_MOVE SIZE_DWORD (f-source 15)) 1965 (sequence 1966 ((SI pcval)) 1967 (set pcval (add SI pc 2)) 1968 (set Rd pcval) 1969 (setf-move SI pcval)) 1970) 1971 1972; MOVEQ i,Rd [ Rd | 001001 | i ] 1973(dni-cdt 1974 moveq "moveq" 1975 "moveq $i,$Rd" 1976 (+ Rd MODE_QUICK_IMMEDIATE Q_MOVEQ i) 1977 (sequence 1978 ((SI newval)) 1979 (set newval i) 1980 (set Rd newval) 1981 (setf-moveq newval)) 1982) 1983 1984(define-pmacro (dni-cdt-sbw name comment syntax fmt fsem) 1985 "Insn generator for insns with signed <op>.b and <op>.w variants" 1986 (begin 1987 (dni-cdt 1988 (.sym name .b-r) (.str "byte " comment) (.str name ".b " syntax) 1989 (.splice (.unsplice fmt) SIGNED_BYTE) 1990 (fsem QI)) 1991 (dni-cdt 1992 (.sym name .w-r) (.str "word " comment) (.str name ".w " syntax) 1993 (.splice (.unsplice fmt) SIGNED_WORD) 1994 (fsem HI))) 1995) 1996 1997; MOVS.z Rs,Rd [ Rd | 0100011z | Rs ] 1998(dni-cdt-sbw 1999 movs "movs.m r,R" 2000 "movs.m ${Rs},${Rd}" 2001 (+ Rd MODE_REGISTER R_MOVX Rs) 2002 (.pmacro 2003 (BW) 2004 (sequence 2005 ((BW newval)) 2006 (set newval Rs) 2007 (set Rd (ext SI newval)) 2008 (setf-move SI newval))) 2009) 2010 2011(define-pmacro (dni-cdt-ubw name comment syntax fmt fsem) 2012 "Similar to dni-cdt-sbw but for unsigned operations" 2013 (begin 2014 (dni-cdt 2015 (.sym name .b-r) (.str "byte " comment) (.str name ".b " syntax) 2016 (.splice (.unsplice fmt) UNSIGNED_BYTE) 2017 (fsem QI)) 2018 (dni-cdt 2019 (.sym name .w-r) (.str "word " comment) (.str name ".w " syntax) 2020 (.splice (.unsplice fmt) UNSIGNED_WORD) 2021 (fsem HI))) 2022) 2023 2024; MOVU.z Rs,Rd [ Rd | 0100010z | Rs ] 2025(dni-cdt-ubw 2026 movu "movu.m r,R" 2027 "movu.m ${Rs},${Rd}" 2028 (+ Rd MODE_REGISTER R_MOVX Rs) 2029 (.pmacro 2030 (BW) 2031 (sequence 2032 ((BW newval)) 2033 (set newval Rs) 2034 (set Rd (zext SI newval)) 2035 (setf-move SI newval))) 2036) 2037 2038; (MOVE.m [PC+],Rd [ Rd | 111001mm | 1111 ]) 2039; For the moment, it doesn't seem worthwhile to make a dni-c-bwd macro; 2040; too many places to parametrize. 2041(dni-c-QI 2042 movecbr "move.b [PC+],R" 2043 "move.b ${sconst8},${Rd}" 2044 (+ Rd MODE_AUTOINCREMENT INDIR_MOVE_M_R SIZE_BYTE (f-source 15) sconst8) 2045 (sequence 2046 ((QI newval)) 2047 (set newval sconst8) 2048 (set-subreg-gr QI (regno Rd) newval) 2049 (setf-move QI newval)) 2050) 2051 2052(dni-c-HI 2053 movecwr "move.w [PC+],R" 2054 "move.w ${sconst16},${Rd}" 2055 (+ Rd MODE_AUTOINCREMENT INDIR_MOVE_M_R SIZE_WORD (f-source 15) sconst16) 2056 (sequence 2057 ((HI newval)) 2058 (set newval sconst16) 2059 (set-subreg-gr HI (regno Rd) newval) 2060 (setf-move HI newval)) 2061) 2062 2063(dni-c-SI 2064 movecdr "move.d [PC+],R" 2065 "move.d ${const32},${Rd}" 2066 (+ Rd MODE_AUTOINCREMENT INDIR_MOVE_M_R SIZE_DWORD (f-source 15) const32) 2067 (sequence 2068 ((SI newval)) 2069 (set newval const32) 2070 (set Rd newval) 2071 (setf-move SI newval)) 2072) 2073 2074; (MOVS.z [PC+],Rd [ Rd | 1100011z | 1111 ]) 2075; Similarly, no likely net improvement for a dni-c-bw. 2076(dni-c-QI 2077 movscbr "movs.b [PC+],R" 2078 "movs.b ${sconst8},${Rd}" 2079 (+ Rd MODE_AUTOINCREMENT INDIR_MOVX SIGNED_BYTE (f-source 15) sconst8) 2080 (sequence 2081 ((SI newval)) 2082 ; FIXME: Make trunc unnecessary. 2083 (set newval (ext SI (trunc QI sconst8))) 2084 (set Rd newval) 2085 (setf-move SI newval)) 2086) 2087 2088(dni-c-HI 2089 movscwr "movs.w [PC+],R" 2090 "movs.w ${sconst16},${Rd}" 2091 (+ Rd MODE_AUTOINCREMENT INDIR_MOVX SIGNED_WORD (f-source 15) sconst16) 2092 (sequence 2093 ((SI newval)) 2094 ; FIXME: Make trunc unnecessary. 2095 (set newval (ext SI (trunc HI sconst16))) 2096 (set Rd newval) 2097 (setf-move SI newval)) 2098) 2099 2100; (MOVU.z [PC+],Rd [ Rd | 1100010z | 1111 ]) 2101(dni-c-QI 2102 movucbr "movu.b [PC+],R" 2103 "movu.b ${uconst8},${Rd}" 2104 (+ Rd MODE_AUTOINCREMENT INDIR_MOVX UNSIGNED_BYTE (f-source 15) uconst8) 2105 (sequence 2106 ((SI newval)) 2107 ; FIXME: Make trunc unnecessary. 2108 (set newval (zext SI (trunc QI uconst8))) 2109 (set Rd newval) 2110 (setf-move SI newval)) 2111) 2112 2113(dni-c-HI 2114 movucwr "movu.w [PC+],R" 2115 "movu.w ${uconst16},${Rd}" 2116 (+ Rd MODE_AUTOINCREMENT INDIR_MOVX UNSIGNED_WORD (f-source 15) uconst16) 2117 (sequence 2118 ((SI newval)) 2119 ; FIXME: Make trunc unnecessary. 2120 (set newval (zext SI (trunc HI uconst16))) 2121 (set Rd newval) 2122 (setf-move SI newval)) 2123) 2124 2125; ADDQ j,Rd [ Rd | 001000 | j ] 2126(dni-cdt 2127 addq "addq j,Rd" 2128 "addq $j,$Rd" 2129 (+ Rd MODE_QUICK_IMMEDIATE Q_ADDQ j) 2130 (cris-arit add SI Rd j) 2131) 2132 2133; SUBQ j,Rd [ Rd | 001010| j ] 2134(dni-cdt 2135 subq "subq j,Rd" 2136 "subq $j,$Rd" 2137 (+ Rd MODE_QUICK_IMMEDIATE Q_SUBQ j) 2138 (cris-arit sub SI Rd j) 2139) 2140 2141; Convenience macros for insns with a memory operand. 2142(define-pmacro 2143 (dni-cmt-attr-tim name comment attr syntax fmt semantics timing) 2144 "dni with memory-access" 2145 (dni name comment attr syntax 2146 ; Specifying MODE_INDIRECT and MODE_AUTOINCREMENT in this 2147 ; manner makes the autoincrementness handily available. 2148 ; It also effectively excludes non-memory use of dni-cmt. 2149 (.splice (.unsplice fmt) MODEMEMP_YES inc) 2150 semantics 2151 timing) 2152) 2153 2154(define-pmacro (dni-cmt-attr name comment attr syntax fmt semantics) 2155 "dni with read memory-access timing" 2156 (dni-cmt-attr-tim name comment attr syntax fmt semantics 2157 (cris-mem-timing)) 2158) 2159 2160(define-pmacro (dni-cmwt-attr name comment attr syntax fmt semantics) 2161 "dni with write memory-access timing" 2162 (dni-cmt-attr-tim name comment attr syntax fmt semantics 2163 (cris-mem-write-timing)) 2164) 2165 2166(define-pmacro QI-size 1) 2167(define-pmacro HI-size 2) 2168(define-pmacro SI-size 4) 2169 2170(define-pmacro (cris-get-mem size regop) 2171 "Handle reading memory in <size>, with source address register\ 2172 (read once, maybe set once) in <regop> or prefixed" 2173 (sequence 2174 size 2175 ((SI addr) (size tmp-mem) (BI postinc)) 2176 2177 ; Cache the incrementness of the operand. 2178 (set postinc inc) 2179 2180 ; Get the address from somewhere. 2181 (set addr 2182 (if SI (eq prefix-set 0) 2183 ; If the insn was prefixed, it's in the prefix-register. 2184 regop 2185 prefixreg)) 2186 2187 ; Get the memory contents. 2188 (set tmp-mem (mem size addr)) 2189 2190 ; For non-prefixed post-increment, we increment the address by the 2191 ; size of the memory access. 2192 (if (ne postinc 0) 2193 (sequence 2194 () 2195 (if (eq prefix-set 0) 2196 (set addr (add addr (.sym size -size)))) 2197 ; Update the source-register for post-increments. 2198 (set regop addr))) 2199 2200 ; Don't forget the return-value. 2201 tmp-mem) 2202) 2203 2204(define-pmacro (cris-set-mem size regop value) 2205 "Handle writing <value> of <size> to memory, with memory address register\ 2206 (read once, maybe set once) in <regop> or prefixed." 2207 (sequence 2208 ((SI addr) (BI postinc)) 2209 2210 ; Cache the incrementness of the operand. 2211 (set postinc inc) 2212 2213 ; Get the address from somewhere. 2214 (set addr 2215 (if SI (eq prefix-set 0) 2216 ; If the insn was prefixed, it's in the prefix-register. 2217 regop 2218 prefixreg)) 2219 2220 ; Set the memory contents. Integral-write semantics apply. 2221 ; FIXME: currently v32 only; when proper semantics needed, fix v10. 2222 (if (andif current-mach-is-v32 (ne xbit 0)) 2223 (if (eq pbit 0) 2224 (sequence 2225 () 2226 (set (mem size addr) value) 2227 ; Write failures are signalled (by whatever entity "sends 2228 ; the signal") by setting P at time of the write above, if X 2229 ; is set. Here, we just need to copy P into C. 2230 (set cbit pbit)) 2231 (set cbit 1)) 2232 (set (mem size addr) value)) 2233 2234 ; For non-prefixed post-increment, we increment the address by the 2235 ; size of the memory access. As for the integral-write, this needs to 2236 ; be tweaked for pre-v32: increment should have been performed if 2237 ; there's a fault at the memory access above. 2238 (if (ne postinc 0) 2239 (sequence 2240 () 2241 (if (eq prefix-set 0) 2242 (set addr (add addr (.sym size -size)))) 2243 ; Update the source-register for post-increments. 2244 (set regop addr)))) 2245) 2246 2247(define-pmacro 2248 (dni-cmt-bwd-attr-tim name comment attr syntax fmt fsem timing) 2249 "Core generator macro for insns with <op>.b, <op>.w and <op>.d variants\ 2250 and a memory operand." 2251 (begin 2252 (dni-cmt-attr-tim 2253 (.sym name .b-m) 2254 (.str "byte mem " comment) 2255 attr 2256 (.str name ".b " syntax) 2257 (.splice (.unsplice fmt) SIZE_BYTE) 2258 (fsem QI) 2259 timing) 2260 (dni-cmt-attr-tim 2261 (.sym name .w-m) 2262 (.str "word mem " comment) 2263 attr 2264 (.str name ".w " syntax) 2265 (.splice (.unsplice fmt) SIZE_WORD) 2266 (fsem HI) 2267 timing) 2268 (dni-cmt-attr-tim 2269 (.sym name .d-m) 2270 (.str "dword mem " comment) 2271 attr 2272 (.str name ".d " syntax) 2273 (.splice (.unsplice fmt) SIZE_DWORD) 2274 (fsem SI) 2275 timing)) 2276) 2277 2278; Further refinement macros. 2279(define-pmacro (dni-cmt-bwd-attr name comment attr syntax fmt fsem) 2280 (dni-cmt-bwd-attr-tim name comment attr syntax fmt fsem 2281 (cris-mem-timing)) 2282) 2283 2284(define-pmacro (dni-cmwt-bwd name comment syntax fmt fsem) 2285 (dni-cmt-bwd-attr-tim name comment () syntax fmt fsem 2286 (cris-mem-write-timing)) 2287) 2288 2289(define-pmacro (dni-cmt-bwd name comment syntax fmt fsem) 2290 (dni-cmt-bwd-attr name comment () syntax fmt fsem) 2291) 2292 2293(define-pmacro (dni-cmt-sbw name comment syntax fmt fsem) 2294 "Core generator macro for insns with <op>.b and <op>.w variants\ 2295 and a signed memory operand." 2296 (begin 2297 (dni-cmt-attr 2298 (.sym name .b-m) (.str "byte mem " comment) 2299 () 2300 (.str name ".b " syntax) 2301 (.splice (.unsplice fmt) SIGNED_BYTE) 2302 (fsem QI)) 2303 (dni-cmt-attr 2304 (.sym name .w-m) (.str "word mem " comment) 2305 () 2306 (.str name ".w " syntax) 2307 (.splice (.unsplice fmt) SIGNED_WORD) 2308 (fsem HI))) 2309) 2310 2311(define-pmacro (dni-cmt-ubw name comment syntax fmt fsem) 2312 "Core generator macro for insns with <op>.b and <op>.w variants\ 2313 and an unsigned memory operand." 2314 (begin 2315 (dni-cmt-attr 2316 (.sym name .b-m) (.str "byte mem " comment) 2317 () 2318 (.str name ".b " syntax) 2319 (.splice (.unsplice fmt) UNSIGNED_BYTE) 2320 (fsem QI)) 2321 (dni-cmt-attr 2322 (.sym name .w-m) (.str "word mem " comment) 2323 () 2324 (.str name ".w " syntax) 2325 (.splice (.unsplice fmt) UNSIGNED_WORD) 2326 (fsem HI))) 2327) 2328 2329; CMP.m Rs,Rd [ Rd | 011011mm | Rs ] 2330(dni-cdt-bwd 2331 cmp-r "compare register to register" 2332 "$Rs,$Rd" 2333 (+ Rd MODE_REGISTER R_CMP Rs) 2334 (.pmacro 2335 (BWD) 2336 (cris-arit6-int 2337 sub BWD (.pmacro (sz regno val) (nop)) 0 2338 Rd Rs cbit cbit)) 2339) 2340 2341; CMP.m [Rs],Rd [ Rd | 101011mm | Rs ] 2342; CMP.m [Rs+],Rd [ Rd | 111011mm | Rs ] 2343(dni-cmt-bwd 2344 cmp-m "compare memory to register" 2345 "[${Rs}${inc}],${Rd}" 2346 (+ INDIR_CMP Rs Rd) 2347 (.pmacro 2348 (BWD) 2349 (cris-arit6-int 2350 sub BWD (.pmacro (sz regno val) (nop)) 0 2351 Rd (cris-get-mem BWD Rs) cbit cbit)) 2352) 2353 2354; (CMP.m [PC+],Rd [ Rd | 111011mm | 1111 ]) 2355(dni-c-QI 2356 cmpcbr "cmp constant byte to register" 2357 "cmp.b $sconst8,$Rd" 2358 (+ Rd MODE_AUTOINCREMENT INDIR_CMP SIZE_BYTE (f-source 15) sconst8) 2359 (cris-arit6-int 2360 sub QI (.pmacro (sz regno val) (nop)) 0 2361 Rd (trunc QI sconst8) cbit cbit) 2362) 2363 2364(dni-c-HI 2365 cmpcwr "cmp constant word to register" 2366 "cmp.w $sconst16,$Rd" 2367 (+ Rd MODE_AUTOINCREMENT INDIR_CMP SIZE_WORD (f-source 15) sconst16) 2368 (cris-arit6-int 2369 sub HI (.pmacro (sz regno val) (nop)) 0 2370 Rd (trunc HI sconst16) cbit cbit) 2371) 2372 2373(dni-c-SI 2374 cmpcdr "cmp constant dword to register" 2375 "cmp.d $const32,$Rd" 2376 (+ Rd MODE_AUTOINCREMENT INDIR_CMP SIZE_DWORD (f-source 15) const32) 2377 (cris-arit6-int 2378 sub SI (.pmacro (sz regno val) (nop)) 0 2379 Rd const32 cbit cbit) 2380) 2381 2382; CMPQ i,Rd [ Rd | 001011 | i ] 2383(dni-cdt 2384 cmpq "cmpq i,Rd" 2385 "cmpq $i,$Rd" 2386 (+ Rd MODE_QUICK_IMMEDIATE Q_CMPQ i) 2387 (cris-arit6-int 2388 sub SI (.pmacro (sz regno val) (nop)) 0 2389 Rd i cbit cbit) 2390) 2391 2392; CMPS.z [Rs],Rd [ Rd | 1000111z | Rs ] 2393; CMPS.z [Rs+],Rd [ Rd | 1100111z | Rs ] 2394(dni-cmt-sbw 2395 cmps-m "cmp sign-extended from memory to register" 2396 "[${Rs}${inc}],$Rd" 2397 (+ Rd INDIR_CMPX Rs) 2398 (.pmacro 2399 (BW) 2400 (cris-arit6-int 2401 sub SI (.pmacro (sz regno val) (nop)) 0 2402 Rd ((.sym BW -ext) (cris-get-mem BW Rs)) cbit cbit)) 2403) 2404 2405; (CMPS.z [PC+],Rd [ Rd | 1100111z | 1111 ]) 2406(dni-c-QI 2407 cmpscbr "cmp sign-extended constant byte to register" 2408 "[${Rs}${inc}],$Rd" 2409 (+ Rd MODE_AUTOINCREMENT INDIR_CMPX SIGNED_BYTE (f-source 15) sconst8) 2410 (cris-arit6-int 2411 sub SI (.pmacro (sz regno val) (nop)) 0 2412 Rd (ext SI (trunc QI sconst8)) cbit cbit) 2413) 2414(dni-c-HI 2415 cmpscwr "cmp sign-extended constant word to register" 2416 "[${Rs}${inc}],$Rd" 2417 (+ Rd MODE_AUTOINCREMENT INDIR_CMPX SIGNED_WORD (f-source 15) sconst16) 2418 (cris-arit6-int 2419 sub SI (.pmacro (sz regno val) (nop)) 0 2420 Rd (ext SI (trunc HI sconst16)) cbit cbit) 2421) 2422 2423; CMPU.z [Rs],Rd [ Rd | 1000110z | Rs ] 2424; CMPU.z [Rs+],Rd [ Rd | 1100110z | Rs ] 2425(dni-cmt-ubw 2426 cmpu-m "cmp zero-extended from memory to register" 2427 "[${Rs}${inc}],$Rd" 2428 (+ Rd INDIR_CMPX Rs) 2429 (.pmacro 2430 (BW) 2431 (cris-arit6-int 2432 sub SI (.pmacro (sz regno val) (nop)) 0 2433 Rd ((.sym BW -zext) (cris-get-mem BW Rs)) cbit cbit)) 2434) 2435 2436; (CMPU.z [PC+],Rd [ Rd | 1100110z | 1111 ]) 2437(dni-c-QI 2438 cmpucbr "cmp zero-extended constant byte to register" 2439 "[${Rs}${inc}],$Rd" 2440 (+ Rd MODE_AUTOINCREMENT INDIR_CMPX UNSIGNED_BYTE (f-source 15) uconst8) 2441 (cris-arit6-int 2442 sub SI (.pmacro (sz regno val) (nop)) 0 2443 Rd (zext SI (trunc QI uconst8)) cbit cbit) 2444) 2445(dni-c-HI 2446 cmpucwr "cmp zero-extended constant word to register" 2447 "[${Rs}${inc}],$Rd" 2448 (+ Rd MODE_AUTOINCREMENT INDIR_CMPX UNSIGNED_WORD (f-source 15) uconst16) 2449 (cris-arit6-int 2450 sub SI (.pmacro (sz regno val) (nop)) 0 2451 Rd (zext SI (trunc HI uconst16)) cbit cbit) 2452) 2453 2454; MOVE.m [Rs],Rd [ Rd | 101001mm | Rs ] 2455; MOVE.m [Rs+],Rd [ Rd | 111001mm | Rs ] 2456(dni-cmt-bwd 2457 move-m "move from memory to register" 2458 "[${Rs}${inc}],${Rd}" 2459 (+ INDIR_MOVE_M_R Rs Rd) 2460 (.pmacro 2461 (BWD) 2462 (sequence 2463 ((SI tmp)) 2464 (set tmp (cris-get-mem BWD Rs)) 2465 (set-subreg-gr 2466 BWD 2467 (if SI (andif prefix-set (not inc)) (regno Rs) (regno Rd)) 2468 tmp) 2469 (setf-move BWD tmp))) 2470) 2471 2472; MOVS.z [Rs],Rd [ Rd | 1000011z | Rs ] 2473; MOVS.z [Rs+],Rd [ Rd | 1100011z | Rs ] 2474(dni-cmt-sbw 2475 movs-m "movs from memory to register" 2476 "[${Rs}${inc}],${Rd}" 2477 (+ INDIR_MOVX Rs Rd) 2478 (.pmacro 2479 (BW) 2480 (sequence 2481 ((SI tmp)) 2482 (set tmp (ext SI (cris-get-mem BW Rs))) 2483 (if (andif prefix-set (not inc)) 2484 (set Rs tmp) 2485 (set Rd tmp)) 2486 (setf-move SI tmp))) 2487) 2488 2489; MOVU.z [Rs],Rd [ Rd | 1000010z | Rs ] 2490; MOVU.z [Rs+],Rd [ Rd | 1100010z | Rs ] 2491(dni-cmt-ubw 2492 movu-m "movu from memory to register" 2493 "[${Rs}${inc}],${Rd}" 2494 (+ INDIR_MOVX Rs Rd) 2495 (.pmacro 2496 (BW) 2497 (sequence 2498 ((SI tmp)) 2499 (set tmp (zext SI (cris-get-mem BW Rs))) 2500 (if (andif prefix-set (not inc)) 2501 (set Rs tmp) 2502 (set Rd tmp)) 2503 (setf-move SI tmp))) 2504) 2505 2506; MOVE Rs,Pd [ Pd | 01100011 | Rs ] 2507(.splice 2508 begin 2509 (.unsplice 2510 (.map 2511 (.pmacro 2512 (VER) 2513 (dni 2514 (.sym move-r-spr VER) 2515 "Move from general register to special register" 2516 ((MACH (.sym cris VER))) 2517 "move ${Rs},${Pd}" 2518 (+ RFIX_MOVE_R_S MODE_REGISTER SIZE_FIXED Rs Pd) 2519 (sequence 2520 ((SI tmp) (SI rno)) 2521 (set tmp Rs) 2522 (set rno (regno Pd)) 2523 (cond 2524 ; See reg-sr setter for most of the special-register semantics. 2525 ; The sanity check for known read-only registers is for program 2526 ; debug help; the real insn would be harmless and have no effect. 2527 ; CGEN-FIXME: regno of symbolic h-sr names doesn't work here. 2528 ((orif (orif (eq rno 0) (eq rno 1)) (orif (eq rno 4) (eq rno 8))) 2529 (error "move-r-spr: trying to set a read-only special register")) 2530 (else (set Pd tmp))) 2531 (reset-x-p)) 2532 (cris-reg-sr-timing))) 2533 (cris-cpu-models))) 2534) 2535 2536(define-pmacro (dni-cdt-ver-attr name comment fattr syntax fmt fsem) 2537 "Generator for each MACH, using default timing." 2538 (.splice 2539 begin 2540 (.unsplice 2541 (.map 2542 (.pmacro (v) (dni-cdt-attr name comment (fattr v) syntax fmt (fsem v))) 2543 (cris-cpu-models)))) 2544) 2545 2546; MOVE Ps,Rd [ Ps | 01100111 | Rd ] 2547; Note that in the insn format, the Rd operand is in the Rs field (the 2548; Rd field by the definition used everywhere else is the Ps position in 2549; this insn). 2550; It gets a little weird here because we can't get this insn into a 2551; define-pmacro unless we make named pmacros for e.g. a separate attr 2552; function and a semantics function: a .pmacro can't refer to the 2553; parameters of the outer define-pmacro. (The manual refers to this as 2554; not implementing "lexical scoping"). 2555(.splice 2556 begin 2557 (.unsplice 2558 (.map 2559 (.pmacro 2560 (VER) 2561 (dni-cdt-attr 2562 (.sym move-spr-r VER) 2563 "Move from special register to general register" 2564 ((MACH (.sym cris VER))) 2565 "move ${Ps},${Rd-sfield}" 2566 (+ Ps RFIX_MOVE_S_R MODE_REGISTER SIZE_FIXED Rd-sfield) 2567 (sequence 2568 ((SI grno) (SI prno) (SI newval)) 2569 (set prno (regno Ps)) 2570 ; CGEN-FIXME: Can't use the following and then "grno" below because 2571 ; CGEN will emit a "tmp_grno" *also* in decodev32.c:crisv32f_decode 2572 ; (set grno (regno Rd-sfield)) 2573 (set newval Ps) 2574 (.splice 2575 cond 2576 (.unsplice 2577 (.map 2578 (.pmacro 2579 (r) 2580 ((eq prno (.cadr2 r)) 2581 (set-subreg-gr (.car2 r) (regno Rd-sfield) newval))) 2582 ((.sym cris-implemented-specregs- VER)))) 2583 (else (error "move-spr-r from unimplemented register"))) 2584 (reset-x-p)))) 2585 (cris-cpu-models))) 2586) 2587 2588; MOVE Ps,PC [ Ps | 01100111 | 1111 ] 2589; The move-special-register-to-pc insns are return-type instructions and 2590; have to be special-cased to get the delay-slot and avoid being indicated 2591; as invalid. 2592(dni-cdt-attr 2593 ret-type 2594 "ret-type" 2595 (MACH-PC) 2596 "ret/reti/retb" 2597 (+ Ps MODE_REGISTER RFIX_MOVE_S_R SIZE_FIXED (f-source 15)) 2598 (sequence 2599 ((SI retaddr)) 2600 (set retaddr Ps) 2601 (reset-x-p) 2602 (delay 1 (set pc retaddr))) 2603) 2604 2605; MOVE [Rs],Pd [ Pd | 10100011 | Rs ] 2606; MOVE [Rs+],Pd [ Pd | 11100011 | Rs ] 2607; We make variants that loads constants or memory for each MACH version, 2608; since each consider some subset of the "special registers" to have 2609; different sizes. FIXME: Should be able to simplify this. 2610(.splice 2611 begin 2612 (.unsplice 2613 (.map 2614 (.pmacro 2615 (VER) 2616 (dni 2617 (.sym move-m-spr VER) 2618 "Move from memory to special register" 2619 ((MACH (.sym cris VER))) 2620 "move [${Rs}${inc}],${Pd}" 2621 (+ Pd INFIX_MOVE_M_S MODEMEMP_YES inc SIZE_FIXED Rs) 2622 (sequence 2623 ((SI rno) (SI newval)) 2624 (set rno (regno Pd)) 2625 (.splice 2626 cond 2627 ; No sanity check for constant special register here, since the 2628 ; memory read side-effect or post-increment may be the goal, or 2629 ; for pre-v32 a prefix assignment side-effect. 2630 (.unsplice 2631 (.map 2632 (.pmacro 2633 (r) 2634 ((eq rno (.cadr2 r)) 2635 (set newval ((.sym (.car2 r) -ext) (cris-get-mem (.car2 r) Rs))))) 2636 ((.sym cris-implemented-specregs- VER)))) 2637 (else (error "Trying to set unimplemented special register"))) 2638 (set Pd newval) 2639 (reset-x-p)) 2640 (cris-mem-sr-timing))) 2641 (cris-cpu-models))) 2642) 2643 2644(define-pmacro QI-operand sconst8) 2645(define-pmacro HI-operand sconst16) 2646(define-pmacro SI-operand const32) 2647 2648(define-pmacro 2649 (cris-move-c-spr VER VERFN) 2650 "Generator for loading constant into special register" 2651 (.splice 2652 begin 2653 (.unsplice 2654 (.map 2655 (.pmacro 2656 (srdef v) 2657 (dni 2658 (.sym move-c-spr v -p (.cadr2 srdef)) 2659 (.str "Move constant to special register p" (.cadr2 srdef)) 2660 ((MACH (.sym cris v))) 2661 (.str "move ${" (.sym (.car2 srdef) -operand) "},${Pd}") 2662 ; We use Pd in semantics without naming it in the format (which 2663 ; would CGEN-FIXME: cause a CGEN error for some reason, likely 2664 ; related to specifying an insn field multiple times). This 2665 ; currently works and is guarded with test-cases (specifically 2666 ; wrt. the timing model) but may need to be tweaked in the future. 2667 ; Note that using instead (ifield f-dest) causes incorrect timing 2668 ; model to be generated; the timing model requires that Pd is set. 2669 (+ (f-dest (.cadr2 srdef)) MODE_AUTOINCREMENT INFIX_MOVE_M_S SIZE_FIXED 2670 (f-source 15) (.sym (.car2 srdef) -operand)) 2671 (sequence 2672 () 2673 (set Pd (.sym (.car2 srdef) -operand)) ; (reg h-sr (.cadr2 srdef)) 2674 (reset-x-p)) 2675 ((.sym cris-timing-const-sr- (.car2 srdef))))) 2676 ((.sym cris-implemented-specregs-const- VER)) 2677 (.map VERFN ((.sym cris-implemented-specregs-const- VER)))))) 2678) 2679 2680; CGEN-FIXME: 2681; Unfortunately we can't iterate over the list of models due to the 2682; problem with referring to the parameters of a surrounding pmacro from 2683; within an enclosed .pmacro (perhaps related to "lexical scoping"). 2684; We get e.g. 'insn already defined:: (move-c-sprvn-p0)' with this: 2685;(.splice 2686; begin (.unsplice (.map (.pmacro (vn) (cris-move-c-spr vn (.pmacro (x) vn))) 2687; (cris-cpu-models))) 2688;) 2689(cris-move-c-spr v0 (.pmacro (x) v0)) 2690(cris-move-c-spr v3 (.pmacro (x) v3)) 2691(cris-move-c-spr v8 (.pmacro (x) v8)) 2692(cris-move-c-spr v10 (.pmacro (x) v10)) 2693(cris-move-c-spr v32 (.pmacro (x) v32)) 2694 2695; MOVE Ps,[Rd] [ Ps | 10100111 | Rd ] 2696; MOVE Ps,[Rd+] [ Ps | 11100111 | Rd ] 2697(.splice 2698 begin 2699 (.unsplice 2700 (.map 2701 (.pmacro 2702 (VER) 2703 (dni-cmwt-attr 2704 (.sym move-spr-m VER) 2705 "Move from special register to memory" 2706 ((MACH (.sym cris VER))) 2707 "move ${Ps},[${Rd-sfield}${inc}]" 2708 (+ INFIX_MOVE_S_M SIZE_FIXED Rd-sfield Ps) 2709 (sequence 2710 ((SI rno)) 2711 (set rno (regno Ps)) 2712 (.splice 2713 cond 2714 (.unsplice 2715 (.map 2716 (.pmacro 2717 (r) 2718 ((eq rno (.cadr2 r)) 2719 (cris-set-mem (.car2 r) Rd-sfield Ps))) 2720 ((.sym cris-implemented-specregs- VER)))) 2721 (else (error "write from unimplemented special register"))) 2722 (reset-x-p)))) 2723 (cris-cpu-models))) 2724) 2725 2726; SBFS [Rs(+)] 2727; Instruction format: |0 0 1 1 1 m 1 1 0 1 1 1| Dest. | 2728(dni-cdt-attr 2729 sbfs 2730 "sbfs" 2731 ((MACH crisv10)) 2732 "sbfs [${Rd-sfield}${inc}]" 2733 (+ (f-dest 3) INFIX_SBFS SIZE_FIXED MODEMEMP_YES inc Rd-sfield) 2734 (error "SBFS isn't implemented") 2735) 2736 2737; MOVE Ss,Rd [ Ss | 11110111 | Rd ] 2738(dni-cdt-attr 2739 move-ss-r 2740 "move from support register to general register" 2741 (MACH-V32) 2742 "move ${Ss},${Rd-sfield}" 2743 (+ Ss INFIX_MOVE_SS SIZE_FIXED (f-mode 3) Rd-sfield) 2744 (sequence 2745 () 2746 (set Rd-sfield Ss) 2747 (reset-x-p)) 2748) 2749 2750; MOVE Rs,Sd [ Sd | 10110111 | Rs ] 2751(dni-cdt-attr 2752 move-r-ss 2753 "move from general register to support register" 2754 (MACH-V32) 2755 "move ${Rs},${Sd}" 2756 (+ Sd INFIX_MOVE_SS SIZE_FIXED (f-mode 2) Rs) 2757 (sequence 2758 () 2759 (set Sd Rs) 2760 (reset-x-p)) 2761) 2762 2763; MOVEM Rs,[Rd] [ Rs | 10111111 | Rd ] 2764; MOVEM Rs,[Rd+] [ Rs | 11111111 | Rd ] 2765 2766(define-pmacro (movem-to-mem-step regn) 2767 ; Without the SI attribute, UINT is generated, which isn't supported by 2768 ; the sim framework. 2769 (if (ge SI (regno Rs-dfield) regn) 2770 (sequence 2771 ((SI tmp)) 2772 (set tmp (reg h-gr regn)) 2773 (set (mem SI addr) tmp) 2774 (set addr (add addr 4)))) 2775) 2776 2777(dni 2778 movem-r-m 2779 "movem to memory" 2780 (MACH-PRE-V32) 2781 "movem ${Rs-dfield},[${Rd-sfield}${inc}]" 2782 (+ INFIX_MOVEM_R_M MODEMEMP_YES inc SIZE_FIXED Rs-dfield Rd-sfield) 2783 (sequence 2784 ((SI addr) (BI postinc)) 2785 ; FIXME: A copy of what's in cris-get-mem. 2786 2787 ; Cache the incrementness of the operand. 2788 (set postinc inc) 2789 2790 ; CGEN-FIXME: Kludge to work around a CGEN bug: it doesn't see that 2791 ; Rs-dfield is used as an input, causing the timing model to be wrong. 2792 (sequence ((SI dummy)) (set dummy Rs-dfield)) 2793 2794 ; Get the address from somewhere. If the insn was prefixed, it's in 2795 ; the prefix-register. 2796 (set addr 2797 (if SI (eq prefix-set 0) 2798 Rd-sfield 2799 prefixreg)) 2800 2801 (.splice 2802 sequence () 2803 (.unsplice (.map movem-to-mem-step (.iota 16 15 -1)))) 2804 2805 ; Update the source-register for post-increments. 2806 (if (ne postinc 0) 2807 (set Rd-sfield 2808 (if SI (eq prefix-set 0) addr prefixreg))) 2809 (reset-x-p)) 2810 (simplecris-movem-timing) 2811) 2812 2813(dni 2814 movem-r-m-v32 2815 "movem to memory" 2816 (MACH-V32) 2817 "movem ${Rs-dfield},[${Rd-sfield}${inc}]" 2818 (+ INFIX_MOVEM_R_M MODEMEMP_YES inc SIZE_FIXED Rs-dfield Rd-sfield) 2819 (sequence 2820 ((SI addr) (BI postinc)) 2821 ; FIXME: Mostly a copy of what's in cris-get-mem. 2822 2823 ; Cache the incrementness of the operand. 2824 (set postinc inc) 2825 2826 ; CGEN-FIXME: See movem-r-m. 2827 (sequence ((SI dummy)) (set dummy Rs-dfield)) 2828 2829 (set addr Rd-sfield) 2830 2831 (.splice 2832 sequence () 2833 (.unsplice (.map movem-to-mem-step (.iota 16)))) 2834 2835 ; Update the source-register for post-increments. 2836 (if (ne postinc 0) 2837 (set Rd-sfield addr)) 2838 (reset-x-p)) 2839 ; Unit u-mem must be specified before the u-movem-* for memory address 2840 ; register stall count to be right. 2841 ((crisv32 (unit u-mem) (unit u-movem-rtom) (unit u-exec-movem) 2842 (unit u-mem-w))) 2843) 2844 2845; MOVEM [Rs],Rd [ Rd | 10111011 | Rs ] 2846; MOVEM [Rs+],Rd [ Rd | 11111011 | Rs ] 2847 2848(define-pmacro 2849 (movem-to-reg-step regn) 2850 ; Without the SI attribute, UINT is generated, which isn't supported by 2851 ; the sim framework. 2852 (if (ge SI (regno Rd) regn) 2853 (sequence 2854 ((SI tmp)) 2855 (set tmp (mem SI addr)) 2856 (set (reg h-gr regn) tmp) 2857 (set addr (add addr 4)))) 2858) 2859 2860(dni 2861 movem-m-r 2862 "movem to register" 2863 (MACH-PRE-V32) 2864 "movem [${Rs}${inc}],${Rd}" 2865 (+ Rd INFIX_MOVEM_M_R MODEMEMP_YES inc SIZE_FIXED Rs) 2866 (sequence 2867 ((SI addr) (BI postinc)) 2868 ; FIXME: Mostly a copy of what's in cris-get-mem. 2869 2870 ; Cache the incrementness of the operand. 2871 (set postinc inc) 2872 2873 ; Get the address from somewhere. If the insn was prefixed, it's in 2874 ; the prefix-register. 2875 (set addr 2876 (if SI (eq prefix-set 0) 2877 Rs 2878 prefixreg)) 2879 2880 ; CGEN-FIXME: See movem-r-m. 2881 (sequence ((SI dummy)) (set dummy Rd)) 2882 2883 (.splice 2884 sequence () 2885 ; The first movem step is left out because it can't happen; it's for 2886 ; PC destination. See the pattern below. 2887 (.unsplice (.map movem-to-reg-step (.iota 15 14 -1)))) 2888 2889 ; Update the source-register for post-increments. 2890 ; FIXME: No postinc-prefixed for v0 IIRC. 2891 (if (ne postinc 0) 2892 (set Rs (if SI (eq prefix-set 0) addr prefixreg))) 2893 (reset-x-p)) 2894 (simplecris-movem-timing) 2895) 2896 2897; (MOVEM [Rs],PC [ 1111 | 10111011 | Rs ]) 2898; (MOVEM [Rs+],PC [ 1111 | 11111011 | Rs ]) 2899; We have to special-case it for PC destination; used in longjump. 2900; We shouldn't *have* to special-case it; the main reason is (FIXME:) 2901; misgeneration of the simulator when the PC case is folded into the 2902; generic PRE-V32 movem; possibly related to then being a COND-CTI rather 2903; than an UNCOND-CTI. 2904(dni-cmt-attr 2905 movem-m-pc 2906 "movem to register, ending with PC" 2907 (MACH-PRE-V32) 2908 "movem [${Rs}${inc}],${Rd}" 2909 (+ (f-dest 15) INFIX_MOVEM_M_R SIZE_FIXED Rs) 2910 (sequence 2911 ((SI addr) (BI postinc)) 2912 ; FIXME: Mostly a copy of what's in cris-get-mem. 2913 2914 ; Cache the incrementness of the operand. 2915 (set postinc inc) 2916 2917 ; Get the address from somewhere. If the insn was prefixed, it's in 2918 ; the prefix-register. 2919 (set addr 2920 (if SI (eq prefix-set 0) 2921 Rs 2922 prefixreg)) 2923 2924 ; FIXME: Add kludge here too *and* a test-case. 2925 2926 (.splice 2927 sequence () 2928 ; The first movem step is for PC destination, used in longjmp. 2929 (set pc (mem SI addr)) 2930 (set addr (add addr 4)) 2931 (.unsplice 2932 (.map 2933 (.pmacro 2934 (regn) 2935 (sequence 2936 ((SI tmp)) 2937 (set tmp (mem SI addr)) 2938 (set (reg h-gr regn) tmp) 2939 (set addr (add addr 4)))) 2940 (.iota 15 14 -1)))) 2941 2942 ; Update the source-register for post-increments. 2943 ; FIXME: No postinc-prefixed for v0. 2944 (if (ne postinc 0) 2945 (set Rs (if SI (eq prefix-set 0) addr prefixreg))) 2946 (reset-x-p)) 2947) 2948 2949(dni 2950 movem-m-r-v32 2951 "movem to register" 2952 (MACH-V32) 2953 "movem [${Rs}${inc}],${Rd}" 2954 (+ INFIX_MOVEM_M_R MODEMEMP_YES inc SIZE_FIXED Rs Rd) 2955 (sequence 2956 ((SI addr) (BI postinc)) 2957 ; FIXME: A copy of what's in cris-get-mem 2958 2959 ; Cache the incrementness of the operand. 2960 (set postinc inc) 2961 2962 ; Get the address from somewhere. 2963 (set addr Rs) 2964 2965 ; CGEN-FIXME: See movem-r-m. 2966 (sequence ((SI dummy)) (set dummy Rd)) 2967 2968 (.splice 2969 sequence () 2970 (.unsplice (.map movem-to-reg-step (.iota 16)))) 2971 2972 ; Update the source-register for post-increments. 2973 ; FIXME: No postinc-prefixed for v0 IIRC. 2974 (if (ne postinc 0) 2975 (set Rs addr)) 2976 (reset-x-p)) 2977 ; u-mem must be specified before the u-movem-* for memory source 2978 ; register stall count to be right. 2979 ((crisv32 (unit u-mem) (unit u-mem-r) (unit u-movem-mtor) 2980 (unit u-exec-movem))) 2981) 2982 2983; ADD.m Rs,Rd [ Rd | 011000mm | Rs ] 2984(dni-cdt-bwd 2985 add "add from register to register" 2986 "$Rs,$Rd" 2987 (+ Rd MODE_REGISTER R_ADD Rs) 2988 (.pmacro (BWD) (cris-arit add BWD Rd Rs)) 2989) 2990 2991; ADD.m [Rs],Rd [ Rd | 101000mm | Rs ] 2992; ADD.m [Rs+],Rd [ Rd | 111000mm | Rs ] 2993(dni-cmt-bwd 2994 add-m "add from memory to register" 2995 "[${Rs}${inc}],${Rd}" 2996 (+ INDIR_ADD Rs Rd) 2997 (.pmacro (BWD) (cris-arit-3op add BWD Rd (cris-get-mem BWD Rs) Rs)) 2998) 2999; (ADD.m [PC+],Rd [ Rd | 111000mm | 1111 ]) 3000(dni-c-QI 3001 addcbr "add constant byte to register" 3002 "add.b ${sconst8}],${Rd}" 3003 (+ Rd MODE_AUTOINCREMENT INDIR_ADD SIZE_BYTE (f-source 15) sconst8) 3004 (cris-arit add QI Rd sconst8) 3005) 3006 3007(dni-c-HI 3008 addcwr "add constant word to register" 3009 "add.w ${sconst16}],${Rd}" 3010 (+ Rd MODE_AUTOINCREMENT INDIR_ADD SIZE_WORD (f-source 15) sconst16) 3011 (cris-arit add HI Rd sconst16) 3012) 3013 3014(dni-c-SI 3015 addcdr "add constant dword to register" 3016 "add.d ${const32}],${Rd}" 3017 (+ Rd MODE_AUTOINCREMENT INDIR_ADD SIZE_DWORD (f-source 15) const32) 3018 (cris-arit add SI Rd const32) 3019) 3020 3021; (ADD.D [PC+],PC [ 1111 | 11100010 | 1111 ]) 3022; This insn is used for DSO-local jumps in PIC code. 3023(dni 3024 addcpc "Relative jump by adding constant to PC" 3025 (MACH-PC) 3026 "add.d ${sconst32},PC" 3027 (+ (f-dest 15) MODE_AUTOINCREMENT INDIR_ADD SIZE_DWORD (f-source 15) const32) 3028 (sequence 3029 ((SI newpc) (SI oldpc) (SI offs)) 3030 (set offs const32) 3031 (set oldpc (add SI pc 6)) 3032 (set newpc (add SI oldpc offs)) 3033 (set pc newpc) 3034 (setf-arit SI add oldpc offs newpc cbit)) 3035 (simplecris-common-timing ((unit u-const32) (unit u-stall) (unit u-exec))) 3036) 3037 3038; ADDS.z Rs,Rd [ Rd | 0100001z | Rs ] 3039(dni-cdt-sbw 3040 adds "add sign-extended from register to register" 3041 "$Rs,$Rd" 3042 (+ Rd MODE_REGISTER R_ADDX Rs) 3043 (.pmacro (BW) (cris-arit add SI Rd ((.sym BW -ext) (trunc BW Rs)))) 3044) 3045 3046; ADDS.z [Rs],Rd [ Rd | 1000001z | Rs ] 3047; ADDS.z [Rs+],Rd [ Rd | 1100001z | Rs ] 3048(dni-cmt-sbw 3049 adds-m "add sign-extended from memory to register" 3050 "[${Rs}${inc}],$Rd" 3051 (+ Rd INDIR_ADDX Rs) 3052 (.pmacro (BW) (cris-arit-3op add SI Rd ((.sym BW -ext) (cris-get-mem BW Rs)) Rs)) 3053) 3054 3055; (ADDS.z [PC+],Rd [ Rd | 1100001z | 1111 ]) 3056(dni-c-QI 3057 addscbr "add sign-extended constant byte to register" 3058 "[${Rs}${inc}],$Rd" 3059 (+ Rd MODE_AUTOINCREMENT INDIR_ADDX SIGNED_BYTE (f-source 15) sconst8) 3060 (cris-arit add SI Rd (ext SI (trunc QI sconst8))) 3061) 3062(dni-c-HI 3063 addscwr "add sign-extended constant word to register" 3064 "[${Rs}${inc}],$Rd" 3065 (+ Rd MODE_AUTOINCREMENT INDIR_ADDX SIGNED_WORD (f-source 15) sconst16) 3066 (cris-arit add SI Rd (ext SI (trunc HI sconst16))) 3067) 3068 3069; (ADDS.w [],PC [ 1111 | 10000011 | 1111 ]) 3070; For a PC destination, we support only the two-operand case 3071; (dest == src), which is used in switch/case statements. 3072; FIXME: Should implement ADD.D [PC],PC and ADDS.B [PC],PC for use if/when 3073; implementing CASE_VECTOR_SHORTEN_MODE. 3074(dni 3075 addspcpc "add sign-extended prefixed arg to PC" 3076 (MACH-PC) 3077 "adds.w [PC],PC" 3078 (+ (f-dest 15) MODE_INDIRECT INDIR_ADDX SIGNED_WORD (f-source 15)) 3079 (sequence 3080 ((SI newpc) (SI oldpc) (HI offs)) 3081 (if (not prefix-set) 3082 (error "Unexpected adds.w [PC],PC without prefix")) 3083 ; We don't use cris-get-mem but instead special-case this one, since we 3084 ; have most instruction fields fixed where cris-get-mem expects 3085 ; field-parametrization by certain names. 3086 (set offs (mem HI prefixreg)) 3087 (set oldpc (add SI pc 2)) 3088 (set newpc (add SI oldpc offs)) 3089 (set pc newpc) 3090 (setf-arit SI add oldpc (ext SI offs) newpc cbit)) 3091 (simplecris-common-timing ((unit u-mem) (unit u-stall) (unit u-exec))) 3092) 3093 3094; ADDU.z Rs,Rd [ Rd | 0100000z | Rs ] 3095(dni-cdt-ubw 3096 addu "add zero-extended from register to register" 3097 "$Rs,$Rd" 3098 (+ Rd MODE_REGISTER R_ADDX Rs) 3099 (.pmacro (BW) (cris-arit add SI Rd ((.sym BW -zext) (trunc BW Rs)))) 3100) 3101 3102; ADDU.z [Rs],Rd [ Rd | 1000000z | Rs ] 3103; ADDU.z [Rs+],Rd [ Rd | 1100000z | Rs ] 3104(dni-cmt-ubw 3105 addu-m "add zero-extended from memory to register" 3106 "[${Rs}${inc}],$Rd" 3107 (+ Rd INDIR_ADDX Rs) 3108 (.pmacro (BW) 3109 (cris-arit-3op add SI Rd ((.sym BW -zext) (cris-get-mem BW Rs)) Rs)) 3110) 3111 3112; (ADDU.z [PC+],Rd [ Rd | 1100000z | 1111 ]) 3113(dni-c-QI 3114 adducbr "add zero-extended constant byte to register" 3115 "[${Rs}${inc}],$Rd" 3116 (+ Rd MODE_AUTOINCREMENT INDIR_ADDX UNSIGNED_BYTE (f-source 15) sconst8) 3117 (cris-arit add SI Rd (zext SI (trunc QI sconst8))) 3118) 3119(dni-c-HI 3120 adducwr "add zero-extended constant word to register" 3121 "[${Rs}${inc}],$Rd" 3122 (+ Rd MODE_AUTOINCREMENT INDIR_ADDX UNSIGNED_WORD (f-source 15) sconst16) 3123 (cris-arit add SI Rd (zext SI (trunc HI sconst16))) 3124) 3125 3126; SUB.m Rs,Rd [ Rd | 011010mm | Rs ] 3127(dni-cdt-bwd 3128 sub "subtract from register to register" 3129 "$Rs,$Rd" 3130 (+ Rd MODE_REGISTER R_SUB Rs) 3131 (.pmacro (BWD) (cris-arit sub BWD Rd Rs)) 3132) 3133 3134; SUB.m [Rs],Rd [ Rd | 101010mm | Rs ] 3135; SUB.m [Rs+],Rd [ Rd | 111010mm | Rs ] 3136(dni-cmt-bwd 3137 sub-m "subtract from memory to register" 3138 "[${Rs}${inc}],${Rd}" 3139 (+ INDIR_SUB Rs Rd) 3140 (.pmacro (BWD) (cris-arit-3op sub BWD Rd (cris-get-mem BWD Rs) Rs)) 3141) 3142 3143; (SUB.m [PC+],Rd [ Rd | 111010mm | 1111 ] 3144(dni-c-QI 3145 subcbr "subtract constant byte from register" 3146 "sub.b ${sconst8}],${Rd}" 3147 (+ Rd MODE_AUTOINCREMENT INDIR_SUB SIZE_BYTE (f-source 15) sconst8) 3148 (cris-arit sub QI Rd sconst8) 3149) 3150 3151(dni-c-HI 3152 subcwr "subtract constant word from register" 3153 "sub.w ${sconst16}],${Rd}" 3154 (+ Rd MODE_AUTOINCREMENT INDIR_SUB SIZE_WORD (f-source 15) sconst16) 3155 (cris-arit sub HI Rd sconst16) 3156) 3157 3158(dni-c-SI 3159 subcdr "subtract constant dword from register" 3160 "sub.d ${const32}],${Rd}" 3161 (+ Rd MODE_AUTOINCREMENT INDIR_SUB SIZE_DWORD (f-source 15) const32) 3162 (cris-arit sub SI Rd const32) 3163) 3164 3165; SUBS.z Rs,Rd [ Rd | 0100101z | Rs ] 3166(dni-cdt-sbw 3167 subs "sub sign-extended from register to register" 3168 "$Rs,$Rd" 3169 (+ Rd MODE_REGISTER R_SUBX Rs) 3170 (.pmacro (BW) (cris-arit sub SI Rd ((.sym BW -ext) (trunc BW Rs)))) 3171) 3172 3173; SUBS.z [Rs],Rd [ Rd | 1000101z | Rs ] 3174; SUBS.z [Rs+],Rd [ Rd | 1100101z | Rs ] 3175(dni-cmt-sbw 3176 subs-m "sub sign-extended from memory to register" 3177 "[${Rs}${inc}],$Rd" 3178 (+ Rd INDIR_SUBX Rs) 3179 (.pmacro (BW) 3180 (cris-arit-3op sub SI Rd ((.sym BW -ext) (cris-get-mem BW Rs)) Rs)) 3181) 3182 3183; (SUBS.z [PC+],Rd [ Rd | 1100101z | 1111 ]) 3184(dni-c-QI 3185 subscbr "sub sign-extended constant byte to register" 3186 "[${Rs}${inc}],$Rd" 3187 (+ Rd MODE_AUTOINCREMENT INDIR_SUBX SIGNED_BYTE (f-source 15) sconst8) 3188 (cris-arit sub SI Rd (ext SI (trunc QI sconst8))) 3189) 3190(dni-c-HI 3191 subscwr "sub sign-extended constant word to register" 3192 "[${Rs}${inc}],$Rd" 3193 (+ Rd MODE_AUTOINCREMENT INDIR_SUBX SIGNED_WORD (f-source 15) sconst16) 3194 (cris-arit sub SI Rd (ext SI (trunc HI sconst16))) 3195) 3196 3197; SUBU.z Rs,Rd [ Rd | 0100100z | Rs ] 3198(dni-cdt-ubw 3199 subu "sub zero-extended from register to register" 3200 "$Rs,$Rd" 3201 (+ Rd MODE_REGISTER R_SUBX Rs) 3202 (.pmacro (BW) (cris-arit sub SI Rd ((.sym BW -zext) (trunc BW Rs)))) 3203) 3204 3205; SUBU.z [Rs],Rd [ Rd | 1000100z | Rs ] 3206; SUBU.z [Rs+],Rd [ Rd | 1100100z | Rs ] 3207(dni-cmt-ubw 3208 subu-m "sub zero-extended from memory to register" 3209 "[${Rs}${inc}],$Rd" 3210 (+ Rd INDIR_SUBX Rs) 3211 (.pmacro (BW) 3212 (cris-arit-3op sub SI Rd ((.sym BW -zext) (cris-get-mem BW Rs)) Rs)) 3213) 3214 3215; (SUBU.z [PC+],Rd [ Rd | 1100100z | 1111 ]) 3216(dni-c-QI 3217 subucbr "sub zero-extended constant byte to register" 3218 "[${Rs}${inc}],$Rd" 3219 (+ Rd MODE_AUTOINCREMENT INDIR_SUBX UNSIGNED_BYTE (f-source 15) sconst8) 3220 (cris-arit sub SI Rd (zext SI (trunc QI sconst8))) 3221) 3222(dni-c-HI 3223 subucwr "sub zero-extended constant word to register" 3224 "[${Rs}${inc}],$Rd" 3225 (+ Rd MODE_AUTOINCREMENT INDIR_SUBX UNSIGNED_WORD (f-source 15) sconst16) 3226 (cris-arit sub SI Rd (zext SI (trunc HI sconst16))) 3227) 3228 3229; ADDC Rs,Rd [ Rd | 01010111 | Rs ] 3230(dni-cdt-attr 3231 addc-r "addc from register to register" 3232 (MACH-V32) 3233 "addc $Rs,$Rd" 3234 (+ Rd MODE_REGISTER RFIX_ADDC SIZE_FIXED Rs) 3235 ; Since this is equivalent to "ax" plus "add.d Rs,Rd", we'll just do 3236 ; that, semantically. 3237 (sequence 3238 () 3239 (set-quiet xbit 1) 3240 (cris-arit add SI Rd Rs)) 3241) 3242 3243; ADDC [Rs],Rd [ Rd | 10011010 | Rs ] 3244; ADDC [Rs+],Rd [ Rd | 11011010 | Rs ] 3245(dni-cmt-attr 3246 addc-m "addc from memory to register" 3247 (MACH-V32) 3248 "addc [${Rs}${inc}],${Rd}" 3249 (+ Rd INDIR_ADDC SIZE_DWORD Rs) 3250 (sequence 3251 () 3252 (set-quiet xbit 1) 3253 (cris-arit add SI Rd (cris-get-mem SI Rs))) 3254) 3255 3256; (ADDC [Rs+],Rd [ Rd | 11011010 | 1111 ]) 3257(dni-c-SI-attr 3258 addc-c "addc constant to register" 3259 (MACH-V32) 3260 "addc ${const32},${Rd}" 3261 (+ Rd MODE_AUTOINCREMENT INDIR_ADDC SIZE_DWORD (f-source 15) const32) 3262 (sequence 3263 () 3264 (set-quiet xbit 1) 3265 (cris-arit add SI Rd const32)) 3266) 3267 3268; LAPC [PC+],Rd [ Rd | 11010111 1111 ] 3269(dni-c-SI-attr 3270 lapc-d "lapc.d" 3271 (MACH-V32) 3272 "lapc.d ${const32-pcrel},${Rd}" 3273 (+ Rd MODE_AUTOINCREMENT INFIX_LAPC SIZE_FIXED (f-source 15) const32-pcrel) 3274 (sequence 3275 () 3276 (set Rd const32-pcrel) 3277 (reset-x-p)) 3278) 3279 3280; LAPCQ qo,Rd [ Rd | 10010111 | qo ] 3281(dni-cdt-attr 3282 lapcq "lapcq" 3283 (MACH-V32) 3284 "lapcq ${qo},${Rd}" 3285 (+ Rd MODE_INDIRECT INFIX_LAPC SIZE_FIXED qo) 3286 (sequence 3287 () 3288 (set Rd qo) 3289 (reset-x-p)) 3290) 3291 3292; ADDI Rs.m,Rd [ Rs | 010100mm | Rd ] 3293(dni-cdt-bwd 3294 addi "addi" 3295 "${Rs-dfield}.m,${Rd-sfield}" 3296 (+ Rd-sfield MODE_REGISTER R_ADDI Rs-dfield) 3297 (.pmacro 3298 (BWD) 3299 (sequence 3300 () 3301 (set Rd-sfield (add SI Rd-sfield (mul Rs-dfield (.sym BWD -size)))) 3302 (reset-x-p))) 3303) 3304 3305; NEG.m Rs,Rd [ Rd | 010110mm | Rs ] 3306(dni-cdt-bwd 3307 neg "neg.m Rs,Rd" 3308 "$Rs,$Rd" 3309 (+ Rd MODE_REGISTER R_NEG Rs) 3310 (.pmacro (BWD) (cris-arit3 sub BWD Rd 0 Rs)) 3311) 3312 3313; TEST.m [Rs] [ 0000101110mm | Rs ] 3314; TEST.m [Rs+] [ 0000111110mm | Rs ] 3315(dni-cmt-bwd 3316 test-m "test.m [Rs(+)]" 3317 "[${Rs}${inc}]" 3318 (+ (f-dest 0) INDIR_TEST Rs) 3319 (.pmacro 3320 (BWD) 3321 (sequence 3322 ((BWD tmpd)) 3323 (set tmpd (cris-get-mem BWD Rs)) 3324 ; This is supposed to be the same result as for cmpq 0,X, hence same code. 3325 (cris-arit6-int 3326 sub BWD (.pmacro (sz regno val) (nop)) 0 tmpd 0 cbit cbit))) 3327) 3328 3329; MOVE.m Rs,[Rd] [ Rs | 101111mm | Rd ] 3330; MOVE.m Rs,[Rd+] [ Rs | 111111mm | Rd ] 3331 3332(dni-cmwt-bwd 3333 move-r-m "move.m R,[]" 3334 "${Rs-dfield},[${Rd-sfield}${inc}]" 3335 (+ Rs-dfield INDIR_MOVE_R_M Rd-sfield) 3336 (.pmacro 3337 (BWD) 3338 (sequence 3339 ((BWD tmpd)) 3340 (set tmpd Rs-dfield) 3341 (cris-set-mem BWD Rd-sfield tmpd) 3342 (reset-x-p))) 3343) 3344 3345; MULS.m Rs,Rd [ Rd | 110100mm | Rs ] 3346(dni-bwd-attr 3347 muls "muls.m Rs,Rd" 3348 ((MACH crisv10,crisv32)) 3349 "$Rs,$Rd" 3350 (+ Rd MODE_MULS INDIR_MUL Rs) 3351 (.pmacro 3352 (BWD) 3353 (sequence 3354 ((DI src1) (DI src2) (DI tmpr)) 3355 (set src1 (ext DI (trunc BWD Rs))) 3356 (set src2 (ext DI (trunc BWD Rd))) 3357 (set tmpr (mul src1 src2)) 3358 (set Rd (trunc SI tmpr)) 3359 (set mof (trunc SI (srl tmpr 32))) 3360 (setf-arit DI muls src1 src2 tmpr cbit))) 3361 ((crisv10 (unit u-multiply) (unit u-exec)) 3362 (crisv32 (unit u-multiply) (unit u-exec))) 3363) 3364 3365; MULU.m Rs,Rd [ Rd | 100100mm | Rs ] 3366(dni-bwd-attr 3367 mulu "mulu.m Rs,Rd" 3368 ((MACH crisv10,crisv32)) 3369 "$Rs,$Rd" 3370 (+ Rd MODE_MULU INDIR_MUL Rs) 3371 (.pmacro 3372 (BWD) 3373 (sequence 3374 ((DI src1) (DI src2) (DI tmpr)) 3375 (set src1 (zext DI (trunc BWD Rs))) 3376 (set src2 (zext DI (trunc BWD Rd))) 3377 (set tmpr (mul src1 src2)) 3378 (set Rd (trunc SI tmpr)) 3379 (set mof (trunc SI (srl tmpr 32))) 3380 (setf-arit DI mulu src1 src2 tmpr cbit))) 3381 ((crisv10 (unit u-multiply) (unit u-exec)) 3382 (crisv32 (unit u-multiply) (unit u-exec))) 3383) 3384 3385; MCP Ps,Rd [ Ps | 01111111 | Rd ] 3386(dni-cdt-attr 3387 mcp "Multiply Carry Propagation" 3388 (MACH-V32) 3389 "mcp $Ps,$Rd" 3390 (+ Ps MODE_REGISTER RFIX_MCP SIZE_FIXED Rd-sfield) 3391 (sequence 3392 () 3393 (set-quiet xbit 1) 3394 (set-quiet zbit 1) 3395 (cris-arit5 add SI Rd-sfield Rd-sfield Ps rbit rbit)) 3396) 3397 3398; MSTEP Rs,Rd [ Rd | 01111111 | Rs ] 3399(dni-cdt-attr 3400 mstep "Multiply step" 3401 (MACH-PRE-V32) 3402 "mstep $Rs,$Rd" 3403 (+ Rd MODE_REGISTER RFIX_MSTEP SIZE_FIXED Rs) 3404 (sequence 3405 ((SI tmpd) (SI tmps)) 3406 (set tmps Rs) 3407 (set tmpd (add (sll Rd 1) (if SI nbit tmps 0))) 3408 (set Rd tmpd) 3409 (setf-move SI tmpd)) 3410) 3411 3412; DSTEP Rs,Rd [ Rd | 01101111 | Rs ] 3413(dni-cdt 3414 dstep "Division step" 3415 "dstep $Rs,$Rd" 3416 (+ Rd MODE_REGISTER RFIX_DSTEP SIZE_FIXED Rs) 3417 (sequence 3418 ((SI tmp) (SI tmps) (SI tmpd)) 3419 (set tmps Rs) 3420 (set tmp (sll Rd 1)) 3421 (set tmpd (if SI (geu tmp tmps) (sub tmp tmps) tmp)) 3422 (set Rd tmpd) 3423 (setf-move SI tmpd)) 3424) 3425 3426; ABS Rs,Rd [ Rd | 01101011 | Rs ] 3427(dni-cdt 3428 abs "Absolut Instruction" 3429 "abs $Rs,$Rd" 3430 (+ Rd MODE_REGISTER RFIX_ABS SIZE_FIXED Rs) 3431 (sequence 3432 ((SI tmpd)) 3433 (set tmpd (abs Rs)) 3434 (set Rd tmpd) 3435 (setf-move SI tmpd)) 3436) 3437 3438; AND.m Rs,Rd [ Rd | 011100mm | Rs ] 3439(dni-cdt-bwd 3440 and "And from register to register" 3441 "$Rs,$Rd" 3442 (+ Rd MODE_REGISTER R_AND Rs) 3443 (.pmacro 3444 (BWD) 3445 (sequence 3446 ((BWD tmpd)) 3447 (set tmpd (and BWD Rd Rs)) 3448 (set-subreg-gr BWD (regno Rd) tmpd) 3449 (setf-move BWD tmpd))) 3450) 3451 3452; AND.m [Rs],Rd [ Rd | 101100mm | Rs ] 3453; AND.m [Rs+],Rd [ Rd | 111100mm | Rs ] 3454(dni-cmt-bwd 3455 and-m "And from memory to register" 3456 "[${Rs}${inc}],${Rd}" 3457 (+ INDIR_AND Rs Rd) 3458 (.pmacro 3459 (BWD) 3460 (sequence 3461 ((BWD tmpd)) 3462 (set tmpd (and BWD Rd (cris-get-mem BWD Rs))) 3463 (set-subreg-gr 3464 BWD 3465 (if SI (andif prefix-set (not inc)) (regno Rs) (regno Rd)) 3466 tmpd) 3467 (setf-move BWD tmpd))) 3468) 3469 3470; (AND.m [PC+],Rd [ Rd | 111100mm | 1111 ]) 3471(dni-c-QI 3472 andcbr "And constant byte to register" 3473 "and.b ${sconst8}],${Rd}" 3474 (+ Rd MODE_AUTOINCREMENT INDIR_AND SIZE_BYTE (f-source 15) sconst8) 3475 (sequence 3476 ((QI tmpd)) 3477 (set tmpd (and QI Rd sconst8)) 3478 (set-subreg-gr QI (regno Rd) tmpd) 3479 (setf-move QI tmpd)) 3480) 3481 3482(dni-c-HI 3483 andcwr "And constant word to register" 3484 "and.w ${sconst16}],${Rd}" 3485 (+ Rd MODE_AUTOINCREMENT INDIR_AND SIZE_WORD (f-source 15) sconst16) 3486 (sequence 3487 ((HI tmpd)) 3488 (set tmpd (and HI Rd sconst16)) 3489 (set-subreg-gr HI (regno Rd) tmpd) 3490 (setf-move HI tmpd)) 3491) 3492 3493(dni-c-SI 3494 andcdr "And constant dword to register" 3495 "and.d ${const32}],${Rd}" 3496 (+ Rd MODE_AUTOINCREMENT INDIR_AND SIZE_DWORD (f-source 15) const32) 3497 (sequence 3498 ((SI tmpd)) 3499 (set tmpd (and SI Rd const32)) 3500 (set-subreg-gr SI (regno Rd) tmpd) 3501 (setf-move SI tmpd)) 3502) 3503 3504; ANDQ i,Rd [ Rd | 001100 | i ] 3505(dni-cdt 3506 andq "And quick-immediate to register" 3507 "andq $i,$Rd" 3508 (+ Rd MODE_QUICK_IMMEDIATE Q_ANDQ i) 3509 (sequence 3510 ((SI tmpd)) 3511 (set tmpd (and SI Rd i)) 3512 (set-subreg-gr SI (regno Rd) tmpd) 3513 (setf-move SI tmpd)) 3514) 3515 3516; OR.m Rs,Rd [ Rd | 011101mm | Rs ] 3517(dni-cdt-bwd 3518 orr "Or from register to register" 3519 "$Rs,$Rd" 3520 (+ Rd MODE_REGISTER R_OR Rs) 3521 (.pmacro 3522 (BWD) 3523 (sequence 3524 ((BWD tmpd)) 3525 (set tmpd (or BWD Rd Rs)) 3526 (set-subreg-gr BWD (regno Rd) tmpd) 3527 (setf-move BWD tmpd))) 3528) 3529 3530; OR.m [Rs],Rd [ Rd | 101101mm | Rs ] 3531; OR.m [Rs+],Rd [ Rd | 111101mm | Rs ] 3532(dni-cmt-bwd 3533 or-m "Or from memory to register" 3534 "[${Rs}${inc}],${Rd}" 3535 (+ INDIR_OR Rs Rd) 3536 (.pmacro 3537 (BWD) 3538 (sequence 3539 ((BWD tmpd)) 3540 (set tmpd (or BWD Rd (cris-get-mem BWD Rs))) 3541 (set-subreg-gr 3542 BWD 3543 (if SI (andif prefix-set (not inc)) (regno Rs) (regno Rd)) 3544 tmpd) 3545 (setf-move BWD tmpd))) 3546) 3547 3548; (OR.m [PC+],Rd [ Rd | 111101mm | 1111 ]) 3549(dni-c-QI 3550 orcbr "Or constant byte to register" 3551 "or.b ${sconst8}],${Rd}" 3552 (+ Rd MODE_AUTOINCREMENT INDIR_OR SIZE_BYTE (f-source 15) sconst8) 3553 (sequence 3554 ((QI tmpd)) 3555 (set tmpd (or QI Rd sconst8)) 3556 (set-subreg-gr QI (regno Rd) tmpd) 3557 (setf-move QI tmpd)) 3558) 3559 3560(dni-c-HI 3561 orcwr "Or constant word to register" 3562 "or.w ${sconst16}],${Rd}" 3563 (+ Rd MODE_AUTOINCREMENT INDIR_OR SIZE_WORD (f-source 15) sconst16) 3564 (sequence 3565 ((HI tmpd)) 3566 (set tmpd (or HI Rd sconst16)) 3567 (set-subreg-gr HI (regno Rd) tmpd) 3568 (setf-move HI tmpd)) 3569) 3570 3571(dni-c-SI 3572 orcdr "Or constant dword to register" 3573 "or.d ${const32}],${Rd}" 3574 (+ Rd MODE_AUTOINCREMENT INDIR_OR SIZE_DWORD (f-source 15) const32) 3575 (sequence 3576 ((SI tmpd)) 3577 (set tmpd (or SI Rd const32)) 3578 (set-subreg-gr SI (regno Rd) tmpd) 3579 (setf-move SI tmpd)) 3580) 3581 3582; ORQ i,Rd [ Rd | 001101 | i ] 3583(dni-cdt 3584 orq "Or quick-immediate to register" 3585 "orq $i,$Rd" 3586 (+ Rd MODE_QUICK_IMMEDIATE Q_ORQ i) 3587 (sequence 3588 ((SI tmpd)) 3589 (set tmpd (or SI Rd i)) 3590 (set-subreg-gr SI (regno Rd) tmpd) 3591 (setf-move SI tmpd)) 3592) 3593 3594; XOR Rs,Rd [ Rd | 01111011 | Rs ] 3595(dni-cdt 3596 xor "Xor from register to register" 3597 "xor $Rs,$Rd" 3598 (+ Rd MODE_REGISTER RFIX_XOR SIZE_FIXED Rs) 3599 (sequence 3600 ((SI tmpd)) 3601 (set tmpd (xor SI Rd Rs)) 3602 (set Rd tmpd) 3603 (setf-move SI tmpd)) 3604) 3605 3606(define-pmacro (swap-r x) 3607 "Perform bit-wise swap within each byte" 3608 (sequence 3609 SI 3610 ((SI tmpr)) 3611 (set tmpr x) 3612 (or (sll (and tmpr #x1010101) 7) 3613 (or (sll (and tmpr #x2020202) 5) 3614 (or (sll (and tmpr #x4040404) 3) 3615 (or (sll (and tmpr #x8080808) 1) 3616 (or (srl (and tmpr #x10101010) 1) 3617 (or (srl (and tmpr #x20202020) 3) 3618 (or (srl (and tmpr #x40404040) 5) 3619 (srl (and tmpr #x80808080) 7))))))))) 3620) 3621 3622(define-pmacro (swap-b x) 3623 "Perform byte-wise swap within each word" 3624 (sequence 3625 SI 3626 ((SI tmpb)) 3627 (set tmpb x) 3628 (or (and (sll tmpb 8) #xff00ff00) 3629 (and (srl tmpb 8) #xff00ff))) 3630) 3631 3632(define-pmacro (swap-w x) 3633 "Perform word-wise swap within each dword" 3634 (sequence 3635 SI 3636 ((SI tmpb)) 3637 (set tmpb x) 3638 (or (and (sll tmpb 16) #xffff0000) 3639 (and (srl tmpb 16) #xffff))) 3640) 3641 3642(define-pmacro (swap-_ x) 3643 "Do nothing swap-wise" 3644 (error SI "SWAP without swap modifier isn't implemented") 3645) 3646 3647(define-pmacro (swap-n x) 3648 "Perform bitwise not (that is, perform a not, not not perform)" 3649 (inv x) 3650) 3651 3652(define-pmacro (swap-br x) "Combine swap-r and swap-b" (swap-r (swap-b x))) 3653(define-pmacro (swap-wr x) "Combine swap-r and swap-w" (swap-r (swap-w x))) 3654(define-pmacro (swap-wb x) "Combine swap-b and swap-w" (swap-b (swap-w x))) 3655(define-pmacro (swap-wbr x) "Combine swap-r and swap-wb" (swap-r (swap-wb x))) 3656(define-pmacro (swap-nr x) "Combine swap-r and swap-n" (swap-r (swap-n x))) 3657(define-pmacro (swap-nb x) "Combine swap-n and swap-b" (swap-b (swap-n x))) 3658(define-pmacro (swap-nbr x) "Combine swap-r and swap-nb" (swap-r (swap-nb x))) 3659(define-pmacro (swap-nw x) "Combine swap-n and swap-w" (swap-w (swap-n x))) 3660(define-pmacro (swap-nwr x) "Combine swap-r and swap-nw" (swap-r (swap-nw x))) 3661(define-pmacro (swap-nwb x) "Combine swap-b and swap-nw" (swap-b (swap-nw x))) 3662(define-pmacro (swap-nwbr x) "Combine swap-r and swap-nwb" (swap-r (swap-nwb x))) 3663 3664(define-pmacro (cris-swap swapcode val) 3665 (sequence 3666 SI 3667 ((SI tmpcode) (SI tmpval) (SI tmpres)) 3668 (set tmpcode swapcode) 3669 (set tmpval val) 3670 (.splice 3671 cond 3672 (.unsplice 3673 (.map 3674 (.pmacro 3675 (x-swapcode x-swap) 3676 ((eq tmpcode x-swapcode) 3677 (set tmpres ((.sym swap- x-swap) tmpval)))) 3678 (.iota 16) 3679 (.splice _ (.unsplice cris-swap-codes))))) 3680 tmpres) 3681) 3682 3683; NOT Rd alias for SWAPN Rd 3684(dni-cdt-attr 3685 not "Not" 3686 ((MACH crisv0,crisv3)) 3687 "not ${Rs}" 3688 (+ (f-dest 8) RFIX_SWAP MODE_REGISTER SIZE_FIXED Rd-sfield) 3689 (sequence 3690 ((SI tmp) (SI tmpd)) 3691 (set tmp Rd-sfield) 3692 (set tmpd (cris-swap 8 tmp)) 3693 (set Rd-sfield tmpd) 3694 (setf-move SI tmpd)) 3695) 3696 3697; SWAP<option> Rd [ N W B R | 01110111 | Rd ] 3698(dni-cdt-attr 3699 swap "Swap" 3700 ((MACH crisv8,crisv10,crisv32)) 3701 "swap${swapoption} ${Rs}" 3702 (+ swapoption RFIX_SWAP MODE_REGISTER SIZE_FIXED Rd-sfield) 3703 (sequence 3704 ((SI tmps) (SI tmpd)) 3705 (set tmps Rd-sfield) 3706 (set tmpd (cris-swap swapoption tmps)) 3707 (set Rd-sfield tmpd) 3708 (setf-move SI tmpd)) 3709) 3710 3711; ASR.m Rs,Rd [ Rd | 011110mm | Rs ] 3712(dni-cdt-bwd 3713 asrr "Arithmetic shift right register count" 3714 "$Rs,$Rd" 3715 (+ Rd MODE_REGISTER R_ASR Rs) 3716 (.pmacro 3717 (BWD) 3718 (sequence 3719 ((BWD tmpd) (SI cnt1) (SI cnt2)) 3720 (set cnt1 Rs) 3721 (set cnt2 (if SI (ne (and cnt1 32) 0) 31 (and cnt1 31))) 3722 (set tmpd (sra SI (ext SI (trunc BWD Rd)) cnt2)) 3723 (set-subreg-gr BWD (regno Rd) tmpd) 3724 (setf-move BWD tmpd))) 3725) 3726 3727; ASRQ c,Rd [ Rd | 0011101 | c ] 3728(dni-cdt 3729 asrq "Arithmetic shift right quick-immediate count" 3730 "asrq $c,${Rd}" 3731 (+ Rd Q_ASHQ MODE_QUICK_IMMEDIATE (f-b5 1) c) 3732 (sequence 3733 ((SI tmpd)) 3734 (set tmpd (sra Rd c)) 3735 (set Rd tmpd) 3736 (setf-move SI tmpd)) 3737) 3738 3739; LSR.m Rs,Rd [ Rd | 011111mm | Rs ] 3740(dni-cdt-bwd 3741 lsrr "Logical shift right register count" 3742 "$Rs,$Rd" 3743 (+ Rd MODE_REGISTER R_LSR Rs) 3744 (.pmacro 3745 (BWD) 3746 (sequence 3747 ((SI tmpd) (SI cnt)) 3748 (set cnt (and Rs 63)) 3749 (set 3750 tmpd 3751 (if SI (ne (and cnt 32) 0) 3752 0 3753 (srl SI (zext SI (trunc BWD Rd)) (and cnt 31)))) 3754 (set-subreg-gr BWD (regno Rd) tmpd) 3755 (setf-move BWD tmpd))) 3756) 3757 3758; LSRQ c,Rd [ Rd | 0011111 | c ] 3759(dni-cdt 3760 lsrq "Logical shift right quick-immediate count" 3761 "lsrq $c,${Rd}" 3762 (+ Rd Q_LSHQ MODE_QUICK_IMMEDIATE (f-b5 1) c) 3763 (sequence 3764 ((SI tmpd)) 3765 (set tmpd (srl Rd c)) 3766 (set Rd tmpd) 3767 (setf-move SI tmpd)) 3768) 3769 3770; LSL.m Rs,Rd [ Rd | 010011mm | Rs ] 3771(dni-cdt-bwd 3772 lslr "Logical shift left register count" 3773 "$Rs,$Rd" 3774 (+ Rd MODE_REGISTER R_LSL Rs) 3775 (.pmacro 3776 (BWD) 3777 (sequence 3778 ((SI tmpd) (SI cnt)) 3779 (set cnt (and Rs 63)) 3780 (set 3781 tmpd 3782 (if SI (ne (and cnt 32) 0) 3783 0 3784 (sll SI (zext SI (trunc BWD Rd)) (and cnt 31)))) 3785 (set-subreg-gr BWD (regno Rd) tmpd) 3786 (setf-move BWD tmpd))) 3787) 3788 3789; LSLQ c,Rd [ Rd | 0011110 | c ] 3790(dni-cdt 3791 lslq "Logical shift left quick-immediate count" 3792 "lslq $c,${Rd}" 3793 (+ Rd Q_LSHQ MODE_QUICK_IMMEDIATE (f-b5 0) c) 3794 (sequence 3795 ((SI tmpd)) 3796 (set tmpd (sll Rd c)) 3797 (set Rd tmpd) 3798 (setf-move SI tmpd)) 3799) 3800 3801; BTST Rs,Rd [ Rd | 01001111 | Rs ] 3802(dni-cdt 3803 btst "Bit test register number" 3804 "$Rs,$Rd" 3805 (+ Rd MODE_REGISTER RFIX_BTST SIZE_FIXED Rs) 3806 (sequence 3807 ((SI tmpd) (SI cnt)) 3808 (set tmpd (sll Rd (sub 31 (and Rs 31)))) 3809 (setf-move SI tmpd)) 3810) 3811 3812; BTSTQ c,Rd [ Rd | 0011100 | c ] 3813(dni-cdt 3814 btstq "Bit test quick-immediate number" 3815 "btstq $c,${Rd}" 3816 (+ Rd Q_ASHQ MODE_QUICK_IMMEDIATE (f-b5 0) c) 3817 (sequence 3818 ((SI tmpd)) 3819 (set tmpd (sll Rd (sub 31 c))) 3820 (setf-move SI tmpd)) 3821) 3822 3823; SETF <list of flags> [ P U I X | 01011011 | N Z V C ] 3824(dni-cdt 3825 setf "Set condition code flags explicitly" 3826 "setf ${list-of-flags}" 3827 ; The zero-flags case gets flag operands wrong; there's a "_" 3828 ; where there should have been nothing. Also, flags are in 3829 ; assembly code allowed to be specified in any order, which 3830 ; doesn't match the "flagbits" settings. Luckily we don't 3831 ; use this field for assembly. 3832 (+ RFIX_SETF MODE_REGISTER SIZE_FIXED list-of-flags) 3833 (.splice 3834 sequence 3835 ((SI tmp)) 3836 (set tmp list-of-flags) 3837 (.unsplice 3838 (.map 3839 (.pmacro (ccbit) 3840 (if (ne (and tmp (sll 1 (.sym ccbit -bitnumber))) 0) 3841 (set (.sym ccbit bit) 1))) 3842 cris-flagnames)) 3843 (set prefix-set 0) 3844 ; Unless x was specified to be set, set it to 0. 3845 (if (eq (and tmp (sll 1 x-bitnumber)) 0) 3846 (set xbit 0))) 3847) 3848 3849; CLEARF <list of flags> [ P U I X | 01011111 | N Z V C ] 3850(dni-cdt 3851 clearf "Clear condition code flags explicitly" 3852 "clearf ${list-of-flags}" 3853 ; The zero-flags case gets flag operands wrong; there's a "_" 3854 ; where there should have been nothing. Also, flags are in 3855 ; assembly code allowed to be specified in any order, which 3856 ; doesn't match the "flagbits" settings. Luckily we don't 3857 ; use this field for assembly. 3858 (+ RFIX_CLEARF MODE_REGISTER SIZE_FIXED list-of-flags) 3859 (.splice 3860 sequence 3861 ((SI tmp)) 3862 (set tmp list-of-flags) 3863 (.unsplice 3864 (.map 3865 (.pmacro (ccbit) 3866 (if (ne (and tmp (sll 1 (.sym ccbit -bitnumber))) 0) 3867 (set (.sym ccbit bit) 0))) 3868 cris-flagnames)) 3869 (reset-x-p)) 3870) 3871 3872(define-pmacro 3873 (rfe-rfn-guts) 3874 "Common parts of RFE and RFN" 3875 (sequence 3876 ((USI oldccs) (USI samebits) (USI shiftbits) (USI keepmask) (BI p1)) 3877 (set oldccs ccs) 3878 ; Keeping U, S and I in user mode is handled by the CCS setter, so we 3879 ; don't have to bother. Actually Q and M are handled too. The reason 3880 ; to mask those out is to not have them shifted down into the second 3881 ; flags level. 3882 (set keepmask #xc0000000) 3883 (set samebits (and oldccs keepmask)) 3884 ; The P bit has its own equation. 3885 (set shiftbits (and (srl (and oldccs #x3ffdfc00) 10) (inv keepmask))) 3886 (set p1 (ne 0 (and oldccs #x20000))) 3887 (set ccs (or (or samebits shiftbits) 3888 (if SI (and rbit (not p1)) 0 #x80)))) 3889) 3890 3891; RFE [ 0010 10010011 0000 ] 3892(dni-cdt-attr 3893 rfe 3894 "RFE" 3895 (MACH-V32) 3896 "rfe" 3897 (+ (f-dest 2) MODE_INDIRECT INFIX_RFE SIZE_FIXED (f-source 0)) 3898 (rfe-rfn-guts) 3899) 3900 3901; SFE [ 0011 10010011 0000 ] 3902(dni-cdt-attr 3903 sfe 3904 "SFE" 3905 (MACH-V32) 3906 "sfe" 3907 (+ (f-dest 3) MODE_INDIRECT INFIX_SFE SIZE_FIXED (f-source 0)) 3908 (sequence 3909 ((SI oldccs) (SI savemask)) 3910 (set savemask #xc0000000) 3911 (set oldccs ccs) 3912 (set ccs 3913 (or (and savemask oldccs) 3914 (and (inv savemask) (sll oldccs 10))))) 3915) 3916 3917; RFG [ 0100 10010011 0000 ] 3918(dni-cdt-attr 3919 rfg 3920 "RFG" 3921 (MACH-V32) 3922 "rfg" 3923 (+ (f-dest 4) MODE_INDIRECT INFIX_RFG SIZE_FIXED (f-source 0)) 3924 (c-call VOID "@cpu@_rfg_handler" pc) 3925) 3926 3927; RFN [ 0101 10010011 0000 ] 3928(dni-cdt-attr 3929 rfn 3930 "RFN" 3931 (MACH-V32) 3932 "rfn" 3933 (+ (f-dest 5) MODE_INDIRECT INFIX_RFN SIZE_FIXED (f-source 0)) 3934 (sequence () (rfe-rfn-guts) (set mbit 1)) 3935) 3936 3937; HALT [ 1111 10010011 0000 ] 3938(dni-cdt-attr 3939 halt 3940 "HALT" 3941 (MACH-V32) 3942 "halt" 3943 (+ (f-dest 15) MODE_INDIRECT INFIX_HALT SIZE_FIXED (f-source 0)) 3944 (set pc (c-call USI "@cpu@_halt_handler" pc)) 3945) 3946 3947; Bcc o [ cc | 0000 | o ] 3948(dni 3949 bcc-b "bcc byte operand" 3950 () 3951 "b${cc} ${o-pcrel}" 3952 (+ cc QHI_BCC MODE_QUICK_IMMEDIATE o-pcrel) 3953 (sequence 3954 ((BI truthval)) 3955 (set truthval (cris-condition cc)) 3956 3957 ; Amazing as it may seem, there's no simpler way to find out 3958 ; whether a branch is taken or not than to mark it through a kludge 3959 ; like this. 3960 (c-call VOID "@cpu@_branch_taken" pc o-pcrel truthval) 3961 3962 (reset-x-p) 3963 (if truthval 3964 (delay 1 3965 (set pc o-pcrel)))) 3966 (.splice (.unsplice (simplecris-timing)) 3967 (crisv32 (unit u-branch) (unit u-exec))) 3968) 3969(dni 3970 ba-b "ba byte operand" 3971 () 3972 "ba ${o-pcrel}" 3973 (+ (f-dest 14) QHI_BCC MODE_QUICK_IMMEDIATE o-pcrel) 3974 (sequence 3975 () 3976 (reset-x-p) 3977 (delay 1 3978 (set pc o-pcrel))) 3979 ((crisv32 (unit u-jump) (unit u-exec))) 3980) 3981 3982; Bcc [PC+] [ cc | 11011111 1111 ] 3983; (We don't implement the generic for pre-V32 but unused variant 3984; "Bcc [Rn(+)]" where n != 15.) 3985(dni 3986 bcc-w "bcc, word operand" 3987 () 3988 "b${cc} ${o-word-pcrel}" 3989 (+ cc MODE_AUTOINCREMENT INFIX_BCC_M SIZE_FIXED (f-source 15) o-word-pcrel) 3990 (sequence 3991 ((BI truthval)) 3992 (set truthval (cris-condition cc)) 3993 3994 ; Amazing as it may seem, there's no simpler way to find out 3995 ; whether a branch is taken or not than to mark it through a kludge 3996 ; like this. 3997 (c-call VOID "@cpu@_branch_taken" pc o-word-pcrel truthval) 3998 3999 (reset-x-p) 4000 (if truthval 4001 (delay 1 4002 (set pc o-word-pcrel)))) 4003 (.splice 4004 (.unsplice (simplecris-common-timing ((unit u-const16) (unit u-exec)))) 4005 (crisv32 (unit u-const16) (unit u-branch) (unit u-exec))) 4006) 4007(dni 4008 ba-w "ba word operand" 4009 () 4010 "ba ${o-word-pcrel}" 4011 (+ (f-dest 14) MODE_AUTOINCREMENT INFIX_BCC_M SIZE_FIXED (f-source 15) o-word-pcrel) 4012 (sequence 4013 () 4014 (reset-x-p) 4015 (delay 1 4016 (set pc o-word-pcrel))) 4017 (.splice 4018 (.unsplice (simplecris-common-timing ((unit u-const16) (unit u-exec)))) 4019 (crisv32 (unit u-const16) (unit u-jump) (unit u-exec))) 4020) 4021 4022; JAS Rs,Pd [ Pd | 10011011 | Rs ] 4023(dni 4024 jas-r "JAS register" 4025 (MACH-V32) 4026 "jas ${Rs},${Pd}" 4027 (+ Pd MODE_INDIRECT INFIX_JAS_R SIZE_FIXED Rs) 4028 (sequence 4029 () 4030 (reset-x-p) 4031 (if (andif (eq (regno Rs) 1) (eq (regno Pd) 11)) 4032 ; We use this as a trigger; a normally reasonably rare instruction 4033 ; used in the v32 trampoline. See comment at bdapqpc. 4034 ; CGEN-FIXME: can't use (regno srp) [== (regno (reg h-sr 11))] 4035 (c-call VOID "cris_flush_simulator_decode_cache" pc)) 4036 (delay 1 4037 (sequence 4038 () 4039 (set Pd (add SI pc 4)) 4040 (set pc Rs)))) 4041 ((crisv32 (unit u-jump-r) (unit u-jump) (unit u-exec))) 4042) 4043; Same semantics in pre-V32, except no delay-slot. 4044; FIXME: Missing JIRC/JSRC/JBRC. 4045(dni-cdt-attr 4046 jump-r "JUMP/JSR/JIR register" 4047 (MACH-PC) 4048 "jump/jsr/jir ${Rs}" 4049 (+ Pd MODE_INDIRECT INFIX_JUMP_R SIZE_FIXED Rs) 4050 (sequence 4051 () 4052 (set Pd (add SI pc 2)) 4053 (set pc Rs) 4054 (reset-x-p)) 4055) 4056 4057; JAS [PC+],Pd [ Pd | 11011011 1111 ] 4058(dni 4059 jas-c "JAS constant" 4060 (MACH-V32) 4061 "jas ${const32},${Pd}" 4062 (+ Pd MODE_AUTOINCREMENT INFIX_JAS_M SIZE_FIXED (f-source 15) const32) 4063 (sequence 4064 () 4065 (reset-x-p) 4066 (delay 1 4067 (sequence 4068 () 4069 (set Pd (add SI pc 8)) 4070 (set pc const32)))) 4071 ((crisv32 (unit u-const32) (unit u-jump) (unit u-exec))) 4072) 4073 4074; JUMP/JSR/JIR | Special r.| 1 m| 0 1 0 0| 1 1| Source | 4075(dni-cmt-attr 4076 jump-m "JUMP/JSR/JIR memory" 4077 (MACH-PC) 4078 "jump/jsr/jir [${Rs}${inc}]" 4079 (+ Pd INFIX_JUMP_M SIZE_FIXED Rs) 4080 (sequence 4081 () 4082 (set Pd (add SI pc 2)) 4083 (set pc (cris-get-mem SI Rs)) 4084 (reset-x-p)) 4085) 4086(dni-c-SI-attr 4087 jump-c "JUMP/JSR/JIR constant" 4088 (MACH-PC) 4089 "jump/jsr/jir ${const32}" 4090 (+ Pd MODE_AUTOINCREMENT INFIX_JUMP_M SIZE_FIXED (f-source 15) const32) 4091 (sequence 4092 () 4093 (set Pd (add SI pc 6)) 4094 (set pc const32) 4095 (reset-x-p)) 4096) 4097 4098; JUMP Ps [ Ps | 10011111 0000 ] 4099(dni 4100 jump-p "JUMP special register" 4101 (MACH-V32) 4102 "jump ${Ps}" 4103 (+ Ps MODE_INDIRECT INFIX_JUMP_P SIZE_FIXED (f-source 0)) 4104 (sequence 4105 () 4106 (reset-x-p) 4107 (delay 1 4108 (set pc Ps))) 4109 ((crisv32 (unit u-jump-sr) 4110 (unit u-exec))) 4111) 4112 4113; BAS [PC+],Pd [ Pd | 11101011 1111 ] 4114(dni 4115 bas-c "BAS constant" 4116 (MACH-V32) 4117 "bas ${const32},${Pd}" 4118 (+ Pd MODE_AUTOINCREMENT INFIX_BAS SIZE_FIXED (f-source 15) const32-pcrel) 4119 (sequence 4120 () 4121 (reset-x-p) 4122 (delay 1 4123 (sequence 4124 () 4125 (set Pd (add SI pc 8)) 4126 (set pc const32-pcrel)))) 4127 ((crisv32 (unit u-const32) (unit u-jump) (unit u-exec))) 4128) 4129 4130; JASC Rs,Pd [ Pd | 10110011 | Rs ] 4131(dni 4132 jasc-r "JASC register" 4133 (MACH-V32) 4134 "jasc ${Rs},${Pd}" 4135 (+ Pd MODE_INDIRECT INFIX_JASC SIZE_FIXED Rs) 4136 (sequence 4137 () 4138 (reset-x-p) 4139 (delay 1 4140 (sequence 4141 () 4142 (set Pd (add SI pc 8)) 4143 (set pc Rs)))) 4144 ((crisv32 (unit u-jump-r) (unit u-skip4) (unit u-jump) (unit u-exec))) 4145) 4146 4147; JASC [PC+],Pd [ Pd | 11110011 1111 ] 4148(dni 4149 jasc-c "JASC constant" 4150 (MACH-V32) 4151 "jasc ${const32},${Pd}" 4152 (+ Pd MODE_AUTOINCREMENT INFIX_JASC SIZE_FIXED (f-source 15) const32) 4153 (sequence 4154 () 4155 (reset-x-p) 4156 (delay 1 4157 (sequence 4158 () 4159 (set Pd (add SI pc 12)) 4160 (set pc const32)))) 4161 ((crisv32 (unit u-const32) (unit u-skip4) (unit u-jump) (unit u-exec))) 4162) 4163 4164; BASC [PC+],Pd [ Pd | 11101111 1111 ] 4165(dni 4166 basc-c "BASC constant" 4167 (MACH-V32) 4168 "basc ${const32},${Pd}" 4169 (+ Pd MODE_AUTOINCREMENT INFIX_BASC SIZE_FIXED (f-source 15) const32-pcrel) 4170 (sequence 4171 () 4172 (reset-x-p) 4173 (delay 1 4174 (sequence 4175 () 4176 (set Pd (add SI pc 12)) 4177 (set pc const32-pcrel)))) 4178 ((crisv32 (unit u-const32) (unit u-skip4) (unit u-jump) (unit u-exec))) 4179) 4180 4181; BREAK n [ 1110 | 10010011 | n ] 4182 4183(dni-cdt 4184 break "break" 4185 "break $n" 4186 (+ (f-operand2 #xe) MODE_INDIRECT INFIX_BREAK SIZE_FIXED n) 4187 (sequence () (reset-x-p) (set pc (c-call USI "@cpu@_break_handler" n pc))) 4188) 4189 4190; BOUND.m Rs,Rd [ Rd | 010111mm | Rs ] 4191(dni-cdt-bwd 4192 bound-r "Bound register" 4193 "${Rs},${Rd}" 4194 (+ Rd R_BOUND MODE_REGISTER Rs) 4195 (.pmacro 4196 (BWD) 4197 (sequence 4198 ((SI tmpopd) (SI tmpops) (SI newval)) 4199 (set tmpops ((.sym BWD -zext) (trunc BWD Rs))) 4200 (set tmpopd Rd) 4201 (set newval (if SI (ltu tmpops tmpopd) tmpops tmpopd)) 4202 (set Rd newval) 4203 (setf-move SI newval))) 4204) 4205 4206; BOUND.m [Rs],Rd [ Rd | 100111mm | Rs ] 4207; BOUND.m [Rs+],Rd [ Rd | 110111mm | Rs ] 4208(dni-cmt-bwd-attr 4209 bound-m "Bound memory" 4210 (MACH-PRE-V32) 4211 "[${Rs}${inc}],${Rd}" 4212 (+ Rd INDIR_BOUND Rs) 4213 (.pmacro 4214 (BWD) 4215 (sequence 4216 ((SI tmpopd) (SI tmpops) (SI newval)) 4217 (set tmpops ((.sym BWD -zext) (cris-get-mem BWD Rs))) 4218 (set tmpopd Rd) 4219 (set newval (if SI (ltu tmpops tmpopd) tmpops tmpopd)) 4220 (if (andif prefix-set (not inc)) 4221 (set Rs newval) 4222 (set Rd newval)) 4223 (setf-move SI newval))) 4224) 4225 4226; (BOUND.m [PC+],Rd [ Rd | 110111mm | 1111 ]) 4227(dni-c-QI 4228 bound-cb "Bound constant byte" 4229 "bound.b [PC+],${Rd}" 4230 (+ Rd MODE_AUTOINCREMENT INDIR_BOUND SIZE_BYTE (f-source 15) uconst8) 4231 (sequence 4232 ((SI tmpopd) (SI tmpops) (SI newval)) 4233 (set tmpops (zext SI (trunc QI uconst8))) 4234 (set tmpopd Rd) 4235 (set newval (if SI (ltu tmpops tmpopd) tmpops tmpopd)) 4236 (set Rd newval) 4237 (setf-move SI newval)) 4238) 4239(dni-c-HI 4240 bound-cw "Bound constant word" 4241 "bound.w [PC+],${Rd}" 4242 (+ Rd MODE_AUTOINCREMENT INDIR_BOUND SIZE_WORD (f-source 15) uconst16) 4243 (sequence 4244 ((SI tmpopd) (SI tmpops) (SI newval)) 4245 (set tmpops (zext SI uconst16)) 4246 (set tmpopd Rd) 4247 (set newval (if SI (ltu tmpops tmpopd) tmpops tmpopd)) 4248 (set Rd newval) 4249 (setf-move SI newval)) 4250) 4251(dni-c-SI 4252 bound-cd "Bound constant dword" 4253 "bound.d [PC+],${Rd}" 4254 (+ Rd MODE_AUTOINCREMENT INDIR_BOUND SIZE_DWORD (f-source 15) const32) 4255 (sequence 4256 ((SI tmpopd) (SI tmpops) (SI newval)) 4257 (set tmpops const32) 4258 (set tmpopd Rd) 4259 (set newval (if SI (ltu tmpops tmpopd) tmpops tmpopd)) 4260 (set Rd newval) 4261 (setf-move SI newval)) 4262) 4263 4264; Scc Rd [ cc | 01010011 | Rd ] 4265(dni-cdt 4266 scc "scc" 4267 "s${cc} ${Rd-sfield}" 4268 (+ cc MODE_REGISTER RFIX_SCC SIZE_FIXED Rd-sfield) 4269 (sequence 4270 ((BI truthval)) 4271 (set truthval (cris-condition cc)) 4272 (set Rd-sfield (zext SI truthval)) 4273 (reset-x-p)) 4274) 4275 4276; LZ Rs,Rd [ Rd | 01110011 | Rs ] 4277(dni-cdt-attr 4278 lz "lz" 4279 (MACH-V3-UP) 4280 "lz ${Rs},${Rd}" 4281 (+ Rd MODE_REGISTER RFIX_LZ SIZE_FIXED Rs) 4282 (sequence 4283 ((SI tmpd) (SI tmp)) 4284 (set tmp Rs) 4285 (set tmpd 0) 4286 (.splice 4287 sequence 4288 () 4289 (.unsplice 4290 (.map 4291 (.pmacro (n) 4292 (if (ge tmp 0) 4293 (sequence 4294 () 4295 (set tmp (sll tmp 1)) 4296 (set tmpd (add tmpd 1))))) 4297 (.iota 32)))) 4298 (set Rd tmpd) 4299 (setf-move SI tmpd)) 4300) 4301 4302; ADDOQ o,Rs,ACR [ Rs | 0001 | o ] 4303(dni-cdt 4304 addoq "addoq" 4305 "addoq $o,$Rs,ACR" 4306 (+ Rs-dfield MODE_QUICK_IMMEDIATE QHI_ADDOQ o) 4307 (sequence 4308 () 4309 (set prefixreg (add SI Rs-dfield o)) 4310 (set prefix-set 1)) 4311) 4312 4313; (BDAPQ o,PC [ 1111 | 0001 | o ]) 4314; This [PC+I] prefix is used in trampolines. 4315(dni-cdt-attr 4316 bdapqpc "bdapq pc operand" 4317 (MACH-PC UNCOND-CTI) 4318 "bdapq $o,PC" 4319 (+ (f-dest 15) MODE_QUICK_IMMEDIATE QHI_BDAP o) 4320 (sequence 4321 () 4322 (set prefixreg (add SI (add SI pc 2) o)) 4323 (set prefix-set 1) 4324 ; When this *rare* instruction is seen, we're may be about to write 4325 ; into code to be executed soon, *probably* covering addresses decoded 4326 ; and executed before. If the simulator does not implement snooping 4327 ; and automatic decoder flush, it will execute old code. This call 4328 ; is a kludge for such simulators, asking it to abandon such cached 4329 ; information. Anyway, it is hopefully enough to make CGEN-sim not 4330 ; hork on gcc trampolines. 4331 ; We mark this insn as UNCOND-CTI so this insn will end a simulator 4332 ; basic block (the atomic unit of translation). 4333 (c-call VOID "cris_flush_simulator_decode_cache" pc)) 4334) 4335 4336; ADDO.m [Rs],Rd,ACR [ Rd | 100101mm | Rs ] 4337; ADDO.m [Rs+],Rd,ACR [ Rd | 110101mm | Rs ] 4338(dni-cmt-bwd 4339 addo-m "addo.m memory" 4340 "[${Rs}${inc}],$Rd,ACR" 4341 (+ Rd INDIR_ADDO Rs) 4342 (.pmacro 4343 (BWD) 4344 (sequence 4345 ((BWD tmps)) 4346 (set tmps (cris-get-mem BWD Rs)) 4347 (set prefixreg (add SI Rd ((.sym BWD -ext) tmps))) 4348 (set prefix-set 1))) 4349) 4350 4351; (ADDO.m [PC+],Rd,ACR [ Rd | 110101mm | 1111 ] 4352(dni-c-QI 4353 addo-cb "addo.b const" 4354 "addo.b [PC+],$Rd,ACR" 4355 (+ Rd MODE_AUTOINCREMENT INDIR_ADDO SIZE_BYTE (f-source 15) sconst8) 4356 (sequence 4357 () 4358 (set prefixreg (add SI Rd (ext SI (trunc QI sconst8)))) 4359 (set prefix-set 1)) 4360) 4361(dni-c-HI 4362 addo-cw "addo.w const" 4363 "addo.w [PC+],$Rd,ACR" 4364 (+ Rd MODE_AUTOINCREMENT INDIR_ADDO SIZE_WORD (f-source 15) sconst16) 4365 (sequence 4366 () 4367 (set prefixreg (add SI Rd (ext SI (trunc HI sconst16)))) 4368 (set prefix-set 1)) 4369) 4370(dni-c-SI 4371 addo-cd "addo.d const" 4372 "addo.d [PC+],$Rd,ACR" 4373 (+ Rd MODE_AUTOINCREMENT INDIR_ADDO SIZE_DWORD (f-source 15) const32) 4374 (sequence 4375 () 4376 (set prefixreg (add SI Rd const32)) 4377 (set prefix-set 1)) 4378) 4379 4380; DIP [] | 0 0 0 0| 1 m| 0 1 0 1| 1 1| Source | 4381 4382(dni-cmt-attr 4383 dip-m "dip mem" 4384 (MACH-PRE-V32) 4385 "dip [${Rs}${inc}]" 4386 (+ (f-dest 0) INFIX_DIP SIZE_FIXED Rs) 4387 (sequence 4388 ((SI tmps)) 4389 (set tmps (cris-get-mem SI Rs)) 4390 (set prefixreg tmps) 4391 (set prefix-set 1)) 4392) 4393 4394; (DIP [] | 0 0 0 0| 1 m| 0 1 0 1| 1 1| Source | ) 4395(dni-c-SI-attr 4396 dip-c "dip [PC+]" 4397 (MACH-PC) 4398 "dip [PC+]" 4399 (+ (f-dest 0) MODE_AUTOINCREMENT INFIX_DIP SIZE_FIXED (f-source 15) const32) 4400 (sequence 4401 () 4402 (set prefixreg const32) 4403 (set prefix-set 1)) 4404) 4405 4406; ADDI Rs.m,Rd,ACR [ Rs | 010101mm | Rd ] 4407; a.k.a. biap 4408(dni-cdt-bwd 4409 addi-acr "addi prefix" 4410 "${Rs-dfield}.m,${Rd-sfield},ACR" 4411 (+ Rd-sfield MODE_REGISTER R_ADDI_ACR Rs-dfield) 4412 (.pmacro 4413 (BWD) 4414 (sequence 4415 () 4416 (set prefixreg (add SI Rd-sfield (mul Rs-dfield (.sym BWD -size)))) 4417 (set prefix-set 1))) 4418) 4419 4420(dni-cdt-bwd-attr 4421 biap-pc "biap.m ${Rs-dfield},PC" 4422 (MACH-PC) 4423 "${Rs-dfield}.m,PC" 4424 (+ Rs-dfield MODE_REGISTER R_ADDI_ACR (f-source 15)) 4425 (.pmacro 4426 (BWD) 4427 (sequence 4428 () 4429 (set prefixreg (add SI (add SI pc 4) (mul Rs-dfield (.sym BWD -size)))) 4430 (set prefix-set 1))) 4431) 4432 4433; FIDXI [Rs] [ 0000 | 11010011 | Rs ] 4434(dni-cdt-attr 4435 fidxi "fidxi [Rs]" 4436 (MACH-V32) 4437 "fidxi [$Rs]" 4438 (+ (f-dest 0) MODE_AUTOINCREMENT INFIX_FIDXI SIZE_FIXED Rs) 4439 (set pc (c-call USI "@cpu@_fidxi_handler" pc Rs)) 4440) 4441 4442; FTAGI [Rs] [ 0001 | 11010011 | Rs ] 4443(dni-cdt-attr 4444 ftagi "ftagi [Rs]" 4445 (MACH-V32) 4446 "fidxi [$Rs]" 4447 (+ (f-dest 1) MODE_AUTOINCREMENT INFIX_FTAGI SIZE_FIXED Rs) 4448 (set pc (c-call USI "@cpu@_ftagi_handler" pc Rs)) 4449) 4450 4451; FIDXD [Rs] [ 0000 | 10101011 | Rs ] 4452(dni-cdt-attr 4453 fidxd "fidxd [Rs]" 4454 (MACH-V32) 4455 "fidxd [$Rs]" 4456 (+ (f-dest 0) MODE_INDIRECT INFIX_FIDXD SIZE_FIXED Rs) 4457 (set pc (c-call USI "@cpu@_fidxd_handler" pc Rs)) 4458) 4459 4460; FTAGD [Rs] [ 0001 | 10101011 | Rs ] 4461(dni-cdt-attr 4462 ftagd "ftagd [Rs]" 4463 (MACH-V32) 4464 "ftagd [$Rs]" 4465 (+ (f-dest 1) MODE_INDIRECT INFIX_FTAGD SIZE_FIXED Rs) 4466 (set pc (c-call USI "@cpu@_ftagd_handler" pc Rs)) 4467) 4468