1This is ../.././gas/doc/as.info, produced by makeinfo version 4.7 from 2../.././gas/doc/as.texinfo. 3 4START-INFO-DIR-ENTRY 5* As: (as). The GNU assembler. 6* Gas: (as). The GNU assembler. 7END-INFO-DIR-ENTRY 8 9 This file documents the GNU Assembler "as". 10 11 Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002 12Free Software Foundation, Inc. 13 14 Permission is granted to copy, distribute and/or modify this document 15under the terms of the GNU Free Documentation License, Version 1.1 or 16any later version published by the Free Software Foundation; with no 17Invariant Sections, with no Front-Cover Texts, and with no Back-Cover 18Texts. A copy of the license is included in the section entitled "GNU 19Free Documentation License". 20 21 22File: as.info, Node: i386-Float, Next: i386-SIMD, Prev: i386-Jumps, Up: i386-Dependent 23 248.12.8 Floating Point 25--------------------- 26 27All 80387 floating point types except packed BCD are supported. (BCD 28support may be added without much difficulty). These data types are 2916-, 32-, and 64- bit integers, and single (32-bit), double (64-bit), 30and extended (80-bit) precision floating point. Each supported type 31has an instruction mnemonic suffix and a constructor associated with 32it. Instruction mnemonic suffixes specify the operand's data type. 33Constructors build these data types into memory. 34 35 * Floating point constructors are `.float' or `.single', `.double', 36 and `.tfloat' for 32-, 64-, and 80-bit formats. These correspond 37 to instruction mnemonic suffixes `s', `l', and `t'. `t' stands for 38 80-bit (ten byte) real. The 80387 only supports this format via 39 the `fldt' (load 80-bit real to stack top) and `fstpt' (store 40 80-bit real and pop stack) instructions. 41 42 * Integer constructors are `.word', `.long' or `.int', and `.quad' 43 for the 16-, 32-, and 64-bit integer formats. The corresponding 44 instruction mnemonic suffixes are `s' (single), `l' (long), and 45 `q' (quad). As with the 80-bit real format, the 64-bit `q' format 46 is only present in the `fildq' (load quad integer to stack top) 47 and `fistpq' (store quad integer and pop stack) instructions. 48 49 Register to register operations should not use instruction mnemonic 50suffixes. `fstl %st, %st(1)' will give a warning, and be assembled as 51if you wrote `fst %st, %st(1)', since all register to register 52operations use 80-bit floating point operands. (Contrast this with 53`fstl %st, mem', which converts `%st' from 80-bit to 64-bit floating 54point format, then stores the result in the 4 byte location `mem') 55 56 57File: as.info, Node: i386-SIMD, Next: i386-16bit, Prev: i386-Float, Up: i386-Dependent 58 598.12.9 Intel's MMX and AMD's 3DNow! SIMD Operations 60--------------------------------------------------- 61 62`as' supports Intel's MMX instruction set (SIMD instructions for 63integer data), available on Intel's Pentium MMX processors and Pentium 64II processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and 65probably others. It also supports AMD's 3DNow! instruction set (SIMD 66instructions for 32-bit floating point data) available on AMD's K6-2 67processor and possibly others in the future. 68 69 Currently, `as' does not support Intel's floating point SIMD, Katmai 70(KNI). 71 72 The eight 64-bit MMX operands, also used by 3DNow!, are called 73`%mm0', `%mm1', ... `%mm7'. They contain eight 8-bit integers, four 7416-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit 75floating point values. The MMX registers cannot be used at the same 76time as the floating point stack. 77 78 See Intel and AMD documentation, keeping in mind that the operand 79order in instructions is reversed from the Intel syntax. 80 81 82File: as.info, Node: i386-16bit, Next: i386-Arch, Prev: i386-SIMD, Up: i386-Dependent 83 848.12.10 Writing 16-bit Code 85--------------------------- 86 87While `as' normally writes only "pure" 32-bit i386 code or 64-bit 88x86-64 code depending on the default configuration, it also supports 89writing code to run in real mode or in 16-bit protected mode code 90segments. To do this, put a `.code16' or `.code16gcc' directive before 91the assembly language instructions to be run in 16-bit mode. You can 92switch `as' back to writing normal 32-bit code with the `.code32' 93directive. 94 95 `.code16gcc' provides experimental support for generating 16-bit 96code from gcc, and differs from `.code16' in that `call', `ret', 97`enter', `leave', `push', `pop', `pusha', `popa', `pushf', and `popf' 98instructions default to 32-bit size. This is so that the stack pointer 99is manipulated in the same way over function calls, allowing access to 100function parameters at the same stack offsets as in 32-bit mode. 101`.code16gcc' also automatically adds address size prefixes where 102necessary to use the 32-bit addressing modes that gcc generates. 103 104 The code which `as' generates in 16-bit mode will not necessarily 105run on a 16-bit pre-80386 processor. To write code that runs on such a 106processor, you must refrain from using _any_ 32-bit constructs which 107require `as' to output address or operand size prefixes. 108 109 Note that writing 16-bit code instructions by explicitly specifying a 110prefix or an instruction mnemonic suffix within a 32-bit code section 111generates different machine instructions than those generated for a 11216-bit code segment. In a 32-bit code section, the following code 113generates the machine opcode bytes `66 6a 04', which pushes the value 114`4' onto the stack, decrementing `%esp' by 2. 115 116 pushw $4 117 118 The same code in a 16-bit code section would generate the machine 119opcode bytes `6a 04' (ie. without the operand size prefix), which is 120correct since the processor default operand size is assumed to be 16 121bits in a 16-bit code section. 122 123 124File: as.info, Node: i386-Bugs, Next: i386-Notes, Prev: i386-Arch, Up: i386-Dependent 125 1268.12.11 AT&T Syntax bugs 127------------------------ 128 129The UnixWare assembler, and probably other AT&T derived ix86 Unix 130assemblers, generate floating point instructions with reversed source 131and destination registers in certain cases. Unfortunately, gcc and 132possibly many other programs use this reversed syntax, so we're stuck 133with it. 134 135 For example 136 137 fsub %st,%st(3) 138 results in `%st(3)' being updated to `%st - %st(3)' rather than the 139expected `%st(3) - %st'. This happens with all the non-commutative 140arithmetic floating point operations with two register operands where 141the source register is `%st' and the destination register is `%st(i)'. 142 143 144File: as.info, Node: i386-Arch, Next: i386-Bugs, Prev: i386-16bit, Up: i386-Dependent 145 1468.12.12 Specifying CPU Architecture 147----------------------------------- 148 149`as' may be told to assemble for a particular CPU (sub-)architecture 150with the `.arch CPU_TYPE' directive. This directive enables a warning 151when gas detects an instruction that is not supported on the CPU 152specified. The choices for CPU_TYPE are: 153 154`i8086' `i186' `i286' `i386' 155`i486' `i586' `i686' `pentium' 156`pentiumpro' `pentiumii' `pentiumiii' `pentium4' 157`k6' `athlon' 158 `sledgehammer' 159`.mmx' `.sse' 160`.sse2' 161`.3dnow' 162 163 Apart from the warning, there are only two other effects on `as' 164operation; Firstly, if you specify a CPU other than `i486', then shift 165by one instructions such as `sarl $1, %eax' will automatically use a 166two byte opcode sequence. The larger three byte opcode sequence is 167used on the 486 (and when no architecture is specified) because it 168executes faster on the 486. Note that you can explicitly request the 169two byte opcode by writing `sarl %eax'. Secondly, if you specify 170`i8086', `i186', or `i286', _and_ `.code16' or `.code16gcc' then byte 171offset conditional jumps will be promoted when necessary to a two 172instruction sequence consisting of a conditional jump of the opposite 173sense around an unconditional jump to the target. 174 175 Following the CPU architecture (but not a sub-architecture, which 176are those starting with a dot), you may specify `jumps' or `nojumps' to 177control automatic promotion of conditional jumps. `jumps' is the 178default, and enables jump promotion; All external jumps will be of the 179long variety, and file-local jumps will be promoted as necessary. 180(*note i386-Jumps::) `nojumps' leaves external conditional jumps as 181byte offset jumps, and warns about file-local conditional jumps that 182`as' promotes. Unconditional jumps are treated as for `jumps'. 183 184 For example 185 186 .arch i8086,nojumps 187 188 189File: as.info, Node: i386-Notes, Prev: i386-Bugs, Up: i386-Dependent 190 1918.12.13 Notes 192------------- 193 194There is some trickery concerning the `mul' and `imul' instructions 195that deserves mention. The 16-, 32-, 64- and 128-bit expanding 196multiplies (base opcode `0xf6'; extension 4 for `mul' and 5 for `imul') 197can be output only in the one operand form. Thus, `imul %ebx, %eax' 198does _not_ select the expanding multiply; the expanding multiply would 199clobber the `%edx' register, and this would confuse `gcc' output. Use 200`imul %ebx' to get the 64-bit product in `%edx:%eax'. 201 202 We have added a two operand form of `imul' when the first operand is 203an immediate mode expression and the second operand is a register. 204This is just a shorthand, so that, multiplying `%eax' by 69, for 205example, can be done with `imul $69, %eax' rather than `imul $69, %eax, 206%eax'. 207 208 209File: as.info, Node: i860-Dependent, Next: i960-Dependent, Prev: i386-Dependent, Up: Machine Dependencies 210 2118.13 Intel i860 Dependent Features 212================================== 213 214* Menu: 215 216* Notes-i860:: i860 Notes 217* Options-i860:: i860 Command-line Options 218* Directives-i860:: i860 Machine Directives 219* Opcodes for i860:: i860 Opcodes 220 221 222File: as.info, Node: Notes-i860, Next: Options-i860, Up: i860-Dependent 223 2248.13.1 i860 Notes 225----------------- 226 227This is a fairly complete i860 assembler which is compatible with the 228UNIX System V/860 Release 4 assembler. However, it does not currently 229support SVR4 PIC (i.e., `@GOT, @GOTOFF, @PLT'). 230 231 Like the SVR4/860 assembler, the output object format is ELF32. 232Currently, this is the only supported object format. If there is 233sufficient interest, other formats such as COFF may be implemented. 234 235 Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter 236being the default. One difference is that AT&T syntax requires the '%' 237prefix on register names while Intel syntax does not. Another 238difference is in the specification of relocatable expressions. The 239Intel syntax is `ha%expression' whereas the SVR4 syntax is 240`[expression]@ha' (and similarly for the "l" and "h" selectors). 241 242 243File: as.info, Node: Options-i860, Next: Directives-i860, Prev: Notes-i860, Up: i860-Dependent 244 2458.13.2 i860 Command-line Options 246-------------------------------- 247 2488.13.2.1 SVR4 compatibility options 249................................... 250 251`-V' 252 Print assembler version. 253 254`-Qy' 255 Ignored. 256 257`-Qn' 258 Ignored. 259 2608.13.2.2 Other options 261...................... 262 263`-EL' 264 Select little endian output (this is the default). 265 266`-EB' 267 Select big endian output. Note that the i860 always reads 268 instructions as little endian data, so this option only effects 269 data and not instructions. 270 271`-mwarn-expand' 272 Emit a warning message if any pseudo-instruction expansions 273 occurred. For example, a `or' instruction with an immediate 274 larger than 16-bits will be expanded into two instructions. This 275 is a very undesirable feature to rely on, so this flag can help 276 detect any code where it happens. One use of it, for instance, has 277 been to find and eliminate any place where `gcc' may emit these 278 pseudo-instructions. 279 280`-mxp' 281 Enable support for the i860XP instructions and control registers. 282 By default, this option is disabled so that only the base 283 instruction set (i.e., i860XR) is supported. 284 285`-mintel-syntax' 286 The i860 assembler defaults to AT&T/SVR4 syntax. This option 287 enables the Intel syntax. 288 289 290File: as.info, Node: Directives-i860, Next: Opcodes for i860, Prev: Options-i860, Up: i860-Dependent 291 2928.13.3 i860 Machine Directives 293------------------------------ 294 295`.dual' 296 Enter dual instruction mode. While this directive is supported, the 297 preferred way to use dual instruction mode is to explicitly code 298 the dual bit with the `d.' prefix. 299 300`.enddual' 301 Exit dual instruction mode. While this directive is supported, the 302 preferred way to use dual instruction mode is to explicitly code 303 the dual bit with the `d.' prefix. 304 305`.atmp' 306 Change the temporary register used when expanding pseudo 307 operations. The default register is `r31'. 308 309 The `.dual', `.enddual', and `.atmp' directives are available only 310in the Intel syntax mode. 311 312 Both syntaxes allow for the standard `.align' directive. However, 313the Intel syntax additionally allows keywords for the alignment 314parameter: "`.align type'", where `type' is one of `.short', `.long', 315`.quad', `.single', `.double' representing alignments of 2, 4, 16, 4, 316and 8, respectively. 317 318 319File: as.info, Node: Opcodes for i860, Prev: Directives-i860, Up: i860-Dependent 320 3218.13.4 i860 Opcodes 322------------------- 323 324All of the Intel i860XR and i860XP machine instructions are supported. 325Please see either _i860 Microprocessor Programmer's Reference Manual_ 326or _i860 Microprocessor Architecture_ for more information. 327 3288.13.4.1 Other instruction support (pseudo-instructions) 329........................................................ 330 331For compatibility with some other i860 assemblers, a number of 332pseudo-instructions are supported. While these are supported, they are 333a very undesirable feature that should be avoided - in particular, when 334they result in an expansion to multiple actual i860 instructions. Below 335are the pseudo-instructions that result in expansions. 336 * Load large immediate into general register: 337 338 The pseudo-instruction `mov imm,%rn' (where the immediate does not 339 fit within a signed 16-bit field) will be expanded into: 340 orh large_imm@h,%r0,%rn 341 or large_imm@l,%rn,%rn 342 343 * Load/store with relocatable address expression: 344 345 For example, the pseudo-instruction `ld.b addr_exp(%rx),%rn' will 346 be expanded into: 347 orh addr_exp@ha,%rx,%r31 348 ld.l addr_exp@l(%r31),%rn 349 350 The analogous expansions apply to `ld.x, st.x, fld.x, pfld.x, 351 fst.x', and `pst.x' as well. 352 353 * Signed large immediate with add/subtract: 354 355 If any of the arithmetic operations `adds, addu, subs, subu' are 356 used with an immediate larger than 16-bits (signed), then they 357 will be expanded. For instance, the pseudo-instruction `adds 358 large_imm,%rx,%rn' expands to: 359 orh large_imm@h,%r0,%r31 360 or large_imm@l,%r31,%r31 361 adds %r31,%rx,%rn 362 363 * Unsigned large immediate with logical operations: 364 365 Logical operations (`or, andnot, or, xor') also result in 366 expansions. The pseudo-instruction `or large_imm,%rx,%rn' results 367 in: 368 orh large_imm@h,%rx,%r31 369 or large_imm@l,%r31,%rn 370 371 Similarly for the others, except for `and' which expands to: 372 andnot (-1 - large_imm)@h,%rx,%r31 373 andnot (-1 - large_imm)@l,%r31,%rn 374 375 376File: as.info, Node: i960-Dependent, Next: IA-64-Dependent, Prev: i860-Dependent, Up: Machine Dependencies 377 3788.14 Intel 80960 Dependent Features 379=================================== 380 381* Menu: 382 383* Options-i960:: i960 Command-line Options 384* Floating Point-i960:: Floating Point 385* Directives-i960:: i960 Machine Directives 386* Opcodes for i960:: i960 Opcodes 387 388 389File: as.info, Node: Options-i960, Next: Floating Point-i960, Up: i960-Dependent 390 3918.14.1 i960 Command-line Options 392-------------------------------- 393 394`-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC' 395 Select the 80960 architecture. Instructions or features not 396 supported by the selected architecture cause fatal errors. 397 398 `-ACA' is equivalent to `-ACA_A'; `-AKC' is equivalent to `-AMC'. 399 Synonyms are provided for compatibility with other tools. 400 401 If you do not specify any of these options, `as' generates code 402 for any instruction or feature that is supported by _some_ version 403 of the 960 (even if this means mixing architectures!). In 404 principle, `as' attempts to deduce the minimal sufficient 405 processor type if none is specified; depending on the object code 406 format, the processor type may be recorded in the object file. If 407 it is critical that the `as' output match a specific architecture, 408 specify that architecture explicitly. 409 410`-b' 411 Add code to collect information about conditional branches taken, 412 for later optimization using branch prediction bits. (The 413 conditional branch instructions have branch prediction bits in the 414 CA, CB, and CC architectures.) If BR represents a conditional 415 branch instruction, the following represents the code generated by 416 the assembler when `-b' is specified: 417 418 call INCREMENT ROUTINE 419 .word 0 # pre-counter 420 Label: BR 421 call INCREMENT ROUTINE 422 .word 0 # post-counter 423 424 The counter following a branch records the number of times that 425 branch was _not_ taken; the differenc between the two counters is 426 the number of times the branch _was_ taken. 427 428 A table of every such `Label' is also generated, so that the 429 external postprocessor `gbr960' (supplied by Intel) can locate all 430 the counters. This table is always labeled `__BRANCH_TABLE__'; 431 this is a local symbol to permit collecting statistics for many 432 separate object files. The table is word aligned, and begins with 433 a two-word header. The first word, initialized to 0, is used in 434 maintaining linked lists of branch tables. The second word is a 435 count of the number of entries in the table, which follow 436 immediately: each is a word, pointing to one of the labels 437 illustrated above. 438 439 +------------+------------+------------+ ... +------------+ 440 | | | | | | 441 | *NEXT | COUNT: N | *BRLAB 1 | | *BRLAB N | 442 | | | | | | 443 +------------+------------+------------+ ... +------------+ 444 445 __BRANCH_TABLE__ layout 446 447 The first word of the header is used to locate multiple branch 448 tables, since each object file may contain one. Normally the links 449 are maintained with a call to an initialization routine, placed at 450 the beginning of each function in the file. The GNU C compiler 451 generates these calls automatically when you give it a `-b' option. 452 For further details, see the documentation of `gbr960'. 453 454`-no-relax' 455 Normally, Compare-and-Branch instructions with targets that require 456 displacements greater than 13 bits (or that have external targets) 457 are replaced with the corresponding compare (or `chkbit') and 458 branch instructions. You can use the `-no-relax' option to 459 specify that `as' should generate errors instead, if the target 460 displacement is larger than 13 bits. 461 462 This option does not affect the Compare-and-Jump instructions; the 463 code emitted for them is _always_ adjusted when necessary 464 (depending on displacement size), regardless of whether you use 465 `-no-relax'. 466 467 468File: as.info, Node: Floating Point-i960, Next: Directives-i960, Prev: Options-i960, Up: i960-Dependent 469 4708.14.2 Floating Point 471--------------------- 472 473`as' generates IEEE floating-point numbers for the directives `.float', 474`.double', `.extended', and `.single'. 475 476 477File: as.info, Node: Directives-i960, Next: Opcodes for i960, Prev: Floating Point-i960, Up: i960-Dependent 478 4798.14.3 i960 Machine Directives 480------------------------------ 481 482`.bss SYMBOL, LENGTH, ALIGN' 483 Reserve LENGTH bytes in the bss section for a local SYMBOL, 484 aligned to the power of two specified by ALIGN. LENGTH and ALIGN 485 must be positive absolute expressions. This directive differs 486 from `.lcomm' only in that it permits you to specify an alignment. 487 *Note `.lcomm': Lcomm. 488 489`.extended FLONUMS' 490 `.extended' expects zero or more flonums, separated by commas; for 491 each flonum, `.extended' emits an IEEE extended-format (80-bit) 492 floating-point number. 493 494`.leafproc CALL-LAB, BAL-LAB' 495 You can use the `.leafproc' directive in conjunction with the 496 optimized `callj' instruction to enable faster calls of leaf 497 procedures. If a procedure is known to call no other procedures, 498 you may define an entry point that skips procedure prolog code 499 (and that does not depend on system-supplied saved context), and 500 declare it as the BAL-LAB using `.leafproc'. If the procedure 501 also has an entry point that goes through the normal prolog, you 502 can specify that entry point as CALL-LAB. 503 504 A `.leafproc' declaration is meant for use in conjunction with the 505 optimized call instruction `callj'; the directive records the data 506 needed later to choose between converting the `callj' into a `bal' 507 or a `call'. 508 509 CALL-LAB is optional; if only one argument is present, or if the 510 two arguments are identical, the single argument is assumed to be 511 the `bal' entry point. 512 513`.sysproc NAME, INDEX' 514 The `.sysproc' directive defines a name for a system procedure. 515 After you define it using `.sysproc', you can use NAME to refer to 516 the system procedure identified by INDEX when calling procedures 517 with the optimized call instruction `callj'. 518 519 Both arguments are required; INDEX must be between 0 and 31 520 (inclusive). 521 522 523File: as.info, Node: Opcodes for i960, Prev: Directives-i960, Up: i960-Dependent 524 5258.14.4 i960 Opcodes 526------------------- 527 528All Intel 960 machine instructions are supported; *note i960 529Command-line Options: Options-i960. for a discussion of selecting the 530instruction subset for a particular 960 architecture. 531 532 Some opcodes are processed beyond simply emitting a single 533corresponding instruction: `callj', and Compare-and-Branch or 534Compare-and-Jump instructions with target displacements larger than 13 535bits. 536 537* Menu: 538 539* callj-i960:: `callj' 540* Compare-and-branch-i960:: Compare-and-Branch 541 542 543File: as.info, Node: callj-i960, Next: Compare-and-branch-i960, Up: Opcodes for i960 544 5458.14.4.1 `callj' 546................ 547 548You can write `callj' to have the assembler or the linker determine the 549most appropriate form of subroutine call: `call', `bal', or `calls'. 550If the assembly source contains enough information--a `.leafproc' or 551`.sysproc' directive defining the operand--then `as' translates the 552`callj'; if not, it simply emits the `callj', leaving it for the linker 553to resolve. 554 555 556File: as.info, Node: Compare-and-branch-i960, Prev: callj-i960, Up: Opcodes for i960 557 5588.14.4.2 Compare-and-Branch 559........................... 560 561The 960 architectures provide combined Compare-and-Branch instructions 562that permit you to store the branch target in the lower 13 bits of the 563instruction word itself. However, if you specify a branch target far 564enough away that its address won't fit in 13 bits, the assembler can 565either issue an error, or convert your Compare-and-Branch instruction 566into separate instructions to do the compare and the branch. 567 568 Whether `as' gives an error or expands the instruction depends on 569two choices you can make: whether you use the `-no-relax' option, and 570whether you use a "Compare and Branch" instruction or a "Compare and 571Jump" instruction. The "Jump" instructions are _always_ expanded if 572necessary; the "Branch" instructions are expanded when necessary 573_unless_ you specify `-no-relax'--in which case `as' gives an error 574instead. 575 576 These are the Compare-and-Branch instructions, their "Jump" variants, 577and the instruction pairs they may expand into: 578 579 Compare and 580 Branch Jump Expanded to 581 ------ ------ ------------ 582 bbc chkbit; bno 583 bbs chkbit; bo 584 cmpibe cmpije cmpi; be 585 cmpibg cmpijg cmpi; bg 586 cmpibge cmpijge cmpi; bge 587 cmpibl cmpijl cmpi; bl 588 cmpible cmpijle cmpi; ble 589 cmpibno cmpijno cmpi; bno 590 cmpibne cmpijne cmpi; bne 591 cmpibo cmpijo cmpi; bo 592 cmpobe cmpoje cmpo; be 593 cmpobg cmpojg cmpo; bg 594 cmpobge cmpojge cmpo; bge 595 cmpobl cmpojl cmpo; bl 596 cmpoble cmpojle cmpo; ble 597 cmpobne cmpojne cmpo; bne 598 599 600File: as.info, Node: IA-64-Dependent, Next: IP2K-Dependent, Prev: i960-Dependent, Up: Machine Dependencies 601 6028.15 IA-64 Dependent Features 603============================= 604 605* Menu: 606 607* IA-64 Options:: Options 608* IA-64 Syntax:: Syntax 609* IA-64 Opcodes:: Opcodes 610 611 612File: as.info, Node: IA-64 Options, Next: IA-64 Syntax, Up: IA-64-Dependent 613 6148.15.1 Options 615-------------- 616 617`-mconstant-gp' 618 This option instructs the assembler to mark the resulting object 619 file as using the "constant GP" model. With this model, it is 620 assumed that the entire program uses a single global pointer (GP) 621 value. Note that this option does not in any fashion affect the 622 machine code emitted by the assembler. All it does is turn on the 623 EF_IA_64_CONS_GP flag in the ELF file header. 624 625`-mauto-pic' 626 This option instructs the assembler to mark the resulting object 627 file as using the "constant GP without function descriptor" data 628 model. This model is like the "constant GP" model, except that it 629 additionally does away with function descriptors. What this means 630 is that the address of a function refers directly to the 631 function's code entry-point. Normally, such an address would 632 refer to a function descriptor, which contains both the code 633 entry-point and the GP-value needed by the function. Note that 634 this option does not in any fashion affect the machine code 635 emitted by the assembler. All it does is turn on the 636 EF_IA_64_NOFUNCDESC_CONS_GP flag in the ELF file header. 637 638`-milp32' 639 640`-milp64' 641 642`-mlp64' 643 644`-mp64' 645 These options select the data model. The assembler defaults to 646 `-mlp64' (LP64 data model). 647 648`-mle' 649 650`-mbe' 651 These options select the byte order. The `-mle' option selects 652 little-endian byte order (default) and `-mbe' selects big-endian 653 byte order. Note that IA-64 machine code always uses 654 little-endian byte order. 655 656`-munwind-check=warning' 657 658`-munwind-check=error' 659 These options control what the assembler will do when performing 660 consistency checks on unwind directives. `-munwind-check=warning' 661 will make the assembler issue a warning when an unwind directive 662 check fails. This is the default. `-munwind-check=error' will 663 make the assembler issue an error when an unwind directive check 664 fails. 665 666`-mhint.b=ok' 667 668`-mhint.b=warning' 669 670`-mhint.b=error' 671 These options control what the assembler will do when the `hint.b' 672 instruction is used. `-mhint.b=ok' will make the assembler accept 673 `hint.b'. `-mint.b=warning' will make the assembler issue a 674 warning when `hint.b' is used. `-mhint.b=error' will make the 675 assembler treat `hint.b' as an error, which is the default. 676 677`-x' 678 679`-xexplicit' 680 These options turn on dependency violation checking. 681 682`-xauto' 683 This option instructs the assembler to automatically insert stop 684 bits where necessary to remove dependency violations. This is the 685 default mode. 686 687`-xnone' 688 This option turns off dependency violation checking. 689 690`-xdebug' 691 This turns on debug output intended to help tracking down bugs in 692 the dependency violation checker. 693 694`-xdebugn' 695 This is a shortcut for -xnone -xdebug. 696 697`-xdebugx' 698 This is a shortcut for -xexplicit -xdebug. 699 700 701 702File: as.info, Node: IA-64 Syntax, Next: IA-64 Opcodes, Prev: IA-64 Options, Up: IA-64-Dependent 703 7048.15.2 Syntax 705------------- 706 707The assembler syntax closely follows the IA-64 Assembly Language 708Reference Guide. 709 710* Menu: 711 712* IA-64-Chars:: Special Characters 713* IA-64-Regs:: Register Names 714* IA-64-Bits:: Bit Names 715 716 717File: as.info, Node: IA-64-Chars, Next: IA-64-Regs, Up: IA-64 Syntax 718 7198.15.2.1 Special Characters 720........................... 721 722`//' is the line comment token. 723 724 `;' can be used instead of a newline to separate statements. 725 726 727File: as.info, Node: IA-64-Regs, Next: IA-64-Bits, Prev: IA-64-Chars, Up: IA-64 Syntax 728 7298.15.2.2 Register Names 730....................... 731 732The 128 integer registers are referred to as `rN'. The 128 733floating-point registers are referred to as `fN'. The 128 application 734registers are referred to as `arN'. The 128 control registers are 735referred to as `crN'. The 64 one-bit predicate registers are referred 736to as `pN'. The 8 branch registers are referred to as `bN'. In 737addition, the assembler defines a number of aliases: `gp' (`r1'), `sp' 738(`r12'), `rp' (`b0'), `ret0' (`r8'), `ret1' (`r9'), `ret2' (`r10'), 739`ret3' (`r9'), `fargN' (`f8+N'), and `fretN' (`f8+N'). 740 741 For convenience, the assembler also defines aliases for all named 742application and control registers. For example, `ar.bsp' refers to the 743register backing store pointer (`ar17'). Similarly, `cr.eoi' refers to 744the end-of-interrupt register (`cr67'). 745 746 747File: as.info, Node: IA-64-Bits, Prev: IA-64-Regs, Up: IA-64 Syntax 748 7498.15.2.3 IA-64 Processor-Status-Register (PSR) Bit Names 750........................................................ 751 752The assembler defines bit masks for each of the bits in the IA-64 753processor status register. For example, `psr.ic' corresponds to a 754value of 0x2000. These masks are primarily intended for use with the 755`ssm'/`sum' and `rsm'/`rum' instructions, but they can be used anywhere 756else where an integer constant is expected. 757 758 759File: as.info, Node: IA-64 Opcodes, Prev: IA-64 Syntax, Up: IA-64-Dependent 760 7618.15.3 Opcodes 762-------------- 763 764For detailed information on the IA-64 machine instruction set, see the 765IA-64 Architecture Handbook 766(http://developer.intel.com/design/itanium/arch_spec.htm). 767 768 769File: as.info, Node: IP2K-Dependent, Next: M32R-Dependent, Prev: IA-64-Dependent, Up: Machine Dependencies 770 7718.16 IP2K Dependent Features 772============================ 773 774* Menu: 775 776* IP2K-Opts:: IP2K Options 777 778 779File: as.info, Node: IP2K-Opts, Up: IP2K-Dependent 780 7818.16.1 IP2K Options 782------------------- 783 784The Ubicom IP2K version of `as' has a few machine dependent options: 785 786`-mip2022ext' 787 `as' can assemble the extended IP2022 instructions, but it will 788 only do so if this is specifically allowed via this command line 789 option. 790 791`-mip2022' 792 This option restores the assembler's default behaviour of not 793 permitting the extended IP2022 instructions to be assembled. 794 795 796 797File: as.info, Node: M32R-Dependent, Next: M68K-Dependent, Prev: IP2K-Dependent, Up: Machine Dependencies 798 7998.17 M32R Dependent Features 800============================ 801 802* Menu: 803 804* M32R-Opts:: M32R Options 805* M32R-Directives:: M32R Directives 806* M32R-Warnings:: M32R Warnings 807 808 809File: as.info, Node: M32R-Opts, Next: M32R-Directives, Up: M32R-Dependent 810 8118.17.1 M32R Options 812------------------- 813 814The Renease M32R version of `as' has a few machine dependent options: 815 816`-m32rx' 817 `as' can assemble code for several different members of the 818 Renesas M32R family. Normally the default is to assemble code for 819 the M32R microprocessor. This option may be used to change the 820 default to the M32RX microprocessor, which adds some more 821 instructions to the basic M32R instruction set, and some 822 additional parameters to some of the original instructions. 823 824`-m32r2' 825 This option changes the target processor to the the M32R2 826 microprocessor. 827 828`-m32r' 829 This option can be used to restore the assembler's default 830 behaviour of assembling for the M32R microprocessor. This can be 831 useful if the default has been changed by a previous command line 832 option. 833 834`-little' 835 This option tells the assembler to produce little-endian code and 836 data. The default is dependent upon how the toolchain was 837 configured. 838 839`-EL' 840 This is a synonum for _-little_. 841 842`-big' 843 This option tells the assembler to produce big-endian code and 844 data. 845 846`-EB' 847 This is a synonum for _-big_. 848 849`-KPIC' 850 This option specifies that the output of the assembler should be 851 marked as position-independent code (PIC). 852 853`-parallel' 854 This option tells the assembler to attempts to combine two 855 sequential instructions into a single, parallel instruction, where 856 it is legal to do so. 857 858`-no-parallel' 859 This option disables a previously enabled _-parallel_ option. 860 861`-no-bitinst' 862 This option disables the support for the extended bit-field 863 instructions provided by the M32R2. If this support needs to be 864 re-enabled the _-bitinst_ switch can be used to restore it. 865 866`-O' 867 This option tells the assembler to attempt to optimize the 868 instructions that it produces. This includes filling delay slots 869 and converting sequential instructions into parallel ones. This 870 option implies _-parallel_. 871 872`-warn-explicit-parallel-conflicts' 873 Instructs `as' to produce warning messages when questionable 874 parallel instructions are encountered. This option is enabled by 875 default, but `gcc' disables it when it invokes `as' directly. 876 Questionable instructions are those whoes behaviour would be 877 different if they were executed sequentially. For example the 878 code fragment `mv r1, r2 || mv r3, r1' produces a different result 879 from `mv r1, r2 \n mv r3, r1' since the former moves r1 into r3 880 and then r2 into r1, whereas the later moves r2 into r1 and r3. 881 882`-Wp' 883 This is a shorter synonym for the 884 _-warn-explicit-parallel-conflicts_ option. 885 886`-no-warn-explicit-parallel-conflicts' 887 Instructs `as' not to produce warning messages when questionable 888 parallel instructions are encountered. 889 890`-Wnp' 891 This is a shorter synonym for the 892 _-no-warn-explicit-parallel-conflicts_ option. 893 894`-ignore-parallel-conflicts' 895 This option tells the assembler's to stop checking parallel 896 instructions for contraint violations. This ability is provided 897 for hardware vendors testing chip designs and should not be used 898 under normal circumstances. 899 900`-no-ignore-parallel-conflicts' 901 This option restores the assembler's default behaviour of checking 902 parallel instructions to detect constraint violations. 903 904`-Ip' 905 This is a shorter synonym for the _-ignore-parallel-conflicts_ 906 option. 907 908`-nIp' 909 This is a shorter synonym for the _-no-ignore-parallel-conflicts_ 910 option. 911 912`-warn-unmatched-high' 913 This option tells the assembler to produce a warning message if a 914 `.high' pseudo op is encountered without a mathcing `.low' pseudo 915 op. The presence of such an unmatches pseudo op usually indicates 916 a programming error. 917 918`-no-warn-unmatched-high' 919 Disables a previously enabled _-warn-unmatched-high_ option. 920 921`-Wuh' 922 This is a shorter synonym for the _-warn-unmatched-high_ option. 923 924`-Wnuh' 925 This is a shorter synonym for the _-no-warn-unmatched-high_ option. 926 927 928 929File: as.info, Node: M32R-Directives, Next: M32R-Warnings, Prev: M32R-Opts, Up: M32R-Dependent 930 9318.17.2 M32R Directives 932---------------------- 933 934The Renease M32R version of `as' has a few architecture specific 935directives: 936 937`low EXPRESSION' 938 The `low' directive computes the value of its expression and 939 places the lower 16-bits of the result into the immediate-field of 940 the instruction. For example: 941 942 or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678 943 add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred 944 945`high EXPRESSION' 946 The `high' directive computes the value of its expression and 947 places the upper 16-bits of the result into the immediate-field of 948 the instruction. For example: 949 950 seth r0, #high(0x12345678) ; compute r0 = 0x12340000 951 seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred 952 953`shigh EXPRESSION' 954 The `shigh' directive is very similar to the `high' directive. It 955 also computes the value of its expression and places the upper 956 16-bits of the result into the immediate-field of the instruction. 957 The difference is that `shigh' also checks to see if the lower 958 16-bits could be interpreted as a signed number, and if so it 959 assumes that a borrow will occur from the upper-16 bits. To 960 compensate for this the `shigh' directive pre-biases the upper 16 961 bit value by adding one to it. For example: 962 963 For example: 964 965 seth r0, #shigh(0x12345678) ; compute r0 = 0x12340000 966 seth r0, #shigh(0x00008000) ; compute r0 = 0x00010000 967 968 In the second example the lower 16-bits are 0x8000. If these are 969 treated as a signed value and sign extended to 32-bits then the 970 value becomes 0xffff8000. If this value is then added to 971 0x00010000 then the result is 0x00008000. 972 973 This behaviour is to allow for the different semantics of the 974 `or3' and `add3' instructions. The `or3' instruction treats its 975 16-bit immediate argument as unsigned whereas the `add3' treats 976 its 16-bit immediate as a signed value. So for example: 977 978 seth r0, #shigh(0x00008000) 979 add3 r0, r0, #low(0x00008000) 980 981 Produces the correct result in r0, whereas: 982 983 seth r0, #shigh(0x00008000) 984 or3 r0, r0, #low(0x00008000) 985 986 Stores 0xffff8000 into r0. 987 988 Note - the `shigh' directive does not know where in the assembly 989 source code the lower 16-bits of the value are going set, so it 990 cannot check to make sure that an `or3' instruction is being used 991 rather than an `add3' instruction. It is up to the programmer to 992 make sure that correct directives are used. 993 994`.m32r' 995 The directive performs a similar thing as the _-m32r_ command line 996 option. It tells the assembler to only accept M32R instructions 997 from now on. An instructions from later M32R architectures are 998 refused. 999 1000`.m32rx' 1001 The directive performs a similar thing as the _-m32rx_ command 1002 line option. It tells the assembler to start accepting the extra 1003 instructions in the M32RX ISA as well as the ordinary M32R ISA. 1004 1005`.m32r2' 1006 The directive performs a similar thing as the _-m32r2_ command 1007 line option. It tells the assembler to start accepting the extra 1008 instructions in the M32R2 ISA as well as the ordinary M32R ISA. 1009 1010`.little' 1011 The directive performs a similar thing as the _-little_ command 1012 line option. It tells the assembler to start producing 1013 little-endian code and data. This option should be used with care 1014 as producing mixed-endian binary files is frought with danger. 1015 1016`.big' 1017 The directive performs a similar thing as the _-big_ command line 1018 option. It tells the assembler to start producing big-endian code 1019 and data. This option should be used with care as producing 1020 mixed-endian binary files is frought with danger. 1021 1022 1023 1024File: as.info, Node: M32R-Warnings, Prev: M32R-Directives, Up: M32R-Dependent 1025 10268.17.3 M32R Warnings 1027-------------------- 1028 1029There are several warning and error messages that can be produced by 1030`as' which are specific to the M32R: 1031 1032`output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?' 1033 This message is only produced if warnings for explicit parallel 1034 conflicts have been enabled. It indicates that the assembler has 1035 encountered a parallel instruction in which the destination 1036 register of the left hand instruction is used as an input register 1037 in the right hand instruction. For example in this code fragment 1038 `mv r1, r2 || neg r3, r1' register r1 is the destination of the 1039 move instruction and the input to the neg instruction. 1040 1041`output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?' 1042 This message is only produced if warnings for explicit parallel 1043 conflicts have been enabled. It indicates that the assembler has 1044 encountered a parallel instruction in which the destination 1045 register of the right hand instruction is used as an input 1046 register in the left hand instruction. For example in this code 1047 fragment `mv r1, r2 || neg r2, r3' register r2 is the destination 1048 of the neg instruction and the input to the move instruction. 1049 1050`instruction `...' is for the M32RX only' 1051 This message is produced when the assembler encounters an 1052 instruction which is only supported by the M32Rx processor, and 1053 the `-m32rx' command line flag has not been specified to allow 1054 assembly of such instructions. 1055 1056`unknown instruction `...'' 1057 This message is produced when the assembler encounters an 1058 instruction which it does not recognise. 1059 1060`only the NOP instruction can be issued in parallel on the m32r' 1061 This message is produced when the assembler encounters a parallel 1062 instruction which does not involve a NOP instruction and the 1063 `-m32rx' command line flag has not been specified. Only the M32Rx 1064 processor is able to execute two instructions in parallel. 1065 1066`instruction `...' cannot be executed in parallel.' 1067 This message is produced when the assembler encounters a parallel 1068 instruction which is made up of one or two instructions which 1069 cannot be executed in parallel. 1070 1071`Instructions share the same execution pipeline' 1072 This message is produced when the assembler encounters a parallel 1073 instruction whoes components both use the same execution pipeline. 1074 1075`Instructions write to the same destination register.' 1076 This message is produced when the assembler encounters a parallel 1077 instruction where both components attempt to modify the same 1078 register. For example these code fragments will produce this 1079 message: `mv r1, r2 || neg r1, r3' `jl r0 || mv r14, r1' `st r2, 1080 @-r1 || mv r1, r3' `mv r1, r2 || ld r0, @r1+' `cmp r1, r2 || addx 1081 r3, r4' (Both write to the condition bit) 1082 1083 1084 1085File: as.info, Node: M68K-Dependent, Next: M68HC11-Dependent, Prev: M32R-Dependent, Up: Machine Dependencies 1086 10878.18 M680x0 Dependent Features 1088============================== 1089 1090* Menu: 1091 1092* M68K-Opts:: M680x0 Options 1093* M68K-Syntax:: Syntax 1094* M68K-Moto-Syntax:: Motorola Syntax 1095* M68K-Float:: Floating Point 1096* M68K-Directives:: 680x0 Machine Directives 1097* M68K-opcodes:: Opcodes 1098 1099 1100File: as.info, Node: M68K-Opts, Next: M68K-Syntax, Up: M68K-Dependent 1101 11028.18.1 M680x0 Options 1103--------------------- 1104 1105The Motorola 680x0 version of `as' has a few machine dependent options: 1106 1107`-l' 1108 You can use the `-l' option to shorten the size of references to 1109 undefined symbols. If you do not use the `-l' option, references 1110 to undefined symbols are wide enough for a full `long' (32 bits). 1111 (Since `as' cannot know where these symbols end up, `as' can only 1112 allocate space for the linker to fill in later. Since `as' does 1113 not know how far away these symbols are, it allocates as much 1114 space as it can.) If you use this option, the references are only 1115 one word wide (16 bits). This may be useful if you want the 1116 object file to be as small as possible, and you know that the 1117 relevant symbols are always less than 17 bits away. 1118 1119`--register-prefix-optional' 1120 For some configurations, especially those where the compiler 1121 normally does not prepend an underscore to the names of user 1122 variables, the assembler requires a `%' before any use of a 1123 register name. This is intended to let the assembler distinguish 1124 between C variables and functions named `a0' through `a7', and so 1125 on. The `%' is always accepted, but is not required for certain 1126 configurations, notably `sun3'. The `--register-prefix-optional' 1127 option may be used to permit omitting the `%' even for 1128 configurations for which it is normally required. If this is 1129 done, it will generally be impossible to refer to C variables and 1130 functions with the same names as register names. 1131 1132`--bitwise-or' 1133 Normally the character `|' is treated as a comment character, which 1134 means that it can not be used in expressions. The `--bitwise-or' 1135 option turns `|' into a normal character. In this mode, you must 1136 either use C style comments, or start comments with a `#' character 1137 at the beginning of a line. 1138 1139`--base-size-default-16 --base-size-default-32' 1140 If you use an addressing mode with a base register without 1141 specifying the size, `as' will normally use the full 32 bit value. 1142 For example, the addressing mode `%a0@(%d0)' is equivalent to 1143 `%a0@(%d0:l)'. You may use the `--base-size-default-16' option to 1144 tell `as' to default to using the 16 bit value. In this case, 1145 `%a0@(%d0)' is equivalent to `%a0@(%d0:w)'. You may use the 1146 `--base-size-default-32' option to restore the default behaviour. 1147 1148`--disp-size-default-16 --disp-size-default-32' 1149 If you use an addressing mode with a displacement, and the value 1150 of the displacement is not known, `as' will normally assume that 1151 the value is 32 bits. For example, if the symbol `disp' has not 1152 been defined, `as' will assemble the addressing mode 1153 `%a0@(disp,%d0)' as though `disp' is a 32 bit value. You may use 1154 the `--disp-size-default-16' option to tell `as' to instead assume 1155 that the displacement is 16 bits. In this case, `as' will 1156 assemble `%a0@(disp,%d0)' as though `disp' is a 16 bit value. You 1157 may use the `--disp-size-default-32' option to restore the default 1158 behaviour. 1159 1160`--pcrel' 1161 Always keep branches PC-relative. In the M680x0 architecture all 1162 branches are defined as PC-relative. However, on some processors 1163 they are limited to word displacements maximum. When `as' needs a 1164 long branch that is not available, it normally emits an absolute 1165 jump instead. This option disables this substitution. When this 1166 option is given and no long branches are available, only word 1167 branches will be emitted. An error message will be generated if a 1168 word branch cannot reach its target. This option has no effect on 1169 68020 and other processors that have long branches. *note Branch 1170 Improvement: M68K-Branch. 1171 1172`-m68000' 1173 `as' can assemble code for several different members of the 1174 Motorola 680x0 family. The default depends upon how `as' was 1175 configured when it was built; normally, the default is to assemble 1176 code for the 68020 microprocessor. The following options may be 1177 used to change the default. These options control which 1178 instructions and addressing modes are permitted. The members of 1179 the 680x0 family are very similar. For detailed information about 1180 the differences, see the Motorola manuals. 1181 1182 `-m68000' 1183 `-m68ec000' 1184 `-m68hc000' 1185 `-m68hc001' 1186 `-m68008' 1187 `-m68302' 1188 `-m68306' 1189 `-m68307' 1190 `-m68322' 1191 `-m68356' 1192 Assemble for the 68000. `-m68008', `-m68302', and so on are 1193 synonyms for `-m68000', since the chips are the same from the 1194 point of view of the assembler. 1195 1196 `-m68010' 1197 Assemble for the 68010. 1198 1199 `-m68020' 1200 `-m68ec020' 1201 Assemble for the 68020. This is normally the default. 1202 1203 `-m68030' 1204 `-m68ec030' 1205 Assemble for the 68030. 1206 1207 `-m68040' 1208 `-m68ec040' 1209 Assemble for the 68040. 1210 1211 `-m68060' 1212 `-m68ec060' 1213 Assemble for the 68060. 1214 1215 `-mcpu32' 1216 `-m68330' 1217 `-m68331' 1218 `-m68332' 1219 `-m68333' 1220 `-m68334' 1221 `-m68336' 1222 `-m68340' 1223 `-m68341' 1224 `-m68349' 1225 `-m68360' 1226 Assemble for the CPU32 family of chips. 1227 1228 `-m5200' 1229 1230 `-m5202' 1231 1232 `-m5204' 1233 1234 `-m5206' 1235 1236 `-m5206e' 1237 1238 `-m521x' 1239 1240 `-m5249' 1241 1242 `-m528x' 1243 1244 `-m5307' 1245 1246 `-m5407' 1247 1248 `-m547x' 1249 1250 `-m548x' 1251 1252 `-mcfv4' 1253 1254 `-mcfv4e' 1255 Assemble for the ColdFire family of chips. 1256 1257 `-m68881' 1258 `-m68882' 1259 Assemble 68881 floating point instructions. This is the 1260 default for the 68020, 68030, and the CPU32. The 68040 and 1261 68060 always support floating point instructions. 1262 1263 `-mno-68881' 1264 Do not assemble 68881 floating point instructions. This is 1265 the default for 68000 and the 68010. The 68040 and 68060 1266 always support floating point instructions, even if this 1267 option is used. 1268 1269 `-m68851' 1270 Assemble 68851 MMU instructions. This is the default for the 1271 68020, 68030, and 68060. The 68040 accepts a somewhat 1272 different set of MMU instructions; `-m68851' and `-m68040' 1273 should not be used together. 1274 1275 `-mno-68851' 1276 Do not assemble 68851 MMU instructions. This is the default 1277 for the 68000, 68010, and the CPU32. The 68040 accepts a 1278 somewhat different set of MMU instructions. 1279 1280 1281File: as.info, Node: M68K-Syntax, Next: M68K-Moto-Syntax, Prev: M68K-Opts, Up: M68K-Dependent 1282 12838.18.2 Syntax 1284------------- 1285 1286This syntax for the Motorola 680x0 was developed at MIT. 1287 1288 The 680x0 version of `as' uses instructions names and syntax 1289compatible with the Sun assembler. Intervening periods are ignored; 1290for example, `movl' is equivalent to `mov.l'. 1291 1292 In the following table APC stands for any of the address registers 1293(`%a0' through `%a7'), the program counter (`%pc'), the zero-address 1294relative to the program counter (`%zpc'), a suppressed address register 1295(`%za0' through `%za7'), or it may be omitted entirely. The use of 1296SIZE means one of `w' or `l', and it may be omitted, along with the 1297leading colon, unless a scale is also specified. The use of SCALE 1298means one of `1', `2', `4', or `8', and it may always be omitted along 1299with the leading colon. 1300 1301 The following addressing modes are understood: 1302"Immediate" 1303 `#NUMBER' 1304 1305"Data Register" 1306 `%d0' through `%d7' 1307 1308"Address Register" 1309 `%a0' through `%a7' 1310 `%a7' is also known as `%sp', i.e. the Stack Pointer. `%a6' is 1311 also known as `%fp', the Frame Pointer. 1312 1313"Address Register Indirect" 1314 `%a0@' through `%a7@' 1315 1316"Address Register Postincrement" 1317 `%a0@+' through `%a7@+' 1318 1319"Address Register Predecrement" 1320 `%a0@-' through `%a7@-' 1321 1322"Indirect Plus Offset" 1323 `APC@(NUMBER)' 1324 1325"Index" 1326 `APC@(NUMBER,REGISTER:SIZE:SCALE)' 1327 1328 The NUMBER may be omitted. 1329 1330"Postindex" 1331 `APC@(NUMBER)@(ONUMBER,REGISTER:SIZE:SCALE)' 1332 1333 The ONUMBER or the REGISTER, but not both, may be omitted. 1334 1335"Preindex" 1336 `APC@(NUMBER,REGISTER:SIZE:SCALE)@(ONUMBER)' 1337 1338 The NUMBER may be omitted. Omitting the REGISTER produces the 1339 Postindex addressing mode. 1340 1341"Absolute" 1342 `SYMBOL', or `DIGITS', optionally followed by `:b', `:w', or `:l'. 1343 1344 1345File: as.info, Node: M68K-Moto-Syntax, Next: M68K-Float, Prev: M68K-Syntax, Up: M68K-Dependent 1346 13478.18.3 Motorola Syntax 1348---------------------- 1349 1350The standard Motorola syntax for this chip differs from the syntax 1351already discussed (*note Syntax: M68K-Syntax.). `as' can accept 1352Motorola syntax for operands, even if MIT syntax is used for other 1353operands in the same instruction. The two kinds of syntax are fully 1354compatible. 1355 1356 In the following table APC stands for any of the address registers 1357(`%a0' through `%a7'), the program counter (`%pc'), the zero-address 1358relative to the program counter (`%zpc'), or a suppressed address 1359register (`%za0' through `%za7'). The use of SIZE means one of `w' or 1360`l', and it may always be omitted along with the leading dot. The use 1361of SCALE means one of `1', `2', `4', or `8', and it may always be 1362omitted along with the leading asterisk. 1363 1364 The following additional addressing modes are understood: 1365 1366"Address Register Indirect" 1367 `(%a0)' through `(%a7)' 1368 `%a7' is also known as `%sp', i.e. the Stack Pointer. `%a6' is 1369 also known as `%fp', the Frame Pointer. 1370 1371"Address Register Postincrement" 1372 `(%a0)+' through `(%a7)+' 1373 1374"Address Register Predecrement" 1375 `-(%a0)' through `-(%a7)' 1376 1377"Indirect Plus Offset" 1378 `NUMBER(%A0)' through `NUMBER(%A7)', or `NUMBER(%PC)'. 1379 1380 The NUMBER may also appear within the parentheses, as in 1381 `(NUMBER,%A0)'. When used with the PC, the NUMBER may be omitted 1382 (with an address register, omitting the NUMBER produces Address 1383 Register Indirect mode). 1384 1385"Index" 1386 `NUMBER(APC,REGISTER.SIZE*SCALE)' 1387 1388 The NUMBER may be omitted, or it may appear within the 1389 parentheses. The APC may be omitted. The REGISTER and the APC 1390 may appear in either order. If both APC and REGISTER are address 1391 registers, and the SIZE and SCALE are omitted, then the first 1392 register is taken as the base register, and the second as the 1393 index register. 1394 1395"Postindex" 1396 `([NUMBER,APC],REGISTER.SIZE*SCALE,ONUMBER)' 1397 1398 The ONUMBER, or the REGISTER, or both, may be omitted. Either the 1399 NUMBER or the APC may be omitted, but not both. 1400 1401"Preindex" 1402 `([NUMBER,APC,REGISTER.SIZE*SCALE],ONUMBER)' 1403 1404 The NUMBER, or the APC, or the REGISTER, or any two of them, may 1405 be omitted. The ONUMBER may be omitted. The REGISTER and the APC 1406 may appear in either order. If both APC and REGISTER are address 1407 registers, and the SIZE and SCALE are omitted, then the first 1408 register is taken as the base register, and the second as the 1409 index register. 1410 1411 1412File: as.info, Node: M68K-Float, Next: M68K-Directives, Prev: M68K-Moto-Syntax, Up: M68K-Dependent 1413 14148.18.4 Floating Point 1415--------------------- 1416 1417Packed decimal (P) format floating literals are not supported. Feel 1418free to add the code! 1419 1420 The floating point formats generated by directives are these. 1421 1422`.float' 1423 `Single' precision floating point constants. 1424 1425`.double' 1426 `Double' precision floating point constants. 1427 1428`.extend' 1429`.ldouble' 1430 `Extended' precision (`long double') floating point constants. 1431 1432 1433File: as.info, Node: M68K-Directives, Next: M68K-opcodes, Prev: M68K-Float, Up: M68K-Dependent 1434 14358.18.5 680x0 Machine Directives 1436------------------------------- 1437 1438In order to be compatible with the Sun assembler the 680x0 assembler 1439understands the following directives. 1440 1441`.data1' 1442 This directive is identical to a `.data 1' directive. 1443 1444`.data2' 1445 This directive is identical to a `.data 2' directive. 1446 1447`.even' 1448 This directive is a special case of the `.align' directive; it 1449 aligns the output to an even byte boundary. 1450 1451`.skip' 1452 This directive is identical to a `.space' directive. 1453 1454 1455File: as.info, Node: M68K-opcodes, Prev: M68K-Directives, Up: M68K-Dependent 1456 14578.18.6 Opcodes 1458-------------- 1459 1460* Menu: 1461 1462* M68K-Branch:: Branch Improvement 1463* M68K-Chars:: Special Characters 1464 1465 1466File: as.info, Node: M68K-Branch, Next: M68K-Chars, Up: M68K-opcodes 1467 14688.18.6.1 Branch Improvement 1469........................... 1470 1471Certain pseudo opcodes are permitted for branch instructions. They 1472expand to the shortest branch instruction that reach the target. 1473Generally these mnemonics are made by substituting `j' for `b' at the 1474start of a Motorola mnemonic. 1475 1476 The following table summarizes the pseudo-operations. A `*' flags 1477cases that are more fully described after the table: 1478 1479 Displacement 1480 +------------------------------------------------------------ 1481 | 68020 68000/10, not PC-relative OK 1482 Pseudo-Op |BYTE WORD LONG ABSOLUTE LONG JUMP ** 1483 +------------------------------------------------------------ 1484 jbsr |bsrs bsrw bsrl jsr 1485 jra |bras braw bral jmp 1486 * jXX |bXXs bXXw bXXl bNXs;jmp 1487 * dbXX | N/A dbXXw dbXX;bras;bral dbXX;bras;jmp 1488 fjXX | N/A fbXXw fbXXl N/A 1489 1490 XX: condition 1491 NX: negative of condition XX 1492 `*'--see full description below 1493 `**'--this expansion mode is disallowed by `--pcrel' 1494 1495`jbsr' 1496`jra' 1497 These are the simplest jump pseudo-operations; they always map to 1498 one particular machine instruction, depending on the displacement 1499 to the branch target. This instruction will be a byte or word 1500 branch is that is sufficient. Otherwise, a long branch will be 1501 emitted if available. If no long branches are available and the 1502 `--pcrel' option is not given, an absolute long jump will be 1503 emitted instead. If no long branches are available, the `--pcrel' 1504 option is given, and a word branch cannot reach the target, an 1505 error message is generated. 1506 1507 In addition to standard branch operands, `as' allows these 1508 pseudo-operations to have all operands that are allowed for jsr 1509 and jmp, substituting these instructions if the operand given is 1510 not valid for a branch instruction. 1511 1512`jXX' 1513 Here, `jXX' stands for an entire family of pseudo-operations, 1514 where XX is a conditional branch or condition-code test. The full 1515 list of pseudo-ops in this family is: 1516 jhi jls jcc jcs jne jeq jvc 1517 jvs jpl jmi jge jlt jgt jle 1518 1519 Usually, each of these pseudo-operations expands to a single branch 1520 instruction. However, if a word branch is not sufficient, no long 1521 branches are available, and the `--pcrel' option is not given, `as' 1522 issues a longer code fragment in terms of NX, the opposite 1523 condition to XX. For example, under these conditions: 1524 jXX foo 1525 gives 1526 bNXs oof 1527 jmp foo 1528 oof: 1529 1530`dbXX' 1531 The full family of pseudo-operations covered here is 1532 dbhi dbls dbcc dbcs dbne dbeq dbvc 1533 dbvs dbpl dbmi dbge dblt dbgt dble 1534 dbf dbra dbt 1535 1536 Motorola `dbXX' instructions allow word displacements only. When 1537 a word displacement is sufficient, each of these pseudo-operations 1538 expands to the corresponding Motorola instruction. When a word 1539 displacement is not sufficient and long branches are available, 1540 when the source reads `dbXX foo', `as' emits 1541 dbXX oo1 1542 bras oo2 1543 oo1:bral foo 1544 oo2: 1545 1546 If, however, long branches are not available and the `--pcrel' 1547 option is not given, `as' emits 1548 dbXX oo1 1549 bras oo2 1550 oo1:jmp foo 1551 oo2: 1552 1553`fjXX' 1554 This family includes 1555 fjne fjeq fjge fjlt fjgt fjle fjf 1556 fjt fjgl fjgle fjnge fjngl fjngle fjngt 1557 fjnle fjnlt fjoge fjogl fjogt fjole fjolt 1558 fjor fjseq fjsf fjsne fjst fjueq fjuge 1559 fjugt fjule fjult fjun 1560 1561 Each of these pseudo-operations always expands to a single Motorola 1562 coprocessor branch instruction, word or long. All Motorola 1563 coprocessor branch instructions allow both word and long 1564 displacements. 1565 1566 1567 1568File: as.info, Node: M68K-Chars, Prev: M68K-Branch, Up: M68K-opcodes 1569 15708.18.6.2 Special Characters 1571........................... 1572 1573The immediate character is `#' for Sun compatibility. The line-comment 1574character is `|' (unless the `--bitwise-or' option is used). If a `#' 1575appears at the beginning of a line, it is treated as a comment unless 1576it looks like `# line file', in which case it is treated normally. 1577 1578 1579File: as.info, Node: M68HC11-Dependent, Next: M88K-Dependent, Prev: M68K-Dependent, Up: Machine Dependencies 1580 15818.19 M68HC11 and M68HC12 Dependent Features 1582=========================================== 1583 1584* Menu: 1585 1586* M68HC11-Opts:: M68HC11 and M68HC12 Options 1587* M68HC11-Syntax:: Syntax 1588* M68HC11-Modifiers:: Symbolic Operand Modifiers 1589* M68HC11-Directives:: Assembler Directives 1590* M68HC11-Float:: Floating Point 1591* M68HC11-opcodes:: Opcodes 1592 1593 1594File: as.info, Node: M68HC11-Opts, Next: M68HC11-Syntax, Up: M68HC11-Dependent 1595 15968.19.1 M68HC11 and M68HC12 Options 1597---------------------------------- 1598 1599The Motorola 68HC11 and 68HC12 version of `as' have a few machine 1600dependent options. 1601 1602`-m68hc11' 1603 This option switches the assembler in the M68HC11 mode. In this 1604 mode, the assembler only accepts 68HC11 operands and mnemonics. It 1605 produces code for the 68HC11. 1606 1607`-m68hc12' 1608 This option switches the assembler in the M68HC12 mode. In this 1609 mode, the assembler also accepts 68HC12 operands and mnemonics. It 1610 produces code for the 68HC12. A few 68HC11 instructions are 1611 replaced by some 68HC12 instructions as recommended by Motorola 1612 specifications. 1613 1614`-m68hcs12' 1615 This option switches the assembler in the M68HCS12 mode. This 1616 mode is similar to `-m68hc12' but specifies to assemble for the 1617 68HCS12 series. The only difference is on the assembling of the 1618 `movb' and `movw' instruction when a PC-relative operand is used. 1619 1620`-mshort' 1621 This option controls the ABI and indicates to use a 16-bit integer 1622 ABI. It has no effect on the assembled instructions. This is the 1623 default. 1624 1625`-mlong' 1626 This option controls the ABI and indicates to use a 32-bit integer 1627 ABI. 1628 1629`-mshort-double' 1630 This option controls the ABI and indicates to use a 32-bit float 1631 ABI. This is the default. 1632 1633`-mlong-double' 1634 This option controls the ABI and indicates to use a 64-bit float 1635 ABI. 1636 1637`--strict-direct-mode' 1638 You can use the `--strict-direct-mode' option to disable the 1639 automatic translation of direct page mode addressing into extended 1640 mode when the instruction does not support direct mode. For 1641 example, the `clr' instruction does not support direct page mode 1642 addressing. When it is used with the direct page mode, `as' will 1643 ignore it and generate an absolute addressing. This option 1644 prevents `as' from doing this, and the wrong usage of the direct 1645 page mode will raise an error. 1646 1647`--short-branchs' 1648 The `--short-branchs' option turns off the translation of relative 1649 branches into absolute branches when the branch offset is out of 1650 range. By default `as' transforms the relative branch (`bsr', 1651 `bgt', `bge', `beq', `bne', `ble', `blt', `bhi', `bcc', `bls', 1652 `bcs', `bmi', `bvs', `bvs', `bra') into an absolute branch when 1653 the offset is out of the -128 .. 127 range. In that case, the 1654 `bsr' instruction is translated into a `jsr', the `bra' 1655 instruction is translated into a `jmp' and the conditional branchs 1656 instructions are inverted and followed by a `jmp'. This option 1657 disables these translations and `as' will generate an error if a 1658 relative branch is out of range. This option does not affect the 1659 optimization associated to the `jbra', `jbsr' and `jbXX' pseudo 1660 opcodes. 1661 1662`--force-long-branchs' 1663 The `--force-long-branchs' option forces the translation of 1664 relative branches into absolute branches. This option does not 1665 affect the optimization associated to the `jbra', `jbsr' and 1666 `jbXX' pseudo opcodes. 1667 1668`--print-insn-syntax' 1669 You can use the `--print-insn-syntax' option to obtain the syntax 1670 description of the instruction when an error is detected. 1671 1672`--print-opcodes' 1673 The `--print-opcodes' option prints the list of all the 1674 instructions with their syntax. The first item of each line 1675 represents the instruction name and the rest of the line indicates 1676 the possible operands for that instruction. The list is printed in 1677 alphabetical order. Once the list is printed `as' exits. 1678 1679`--generate-example' 1680 The `--generate-example' option is similar to `--print-opcodes' 1681 but it generates an example for each instruction instead. 1682 1683 1684File: as.info, Node: M68HC11-Syntax, Next: M68HC11-Modifiers, Prev: M68HC11-Opts, Up: M68HC11-Dependent 1685 16868.19.2 Syntax 1687------------- 1688 1689In the M68HC11 syntax, the instruction name comes first and it may be 1690followed by one or several operands (up to three). Operands are 1691separated by comma (`,'). In the normal mode, `as' will complain if too 1692many operands are specified for a given instruction. In the MRI mode 1693(turned on with `-M' option), it will treat them as comments. Example: 1694 1695 inx 1696 lda #23 1697 bset 2,x #4 1698 brclr *bot #8 foo 1699 1700 The following addressing modes are understood for 68HC11 and 68HC12: 1701"Immediate" 1702 `#NUMBER' 1703 1704"Address Register" 1705 `NUMBER,X', `NUMBER,Y' 1706 1707 The NUMBER may be omitted in which case 0 is assumed. 1708 1709"Direct Addressing mode" 1710 `*SYMBOL', or `*DIGITS' 1711 1712"Absolute" 1713 `SYMBOL', or `DIGITS' 1714 1715 The M68HC12 has other more complex addressing modes. All of them are 1716supported and they are represented below: 1717 1718"Constant Offset Indexed Addressing Mode" 1719 `NUMBER,REG' 1720 1721 The NUMBER may be omitted in which case 0 is assumed. The 1722 register can be either `X', `Y', `SP' or `PC'. The assembler will 1723 use the smaller post-byte definition according to the constant 1724 value (5-bit constant offset, 9-bit constant offset or 16-bit 1725 constant offset). If the constant is not known by the assembler 1726 it will use the 16-bit constant offset post-byte and the value 1727 will be resolved at link time. 1728 1729"Offset Indexed Indirect" 1730 `[NUMBER,REG]' 1731 1732 The register can be either `X', `Y', `SP' or `PC'. 1733 1734"Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement" 1735 `NUMBER,-REG' `NUMBER,+REG' `NUMBER,REG-' `NUMBER,REG+' 1736 1737 The number must be in the range `-8'..`+8' and must not be 0. The 1738 register can be either `X', `Y', `SP' or `PC'. 1739 1740"Accumulator Offset" 1741 `ACC,REG' 1742 1743 The accumulator register can be either `A', `B' or `D'. The 1744 register can be either `X', `Y', `SP' or `PC'. 1745 1746"Accumulator D offset indexed-indirect" 1747 `[D,REG]' 1748 1749 The register can be either `X', `Y', `SP' or `PC'. 1750 1751 1752 For example: 1753 1754 ldab 1024,sp 1755 ldd [10,x] 1756 orab 3,+x 1757 stab -2,y- 1758 ldx a,pc 1759 sty [d,sp] 1760 1761 1762File: as.info, Node: M68HC11-Modifiers, Next: M68HC11-Directives, Prev: M68HC11-Syntax, Up: M68HC11-Dependent 1763 17648.19.3 Symbolic Operand Modifiers 1765--------------------------------- 1766 1767The assembler supports several modifiers when using symbol addresses in 176868HC11 and 68HC12 instruction operands. The general syntax is the 1769following: 1770 1771 %modifier(symbol) 1772 1773`%addr' 1774 This modifier indicates to the assembler and linker to use the 1775 16-bit physical address corresponding to the symbol. This is 1776 intended to be used on memory window systems to map a symbol in 1777 the memory bank window. If the symbol is in a memory expansion 1778 part, the physical address corresponds to the symbol address 1779 within the memory bank window. If the symbol is not in a memory 1780 expansion part, this is the symbol address (using or not using the 1781 %addr modifier has no effect in that case). 1782 1783`%page' 1784 This modifier indicates to use the memory page number corresponding 1785 to the symbol. If the symbol is in a memory expansion part, its 1786 page number is computed by the linker as a number used to map the 1787 page containing the symbol in the memory bank window. If the 1788 symbol is not in a memory expansion part, the page number is 0. 1789 1790`%hi' 1791 This modifier indicates to use the 8-bit high part of the physical 1792 address of the symbol. 1793 1794`%lo' 1795 This modifier indicates to use the 8-bit low part of the physical 1796 address of the symbol. 1797 1798 1799 For example a 68HC12 call to a function `foo_example' stored in 1800memory expansion part could be written as follows: 1801 1802 call %addr(foo_example),%page(foo_example) 1803 1804 and this is equivalent to 1805 1806 call foo_example 1807 1808 And for 68HC11 it could be written as follows: 1809 1810 ldab #%page(foo_example) 1811 stab _page_switch 1812 jsr %addr(foo_example) 1813 1814 1815File: as.info, Node: M68HC11-Directives, Next: M68HC11-Float, Prev: M68HC11-Modifiers, Up: M68HC11-Dependent 1816 18178.19.4 Assembler Directives 1818--------------------------- 1819 1820The 68HC11 and 68HC12 version of `as' have the following specific 1821assembler directives: 1822 1823`.relax' 1824 The relax directive is used by the `GNU Compiler' to emit a 1825 specific relocation to mark a group of instructions for linker 1826 relaxation. The sequence of instructions within the group must be 1827 known to the linker so that relaxation can be performed. 1828 1829`.mode [mshort|mlong|mshort-double|mlong-double]' 1830 This directive specifies the ABI. It overrides the `-mshort', 1831 `-mlong', `-mshort-double' and `-mlong-double' options. 1832 1833`.far SYMBOL' 1834 This directive marks the symbol as a `far' symbol meaning that it 1835 uses a `call/rtc' calling convention as opposed to `jsr/rts'. 1836 During a final link, the linker will identify references to the 1837 `far' symbol and will verify the proper calling convention. 1838 1839`.interrupt SYMBOL' 1840 This directive marks the symbol as an interrupt entry point. This 1841 information is then used by the debugger to correctly unwind the 1842 frame across interrupts. 1843 1844`.xrefb SYMBOL' 1845 This directive is defined for compatibility with the 1846 `Specification for Motorola 8 and 16-Bit Assembly Language Input 1847 Standard' and is ignored. 1848 1849 1850 1851File: as.info, Node: M68HC11-Float, Next: M68HC11-opcodes, Prev: M68HC11-Directives, Up: M68HC11-Dependent 1852 18538.19.5 Floating Point 1854--------------------- 1855 1856Packed decimal (P) format floating literals are not supported. Feel 1857free to add the code! 1858 1859 The floating point formats generated by directives are these. 1860 1861`.float' 1862 `Single' precision floating point constants. 1863 1864`.double' 1865 `Double' precision floating point constants. 1866 1867`.extend' 1868`.ldouble' 1869 `Extended' precision (`long double') floating point constants. 1870 1871 1872File: as.info, Node: M68HC11-opcodes, Prev: M68HC11-Float, Up: M68HC11-Dependent 1873 18748.19.6 Opcodes 1875-------------- 1876 1877* Menu: 1878 1879* M68HC11-Branch:: Branch Improvement 1880 1881 1882File: as.info, Node: M68HC11-Branch, Up: M68HC11-opcodes 1883 18848.19.6.1 Branch Improvement 1885........................... 1886 1887Certain pseudo opcodes are permitted for branch instructions. They 1888expand to the shortest branch instruction that reach the target. 1889Generally these mnemonics are made by prepending `j' to the start of 1890Motorola mnemonic. These pseudo opcodes are not affected by the 1891`--short-branchs' or `--force-long-branchs' options. 1892 1893 The following table summarizes the pseudo-operations. 1894 1895 Displacement Width 1896 +-------------------------------------------------------------+ 1897 | Options | 1898 | --short-branchs --force-long-branchs | 1899 +--------------------------+----------------------------------+ 1900 Op |BYTE WORD | BYTE WORD | 1901 +--------------------------+----------------------------------+ 1902 bsr | bsr <pc-rel> <error> | jsr <abs> | 1903 bra | bra <pc-rel> <error> | jmp <abs> | 1904 jbsr | bsr <pc-rel> jsr <abs> | bsr <pc-rel> jsr <abs> | 1905 jbra | bra <pc-rel> jmp <abs> | bra <pc-rel> jmp <abs> | 1906 bXX | bXX <pc-rel> <error> | bNX +3; jmp <abs> | 1907 jbXX | bXX <pc-rel> bNX +3; | bXX <pc-rel> bNX +3; jmp <abs> | 1908 | jmp <abs> | | 1909 +--------------------------+----------------------------------+ 1910 XX: condition 1911 NX: negative of condition XX 1912 1913`jbsr' 1914`jbra' 1915 These are the simplest jump pseudo-operations; they always map to 1916 one particular machine instruction, depending on the displacement 1917 to the branch target. 1918 1919`jbXX' 1920 Here, `jbXX' stands for an entire family of pseudo-operations, 1921 where XX is a conditional branch or condition-code test. The full 1922 list of pseudo-ops in this family is: 1923 jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo 1924 jbcs jbne jblt jble jbls jbvc jbmi 1925 1926 For the cases of non-PC relative displacements and long 1927 displacements, `as' issues a longer code fragment in terms of NX, 1928 the opposite condition to XX. For example, for the non-PC 1929 relative case: 1930 jbXX foo 1931 gives 1932 bNXs oof 1933 jmp foo 1934 oof: 1935 1936 1937 1938File: as.info, Node: M88K-Dependent, Next: MIPS-Dependent, Prev: M68HC11-Dependent, Up: Machine Dependencies 1939 19408.20 Motorola M88K Dependent Features 1941===================================== 1942 1943* Menu: 1944 1945* M88K Directives:: M88K Machine Directives 1946 1947 1948File: as.info, Node: M88K Directives, Up: M88K-Dependent 1949 19508.20.1 M88K Machine Directives 1951------------------------------ 1952 1953The M88K version of the assembler supports the following machine 1954directives: 1955 1956`.align' 1957 This directive aligns the section program counter on the next 1958 4-byte boundary. 1959 1960`.dfloat EXPR' 1961 This assembles a double precision (64-bit) floating point constant. 1962 1963`.ffloat EXPR' 1964 This assembles a single precision (32-bit) floating point constant. 1965 1966`.half EXPR' 1967 This directive assembles a half-word (16-bit) constant. 1968 1969`.word EXPR' 1970 This assembles a word (32-bit) constant. 1971 1972`.string "STR"' 1973 This directive behaves like the standard `.ascii' directive for 1974 copying STR into the object file. The string is not terminated 1975 with a null byte. 1976 1977`.set SYMBOL, VALUE' 1978 This directive creates a symbol named SYMBOL which is an alias for 1979 another symbol (possibly not yet defined). This should not be 1980 confused with the mnemonic `set', which is a legitimate M88K 1981 instruction. 1982 1983`.def SYMBOL, VALUE' 1984 This directive is synonymous with `.set' and is presumably provided 1985 for compatibility with other M88K assemblers. 1986 1987`.bss SYMBOL, LENGTH, ALIGN' 1988 Reserve LENGTH bytes in the bss section for a local SYMBOL, 1989 aligned to the power of two specified by ALIGN. LENGTH and ALIGN 1990 must be positive absolute expressions. This directive differs 1991 from `.lcomm' only in that it permits you to specify an alignment. 1992 *Note `.lcomm': Lcomm. 1993 1994 1995 1996File: as.info, Node: MIPS-Dependent, Next: MMIX-Dependent, Prev: M88K-Dependent, Up: Machine Dependencies 1997 19988.21 MIPS Dependent Features 1999============================ 2000 2001 GNU `as' for MIPS architectures supports several different MIPS 2002processors, and MIPS ISA levels I through V, MIPS32, and MIPS64. For 2003information about the MIPS instruction set, see `MIPS RISC 2004Architecture', by Kane and Heindrich (Prentice-Hall). For an overview 2005of MIPS assembly conventions, see "Appendix D: Assembly Language 2006Programming" in the same work. 2007 2008* Menu: 2009 2010* MIPS Opts:: Assembler options 2011* MIPS Object:: ECOFF object code 2012* MIPS Stabs:: Directives for debugging information 2013* MIPS ISA:: Directives to override the ISA level 2014* MIPS symbol sizes:: Directives to override the size of symbols 2015* MIPS autoextend:: Directives for extending MIPS 16 bit instructions 2016* MIPS insn:: Directive to mark data as an instruction 2017* MIPS option stack:: Directives to save and restore options 2018* MIPS ASE instruction generation overrides:: Directives to control 2019 generation of MIPS ASE instructions 2020 2021 2022File: as.info, Node: MIPS Opts, Next: MIPS Object, Up: MIPS-Dependent 2023 20248.21.1 Assembler options 2025------------------------ 2026 2027The MIPS configurations of GNU `as' support these special options: 2028 2029`-G NUM' 2030 This option sets the largest size of an object that can be 2031 referenced implicitly with the `gp' register. It is only accepted 2032 for targets that use ECOFF format. The default value is 8. 2033 2034`-EB' 2035`-EL' 2036 Any MIPS configuration of `as' can select big-endian or 2037 little-endian output at run time (unlike the other GNU development 2038 tools, which must be configured for one or the other). Use `-EB' 2039 to select big-endian output, and `-EL' for little-endian. 2040 2041`-mips1' 2042`-mips2' 2043`-mips3' 2044`-mips4' 2045`-mips5' 2046`-mips32' 2047`-mips32r2' 2048`-mips64' 2049`-mips64r2' 2050 Generate code for a particular MIPS Instruction Set Architecture 2051 level. `-mips1' corresponds to the R2000 and R3000 processors, 2052 `-mips2' to the R6000 processor, `-mips3' to the R4000 processor, 2053 and `-mips4' to the R8000 and R10000 processors. `-mips5', 2054 `-mips32', `-mips32r2', `-mips64', and `-mips64r2' correspond to 2055 generic MIPS V, MIPS32, MIPS32 RELEASE 2, MIPS64, and MIPS64 2056 RELEASE 2 ISA processors, respectively. You can also switch 2057 instruction sets during the assembly; see *Note Directives to 2058 override the ISA level: MIPS ISA. 2059 2060`-mgp32' 2061`-mfp32' 2062 Some macros have different expansions for 32-bit and 64-bit 2063 registers. The register sizes are normally inferred from the ISA 2064 and ABI, but these flags force a certain group of registers to be 2065 treated as 32 bits wide at all times. `-mgp32' controls the size 2066 of general-purpose registers and `-mfp32' controls the size of 2067 floating-point registers. 2068 2069 On some MIPS variants there is a 32-bit mode flag; when this flag 2070 is set, 64-bit instructions generate a trap. Also, some 32-bit 2071 OSes only save the 32-bit registers on a context switch, so it is 2072 essential never to use the 64-bit registers. 2073 2074`-mgp64' 2075 Assume that 64-bit general purpose registers are available. This 2076 is provided in the interests of symmetry with -gp32. 2077 2078`-mips16' 2079`-no-mips16' 2080 Generate code for the MIPS 16 processor. This is equivalent to 2081 putting `.set mips16' at the start of the assembly file. 2082 `-no-mips16' turns off this option. 2083 2084`-mips3d' 2085`-no-mips3d' 2086 Generate code for the MIPS-3D Application Specific Extension. 2087 This tells the assembler to accept MIPS-3D instructions. 2088 `-no-mips3d' turns off this option. 2089 2090`-mdmx' 2091`-no-mdmx' 2092 Generate code for the MDMX Application Specific Extension. This 2093 tells the assembler to accept MDMX instructions. `-no-mdmx' turns 2094 off this option. 2095 2096`-mfix7000' 2097`-mno-fix7000' 2098 Cause nops to be inserted if the read of the destination register 2099 of an mfhi or mflo instruction occurs in the following two 2100 instructions. 2101 2102`-mfix-vr4120' 2103`-no-mfix-vr4120' 2104 Insert nops to work around certain VR4120 errata. This option is 2105 intended to be used on GCC-generated code: it is not designed to 2106 catch all problems in hand-written assembler code. 2107 2108`-mfix-vr4130' 2109`-no-mfix-vr4130' 2110 Insert nops to work around the VR4130 `mflo'/`mfhi' errata. 2111 2112`-m4010' 2113`-no-m4010' 2114 Generate code for the LSI R4010 chip. This tells the assembler to 2115 accept the R4010 specific instructions (`addciu', `ffc', etc.), 2116 and to not schedule `nop' instructions around accesses to the `HI' 2117 and `LO' registers. `-no-m4010' turns off this option. 2118 2119`-m4650' 2120`-no-m4650' 2121 Generate code for the MIPS R4650 chip. This tells the assembler 2122 to accept the `mad' and `madu' instruction, and to not schedule 2123 `nop' instructions around accesses to the `HI' and `LO' registers. 2124 `-no-m4650' turns off this option. 2125 2126`-m3900' 2127`-no-m3900' 2128`-m4100' 2129`-no-m4100' 2130 For each option `-mNNNN', generate code for the MIPS RNNNN chip. 2131 This tells the assembler to accept instructions specific to that 2132 chip, and to schedule for that chip's hazards. 2133 2134`-march=CPU' 2135 Generate code for a particular MIPS cpu. It is exactly equivalent 2136 to `-mCPU', except that there are more value of CPU understood. 2137 Valid CPU value are: 2138 2139 2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130, 2140 vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231, 2141 rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000, 2142 10000, 12000, mips32-4k, sb1 2143 2144`-mtune=CPU' 2145 Schedule and tune for a particular MIPS cpu. Valid CPU values are 2146 identical to `-march=CPU'. 2147 2148`-mabi=ABI' 2149 Record which ABI the source code uses. The recognized arguments 2150 are: `32', `n32', `o64', `64' and `eabi'. 2151 2152`-msym32' 2153`-mno-sym32' 2154 Equivalent to adding `.set sym32' or `.set nosym32' to the 2155 beginning of the assembler input. *Note MIPS symbol sizes::. 2156 2157`-nocpp' 2158 This option is ignored. It is accepted for command-line 2159 compatibility with other assemblers, which use it to turn off C 2160 style preprocessing. With GNU `as', there is no need for 2161 `-nocpp', because the GNU assembler itself never runs the C 2162 preprocessor. 2163 2164`--construct-floats' 2165`--no-construct-floats' 2166 The `--no-construct-floats' option disables the construction of 2167 double width floating point constants by loading the two halves of 2168 the value into the two single width floating point registers that 2169 make up the double width register. This feature is useful if the 2170 processor support the FR bit in its status register, and this bit 2171 is known (by the programmer) to be set. This bit prevents the 2172 aliasing of the double width register by the single width 2173 registers. 2174 2175 By default `--construct-floats' is selected, allowing construction 2176 of these floating point constants. 2177 2178`--trap' 2179`--no-break' 2180 `as' automatically macro expands certain division and 2181 multiplication instructions to check for overflow and division by 2182 zero. This option causes `as' to generate code to take a trap 2183 exception rather than a break exception when an error is detected. 2184 The trap instructions are only supported at Instruction Set 2185 Architecture level 2 and higher. 2186 2187`--break' 2188`--no-trap' 2189 Generate code to take a break exception rather than a trap 2190 exception when an error is detected. This is the default. 2191 2192`-mpdr' 2193`-mno-pdr' 2194 Control generation of `.pdr' sections. Off by default on IRIX, on 2195 elsewhere. 2196 2197`-mshared' 2198`-mno-shared' 2199 When generating code using the Unix calling conventions (selected 2200 by `-KPIC' or `-mcall_shared'), gas will normally generate code 2201 which can go into a shared library. The `-mno-shared' option 2202 tells gas to generate code which uses the calling convention, but 2203 can not go into a shared library. The resulting code is slightly 2204 more efficient. This option only affects the handling of the 2205 `.cpload' and `.cpsetup' pseudo-ops. 2206 2207 2208File: as.info, Node: MIPS Object, Next: MIPS Stabs, Prev: MIPS Opts, Up: MIPS-Dependent 2209 22108.21.2 MIPS ECOFF object code 2211----------------------------- 2212 2213Assembling for a MIPS ECOFF target supports some additional sections 2214besides the usual `.text', `.data' and `.bss'. The additional sections 2215are `.rdata', used for read-only data, `.sdata', used for small data, 2216and `.sbss', used for small common objects. 2217 2218 When assembling for ECOFF, the assembler uses the `$gp' (`$28') 2219register to form the address of a "small object". Any object in the 2220`.sdata' or `.sbss' sections is considered "small" in this sense. For 2221external objects, or for objects in the `.bss' section, you can use the 2222`gcc' `-G' option to control the size of objects addressed via `$gp'; 2223the default value is 8, meaning that a reference to any object eight 2224bytes or smaller uses `$gp'. Passing `-G 0' to `as' prevents it from 2225using the `$gp' register on the basis of object size (but the assembler 2226uses `$gp' for objects in `.sdata' or `sbss' in any case). The size of 2227an object in the `.bss' section is set by the `.comm' or `.lcomm' 2228directive that defines it. The size of an external object may be set 2229with the `.extern' directive. For example, `.extern sym,4' declares 2230that the object at `sym' is 4 bytes in length, whie leaving `sym' 2231otherwise undefined. 2232 2233 Using small ECOFF objects requires linker support, and assumes that 2234the `$gp' register is correctly initialized (normally done 2235automatically by the startup code). MIPS ECOFF assembly code must not 2236modify the `$gp' register. 2237 2238 2239File: as.info, Node: MIPS Stabs, Next: MIPS ISA, Prev: MIPS Object, Up: MIPS-Dependent 2240 22418.21.3 Directives for debugging information 2242------------------------------------------- 2243 2244MIPS ECOFF `as' supports several directives used for generating 2245debugging information which are not support by traditional MIPS 2246assemblers. These are `.def', `.endef', `.dim', `.file', `.scl', 2247`.size', `.tag', `.type', `.val', `.stabd', `.stabn', and `.stabs'. 2248The debugging information generated by the three `.stab' directives can 2249only be read by GDB, not by traditional MIPS debuggers (this 2250enhancement is required to fully support C++ debugging). These 2251directives are primarily used by compilers, not assembly language 2252programmers! 2253 2254 2255File: as.info, Node: MIPS symbol sizes, Next: MIPS autoextend, Prev: MIPS ISA, Up: MIPS-Dependent 2256 22578.21.4 Directives to override the size of symbols 2258------------------------------------------------- 2259 2260The n64 ABI allows symbols to have any 64-bit value. Although this 2261provides a great deal of flexibility, it means that some macros have 2262much longer expansions than their 32-bit counterparts. For example, 2263the non-PIC expansion of `dla $4,sym' is usually: 2264 2265 lui $4,%highest(sym) 2266 lui $1,%hi(sym) 2267 daddiu $4,$4,%higher(sym) 2268 daddiu $1,$1,%lo(sym) 2269 dsll32 $4,$4,0 2270 daddu $4,$4,$1 2271 2272 whereas the 32-bit expansion is simply: 2273 2274 lui $4,%hi(sym) 2275 daddiu $4,$4,%lo(sym) 2276 2277 n64 code is sometimes constructed in such a way that all symbolic 2278constants are known to have 32-bit values, and in such cases, it's 2279preferable to use the 32-bit expansion instead of the 64-bit expansion. 2280 2281 You can use the `.set sym32' directive to tell the assembler that, 2282from this point on, all expressions of the form `SYMBOL' or `SYMBOL + 2283OFFSET' have 32-bit values. For example: 2284 2285 .set sym32 2286 dla $4,sym 2287 lw $4,sym+16 2288 sw $4,sym+0x8000($4) 2289 2290 will cause the assembler to treat `sym', `sym+16' and `sym+0x8000' 2291as 32-bit values. The handling of non-symbolic addresses is not 2292affected. 2293 2294 The directive `.set nosym32' ends a `.set sym32' block and reverts 2295to the normal behavior. It is also possible to change the symbol size 2296using the command-line options `-msym32' and `-mno-sym32'. 2297 2298 These options and directives are always accepted, but at present, 2299they have no effect for anything other than n64. 2300 2301 2302File: as.info, Node: MIPS ISA, Next: MIPS symbol sizes, Prev: MIPS Stabs, Up: MIPS-Dependent 2303 23048.21.5 Directives to override the ISA level 2305------------------------------------------- 2306 2307GNU `as' supports an additional directive to change the MIPS 2308Instruction Set Architecture level on the fly: `.set mipsN'. N should 2309be a number from 0 to 5, or 32, 32r2, 64 or 64r2. The values other 2310than 0 make the assembler accept instructions for the corresponding ISA 2311level, from that point on in the assembly. `.set mipsN' affects not 2312only which instructions are permitted, but also how certain macros are 2313expanded. `.set mips0' restores the ISA level to its original level: 2314either the level you selected with command line options, or the default 2315for your configuration. You can use this feature to permit specific 2316R4000 instructions while assembling in 32 bit mode. Use this directive 2317with care! 2318 2319 The directive `.set mips16' puts the assembler into MIPS 16 mode, in 2320which it will assemble instructions for the MIPS 16 processor. Use 2321`.set nomips16' to return to normal 32 bit mode. 2322 2323 Traditional MIPS assemblers do not support this directive. 2324 2325 2326File: as.info, Node: MIPS autoextend, Next: MIPS insn, Prev: MIPS symbol sizes, Up: MIPS-Dependent 2327 23288.21.6 Directives for extending MIPS 16 bit instructions 2329-------------------------------------------------------- 2330 2331By default, MIPS 16 instructions are automatically extended to 32 bits 2332when necessary. The directive `.set noautoextend' will turn this off. 2333When `.set noautoextend' is in effect, any 32 bit instruction must be 2334explicitly extended with the `.e' modifier (e.g., `li.e $4,1000'). The 2335directive `.set autoextend' may be used to once again automatically 2336extend instructions when necessary. 2337 2338 This directive is only meaningful when in MIPS 16 mode. Traditional 2339MIPS assemblers do not support this directive. 2340 2341 2342File: as.info, Node: MIPS insn, Next: MIPS option stack, Prev: MIPS autoextend, Up: MIPS-Dependent 2343 23448.21.7 Directive to mark data as an instruction 2345----------------------------------------------- 2346 2347The `.insn' directive tells `as' that the following data is actually 2348instructions. This makes a difference in MIPS 16 mode: when loading 2349the address of a label which precedes instructions, `as' automatically 2350adds 1 to the value, so that jumping to the loaded address will do the 2351right thing. 2352 2353 2354File: as.info, Node: MIPS option stack, Next: MIPS ASE instruction generation overrides, Prev: MIPS insn, Up: MIPS-Dependent 2355 23568.21.8 Directives to save and restore options 2357--------------------------------------------- 2358 2359The directives `.set push' and `.set pop' may be used to save and 2360restore the current settings for all the options which are controlled 2361by `.set'. The `.set push' directive saves the current settings on a 2362stack. The `.set pop' directive pops the stack and restores the 2363settings. 2364 2365 These directives can be useful inside an macro which must change an 2366option such as the ISA level or instruction reordering but does not want 2367to change the state of the code which invoked the macro. 2368 2369 Traditional MIPS assemblers do not support these directives. 2370 2371 2372File: as.info, Node: MIPS ASE instruction generation overrides, Prev: MIPS option stack, Up: MIPS-Dependent 2373 23748.21.9 Directives to control generation of MIPS ASE instructions 2375---------------------------------------------------------------- 2376 2377The directive `.set mips3d' makes the assembler accept instructions 2378from the MIPS-3D Application Specific Extension from that point on in 2379the assembly. The `.set nomips3d' directive prevents MIPS-3D 2380instructions from being accepted. 2381 2382 The directive `.set mdmx' makes the assembler accept instructions 2383from the MDMX Application Specific Extension from that point on in the 2384assembly. The `.set nomdmx' directive prevents MDMX instructions from 2385being accepted. 2386 2387 Traditional MIPS assemblers do not support these directives. 2388 2389 2390File: as.info, Node: MMIX-Dependent, Next: MSP430-Dependent, Prev: MIPS-Dependent, Up: Machine Dependencies 2391 23928.22 MMIX Dependent Features 2393============================ 2394 2395* Menu: 2396 2397* MMIX-Opts:: Command-line Options 2398* MMIX-Expand:: Instruction expansion 2399* MMIX-Syntax:: Syntax 2400* MMIX-mmixal:: Differences to `mmixal' syntax and semantics 2401 2402 2403File: as.info, Node: MMIX-Opts, Next: MMIX-Expand, Up: MMIX-Dependent 2404 24058.22.1 Command-line Options 2406--------------------------- 2407 2408The MMIX version of `as' has some machine-dependent options. 2409 2410 When `--fixed-special-register-names' is specified, only the register 2411names specified in *Note MMIX-Regs:: are recognized in the instructions 2412`PUT' and `GET'. 2413 2414 You can use the `--globalize-symbols' to make all symbols global. 2415This option is useful when splitting up a `mmixal' program into several 2416files. 2417 2418 The `--gnu-syntax' turns off most syntax compatibility with 2419`mmixal'. Its usability is currently doubtful. 2420 2421 The `--relax' option is not fully supported, but will eventually make 2422the object file prepared for linker relaxation. 2423 2424 If you want to avoid inadvertently calling a predefined symbol and 2425would rather get an error, for example when using `as' with a compiler 2426or other machine-generated code, specify `--no-predefined-syms'. This 2427turns off built-in predefined definitions of all such symbols, 2428including rounding-mode symbols, segment symbols, `BIT' symbols, and 2429`TRAP' symbols used in `mmix' "system calls". It also turns off 2430predefined special-register names, except when used in `PUT' and `GET' 2431instructions. 2432 2433 By default, some instructions are expanded to fit the size of the 2434operand or an external symbol (*note MMIX-Expand::). By passing 2435`--no-expand', no such expansion will be done, instead causing errors 2436at link time if the operand does not fit. 2437 2438 The `mmixal' documentation (*note mmixsite::) specifies that global 2439registers allocated with the `GREG' directive (*note MMIX-greg::) and 2440initialized to the same non-zero value, will refer to the same global 2441register. This isn't strictly enforceable in `as' since the final 2442addresses aren't known until link-time, but it will do an effort unless 2443the `--no-merge-gregs' option is specified. (Register merging isn't 2444yet implemented in `ld'.) 2445 2446 `as' will warn every time it expands an instruction to fit an 2447operand unless the option `-x' is specified. It is believed that this 2448behaviour is more useful than just mimicking `mmixal''s behaviour, in 2449which instructions are only expanded if the `-x' option is specified, 2450and assembly fails otherwise, when an instruction needs to be expanded. 2451It needs to be kept in mind that `mmixal' is both an assembler and 2452linker, while `as' will expand instructions that at link stage can be 2453contracted. (Though linker relaxation isn't yet implemented in `ld'.) 2454The option `-x' also imples `--linker-allocated-gregs'. 2455 2456 If instruction expansion is enabled, `as' can expand a `PUSHJ' 2457instruction into a series of instructions. The shortest expansion is 2458to not expand it, but just mark the call as redirectable to a stub, 2459which `ld' creates at link-time, but only if the original `PUSHJ' 2460instruction is found not to reach the target. The stub consists of the 2461necessary instructions to form a jump to the target. This happens if 2462`as' can assert that the `PUSHJ' instruction can reach such a stub. 2463The option `--no-pushj-stubs' disables this shorter expansion, and the 2464longer series of instructions is then created at assembly-time. The 2465option `--no-stubs' is a synonym, intended for compatibility with 2466future releases, where generation of stubs for other instructions may 2467be implemented. 2468 2469 Usually a two-operand-expression (*note GREG-base::) without a 2470matching `GREG' directive is treated as an error by `as'. When the 2471option `--linker-allocated-gregs' is in effect, they are instead passed 2472through to the linker, which will allocate as many global registers as 2473is needed. 2474 2475 2476File: as.info, Node: MMIX-Expand, Next: MMIX-Syntax, Prev: MMIX-Opts, Up: MMIX-Dependent 2477 24788.22.2 Instruction expansion 2479---------------------------- 2480 2481When `as' encounters an instruction with an operand that is either not 2482known or does not fit the operand size of the instruction, `as' (and 2483`ld') will expand the instruction into a sequence of instructions 2484semantically equivalent to the operand fitting the instruction. 2485Expansion will take place for the following instructions: 2486 2487`GETA' 2488 Expands to a sequence of four instructions: `SETL', `INCML', 2489 `INCMH' and `INCH'. The operand must be a multiple of four. 2490 2491Conditional branches 2492 A branch instruction is turned into a branch with the complemented 2493 condition and prediction bit over five instructions; four 2494 instructions setting `$255' to the operand value, which like with 2495 `GETA' must be a multiple of four, and a final `GO $255,$255,0'. 2496 2497`PUSHJ' 2498 Similar to expansion for conditional branches; four instructions 2499 set `$255' to the operand value, followed by a `PUSHGO 2500 $255,$255,0'. 2501 2502`JMP' 2503 Similar to conditional branches and `PUSHJ'. The final instruction 2504 is `GO $255,$255,0'. 2505 2506 The linker `ld' is expected to shrink these expansions for code 2507assembled with `--relax' (though not currently implemented). 2508 2509 2510File: as.info, Node: MMIX-Syntax, Next: MMIX-mmixal, Prev: MMIX-Expand, Up: MMIX-Dependent 2511 25128.22.3 Syntax 2513------------- 2514 2515The assembly syntax is supposed to be upward compatible with that 2516described in Sections 1.3 and 1.4 of `The Art of Computer Programming, 2517Volume 1'. Draft versions of those chapters as well as other MMIX 2518information is located at 2519`http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html'. Most code 2520examples from the mmixal package located there should work unmodified 2521when assembled and linked as single files, with a few noteworthy 2522exceptions (*note MMIX-mmixal::). 2523 2524 Before an instruction is emitted, the current location is aligned to 2525the next four-byte boundary. If a label is defined at the beginning of 2526the line, its value will be the aligned value. 2527 2528 In addition to the traditional hex-prefix `0x', a hexadecimal number 2529can also be specified by the prefix character `#'. 2530 2531 After all operands to an MMIX instruction or directive have been 2532specified, the rest of the line is ignored, treated as a comment. 2533 2534* Menu: 2535 2536* MMIX-Chars:: Special Characters 2537* MMIX-Symbols:: Symbols 2538* MMIX-Regs:: Register Names 2539* MMIX-Pseudos:: Assembler Directives 2540 2541 2542File: as.info, Node: MMIX-Chars, Next: MMIX-Symbols, Up: MMIX-Syntax 2543 25448.22.3.1 Special Characters 2545........................... 2546 2547The characters `*' and `#' are line comment characters; each start a 2548comment at the beginning of a line, but only at the beginning of a 2549line. A `#' prefixes a hexadecimal number if found elsewhere on a line. 2550 2551 Two other characters, `%' and `!', each start a comment anywhere on 2552the line. Thus you can't use the `modulus' and `not' operators in 2553expressions normally associated with these two characters. 2554 2555 A `;' is a line separator, treated as a new-line, so separate 2556instructions can be specified on a single line. 2557 2558 2559File: as.info, Node: MMIX-Symbols, Next: MMIX-Regs, Prev: MMIX-Chars, Up: MMIX-Syntax 2560 25618.22.3.2 Symbols 2562................ 2563 2564The character `:' is permitted in identifiers. There are two 2565exceptions to it being treated as any other symbol character: if a 2566symbol begins with `:', it means that the symbol is in the global 2567namespace and that the current prefix should not be prepended to that 2568symbol (*note MMIX-prefix::). The `:' is then not considered part of 2569the symbol. For a symbol in the label position (first on a line), a `:' 2570at the end of a symbol is silently stripped off. A label is permitted, 2571but not required, to be followed by a `:', as with many other assembly 2572formats. 2573 2574 The character `@' in an expression, is a synonym for `.', the 2575current location. 2576 2577 In addition to the common forward and backward local symbol formats 2578(*note Symbol Names::), they can be specified with upper-case `B' and 2579`F', as in `8B' and `9F'. A local label defined for the current 2580position is written with a `H' appended to the number: 2581 3H LDB $0,$1,2 2582 This and traditional local-label formats cannot be mixed: a label 2583must be defined and referred to using the same format. 2584 2585 There's a minor caveat: just as for the ordinary local symbols, the 2586local symbols are translated into ordinary symbols using control 2587characters are to hide the ordinal number of the symbol. 2588Unfortunately, these symbols are not translated back in error messages. 2589Thus you may see confusing error messages when local symbols are used. 2590Control characters `\003' (control-C) and `\004' (control-D) are used 2591for the MMIX-specific local-symbol syntax. 2592 2593 The symbol `Main' is handled specially; it is always global. 2594 2595 By defining the symbols `__.MMIX.start..text' and 2596`__.MMIX.start..data', the address of respectively the `.text' and 2597`.data' segments of the final program can be defined, though when 2598linking more than one object file, the code or data in the object file 2599containing the symbol is not guaranteed to be start at that position; 2600just the final executable. *Note MMIX-loc::. 2601 2602 2603File: as.info, Node: MMIX-Regs, Next: MMIX-Pseudos, Prev: MMIX-Symbols, Up: MMIX-Syntax 2604 26058.22.3.3 Register names 2606....................... 2607 2608Local and global registers are specified as `$0' to `$255'. The 2609recognized special register names are `rJ', `rA', `rB', `rC', `rD', 2610`rE', `rF', `rG', `rH', `rI', `rK', `rL', `rM', `rN', `rO', `rP', `rQ', 2611`rR', `rS', `rT', `rU', `rV', `rW', `rX', `rY', `rZ', `rBB', `rTT', 2612`rWW', `rXX', `rYY' and `rZZ'. A leading `:' is optional for special 2613register names. 2614 2615 Local and global symbols can be equated to register names and used in 2616place of ordinary registers. 2617 2618 Similarly for special registers, local and global symbols can be 2619used. Also, symbols equated from numbers and constant expressions are 2620allowed in place of a special register, except when either of the 2621options `--no-predefined-syms' and `--fixed-special-register-names' are 2622specified. Then only the special register names above are allowed for 2623the instructions having a special register operand; `GET' and `PUT'. 2624 2625 2626File: as.info, Node: MMIX-Pseudos, Prev: MMIX-Regs, Up: MMIX-Syntax 2627 26288.22.3.4 Assembler Directives 2629............................. 2630 2631`LOC' 2632 The `LOC' directive sets the current location to the value of the 2633 operand field, which may include changing sections. If the 2634 operand is a constant, the section is set to either `.data' if the 2635 value is `0x2000000000000000' or larger, else it is set to `.text'. 2636 Within a section, the current location may only be changed to 2637 monotonically higher addresses. A LOC expression must be a 2638 previously defined symbol or a "pure" constant. 2639 2640 An example, which sets the label PREV to the current location, and 2641 updates the current location to eight bytes forward: 2642 prev LOC @+8 2643 2644 When a LOC has a constant as its operand, a symbol 2645 `__.MMIX.start..text' or `__.MMIX.start..data' is defined 2646 depending on the address as mentioned above. Each such symbol is 2647 interpreted as special by the linker, locating the section at that 2648 address. Note that if multiple files are linked, the first object 2649 file with that section will be mapped to that address (not 2650 necessarily the file with the LOC definition). 2651 2652`LOCAL' 2653 Example: 2654 LOCAL external_symbol 2655 LOCAL 42 2656 .local asymbol 2657 2658 This directive-operation generates a link-time assertion that the 2659 operand does not correspond to a global register. The operand is 2660 an expression that at link-time resolves to a register symbol or a 2661 number. A number is treated as the register having that number. 2662 There is one restriction on the use of this directive: the 2663 pseudo-directive must be placed in a section with contents, code 2664 or data. 2665 2666`IS' 2667 The `IS' directive: 2668 asymbol IS an_expression 2669 sets the symbol `asymbol' to `an_expression'. A symbol may not be 2670 set more than once using this directive. Local labels may be set 2671 using this directive, for example: 2672 5H IS @+4 2673 2674`GREG' 2675 This directive reserves a global register, gives it an initial 2676 value and optionally gives it a symbolic name. Some examples: 2677 2678 areg GREG 2679 breg GREG data_value 2680 GREG data_buffer 2681 .greg creg, another_data_value 2682 2683 The symbolic register name can be used in place of a (non-special) 2684 register. If a value isn't provided, it defaults to zero. Unless 2685 the option `--no-merge-gregs' is specified, non-zero registers 2686 allocated with this directive may be eliminated by `as'; another 2687 register with the same value used in its place. Any of the 2688 instructions `CSWAP', `GO', `LDA', `LDBU', `LDB', `LDHT', `LDOU', 2689 `LDO', `LDSF', `LDTU', `LDT', `LDUNC', `LDVTS', `LDWU', `LDW', 2690 `PREGO', `PRELD', `PREST', `PUSHGO', `STBU', `STB', `STCO', `STHT', 2691 `STOU', `STSF', `STTU', `STT', `STUNC', `SYNCD', `SYNCID', can 2692 have a value nearby an initial value in place of its second and 2693 third operands. Here, "nearby" is defined as within the range 2694 0...255 from the initial value of such an allocated register. 2695 2696 buffer1 BYTE 0,0,0,0,0 2697 buffer2 BYTE 0,0,0,0,0 2698 ... 2699 GREG buffer1 2700 LDOU $42,buffer2 2701 In the example above, the `Y' field of the `LDOUI' instruction 2702 (LDOU with a constant Z) will be replaced with the global register 2703 allocated for `buffer1', and the `Z' field will have the value 5, 2704 the offset from `buffer1' to `buffer2'. The result is equivalent 2705 to this code: 2706 buffer1 BYTE 0,0,0,0,0 2707 buffer2 BYTE 0,0,0,0,0 2708 ... 2709 tmpreg GREG buffer1 2710 LDOU $42,tmpreg,(buffer2-buffer1) 2711 2712 Global registers allocated with this directive are allocated in 2713 order higher-to-lower within a file. Other than that, the exact 2714 order of register allocation and elimination is undefined. For 2715 example, the order is undefined when more than one file with such 2716 directives are linked together. With the options `-x' and 2717 `--linker-allocated-gregs', `GREG' directives for two-operand 2718 cases like the one mentioned above can be omitted. Sufficient 2719 global registers will then be allocated by the linker. 2720 2721`BYTE' 2722 The `BYTE' directive takes a series of operands separated by a 2723 comma. If an operand is a string (*note Strings::), each 2724 character of that string is emitted as a byte. Other operands 2725 must be constant expressions without forward references, in the 2726 range 0...255. If you need operands having expressions with 2727 forward references, use `.byte' (*note Byte::). An operand can be 2728 omitted, defaulting to a zero value. 2729 2730`WYDE' 2731`TETRA' 2732`OCTA' 2733 The directives `WYDE', `TETRA' and `OCTA' emit constants of two, 2734 four and eight bytes size respectively. Before anything else 2735 happens for the directive, the current location is aligned to the 2736 respective constant-size boundary. If a label is defined at the 2737 beginning of the line, its value will be that after the alignment. 2738 A single operand can be omitted, defaulting to a zero value 2739 emitted for the directive. Operands can be expressed as strings 2740 (*note Strings::), in which case each character in the string is 2741 emitted as a separate constant of the size indicated by the 2742 directive. 2743 2744`PREFIX' 2745 The `PREFIX' directive sets a symbol name prefix to be prepended to 2746 all symbols (except local symbols, *note MMIX-Symbols::), that are 2747 not prefixed with `:', until the next `PREFIX' directive. Such 2748 prefixes accumulate. For example, 2749 PREFIX a 2750 PREFIX b 2751 c IS 0 2752 defines a symbol `abc' with the value 0. 2753 2754`BSPEC' 2755`ESPEC' 2756 A pair of `BSPEC' and `ESPEC' directives delimit a section of 2757 special contents (without specified semantics). Example: 2758 BSPEC 42 2759 TETRA 1,2,3 2760 ESPEC 2761 The single operand to `BSPEC' must be number in the range 0...255. 2762 The `BSPEC' number 80 is used by the GNU binutils implementation. 2763 2764 2765File: as.info, Node: MMIX-mmixal, Prev: MMIX-Syntax, Up: MMIX-Dependent 2766 27678.22.4 Differences to `mmixal' 2768------------------------------ 2769 2770The binutils `as' and `ld' combination has a few differences in 2771function compared to `mmixal' (*note mmixsite::). 2772 2773 The replacement of a symbol with a GREG-allocated register (*note 2774GREG-base::) is not handled the exactly same way in `as' as in 2775`mmixal'. This is apparent in the `mmixal' example file `inout.mms', 2776where different registers with different offsets, eventually yielding 2777the same address, are used in the first instruction. This type of 2778difference should however not affect the function of any program unless 2779it has specific assumptions about the allocated register number. 2780 2781 Line numbers (in the `mmo' object format) are currently not 2782supported. 2783 2784 Expression operator precedence is not that of mmixal: operator 2785precedence is that of the C programming language. It's recommended to 2786use parentheses to explicitly specify wanted operator precedence 2787whenever more than one type of operators are used. 2788 2789 The serialize unary operator `&', the fractional division operator 2790`//', the logical not operator `!' and the modulus operator `%' are not 2791available. 2792 2793 Symbols are not global by default, unless the option 2794`--globalize-symbols' is passed. Use the `.global' directive to 2795globalize symbols (*note Global::). 2796 2797 Operand syntax is a bit stricter with `as' than `mmixal'. For 2798example, you can't say `addu 1,2,3', instead you must write `addu 2799$1,$2,3'. 2800 2801 You can't LOC to a lower address than those already visited (i.e. 2802"backwards"). 2803 2804 A LOC directive must come before any emitted code. 2805 2806 Predefined symbols are visible as file-local symbols after use. (In 2807the ELF file, that is--the linked mmo file has no notion of a file-local 2808symbol.) 2809 2810 Some mapping of constant expressions to sections in LOC expressions 2811is attempted, but that functionality is easily confused and should be 2812avoided unless compatibility with `mmixal' is required. A LOC 2813expression to `0x2000000000000000' or higher, maps to the `.data' 2814section and lower addresses map to the `.text' section (*note 2815MMIX-loc::). 2816 2817 The code and data areas are each contiguous. Sparse programs with 2818far-away LOC directives will take up the same amount of space as a 2819contiguous program with zeros filled in the gaps between the LOC 2820directives. If you need sparse programs, you might try and get the 2821wanted effect with a linker script and splitting up the code parts into 2822sections (*note Section::). Assembly code for this, to be compatible 2823with `mmixal', would look something like: 2824 .if 0 2825 LOC away_expression 2826 .else 2827 .section away,"ax" 2828 .fi 2829 `as' will not execute the LOC directive and `mmixal' ignores the 2830lines with `.'. This construct can be used generally to help 2831compatibility. 2832 2833 Symbols can't be defined twice-not even to the same value. 2834 2835 Instruction mnemonics are recognized case-insensitive, though the 2836`IS' and `GREG' pseudo-operations must be specified in upper-case 2837characters. 2838 2839 There's no unicode support. 2840 2841 The following is a list of programs in `mmix.tar.gz', available at 2842`http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html', last 2843checked with the version dated 2001-08-25 (md5sum 2844c393470cfc86fac040487d22d2bf0172) that assemble with `mmixal' but do 2845not assemble with `as': 2846 2847`silly.mms' 2848 LOC to a previous address. 2849 2850`sim.mms' 2851 Redefines symbol `Done'. 2852 2853`test.mms' 2854 Uses the serial operator `&'. 2855 2856 2857File: as.info, Node: MSP430-Dependent, Next: SH-Dependent, Prev: MMIX-Dependent, Up: Machine Dependencies 2858 28598.23 MSP 430 Dependent Features 2860=============================== 2861 2862* Menu: 2863 2864* MSP430 Options:: Options 2865* MSP430 Syntax:: Syntax 2866* MSP430 Floating Point:: Floating Point 2867* MSP430 Directives:: MSP 430 Machine Directives 2868* MSP430 Opcodes:: Opcodes 2869* MSP430 Profiling Capability:: Profiling Capability 2870 2871 2872File: as.info, Node: MSP430 Options, Next: MSP430 Syntax, Up: MSP430-Dependent 2873 28748.23.1 Options 2875-------------- 2876 2877`as' has only -m flag which selects the mpu arch. Currently has no 2878effect. 2879 2880 2881File: as.info, Node: MSP430 Syntax, Next: MSP430 Floating Point, Prev: MSP430 Options, Up: MSP430-Dependent 2882 28838.23.2 Syntax 2884------------- 2885 2886* Menu: 2887 2888* MSP430-Macros:: Macros 2889* MSP430-Chars:: Special Characters 2890* MSP430-Regs:: Register Names 2891* MSP430-Ext:: Assembler Extensions 2892 2893 2894File: as.info, Node: MSP430-Macros, Next: MSP430-Chars, Up: MSP430 Syntax 2895 28968.23.2.1 Macros 2897............... 2898 2899The macro syntax used on the MSP 430 is like that described in the MSP 2900430 Family Assembler Specification. Normal `as' macros should still 2901work. 2902 2903 Additional built-in macros are: 2904 2905`llo(exp)' 2906 Extracts least significant word from 32-bit expression 'exp'. 2907 2908`lhi(exp)' 2909 Extracts most significant word from 32-bit expression 'exp'. 2910 2911`hlo(exp)' 2912 Extracts 3rd word from 64-bit expression 'exp'. 2913 2914`hhi(exp)' 2915 Extracts 4rd word from 64-bit expression 'exp'. 2916 2917 2918 They normally being used as an immediate source operand. 2919 mov #llo(1), r10 ; == mov #1, r10 2920 mov #lhi(1), r10 ; == mov #0, r10 2921 2922 2923File: as.info, Node: MSP430-Chars, Next: MSP430-Regs, Prev: MSP430-Macros, Up: MSP430 Syntax 2924 29258.23.2.2 Special Characters 2926........................... 2927 2928`;' is the line comment character. 2929 2930 The character `$' in jump instructions indicates current location and 2931implemented only for TI syntax compatibility. 2932 2933 2934File: as.info, Node: MSP430-Regs, Next: MSP430-Ext, Prev: MSP430-Chars, Up: MSP430 Syntax 2935 29368.23.2.3 Register Names 2937....................... 2938 2939General-purpose registers are represented by predefined symbols of the 2940form `rN' (for global registers), where N represents a number between 2941`0' and `15'. The leading letters may be in either upper or lower 2942case; for example, `r13' and `R7' are both valid register names. 2943 2944 Register names `PC', `SP' and `SR' cannot be used as register names 2945and will be treated as variables. Use `r0', `r1', and `r2' instead. 2946 2947 2948File: as.info, Node: MSP430-Ext, Prev: MSP430-Regs, Up: MSP430 Syntax 2949 29508.23.2.4 Assembler Extensions 2951............................. 2952 2953`@rN' 2954 As destination operand being treated as `0(rn)' 2955 2956`0(rN)' 2957 As source operand being treated as `@rn' 2958 2959`jCOND +N' 2960 Skips next N bytes followed by jump instruction and equivalent to 2961 `jCOND $+N+2' 2962 2963 2964 Also, there are some instructions, which cannot be found in other 2965assemblers. These are branch instructions, which has different opcodes 2966upon jump distance. They all got PC relative addressing mode. 2967 2968`beq label' 2969 A polymorph instruction which is `jeq label' in case if jump 2970 distance within allowed range for cpu's jump instruction. If not, 2971 this unrolls into a sequence of 2972 jne $+6 2973 br label 2974 2975`bne label' 2976 A polymorph instruction which is `jne label' or `jeq +4; br label' 2977 2978`blt label' 2979 A polymorph instruction which is `jl label' or `jge +4; br label' 2980 2981`bltn label' 2982 A polymorph instruction which is `jn label' or `jn +2; jmp +4; br 2983 label' 2984 2985`bltu label' 2986 A polymorph instruction which is `jlo label' or `jhs +2; br label' 2987 2988`bge label' 2989 A polymorph instruction which is `jge label' or `jl +4; br label' 2990 2991`bgeu label' 2992 A polymorph instruction which is `jhs label' or `jlo +4; br label' 2993 2994`bgt label' 2995 A polymorph instruction which is `jeq +2; jge label' or `jeq +6; 2996 jl +4; br label' 2997 2998`bgtu label' 2999 A polymorph instruction which is `jeq +2; jhs label' or `jeq +6; 3000 jlo +4; br label' 3001 3002`bleu label' 3003 A polymorph instruction which is `jeq label; jlo label' or `jeq 3004 +2; jhs +4; br label' 3005 3006`ble label' 3007 A polymorph instruction which is `jeq label; jl label' or `jeq 3008 +2; jge +4; br label' 3009 3010`jump label' 3011 A polymorph instruction which is `jmp label' or `br label' 3012 3013 3014File: as.info, Node: MSP430 Floating Point, Next: MSP430 Directives, Prev: MSP430 Syntax, Up: MSP430-Dependent 3015 30168.23.3 Floating Point 3017--------------------- 3018 3019The MSP 430 family uses IEEE 32-bit floating-point numbers. 3020 3021 3022File: as.info, Node: MSP430 Directives, Next: MSP430 Opcodes, Prev: MSP430 Floating Point, Up: MSP430-Dependent 3023 30248.23.4 MSP 430 Machine Directives 3025--------------------------------- 3026 3027`.file' 3028 This directive is ignored; it is accepted for compatibility with 3029 other MSP 430 assemblers. 3030 3031 _Warning:_ in other versions of the GNU assembler, `.file' is 3032 used for the directive called `.app-file' in the MSP 430 3033 support. 3034 3035`.line' 3036 This directive is ignored; it is accepted for compatibility with 3037 other MSP 430 assemblers. 3038 3039`.arch' 3040 Currently this directive is ignored; it is accepted for 3041 compatibility with other MSP 430 assemblers. 3042 3043`.profiler' 3044 This directive instructs assembler to add new profile entry to the 3045 object file. 3046 3047 3048 3049File: as.info, Node: MSP430 Opcodes, Next: MSP430 Profiling Capability, Prev: MSP430 Directives, Up: MSP430-Dependent 3050 30518.23.5 Opcodes 3052-------------- 3053 3054`as' implements all the standard MSP 430 opcodes. No additional 3055pseudo-instructions are needed on this family. 3056 3057 For information on the 430 machine instruction set, see `MSP430 3058User's Manual, document slau049b', Texas Instrument, Inc. 3059 3060 3061File: as.info, Node: MSP430 Profiling Capability, Prev: MSP430 Opcodes, Up: MSP430-Dependent 3062 30638.23.6 Profiling Capability 3064--------------------------- 3065 3066It is a performance hit to use gcc's profiling approach for this tiny 3067target. Even more - jtag hardware facility does not perform any 3068profiling functions. However we've got gdb's built-in simulator where 3069we can do anything. 3070 3071 We define new section `.profiler' which holds all profiling 3072information. We define new pseudo operation `.profiler' which will 3073instruct assembler to add new profile entry to the object file. Profile 3074should take place at the present address. 3075 3076 Pseudo operation format: 3077 3078 `.profiler flags,function_to_profile [, cycle_corrector, extra]' 3079 3080 where: 3081 3082 `flags' is a combination of the following characters: 3083 3084 `s' 3085 function entry 3086 3087 `x' 3088 function exit 3089 3090 `i' 3091 function is in init section 3092 3093 `f' 3094 function is in fini section 3095 3096 `l' 3097 library call 3098 3099 `c' 3100 libc standard call 3101 3102 `d' 3103 stack value demand 3104 3105 `I' 3106 interrupt service routine 3107 3108 `P' 3109 prologue start 3110 3111 `p' 3112 prologue end 3113 3114 `E' 3115 epilogue start 3116 3117 `e' 3118 epilogue end 3119 3120 `j' 3121 long jump / sjlj unwind 3122 3123 `a' 3124 an arbitrary code fragment 3125 3126 `t' 3127 extra parameter saved (a constant value like frame size) 3128 3129`function_to_profile' 3130 a function address 3131 3132`cycle_corrector' 3133 a value which should be added to the cycle counter, zero if 3134 omitted. 3135 3136`extra' 3137 any extra parameter, zero if omitted. 3138 3139 3140 For example: 3141 .global fxx 3142 .type fxx,@function 3143 fxx: 3144 .LFrameOffset_fxx=0x08 3145 .profiler "scdP", fxx ; function entry. 3146 ; we also demand stack value to be saved 3147 push r11 3148 push r10 3149 push r9 3150 push r8 3151 .profiler "cdpt",fxx,0, .LFrameOffset_fxx ; check stack value at this point 3152 ; (this is a prologue end) 3153 ; note, that spare var filled with 3154 ; the farme size 3155 mov r15,r8 3156 ... 3157 .profiler cdE,fxx ; check stack 3158 pop r8 3159 pop r9 3160 pop r10 3161 pop r11 3162 .profiler xcde,fxx,3 ; exit adds 3 to the cycle counter 3163 ret ; cause 'ret' insn takes 3 cycles 3164 3165 3166File: as.info, Node: PDP-11-Dependent, Next: PJ-Dependent, Prev: SH64-Dependent, Up: Machine Dependencies 3167 31688.24 PDP-11 Dependent Features 3169============================== 3170 3171* Menu: 3172 3173* PDP-11-Options:: Options 3174* PDP-11-Pseudos:: Assembler Directives 3175* PDP-11-Syntax:: DEC Syntax versus BSD Syntax 3176* PDP-11-Mnemonics:: Instruction Naming 3177* PDP-11-Synthetic:: Synthetic Instructions 3178 3179 3180File: as.info, Node: PDP-11-Options, Next: PDP-11-Pseudos, Up: PDP-11-Dependent 3181 31828.24.1 Options 3183-------------- 3184 3185The PDP-11 version of `as' has a rich set of machine dependent options. 3186 31878.24.1.1 Code Generation Options 3188................................ 3189 3190`-mpic | -mno-pic' 3191 Generate position-independent (or position-dependent) code. 3192 3193 The default is to generate position-independent code. 3194 31958.24.1.2 Instruction Set Extension Options 3196.......................................... 3197 3198These options enables or disables the use of extensions over the base 3199line instruction set as introduced by the first PDP-11 CPU: the KA11. 3200Most options come in two variants: a `-m'EXTENSION that enables 3201EXTENSION, and a `-mno-'EXTENSION that disables EXTENSION. 3202 3203 The default is to enable all extensions. 3204 3205`-mall | -mall-extensions' 3206 Enable all instruction set extensions. 3207 3208`-mno-extensions' 3209 Disable all instruction set extensions. 3210 3211`-mcis | -mno-cis' 3212 Enable (or disable) the use of the commercial instruction set, 3213 which consists of these instructions: `ADDNI', `ADDN', `ADDPI', 3214 `ADDP', `ASHNI', `ASHN', `ASHPI', `ASHP', `CMPCI', `CMPC', 3215 `CMPNI', `CMPN', `CMPPI', `CMPP', `CVTLNI', `CVTLN', `CVTLPI', 3216 `CVTLP', `CVTNLI', `CVTNL', `CVTNPI', `CVTNP', `CVTPLI', `CVTPL', 3217 `CVTPNI', `CVTPN', `DIVPI', `DIVP', `L2DR', `L3DR', `LOCCI', 3218 `LOCC', `MATCI', `MATC', `MOVCI', `MOVC', `MOVRCI', `MOVRC', 3219 `MOVTCI', `MOVTC', `MULPI', `MULP', `SCANCI', `SCANC', `SKPCI', 3220 `SKPC', `SPANCI', `SPANC', `SUBNI', `SUBN', `SUBPI', and `SUBP'. 3221 3222`-mcsm | -mno-csm' 3223 Enable (or disable) the use of the `CSM' instruction. 3224 3225`-meis | -mno-eis' 3226 Enable (or disable) the use of the extended instruction set, which 3227 consists of these instructions: `ASHC', `ASH', `DIV', `MARK', 3228 `MUL', `RTT', `SOB' `SXT', and `XOR'. 3229 3230`-mfis | -mkev11' 3231`-mno-fis | -mno-kev11' 3232 Enable (or disable) the use of the KEV11 floating-point 3233 instructions: `FADD', `FDIV', `FMUL', and `FSUB'. 3234 3235`-mfpp | -mfpu | -mfp-11' 3236`-mno-fpp | -mno-fpu | -mno-fp-11' 3237 Enable (or disable) the use of FP-11 floating-point instructions: 3238 `ABSF', `ADDF', `CFCC', `CLRF', `CMPF', `DIVF', `LDCFF', `LDCIF', 3239 `LDEXP', `LDF', `LDFPS', `MODF', `MULF', `NEGF', `SETD', `SETF', 3240 `SETI', `SETL', `STCFF', `STCFI', `STEXP', `STF', `STFPS', `STST', 3241 `SUBF', and `TSTF'. 3242 3243`-mlimited-eis | -mno-limited-eis' 3244 Enable (or disable) the use of the limited extended instruction 3245 set: `MARK', `RTT', `SOB', `SXT', and `XOR'. 3246 3247 The -mno-limited-eis options also implies -mno-eis. 3248 3249`-mmfpt | -mno-mfpt' 3250 Enable (or disable) the use of the `MFPT' instruction. 3251 3252`-mmultiproc | -mno-multiproc' 3253 Enable (or disable) the use of multiprocessor instructions: 3254 `TSTSET' and `WRTLCK'. 3255 3256`-mmxps | -mno-mxps' 3257 Enable (or disable) the use of the `MFPS' and `MTPS' instructions. 3258 3259`-mspl | -mno-spl' 3260 Enable (or disable) the use of the `SPL' instruction. 3261 3262 Enable (or disable) the use of the microcode instructions: `LDUB', 3263 `MED', and `XFC'. 3264 32658.24.1.3 CPU Model Options 3266.......................... 3267 3268These options enable the instruction set extensions supported by a 3269particular CPU, and disables all other extensions. 3270 3271`-mka11' 3272 KA11 CPU. Base line instruction set only. 3273 3274`-mkb11' 3275 KB11 CPU. Enable extended instruction set and `SPL'. 3276 3277`-mkd11a' 3278 KD11-A CPU. Enable limited extended instruction set. 3279 3280`-mkd11b' 3281 KD11-B CPU. Base line instruction set only. 3282 3283`-mkd11d' 3284 KD11-D CPU. Base line instruction set only. 3285 3286`-mkd11e' 3287 KD11-E CPU. Enable extended instruction set, `MFPS', and `MTPS'. 3288 3289`-mkd11f | -mkd11h | -mkd11q' 3290 KD11-F, KD11-H, or KD11-Q CPU. Enable limited extended 3291 instruction set, `MFPS', and `MTPS'. 3292 3293`-mkd11k' 3294 KD11-K CPU. Enable extended instruction set, `LDUB', `MED', 3295 `MFPS', `MFPT', `MTPS', and `XFC'. 3296 3297`-mkd11z' 3298 KD11-Z CPU. Enable extended instruction set, `CSM', `MFPS', 3299 `MFPT', `MTPS', and `SPL'. 3300 3301`-mf11' 3302 F11 CPU. Enable extended instruction set, `MFPS', `MFPT', and 3303 `MTPS'. 3304 3305`-mj11' 3306 J11 CPU. Enable extended instruction set, `CSM', `MFPS', `MFPT', 3307 `MTPS', `SPL', `TSTSET', and `WRTLCK'. 3308 3309`-mt11' 3310 T11 CPU. Enable limited extended instruction set, `MFPS', and 3311 `MTPS'. 3312 33138.24.1.4 Machine Model Options 3314.............................. 3315 3316These options enable the instruction set extensions supported by a 3317particular machine model, and disables all other extensions. 3318 3319`-m11/03' 3320 Same as `-mkd11f'. 3321 3322`-m11/04' 3323 Same as `-mkd11d'. 3324 3325`-m11/05 | -m11/10' 3326 Same as `-mkd11b'. 3327 3328`-m11/15 | -m11/20' 3329 Same as `-mka11'. 3330 3331`-m11/21' 3332 Same as `-mt11'. 3333 3334`-m11/23 | -m11/24' 3335 Same as `-mf11'. 3336 3337`-m11/34' 3338 Same as `-mkd11e'. 3339 3340`-m11/34a' 3341 Ame as `-mkd11e' `-mfpp'. 3342 3343`-m11/35 | -m11/40' 3344 Same as `-mkd11a'. 3345 3346`-m11/44' 3347 Same as `-mkd11z'. 3348 3349`-m11/45 | -m11/50 | -m11/55 | -m11/70' 3350 Same as `-mkb11'. 3351 3352`-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94' 3353 Same as `-mj11'. 3354 3355`-m11/60' 3356 Same as `-mkd11k'. 3357 3358 3359File: as.info, Node: PDP-11-Pseudos, Next: PDP-11-Syntax, Prev: PDP-11-Options, Up: PDP-11-Dependent 3360 33618.24.2 Assembler Directives 3362--------------------------- 3363 3364The PDP-11 version of `as' has a few machine dependent assembler 3365directives. 3366 3367`.bss' 3368 Switch to the `bss' section. 3369 3370`.even' 3371 Align the location counter to an even number. 3372 3373 3374File: as.info, Node: PDP-11-Syntax, Next: PDP-11-Mnemonics, Prev: PDP-11-Pseudos, Up: PDP-11-Dependent 3375 33768.24.3 PDP-11 Assembly Language Syntax 3377-------------------------------------- 3378 3379`as' supports both DEC syntax and BSD syntax. The only difference is 3380that in DEC syntax, a `#' character is used to denote an immediate 3381constants, while in BSD syntax the character for this purpose is `$'. 3382 3383 eneral-purpose registers are named `r0' through `r7'. Mnemonic 3384alternatives for `r6' and `r7' are `sp' and `pc', respectively. 3385 3386 Floating-point registers are named `ac0' through `ac3', or 3387alternatively `fr0' through `fr3'. 3388 3389 Comments are started with a `#' or a `/' character, and extend to 3390the end of the line. (FIXME: clash with immediates?) 3391 3392 3393File: as.info, Node: PDP-11-Mnemonics, Next: PDP-11-Synthetic, Prev: PDP-11-Syntax, Up: PDP-11-Dependent 3394 33958.24.4 Instruction Naming 3396------------------------- 3397 3398Some instructions have alternative names. 3399 3400`BCC' 3401 `BHIS' 3402 3403`BCS' 3404 `BLO' 3405 3406`L2DR' 3407 `L2D' 3408 3409`L3DR' 3410 `L3D' 3411 3412`SYS' 3413 `TRAP' 3414 3415 3416File: as.info, Node: PDP-11-Synthetic, Prev: PDP-11-Mnemonics, Up: PDP-11-Dependent 3417 34188.24.5 Synthetic Instructions 3419----------------------------- 3420 3421The `JBR' and `J'CC synthetic instructions are not supported yet. 3422 3423 3424File: as.info, Node: PJ-Dependent, Next: PPC-Dependent, Prev: PDP-11-Dependent, Up: Machine Dependencies 3425 34268.25 picoJava Dependent Features 3427================================ 3428 3429* Menu: 3430 3431* PJ Options:: Options 3432 3433 3434File: as.info, Node: PJ Options, Up: PJ-Dependent 3435 34368.25.1 Options 3437-------------- 3438 3439`as' has two additional command-line options for the picoJava 3440architecture. 3441`-ml' 3442 This option selects little endian data output. 3443 3444`-mb' 3445 This option selects big endian data output. 3446 3447 3448File: as.info, Node: PPC-Dependent, Next: Sparc-Dependent, Prev: PJ-Dependent, Up: Machine Dependencies 3449 34508.26 PowerPC Dependent Features 3451=============================== 3452 3453* Menu: 3454 3455* PowerPC-Opts:: Options 3456* PowerPC-Pseudo:: PowerPC Assembler Directives 3457 3458 3459File: as.info, Node: PowerPC-Opts, Next: PowerPC-Pseudo, Up: PPC-Dependent 3460 34618.26.1 Options 3462-------------- 3463 3464The PowerPC chip family includes several successive levels, using the 3465same core instruction set, but including a few additional instructions 3466at each level. There are exceptions to this however. For details on 3467what instructions each variant supports, please see the chip's 3468architecture reference manual. 3469 3470 The following table lists all available PowerPC options. 3471 3472`-mpwrx | -mpwr2' 3473 Generate code for POWER/2 (RIOS2). 3474 3475`-mpwr' 3476 Generate code for POWER (RIOS1) 3477 3478`-m601' 3479 Generate code for PowerPC 601. 3480 3481`-mppc, -mppc32, -m603, -m604' 3482 Generate code for PowerPC 603/604. 3483 3484`-m403, -m405' 3485 Generate code for PowerPC 403/405. 3486 3487`-m440' 3488 Generate code for PowerPC 440. BookE and some 405 instructions. 3489 3490`-m7400, -m7410, -m7450, -m7455' 3491 Generate code for PowerPC 7400/7410/7450/7455. 3492 3493`-mppc64, -m620' 3494 Generate code for PowerPC 620/625/630. 3495 3496`-mppc64bridge' 3497 Generate code for PowerPC 64, including bridge insns. 3498 3499`-mbooke64' 3500 Generate code for 64-bit BookE. 3501 3502`-mbooke, mbooke32' 3503 Generate code for 32-bit BookE. 3504 3505`-maltivec' 3506 Generate code for processors with AltiVec instructions. 3507 3508`-mpower4' 3509 Generate code for Power4 architecture. 3510 3511`-mcom' 3512 Generate code Power/PowerPC common instructions. 3513 3514`-many' 3515 Generate code for any architecture (PWR/PWRX/PPC). 3516 3517`-mregnames' 3518 Allow symbolic names for registers. 3519 3520`-mno-regnames' 3521 Do not allow symbolic names for registers. 3522 3523`-mrelocatable' 3524 Support for GCC's -mrelocatble option. 3525 3526`-mrelocatable-lib' 3527 Support for GCC's -mrelocatble-lib option. 3528 3529`-memb' 3530 Set PPC_EMB bit in ELF flags. 3531 3532`-mlittle, -mlittle-endian' 3533 Generate code for a little endian machine. 3534 3535`-mbig, -mbig-endian' 3536 Generate code for a big endian machine. 3537 3538`-msolaris' 3539 Generate code for Solaris. 3540 3541`-mno-solaris' 3542 Do not generate code for Solaris. 3543 3544 3545File: as.info, Node: PowerPC-Pseudo, Prev: PowerPC-Opts, Up: PPC-Dependent 3546 35478.26.2 PowerPC Assembler Directives 3548----------------------------------- 3549 3550A number of assembler directives are available for PowerPC. The 3551following table is far from complete. 3552 3553`.machine "string"' 3554 This directive allows you to change the machine for which code is 3555 generated. `"string"' may be any of the -m cpu selection options 3556 (without the -m) enclosed in double quotes, `"push"', or `"pop"'. 3557 `.machine "push"' saves the currently selected cpu, which may be 3558 restored with `.machine "pop"'. 3559 3560 3561File: as.info, Node: SH-Dependent, Next: SH64-Dependent, Prev: MSP430-Dependent, Up: Machine Dependencies 3562 35638.27 Renesas / SuperH SH Dependent Features 3564=========================================== 3565 3566* Menu: 3567 3568* SH Options:: Options 3569* SH Syntax:: Syntax 3570* SH Floating Point:: Floating Point 3571* SH Directives:: SH Machine Directives 3572* SH Opcodes:: Opcodes 3573 3574 3575File: as.info, Node: SH Options, Next: SH Syntax, Up: SH-Dependent 3576 35778.27.1 Options 3578-------------- 3579 3580`as' has following command-line options for the Renesas (formerly 3581Hitachi) / SuperH SH family. 3582 3583`-little' 3584 Generate little endian code. 3585 3586`-big' 3587 Generate big endian code. 3588 3589`-relax' 3590 Alter jump instructions for long displacements. 3591 3592`-small' 3593 Align sections to 4 byte boundaries, not 16. 3594 3595`-dsp' 3596 Enable sh-dsp insns, and disable sh3e / sh4 insns. 3597 3598`-renesas' 3599 Disable optimization with section symbol for compatibility with 3600 Renesas assembler. 3601 3602`-isa=sh4 | sh4a' 3603 Specify the sh4 or sh4a instruction set. 3604 3605`-isa=dsp' 3606 Enable sh-dsp insns, and disable sh3e / sh4 insns. 3607 3608`-isa=fp' 3609 Enable sh2e, sh3e, sh4, and sh4a insn sets. 3610 3611`-isa=all' 3612 Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. 3613 3614 3615 3616File: as.info, Node: SH Syntax, Next: SH Floating Point, Prev: SH Options, Up: SH-Dependent 3617 36188.27.2 Syntax 3619------------- 3620 3621* Menu: 3622 3623* SH-Chars:: Special Characters 3624* SH-Regs:: Register Names 3625* SH-Addressing:: Addressing Modes 3626 3627 3628File: as.info, Node: SH-Chars, Next: SH-Regs, Up: SH Syntax 3629 36308.27.2.1 Special Characters 3631........................... 3632 3633`!' is the line comment character. 3634 3635 You can use `;' instead of a newline to separate statements. 3636 3637 Since `$' has no special meaning, you may use it in symbol names. 3638 3639 3640File: as.info, Node: SH-Regs, Next: SH-Addressing, Prev: SH-Chars, Up: SH Syntax 3641 36428.27.2.2 Register Names 3643....................... 3644 3645You can use the predefined symbols `r0', `r1', `r2', `r3', `r4', `r5', 3646`r6', `r7', `r8', `r9', `r10', `r11', `r12', `r13', `r14', and `r15' to 3647refer to the SH registers. 3648 3649 The SH also has these control registers: 3650 3651`pr' 3652 procedure register (holds return address) 3653 3654`pc' 3655 program counter 3656 3657`mach' 3658`macl' 3659 high and low multiply accumulator registers 3660 3661`sr' 3662 status register 3663 3664`gbr' 3665 global base register 3666 3667`vbr' 3668 vector base register (for interrupt vectors) 3669 3670 3671File: as.info, Node: SH-Addressing, Prev: SH-Regs, Up: SH Syntax 3672 36738.27.2.3 Addressing Modes 3674......................... 3675 3676`as' understands the following addressing modes for the SH. `RN' in 3677the following refers to any of the numbered registers, but _not_ the 3678control registers. 3679 3680`RN' 3681 Register direct 3682 3683`@RN' 3684 Register indirect 3685 3686`@-RN' 3687 Register indirect with pre-decrement 3688 3689`@RN+' 3690 Register indirect with post-increment 3691 3692`@(DISP, RN)' 3693 Register indirect with displacement 3694 3695`@(R0, RN)' 3696 Register indexed 3697 3698`@(DISP, GBR)' 3699 `GBR' offset 3700 3701`@(R0, GBR)' 3702 GBR indexed 3703 3704`ADDR' 3705`@(DISP, PC)' 3706 PC relative address (for branch or for addressing memory). The 3707 `as' implementation allows you to use the simpler form ADDR 3708 anywhere a PC relative address is called for; the alternate form 3709 is supported for compatibility with other assemblers. 3710 3711`#IMM' 3712 Immediate data 3713 3714 3715File: as.info, Node: SH Floating Point, Next: SH Directives, Prev: SH Syntax, Up: SH-Dependent 3716 37178.27.3 Floating Point 3718--------------------- 3719 3720SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other 3721SH groups can use `.float' directive to generate IEEE floating-point 3722numbers. 3723 3724 SH2E and SH3E support single-precision floating point calculations as 3725well as entirely PCAPI compatible emulation of double-precision 3726floating point calculations. SH2E and SH3E instructions are a subset of 3727the floating point calculations conforming to the IEEE754 standard. 3728 3729 In addition to single-precision and double-precision floating-point 3730operation capability, the on-chip FPU of SH4 has a 128-bit graphic 3731engine that enables 32-bit floating-point data to be processed 128 bits 3732at a time. It also supports 4 * 4 array operations and inner product 3733operations. Also, a superscalar architecture is employed that enables 3734simultaneous execution of two instructions (including FPU 3735instructions), providing performance of up to twice that of 3736conventional architectures at the same frequency. 3737 3738 3739File: as.info, Node: SH Directives, Next: SH Opcodes, Prev: SH Floating Point, Up: SH-Dependent 3740 37418.27.4 SH Machine Directives 3742---------------------------- 3743 3744`uaword' 3745`ualong' 3746 `as' will issue a warning when a misaligned `.word' or `.long' 3747 directive is used. You may use `.uaword' or `.ualong' to indicate 3748 that the value is intentionally misaligned. 3749 3750 3751File: as.info, Node: SH Opcodes, Prev: SH Directives, Up: SH-Dependent 3752 37538.27.5 Opcodes 3754-------------- 3755 3756For detailed information on the SH machine instruction set, see 3757`SH-Microcomputer User's Manual' (Renesas) or `SH-4 32-bit CPU Core 3758Architecture' (SuperH) and `SuperH (SH) 64-Bit RISC Series' (SuperH). 3759 3760 `as' implements all the standard SH opcodes. No additional 3761pseudo-instructions are needed on this family. Note, however, that 3762because `as' supports a simpler form of PC-relative addressing, you may 3763simply write (for example) 3764 3765 mov.l bar,r0 3766 3767where other assemblers might require an explicit displacement to `bar' 3768from the program counter: 3769 3770 mov.l @(DISP, PC) 3771 3772 Here is a summary of SH opcodes: 3773 3774 Legend: 3775 Rn a numbered register 3776 Rm another numbered register 3777 #imm immediate data 3778 disp displacement 3779 disp8 8-bit displacement 3780 disp12 12-bit displacement 3781 3782 add #imm,Rn lds.l @Rn+,PR 3783 add Rm,Rn mac.w @Rm+,@Rn+ 3784 addc Rm,Rn mov #imm,Rn 3785 addv Rm,Rn mov Rm,Rn 3786 and #imm,R0 mov.b Rm,@(R0,Rn) 3787 and Rm,Rn mov.b Rm,@-Rn 3788 and.b #imm,@(R0,GBR) mov.b Rm,@Rn 3789 bf disp8 mov.b @(disp,Rm),R0 3790 bra disp12 mov.b @(disp,GBR),R0 3791 bsr disp12 mov.b @(R0,Rm),Rn 3792 bt disp8 mov.b @Rm+,Rn 3793 clrmac mov.b @Rm,Rn 3794 clrt mov.b R0,@(disp,Rm) 3795 cmp/eq #imm,R0 mov.b R0,@(disp,GBR) 3796 cmp/eq Rm,Rn mov.l Rm,@(disp,Rn) 3797 cmp/ge Rm,Rn mov.l Rm,@(R0,Rn) 3798 cmp/gt Rm,Rn mov.l Rm,@-Rn 3799 cmp/hi Rm,Rn mov.l Rm,@Rn 3800 cmp/hs Rm,Rn mov.l @(disp,Rn),Rm 3801 cmp/pl Rn mov.l @(disp,GBR),R0 3802 cmp/pz Rn mov.l @(disp,PC),Rn 3803 cmp/str Rm,Rn mov.l @(R0,Rm),Rn 3804 div0s Rm,Rn mov.l @Rm+,Rn 3805 div0u mov.l @Rm,Rn 3806 div1 Rm,Rn mov.l R0,@(disp,GBR) 3807 exts.b Rm,Rn mov.w Rm,@(R0,Rn) 3808 exts.w Rm,Rn mov.w Rm,@-Rn 3809 extu.b Rm,Rn mov.w Rm,@Rn 3810 extu.w Rm,Rn mov.w @(disp,Rm),R0 3811 jmp @Rn mov.w @(disp,GBR),R0 3812 jsr @Rn mov.w @(disp,PC),Rn 3813 ldc Rn,GBR mov.w @(R0,Rm),Rn 3814 ldc Rn,SR mov.w @Rm+,Rn 3815 ldc Rn,VBR mov.w @Rm,Rn 3816 ldc.l @Rn+,GBR mov.w R0,@(disp,Rm) 3817 ldc.l @Rn+,SR mov.w R0,@(disp,GBR) 3818 ldc.l @Rn+,VBR mova @(disp,PC),R0 3819 lds Rn,MACH movt Rn 3820 lds Rn,MACL muls Rm,Rn 3821 lds Rn,PR mulu Rm,Rn 3822 lds.l @Rn+,MACH neg Rm,Rn 3823 lds.l @Rn+,MACL negc Rm,Rn 3824 3825 nop stc VBR,Rn 3826 not Rm,Rn stc.l GBR,@-Rn 3827 or #imm,R0 stc.l SR,@-Rn 3828 or Rm,Rn stc.l VBR,@-Rn 3829 or.b #imm,@(R0,GBR) sts MACH,Rn 3830 rotcl Rn sts MACL,Rn 3831 rotcr Rn sts PR,Rn 3832 rotl Rn sts.l MACH,@-Rn 3833 rotr Rn sts.l MACL,@-Rn 3834 rte sts.l PR,@-Rn 3835 rts sub Rm,Rn 3836 sett subc Rm,Rn 3837 shal Rn subv Rm,Rn 3838 shar Rn swap.b Rm,Rn 3839 shll Rn swap.w Rm,Rn 3840 shll16 Rn tas.b @Rn 3841 shll2 Rn trapa #imm 3842 shll8 Rn tst #imm,R0 3843 shlr Rn tst Rm,Rn 3844 shlr16 Rn tst.b #imm,@(R0,GBR) 3845 shlr2 Rn xor #imm,R0 3846 shlr8 Rn xor Rm,Rn 3847 sleep xor.b #imm,@(R0,GBR) 3848 stc GBR,Rn xtrct Rm,Rn 3849 stc SR,Rn 3850 3851 3852File: as.info, Node: SH64-Dependent, Next: PDP-11-Dependent, Prev: SH-Dependent, Up: Machine Dependencies 3853 38548.28 SuperH SH64 Dependent Features 3855=================================== 3856 3857* Menu: 3858 3859* SH64 Options:: Options 3860* SH64 Syntax:: Syntax 3861* SH64 Directives:: SH64 Machine Directives 3862* SH64 Opcodes:: Opcodes 3863 3864 3865File: as.info, Node: SH64 Options, Next: SH64 Syntax, Up: SH64-Dependent 3866 38678.28.1 Options 3868-------------- 3869 3870`-isa=sh4 | sh4a' 3871 Specify the sh4 or sh4a instruction set. 3872 3873`-isa=dsp' 3874 Enable sh-dsp insns, and disable sh3e / sh4 insns. 3875 3876`-isa=fp' 3877 Enable sh2e, sh3e, sh4, and sh4a insn sets. 3878 3879`-isa=all' 3880 Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. 3881 3882`-isa=shmedia | -isa=shcompact' 3883 Specify the default instruction set. `SHmedia' specifies the 3884 32-bit opcodes, and `SHcompact' specifies the 16-bit opcodes 3885 compatible with previous SH families. The default depends on the 3886 ABI selected; the default for the 64-bit ABI is SHmedia, and the 3887 default for the 32-bit ABI is SHcompact. If neither the ABI nor 3888 the ISA is specified, the default is 32-bit SHcompact. 3889 3890 Note that the `.mode' pseudo-op is not permitted if the ISA is not 3891 specified on the command line. 3892 3893`-abi=32 | -abi=64' 3894 Specify the default ABI. If the ISA is specified and the ABI is 3895 not, the default ABI depends on the ISA, with SHmedia defaulting 3896 to 64-bit and SHcompact defaulting to 32-bit. 3897 3898 Note that the `.abi' pseudo-op is not permitted if the ABI is not 3899 specified on the command line. When the ABI is specified on the 3900 command line, any `.abi' pseudo-ops in the source must match it. 3901 3902`-shcompact-const-crange' 3903 Emit code-range descriptors for constants in SHcompact code 3904 sections. 3905 3906`-no-mix' 3907 Disallow SHmedia code in the same section as constants and 3908 SHcompact code. 3909 3910`-no-expand' 3911 Do not expand MOVI, PT, PTA or PTB instructions. 3912 3913`-expand-pt32' 3914 With -abi=64, expand PT, PTA and PTB instructions to 32 bits only. 3915 3916 3917 3918File: as.info, Node: SH64 Syntax, Next: SH64 Directives, Prev: SH64 Options, Up: SH64-Dependent 3919 39208.28.2 Syntax 3921------------- 3922 3923* Menu: 3924 3925* SH64-Chars:: Special Characters 3926* SH64-Regs:: Register Names 3927* SH64-Addressing:: Addressing Modes 3928 3929 3930File: as.info, Node: SH64-Chars, Next: SH64-Regs, Up: SH64 Syntax 3931 39328.28.2.1 Special Characters 3933........................... 3934 3935`!' is the line comment character. 3936 3937 You can use `;' instead of a newline to separate statements. 3938 3939 Since `$' has no special meaning, you may use it in symbol names. 3940 3941 3942File: as.info, Node: SH64-Regs, Next: SH64-Addressing, Prev: SH64-Chars, Up: SH64 Syntax 3943 39448.28.2.2 Register Names 3945....................... 3946 3947You can use the predefined symbols `r0' through `r63' to refer to the 3948SH64 general registers, `cr0' through `cr63' for control registers, 3949`tr0' through `tr7' for target address registers, `fr0' through `fr63' 3950for single-precision floating point registers, `dr0' through `dr62' 3951(even numbered registers only) for double-precision floating point 3952registers, `fv0' through `fv60' (multiples of four only) for 3953single-precision floating point vectors, `fp0' through `fp62' (even 3954numbered registers only) for single-precision floating point pairs, 3955`mtrx0' through `mtrx48' (multiples of 16 only) for 4x4 matrices of 3956single-precision floating point registers, `pc' for the program 3957counter, and `fpscr' for the floating point status and control register. 3958 3959 You can also refer to the control registers by the mnemonics `sr', 3960`ssr', `pssr', `intevt', `expevt', `pexpevt', `tra', `spc', `pspc', 3961`resvec', `vbr', `tea', `dcr', `kcr0', `kcr1', `ctc', and `usr'. 3962 3963 3964File: as.info, Node: SH64-Addressing, Prev: SH64-Regs, Up: SH64 Syntax 3965 39668.28.2.3 Addressing Modes 3967......................... 3968 3969SH64 operands consist of either a register or immediate value. The 3970immediate value can be a constant or label reference (or portion of a 3971label reference), as in this example: 3972 3973 movi 4,r2 3974 pt function, tr4 3975 movi (function >> 16) & 65535,r0 3976 shori function & 65535, r0 3977 ld.l r0,4,r0 3978 3979 Instruction label references can reference labels in either SHmedia 3980or SHcompact. To differentiate between the two, labels in SHmedia 3981sections will always have the least significant bit set (i.e. they will 3982be odd), which SHcompact labels will have the least significant bit 3983reset (i.e. they will be even). If you need to reference the actual 3984address of a label, you can use the `datalabel' modifier, as in this 3985example: 3986 3987 .long function 3988 .long datalabel function 3989 3990 In that example, the first longword may or may not have the least 3991significant bit set depending on whether the label is an SHmedia label 3992or an SHcompact label. The second longword will be the actual address 3993of the label, regardless of what type of label it is. 3994 3995 3996File: as.info, Node: SH64 Directives, Next: SH64 Opcodes, Prev: SH64 Syntax, Up: SH64-Dependent 3997 39988.28.3 SH64 Machine Directives 3999------------------------------ 4000 4001In addition to the SH directives, the SH64 provides the following 4002directives: 4003 4004`.mode [shmedia|shcompact]' 4005`.isa [shmedia|shcompact]' 4006 Specify the ISA for the following instructions (the two directives 4007 are equivalent). Note that programs such as `objdump' rely on 4008 symbolic labels to determine when such mode switches occur (by 4009 checking the least significant bit of the label's address), so 4010 such mode/isa changes should always be followed by a label (in 4011 practice, this is true anyway). Note that you cannot use these 4012 directives if you didn't specify an ISA on the command line. 4013 4014`.abi [32|64]' 4015 Specify the ABI for the following instructions. Note that you 4016 cannot use this directive unless you specified an ABI on the 4017 command line, and the ABIs specified must match. 4018 4019`.uaquad' 4020 Like .uaword and .ualong, this allows you to specify an 4021 intentionally unaligned quadword (64 bit word). 4022 4023 4024 4025File: as.info, Node: SH64 Opcodes, Prev: SH64 Directives, Up: SH64-Dependent 4026 40278.28.4 Opcodes 4028-------------- 4029 4030For detailed information on the SH64 machine instruction set, see 4031`SuperH 64 bit RISC Series Architecture Manual' (SuperH, Inc.). 4032 4033 `as' implements all the standard SH64 opcodes. In addition, the 4034following pseudo-opcodes may be expanded into one or more alternate 4035opcodes: 4036 4037`movi' 4038 If the value doesn't fit into a standard `movi' opcode, `as' will 4039 replace the `movi' with a sequence of `movi' and `shori' opcodes. 4040 4041`pt' 4042 This expands to a sequence of `movi' and `shori' opcode, followed 4043 by a `ptrel' opcode, or to a `pta' or `ptb' opcode, depending on 4044 the label referenced. 4045 4046 4047 4048File: as.info, Node: Sparc-Dependent, Next: TIC54X-Dependent, Prev: PPC-Dependent, Up: Machine Dependencies 4049 40508.29 SPARC Dependent Features 4051============================= 4052 4053* Menu: 4054 4055* Sparc-Opts:: Options 4056* Sparc-Aligned-Data:: Option to enforce aligned data 4057* Sparc-Float:: Floating Point 4058* Sparc-Directives:: Sparc Machine Directives 4059 4060 4061File: as.info, Node: Sparc-Opts, Next: Sparc-Aligned-Data, Up: Sparc-Dependent 4062 40638.29.1 Options 4064-------------- 4065 4066The SPARC chip family includes several successive levels, using the same 4067core instruction set, but including a few additional instructions at 4068each level. There are exceptions to this however. For details on what 4069instructions each variant supports, please see the chip's architecture 4070reference manual. 4071 4072 By default, `as' assumes the core instruction set (SPARC v6), but 4073"bumps" the architecture level as needed: it switches to successively 4074higher architectures as it encounters instructions that only exist in 4075the higher levels. 4076 4077 If not configured for SPARC v9 (`sparc64-*-*') GAS will not bump 4078passed sparclite by default, an option must be passed to enable the v9 4079instructions. 4080 4081 GAS treats sparclite as being compatible with v8, unless an 4082architecture is explicitly requested. SPARC v9 is always incompatible 4083with sparclite. 4084 4085`-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite' 4086`-Av8plus | -Av8plusa | -Av9 | -Av9a' 4087 Use one of the `-A' options to select one of the SPARC 4088 architectures explicitly. If you select an architecture 4089 explicitly, `as' reports a fatal error if it encounters an 4090 instruction or feature requiring an incompatible or higher level. 4091 4092 `-Av8plus' and `-Av8plusa' select a 32 bit environment. 4093 4094 `-Av9' and `-Av9a' select a 64 bit environment and are not 4095 available unless GAS is explicitly configured with 64 bit 4096 environment support. 4097 4098 `-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with 4099 UltraSPARC extensions. 4100 4101`-xarch=v8plus | -xarch=v8plusa' 4102 For compatibility with the Solaris v9 assembler. These options are 4103 equivalent to -Av8plus and -Av8plusa, respectively. 4104 4105`-bump' 4106 Warn whenever it is necessary to switch to another level. If an 4107 architecture level is explicitly requested, GAS will not issue 4108 warnings until that level is reached, and will then bump the level 4109 as required (except between incompatible levels). 4110 4111`-32 | -64' 4112 Select the word size, either 32 bits or 64 bits. These options 4113 are only available with the ELF object file format, and require 4114 that the necessary BFD support has been included. 4115 4116 4117File: as.info, Node: Sparc-Aligned-Data, Next: Sparc-Float, Prev: Sparc-Opts, Up: Sparc-Dependent 4118 41198.29.2 Enforcing aligned data 4120----------------------------- 4121 4122SPARC GAS normally permits data to be misaligned. For example, it 4123permits the `.long' pseudo-op to be used on a byte boundary. However, 4124the native SunOS and Solaris assemblers issue an error when they see 4125misaligned data. 4126 4127 You can use the `--enforce-aligned-data' option to make SPARC GAS 4128also issue an error about misaligned data, just as the SunOS and Solaris 4129assemblers do. 4130 4131 The `--enforce-aligned-data' option is not the default because gcc 4132issues misaligned data pseudo-ops when it initializes certain packed 4133data structures (structures defined using the `packed' attribute). You 4134may have to assemble with GAS in order to initialize packed data 4135structures in your own code. 4136 4137 4138File: as.info, Node: Sparc-Float, Next: Sparc-Directives, Prev: Sparc-Aligned-Data, Up: Sparc-Dependent 4139 41408.29.3 Floating Point 4141--------------------- 4142 4143The Sparc uses IEEE floating-point numbers. 4144 4145 4146File: as.info, Node: Sparc-Directives, Prev: Sparc-Float, Up: Sparc-Dependent 4147 41488.29.4 Sparc Machine Directives 4149------------------------------- 4150 4151The Sparc version of `as' supports the following additional machine 4152directives: 4153 4154`.align' 4155 This must be followed by the desired alignment in bytes. 4156 4157`.common' 4158 This must be followed by a symbol name, a positive number, and 4159 `"bss"'. This behaves somewhat like `.comm', but the syntax is 4160 different. 4161 4162`.half' 4163 This is functionally identical to `.short'. 4164 4165`.nword' 4166 On the Sparc, the `.nword' directive produces native word sized 4167 value, ie. if assembling with -32 it is equivalent to `.word', if 4168 assembling with -64 it is equivalent to `.xword'. 4169 4170`.proc' 4171 This directive is ignored. Any text following it on the same line 4172 is also ignored. 4173 4174`.register' 4175 This directive declares use of a global application or system 4176 register. It must be followed by a register name %g2, %g3, %g6 or 4177 %g7, comma and the symbol name for that register. If symbol name 4178 is `#scratch', it is a scratch register, if it is `#ignore', it 4179 just suppresses any errors about using undeclared global register, 4180 but does not emit any information about it into the object file. 4181 This can be useful e.g. if you save the register before use and 4182 restore it after. 4183 4184`.reserve' 4185 This must be followed by a symbol name, a positive number, and 4186 `"bss"'. This behaves somewhat like `.lcomm', but the syntax is 4187 different. 4188 4189`.seg' 4190 This must be followed by `"text"', `"data"', or `"data1"'. It 4191 behaves like `.text', `.data', or `.data 1'. 4192 4193`.skip' 4194 This is functionally identical to the `.space' directive. 4195 4196`.word' 4197 On the Sparc, the `.word' directive produces 32 bit values, 4198 instead of the 16 bit values it produces on many other machines. 4199 4200`.xword' 4201 On the Sparc V9 processor, the `.xword' directive produces 64 bit 4202 values. 4203 4204 4205File: as.info, Node: TIC54X-Dependent, Next: V850-Dependent, Prev: Sparc-Dependent, Up: Machine Dependencies 4206 42078.30 TIC54X Dependent Features 4208============================== 4209 4210* Menu: 4211 4212* TIC54X-Opts:: Command-line Options 4213* TIC54X-Block:: Blocking 4214* TIC54X-Env:: Environment Settings 4215* TIC54X-Constants:: Constants Syntax 4216* TIC54X-Subsyms:: String Substitution 4217* TIC54X-Locals:: Local Label Syntax 4218* TIC54X-Builtins:: Builtin Assembler Math Functions 4219* TIC54X-Ext:: Extended Addressing Support 4220* TIC54X-Directives:: Directives 4221* TIC54X-Macros:: Macro Features 4222* TIC54X-MMRegs:: Memory-mapped Registers 4223 4224 4225File: as.info, Node: TIC54X-Opts, Next: TIC54X-Block, Up: TIC54X-Dependent 4226 42278.30.1 Options 4228-------------- 4229 4230The TMS320C54x version of `as' has a few machine-dependent options. 4231 4232 You can use the `-mfar-mode' option to enable extended addressing 4233mode. All addresses will be assumed to be > 16 bits, and the 4234appropriate relocation types will be used. This option is equivalent 4235to using the `.far_mode' directive in the assembly code. If you do not 4236use the `-mfar-mode' option, all references will be assumed to be 16 4237bits. This option may be abbreviated to `-mf'. 4238 4239 You can use the `-mcpu' option to specify a particular CPU. This 4240option is equivalent to using the `.version' directive in the assembly 4241code. For recognized CPU codes, see *Note `.version': 4242TIC54X-Directives. The default CPU version is `542'. 4243 4244 You can use the `-merrors-to-file' option to redirect error output 4245to a file (this provided for those deficient environments which don't 4246provide adequate output redirection). This option may be abbreviated to 4247`-me'. 4248 4249 4250File: as.info, Node: TIC54X-Block, Next: TIC54X-Env, Prev: TIC54X-Opts, Up: TIC54X-Dependent 4251 42528.30.2 Blocking 4253--------------- 4254 4255A blocked section or memory block is guaranteed not to cross the 4256blocking boundary (usually a page, or 128 words) if it is smaller than 4257the blocking size, or to start on a page boundary if it is larger than 4258the blocking size. 4259 4260 4261File: as.info, Node: TIC54X-Env, Next: TIC54X-Constants, Prev: TIC54X-Block, Up: TIC54X-Dependent 4262 42638.30.3 Environment Settings 4264--------------------------- 4265 4266`C54XDSP_DIR' and `A_DIR' are semicolon-separated paths which are added 4267to the list of directories normally searched for source and include 4268files. `C54XDSP_DIR' will override `A_DIR'. 4269 4270 4271File: as.info, Node: TIC54X-Constants, Next: TIC54X-Subsyms, Prev: TIC54X-Env, Up: TIC54X-Dependent 4272 42738.30.4 Constants Syntax 4274----------------------- 4275 4276The TIC54X version of `as' allows the following additional constant 4277formats, using a suffix to indicate the radix: 4278 4279 Binary `000000B, 011000b' 4280 Octal `10Q, 224q' 4281 Hexadecimal `45h, 0FH' 4282 4283 4284File: as.info, Node: TIC54X-Subsyms, Next: TIC54X-Locals, Prev: TIC54X-Constants, Up: TIC54X-Dependent 4285 42868.30.5 String Substitution 4287-------------------------- 4288 4289A subset of allowable symbols (which we'll call subsyms) may be assigned 4290arbitrary string values. This is roughly equivalent to C preprocessor 4291#define macros. When `as' encounters one of these symbols, the symbol 4292is replaced in the input stream by its string value. Subsym names 4293*must* begin with a letter. 4294 4295 Subsyms may be defined using the `.asg' and `.eval' directives 4296(*Note `.asg': TIC54X-Directives, *Note `.eval': TIC54X-Directives. 4297 4298 Expansion is recursive until a previously encountered symbol is 4299seen, at which point substitution stops. 4300 4301 In this example, x is replaced with SYM2; SYM2 is replaced with 4302SYM1, and SYM1 is replaced with x. At this point, x has already been 4303encountered and the substitution stops. 4304 4305 .asg "x",SYM1 4306 .asg "SYM1",SYM2 4307 .asg "SYM2",x 4308 add x,a ; final code assembled is "add x, a" 4309 4310 Macro parameters are converted to subsyms; a side effect of this is 4311the normal `as' '\ARG' dereferencing syntax is unnecessary. Subsyms 4312defined within a macro will have global scope, unless the `.var' 4313directive is used to identify the subsym as a local macro variable 4314*note `.var': TIC54X-Directives. 4315 4316 Substitution may be forced in situations where replacement might be 4317ambiguous by placing colons on either side of the subsym. The following 4318code: 4319 4320 .eval "10",x 4321 LAB:X: add #x, a 4322 4323 When assembled becomes: 4324 4325 LAB10 add #10, a 4326 4327 Smaller parts of the string assigned to a subsym may be accessed with 4328the following syntax: 4329 4330``:SYMBOL(CHAR_INDEX):'' 4331 Evaluates to a single-character string, the character at 4332 CHAR_INDEX. 4333 4334``:SYMBOL(START,LENGTH):'' 4335 Evaluates to a substring of SYMBOL beginning at START with length 4336 LENGTH. 4337 4338 4339File: as.info, Node: TIC54X-Locals, Next: TIC54X-Builtins, Prev: TIC54X-Subsyms, Up: TIC54X-Dependent 4340 43418.30.6 Local Labels 4342------------------- 4343 4344Local labels may be defined in two ways: 4345 4346 * $N, where N is a decimal number between 0 and 9 4347 4348 * LABEL?, where LABEL is any legal symbol name. 4349 4350 Local labels thus defined may be redefined or automatically 4351generated. The scope of a local label is based on when it may be 4352undefined or reset. This happens when one of the following situations 4353is encountered: 4354 4355 * .newblock directive *note `.newblock': TIC54X-Directives. 4356 4357 * The current section is changed (.sect, .text, or .data) 4358 4359 * Entering or leaving an included file 4360 4361 * The macro scope where the label was defined is exited 4362 4363 4364File: as.info, Node: TIC54X-Builtins, Next: TIC54X-Ext, Prev: TIC54X-Locals, Up: TIC54X-Dependent 4365 43668.30.7 Math Builtins 4367-------------------- 4368 4369The following built-in functions may be used to generate a 4370floating-point value. All return a floating-point value except `$cvi', 4371`$int', and `$sgn', which return an integer value. 4372 4373``$acos(EXPR)'' 4374 Returns the floating point arccosine of EXPR. 4375 4376``$asin(EXPR)'' 4377 Returns the floating point arcsine of EXPR. 4378 4379``$atan(EXPR)'' 4380 Returns the floating point arctangent of EXPR. 4381 4382``$atan2(EXPR1,EXPR2)'' 4383 Returns the floating point arctangent of EXPR1 / EXPR2. 4384 4385``$ceil(EXPR)'' 4386 Returns the smallest integer not less than EXPR as floating point. 4387 4388``$cosh(EXPR)'' 4389 Returns the floating point hyperbolic cosine of EXPR. 4390 4391``$cos(EXPR)'' 4392 Returns the floating point cosine of EXPR. 4393 4394``$cvf(EXPR)'' 4395 Returns the integer value EXPR converted to floating-point. 4396 4397``$cvi(EXPR)'' 4398 Returns the floating point value EXPR converted to integer. 4399 4400``$exp(EXPR)'' 4401 Returns the floating point value e ^ EXPR. 4402 4403``$fabs(EXPR)'' 4404 Returns the floating point absolute value of EXPR. 4405 4406``$floor(EXPR)'' 4407 Returns the largest integer that is not greater than EXPR as 4408 floating point. 4409 4410``$fmod(EXPR1,EXPR2)'' 4411 Returns the floating point remainder of EXPR1 / EXPR2. 4412 4413``$int(EXPR)'' 4414 Returns 1 if EXPR evaluates to an integer, zero otherwise. 4415 4416``$ldexp(EXPR1,EXPR2)'' 4417 Returns the floating point value EXPR1 * 2 ^ EXPR2. 4418 4419``$log10(EXPR)'' 4420 Returns the base 10 logarithm of EXPR. 4421 4422``$log(EXPR)'' 4423 Returns the natural logarithm of EXPR. 4424 4425``$max(EXPR1,EXPR2)'' 4426 Returns the floating point maximum of EXPR1 and EXPR2. 4427 4428``$min(EXPR1,EXPR2)'' 4429 Returns the floating point minimum of EXPR1 and EXPR2. 4430 4431``$pow(EXPR1,EXPR2)'' 4432 Returns the floating point value EXPR1 ^ EXPR2. 4433 4434``$round(EXPR)'' 4435 Returns the nearest integer to EXPR as a floating point number. 4436 4437``$sgn(EXPR)'' 4438 Returns -1, 0, or 1 based on the sign of EXPR. 4439 4440``$sin(EXPR)'' 4441 Returns the floating point sine of EXPR. 4442 4443``$sinh(EXPR)'' 4444 Returns the floating point hyperbolic sine of EXPR. 4445 4446``$sqrt(EXPR)'' 4447 Returns the floating point square root of EXPR. 4448 4449``$tan(EXPR)'' 4450 Returns the floating point tangent of EXPR. 4451 4452``$tanh(EXPR)'' 4453 Returns the floating point hyperbolic tangent of EXPR. 4454 4455``$trunc(EXPR)'' 4456 Returns the integer value of EXPR truncated towards zero as 4457 floating point. 4458 4459 4460 4461File: as.info, Node: TIC54X-Ext, Next: TIC54X-Directives, Prev: TIC54X-Builtins, Up: TIC54X-Dependent 4462 44638.30.8 Extended Addressing 4464-------------------------- 4465 4466The `LDX' pseudo-op is provided for loading the extended addressing bits 4467of a label or address. For example, if an address `_label' resides in 4468extended program memory, the value of `_label' may be loaded as follows: 4469 ldx #_label,16,a ; loads extended bits of _label 4470 or #_label,a ; loads lower 16 bits of _label 4471 bacc a ; full address is in accumulator A 4472 4473 4474File: as.info, Node: TIC54X-Directives, Next: TIC54X-Macros, Prev: TIC54X-Ext, Up: TIC54X-Dependent 4475 44768.30.9 Directives 4477----------------- 4478 4479`.align [SIZE]' 4480`.even' 4481 Align the section program counter on the next boundary, based on 4482 SIZE. SIZE may be any power of 2. `.even' is equivalent to 4483 `.align' with a SIZE of 2. 4484 `1' 4485 Align SPC to word boundary 4486 4487 `2' 4488 Align SPC to longword boundary (same as .even) 4489 4490 `128' 4491 Align SPC to page boundary 4492 4493`.asg STRING, NAME' 4494 Assign NAME the string STRING. String replacement is performed on 4495 STRING before assignment. 4496 4497`.eval STRING, NAME' 4498 Evaluate the contents of string STRING and assign the result as a 4499 string to the subsym NAME. String replacement is performed on 4500 STRING before assignment. 4501 4502`.bss SYMBOL, SIZE [, [BLOCKING_FLAG] [,ALIGNMENT_FLAG]]' 4503 Reserve space for SYMBOL in the .bss section. SIZE is in words. 4504 If present, BLOCKING_FLAG indicates the allocated space should be 4505 aligned on a page boundary if it would otherwise cross a page 4506 boundary. If present, ALIGNMENT_FLAG causes the assembler to 4507 allocate SIZE on a long word boundary. 4508 4509`.byte VALUE [,...,VALUE_N]' 4510`.ubyte VALUE [,...,VALUE_N]' 4511`.char VALUE [,...,VALUE_N]' 4512`.uchar VALUE [,...,VALUE_N]' 4513 Place one or more bytes into consecutive words of the current 4514 section. The upper 8 bits of each word is zero-filled. If a 4515 label is used, it points to the word allocated for the first byte 4516 encountered. 4517 4518`.clink ["SECTION_NAME"]' 4519 Set STYP_CLINK flag for this section, which indicates to the 4520 linker that if no symbols from this section are referenced, the 4521 section should not be included in the link. If SECTION_NAME is 4522 omitted, the current section is used. 4523 4524`.c_mode' 4525 TBD. 4526 4527`.copy "FILENAME" | FILENAME' 4528`.include "FILENAME" | FILENAME' 4529 Read source statements from FILENAME. The normal include search 4530 path is used. Normally .copy will cause statements from the 4531 included file to be printed in the assembly listing and .include 4532 will not, but this distinction is not currently implemented. 4533 4534`.data' 4535 Begin assembling code into the .data section. 4536 4537`.double VALUE [,...,VALUE_N]' 4538`.ldouble VALUE [,...,VALUE_N]' 4539`.float VALUE [,...,VALUE_N]' 4540`.xfloat VALUE [,...,VALUE_N]' 4541 Place an IEEE single-precision floating-point representation of 4542 one or more floating-point values into the current section. All 4543 but `.xfloat' align the result on a longword boundary. Values are 4544 stored most-significant word first. 4545 4546`.drlist' 4547`.drnolist' 4548 Control printing of directives to the listing file. Ignored. 4549 4550`.emsg STRING' 4551`.mmsg STRING' 4552`.wmsg STRING' 4553 Emit a user-defined error, message, or warning, respectively. 4554 4555`.far_mode' 4556 Use extended addressing when assembling statements. This should 4557 appear only once per file, and is equivalent to the -mfar-mode 4558 option *note `-mfar-mode': TIC54X-Opts. 4559 4560`.fclist' 4561`.fcnolist' 4562 Control printing of false conditional blocks to the listing file. 4563 4564`.field VALUE [,SIZE]' 4565 Initialize a bitfield of SIZE bits in the current section. If 4566 VALUE is relocatable, then SIZE must be 16. SIZE defaults to 16 4567 bits. If VALUE does not fit into SIZE bits, the value will be 4568 truncated. Successive `.field' directives will pack starting at 4569 the current word, filling the most significant bits first, and 4570 aligning to the start of the next word if the field size does not 4571 fit into the space remaining in the current word. A `.align' 4572 directive with an operand of 1 will force the next `.field' 4573 directive to begin packing into a new word. If a label is used, it 4574 points to the word that contains the specified field. 4575 4576`.global SYMBOL [,...,SYMBOL_N]' 4577`.def SYMBOL [,...,SYMBOL_N]' 4578`.ref SYMBOL [,...,SYMBOL_N]' 4579 `.def' nominally identifies a symbol defined in the current file 4580 and availalbe to other files. `.ref' identifies a symbol used in 4581 the current file but defined elsewhere. Both map to the standard 4582 `.global' directive. 4583 4584`.half VALUE [,...,VALUE_N]' 4585`.uhalf VALUE [,...,VALUE_N]' 4586`.short VALUE [,...,VALUE_N]' 4587`.ushort VALUE [,...,VALUE_N]' 4588`.int VALUE [,...,VALUE_N]' 4589`.uint VALUE [,...,VALUE_N]' 4590`.word VALUE [,...,VALUE_N]' 4591`.uword VALUE [,...,VALUE_N]' 4592 Place one or more values into consecutive words of the current 4593 section. If a label is used, it points to the word allocated for 4594 the first value encountered. 4595 4596`.label SYMBOL' 4597 Define a special SYMBOL to refer to the load time address of the 4598 current section program counter. 4599 4600`.length' 4601`.width' 4602 Set the page length and width of the output listing file. Ignored. 4603 4604`.list' 4605`.nolist' 4606 Control whether the source listing is printed. Ignored. 4607 4608`.long VALUE [,...,VALUE_N]' 4609`.ulong VALUE [,...,VALUE_N]' 4610`.xlong VALUE [,...,VALUE_N]' 4611 Place one or more 32-bit values into consecutive words in the 4612 current section. The most significant word is stored first. 4613 `.long' and `.ulong' align the result on a longword boundary; 4614 `xlong' does not. 4615 4616`.loop [COUNT]' 4617`.break [CONDITION]' 4618`.endloop' 4619 Repeatedly assemble a block of code. `.loop' begins the block, and 4620 `.endloop' marks its termination. COUNT defaults to 1024, and 4621 indicates the number of times the block should be repeated. 4622 `.break' terminates the loop so that assembly begins after the 4623 `.endloop' directive. The optional CONDITION will cause the loop 4624 to terminate only if it evaluates to zero. 4625 4626`MACRO_NAME .macro [PARAM1][,...PARAM_N]' 4627`[.mexit]' 4628`.endm' 4629 See the section on macros for more explanation (*Note 4630 TIC54X-Macros::. 4631 4632`.mlib "FILENAME" | FILENAME' 4633 Load the macro library FILENAME. FILENAME must be an archived 4634 library (BFD ar-compatible) of text files, expected to contain 4635 only macro definitions. The standard include search path is used. 4636 4637`.mlist' 4638 4639`.mnolist' 4640 Control whether to include macro and loop block expansions in the 4641 listing output. Ignored. 4642 4643`.mmregs' 4644 Define global symbolic names for the 'c54x registers. Supposedly 4645 equivalent to executing `.set' directives for each register with 4646 its memory-mapped value, but in reality is provided only for 4647 compatibility and does nothing. 4648 4649`.newblock' 4650 This directive resets any TIC54X local labels currently defined. 4651 Normal `as' local labels are unaffected. 4652 4653`.option OPTION_LIST' 4654 Set listing options. Ignored. 4655 4656`.sblock "SECTION_NAME" | SECTION_NAME [,"NAME_N" | NAME_N]' 4657 Designate SECTION_NAME for blocking. Blocking guarantees that a 4658 section will start on a page boundary (128 words) if it would 4659 otherwise cross a page boundary. Only initialized sections may be 4660 designated with this directive. See also *Note TIC54X-Block::. 4661 4662`.sect "SECTION_NAME"' 4663 Define a named initialized section and make it the current section. 4664 4665`SYMBOL .set "VALUE"' 4666`SYMBOL .equ "VALUE"' 4667 Equate a constant VALUE to a SYMBOL, which is placed in the symbol 4668 table. SYMBOL may not be previously defined. 4669 4670`.space SIZE_IN_BITS' 4671`.bes SIZE_IN_BITS' 4672 Reserve the given number of bits in the current section and 4673 zero-fill them. If a label is used with `.space', it points to the 4674 *first* word reserved. With `.bes', the label points to the 4675 *last* word reserved. 4676 4677`.sslist' 4678`.ssnolist' 4679 Controls the inclusion of subsym replacement in the listing 4680 output. Ignored. 4681 4682`.string "STRING" [,...,"STRING_N"]' 4683`.pstring "STRING" [,...,"STRING_N"]' 4684 Place 8-bit characters from STRING into the current section. 4685 `.string' zero-fills the upper 8 bits of each word, while 4686 `.pstring' puts two characters into each word, filling the 4687 most-significant bits first. Unused space is zero-filled. If a 4688 label is used, it points to the first word initialized. 4689 4690`[STAG] .struct [OFFSET]' 4691`[NAME_1] element [COUNT_1]' 4692`[NAME_2] element [COUNT_2]' 4693`[TNAME] .tag STAGX [TCOUNT]' 4694`...' 4695`[NAME_N] element [COUNT_N]' 4696`[SSIZE] .endstruct' 4697`LABEL .tag [STAG]' 4698 Assign symbolic offsets to the elements of a structure. STAG 4699 defines a symbol to use to reference the structure. OFFSET 4700 indicates a starting value to use for the first element 4701 encountered; otherwise it defaults to zero. Each element can have 4702 a named offset, NAME, which is a symbol assigned the value of the 4703 element's offset into the structure. If STAG is missing, these 4704 become global symbols. COUNT adjusts the offset that many times, 4705 as if `element' were an array. `element' may be one of `.byte', 4706 `.word', `.long', `.float', or any equivalent of those, and the 4707 structure offset is adjusted accordingly. `.field' and `.string' 4708 are also allowed; the size of `.field' is one bit, and `.string' 4709 is considered to be one word in size. Only element descriptors, 4710 structure/union tags, `.align' and conditional assembly directives 4711 are allowed within `.struct'/`.endstruct'. `.align' aligns member 4712 offsets to word boundaries only. SSIZE, if provided, will always 4713 be assigned the size of the structure. 4714 4715 The `.tag' directive, in addition to being used to define a 4716 structure/union element within a structure, may be used to apply a 4717 structure to a symbol. Once applied to LABEL, the individual 4718 structure elements may be applied to LABEL to produce the desired 4719 offsets using LABEL as the structure base. 4720 4721`.tab' 4722 Set the tab size in the output listing. Ignored. 4723 4724`[UTAG] .union' 4725`[NAME_1] element [COUNT_1]' 4726`[NAME_2] element [COUNT_2]' 4727`[TNAME] .tag UTAGX[,TCOUNT]' 4728`...' 4729`[NAME_N] element [COUNT_N]' 4730`[USIZE] .endstruct' 4731`LABEL .tag [UTAG]' 4732 Similar to `.struct', but the offset after each element is reset to 4733 zero, and the USIZE is set to the maximum of all defined elements. 4734 Starting offset for the union is always zero. 4735 4736`[SYMBOL] .usect "SECTION_NAME", SIZE, [,[BLOCKING_FLAG] [,ALIGNMENT_FLAG]]' 4737 Reserve space for variables in a named, uninitialized section 4738 (similar to .bss). `.usect' allows definitions sections 4739 independent of .bss. SYMBOL points to the first location reserved 4740 by this allocation. The symbol may be used as a variable name. 4741 SIZE is the allocated size in words. BLOCKING_FLAG indicates 4742 whether to block this section on a page boundary (128 words) 4743 (*note TIC54X-Block::). ALIGNMENT FLAG indicates whether the 4744 section should be longword-aligned. 4745 4746`.var SYM[,..., SYM_N]' 4747 Define a subsym to be a local variable within a macro. See *Note 4748 TIC54X-Macros::. 4749 4750`.version VERSION' 4751 Set which processor to build instructions for. Though the 4752 following values are accepted, the op is ignored. 4753 `541' 4754 `542' 4755 `543' 4756 `545' 4757 `545LP' 4758 `546LP' 4759 `548' 4760 `549' 4761 4762 4763File: as.info, Node: TIC54X-Macros, Next: TIC54X-MMRegs, Prev: TIC54X-Directives, Up: TIC54X-Dependent 4764 47658.30.10 Macros 4766-------------- 4767 4768Macros do not require explicit dereferencing of arguments (i.e. \ARG). 4769 4770 During macro expansion, the macro parameters are converted to 4771subsyms. If the number of arguments passed the macro invocation 4772exceeds the number of parameters defined, the last parameter is 4773assigned the string equivalent of all remaining arguments. If fewer 4774arguments are given than parameters, the missing parameters are 4775assigned empty strings. To include a comma in an argument, you must 4776enclose the argument in quotes. 4777 4778 The following built-in subsym functions allow examination of the 4779string value of subsyms (or ordinary strings). The arguments are 4780strings unless otherwise indicated (subsyms passed as args will be 4781replaced by the strings they represent). 4782``$symlen(STR)'' 4783 Returns the length of STR. 4784 4785``$symcmp(STR1,STR2)'' 4786 Returns 0 if STR1 == STR2, non-zero otherwise. 4787 4788``$firstch(STR,CH)'' 4789 Returns index of the first occurrence of character constant CH in 4790 STR. 4791 4792``$lastch(STR,CH)'' 4793 Returns index of the last occurrence of character constant CH in 4794 STR. 4795 4796``$isdefed(SYMBOL)'' 4797 Returns zero if the symbol SYMBOL is not in the symbol table, 4798 non-zero otherwise. 4799 4800``$ismember(SYMBOL,LIST)'' 4801 Assign the first member of comma-separated string LIST to SYMBOL; 4802 LIST is reassigned the remainder of the list. Returns zero if 4803 LIST is a null string. Both arguments must be subsyms. 4804 4805``$iscons(EXPR)'' 4806 Returns 1 if string EXPR is binary, 2 if octal, 3 if hexadecimal, 4807 4 if a character, 5 if decimal, and zero if not an integer. 4808 4809``$isname(NAME)'' 4810 Returns 1 if NAME is a valid symbol name, zero otherwise. 4811 4812``$isreg(REG)'' 4813 Returns 1 if REG is a valid predefined register name (AR0-AR7 4814 only). 4815 4816``$structsz(STAG)'' 4817 Returns the size of the structure or union represented by STAG. 4818 4819``$structacc(STAG)'' 4820 Returns the reference point of the structure or union represented 4821 by STAG. Always returns zero. 4822 4823 4824 4825File: as.info, Node: TIC54X-MMRegs, Prev: TIC54X-Macros, Up: TIC54X-Dependent 4826 48278.30.11 Memory-mapped Registers 4828------------------------------- 4829 4830The following symbols are recognized as memory-mapped registers: 4831 4832 4833 4834File: as.info, Node: Z8000-Dependent, Next: Vax-Dependent, Prev: Xtensa-Dependent, Up: Machine Dependencies 4835 48368.31 Z8000 Dependent Features 4837============================= 4838 4839 The Z8000 as supports both members of the Z8000 family: the 4840unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with 484124 bit addresses. 4842 4843 When the assembler is in unsegmented mode (specified with the 4844`unsegm' directive), an address takes up one word (16 bit) sized 4845register. When the assembler is in segmented mode (specified with the 4846`segm' directive), a 24-bit address takes up a long (32 bit) register. 4847*Note Assembler Directives for the Z8000: Z8000 Directives, for a list 4848of other Z8000 specific assembler directives. 4849 4850* Menu: 4851 4852* Z8000 Options:: Command-line options for the Z8000 4853* Z8000 Syntax:: Assembler syntax for the Z8000 4854* Z8000 Directives:: Special directives for the Z8000 4855* Z8000 Opcodes:: Opcodes 4856 4857 4858File: as.info, Node: Z8000 Options, Next: Z8000 Syntax, Up: Z8000-Dependent 4859 48608.31.1 Options 4861-------------- 4862 4863`-z8001' 4864 Generate segmented code by default. 4865 4866`-z8002' 4867 Generate unsegmented code by default. 4868 4869 4870File: as.info, Node: Z8000 Syntax, Next: Z8000 Directives, Prev: Z8000 Options, Up: Z8000-Dependent 4871 48728.31.2 Syntax 4873------------- 4874 4875* Menu: 4876 4877* Z8000-Chars:: Special Characters 4878* Z8000-Regs:: Register Names 4879* Z8000-Addressing:: Addressing Modes 4880 4881 4882File: as.info, Node: Z8000-Chars, Next: Z8000-Regs, Up: Z8000 Syntax 4883 48848.31.2.1 Special Characters 4885........................... 4886 4887`!' is the line comment character. 4888 4889 You can use `;' instead of a newline to separate statements. 4890 4891 4892File: as.info, Node: Z8000-Regs, Next: Z8000-Addressing, Prev: Z8000-Chars, Up: Z8000 Syntax 4893 48948.31.2.2 Register Names 4895....................... 4896 4897The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can refer 4898to different sized groups of registers by register number, with the 4899prefix `r' for 16 bit registers, `rr' for 32 bit registers and `rq' for 490064 bit registers. You can also refer to the contents of the first 4901eight (of the sixteen 16 bit registers) by bytes. They are named `rlN' 4902and `rhN'. 4903 4904_byte registers_ 4905 rl0 rh0 rl1 rh1 rl2 rh2 rl3 rh3 4906 rl4 rh4 rl5 rh5 rl6 rh6 rl7 rh7 4907 4908_word registers_ 4909 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 4910 4911_long word registers_ 4912 rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14 4913 4914_quad word registers_ 4915 rq0 rq4 rq8 rq12 4916 4917 4918File: as.info, Node: Z8000-Addressing, Prev: Z8000-Regs, Up: Z8000 Syntax 4919 49208.31.2.3 Addressing Modes 4921......................... 4922 4923as understands the following addressing modes for the Z8000: 4924 4925`rlN' 4926`rhN' 4927`rN' 4928`rrN' 4929`rqN' 4930 Register direct: 8bit, 16bit, 32bit, and 64bit registers. 4931 4932`@rN' 4933`@rrN' 4934 Indirect register: @rrN in segmented mode, @rN in unsegmented 4935 mode. 4936 4937`ADDR' 4938 Direct: the 16 bit or 24 bit address (depending on whether the 4939 assembler is in segmented or unsegmented mode) of the operand is 4940 in the instruction. 4941 4942`address(rN)' 4943 Indexed: the 16 or 24 bit address is added to the 16 bit register 4944 to produce the final address in memory of the operand. 4945 4946`rN(#IMM)' 4947`rrN(#IMM)' 4948 Base Address: the 16 or 24 bit register is added to the 16 bit sign 4949 extended immediate displacement to produce the final address in 4950 memory of the operand. 4951 4952`rN(rM)' 4953`rrN(rM)' 4954 Base Index: the 16 or 24 bit register rN or rrN is added to the 4955 sign extended 16 bit index register rM to produce the final 4956 address in memory of the operand. 4957 4958`#XX' 4959 Immediate data XX. 4960 4961 4962File: as.info, Node: Z8000 Directives, Next: Z8000 Opcodes, Prev: Z8000 Syntax, Up: Z8000-Dependent 4963 49648.31.3 Assembler Directives for the Z8000 4965----------------------------------------- 4966 4967The Z8000 port of as includes additional assembler directives, for 4968compatibility with other Z8000 assemblers. These do not begin with `.' 4969(unlike the ordinary as directives). 4970 4971`segm' 4972`.z8001' 4973 Generate code for the segmented Z8001. 4974 4975`unsegm' 4976`.z8002' 4977 Generate code for the unsegmented Z8002. 4978 4979`name' 4980 Synonym for `.file' 4981 4982`global' 4983 Synonym for `.global' 4984 4985`wval' 4986 Synonym for `.word' 4987 4988`lval' 4989 Synonym for `.long' 4990 4991`bval' 4992 Synonym for `.byte' 4993 4994`sval' 4995 Assemble a string. `sval' expects one string literal, delimited by 4996 single quotes. It assembles each byte of the string into 4997 consecutive addresses. You can use the escape sequence `%XX' 4998 (where XX represents a two-digit hexadecimal number) to represent 4999 the character whose ASCII value is XX. Use this feature to 5000 describe single quote and other characters that may not appear in 5001 string literals as themselves. For example, the C statement 5002 `char *a = "he said \"it's 50% off\"";' is represented in Z8000 5003 assembly language (shown with the assembler output in hex at the 5004 left) as 5005 5006 68652073 sval 'he said %22it%27s 50%25 off%22%00' 5007 61696420 5008 22697427 5009 73203530 5010 25206F66 5011 662200 5012 5013`rsect' 5014 synonym for `.section' 5015 5016`block' 5017 synonym for `.space' 5018 5019`even' 5020 special case of `.align'; aligns output to even byte boundary. 5021 5022 5023File: as.info, Node: Z8000 Opcodes, Prev: Z8000 Directives, Up: Z8000-Dependent 5024 50258.31.4 Opcodes 5026-------------- 5027 5028For detailed information on the Z8000 machine instruction set, see 5029`Z8000 Technical Manual'. 5030 5031 The following table summarizes the opcodes and their arguments: 5032 5033 rs 16 bit source register 5034 rd 16 bit destination register 5035 rbs 8 bit source register 5036 rbd 8 bit destination register 5037 rrs 32 bit source register 5038 rrd 32 bit destination register 5039 rqs 64 bit source register 5040 rqd 64 bit destination register 5041 addr 16/24 bit address 5042 imm immediate data 5043 5044 adc rd,rs clrb addr cpsir @rd,@rs,rr,cc 5045 adcb rbd,rbs clrb addr(rd) cpsirb @rd,@rs,rr,cc 5046 add rd,@rs clrb rbd dab rbd 5047 add rd,addr com @rd dbjnz rbd,disp7 5048 add rd,addr(rs) com addr dec @rd,imm4m1 5049 add rd,imm16 com addr(rd) dec addr(rd),imm4m1 5050 add rd,rs com rd dec addr,imm4m1 5051 addb rbd,@rs comb @rd dec rd,imm4m1 5052 addb rbd,addr comb addr decb @rd,imm4m1 5053 addb rbd,addr(rs) comb addr(rd) decb addr(rd),imm4m1 5054 addb rbd,imm8 comb rbd decb addr,imm4m1 5055 addb rbd,rbs comflg flags decb rbd,imm4m1 5056 addl rrd,@rs cp @rd,imm16 di i2 5057 addl rrd,addr cp addr(rd),imm16 div rrd,@rs 5058 addl rrd,addr(rs) cp addr,imm16 div rrd,addr 5059 addl rrd,imm32 cp rd,@rs div rrd,addr(rs) 5060 addl rrd,rrs cp rd,addr div rrd,imm16 5061 and rd,@rs cp rd,addr(rs) div rrd,rs 5062 and rd,addr cp rd,imm16 divl rqd,@rs 5063 and rd,addr(rs) cp rd,rs divl rqd,addr 5064 and rd,imm16 cpb @rd,imm8 divl rqd,addr(rs) 5065 and rd,rs cpb addr(rd),imm8 divl rqd,imm32 5066 andb rbd,@rs cpb addr,imm8 divl rqd,rrs 5067 andb rbd,addr cpb rbd,@rs djnz rd,disp7 5068 andb rbd,addr(rs) cpb rbd,addr ei i2 5069 andb rbd,imm8 cpb rbd,addr(rs) ex rd,@rs 5070 andb rbd,rbs cpb rbd,imm8 ex rd,addr 5071 bit @rd,imm4 cpb rbd,rbs ex rd,addr(rs) 5072 bit addr(rd),imm4 cpd rd,@rs,rr,cc ex rd,rs 5073 bit addr,imm4 cpdb rbd,@rs,rr,cc exb rbd,@rs 5074 bit rd,imm4 cpdr rd,@rs,rr,cc exb rbd,addr 5075 bit rd,rs cpdrb rbd,@rs,rr,cc exb rbd,addr(rs) 5076 bitb @rd,imm4 cpi rd,@rs,rr,cc exb rbd,rbs 5077 bitb addr(rd),imm4 cpib rbd,@rs,rr,cc ext0e imm8 5078 bitb addr,imm4 cpir rd,@rs,rr,cc ext0f imm8 5079 bitb rbd,imm4 cpirb rbd,@rs,rr,cc ext8e imm8 5080 bitb rbd,rs cpl rrd,@rs ext8f imm8 5081 bpt cpl rrd,addr exts rrd 5082 call @rd cpl rrd,addr(rs) extsb rd 5083 call addr cpl rrd,imm32 extsl rqd 5084 call addr(rd) cpl rrd,rrs halt 5085 calr disp12 cpsd @rd,@rs,rr,cc in rd,@rs 5086 clr @rd cpsdb @rd,@rs,rr,cc in rd,imm16 5087 clr addr cpsdr @rd,@rs,rr,cc inb rbd,@rs 5088 clr addr(rd) cpsdrb @rd,@rs,rr,cc inb rbd,imm16 5089 clr rd cpsi @rd,@rs,rr,cc inc @rd,imm4m1 5090 clrb @rd cpsib @rd,@rs,rr,cc inc addr(rd),imm4m1 5091 inc addr,imm4m1 ldb rbd,rs(rx) mult rrd,addr(rs) 5092 inc rd,imm4m1 ldb rd(imm16),rbs mult rrd,imm16 5093 incb @rd,imm4m1 ldb rd(rx),rbs mult rrd,rs 5094 incb addr(rd),imm4m1 ldctl ctrl,rs multl rqd,@rs 5095 incb addr,imm4m1 ldctl rd,ctrl multl rqd,addr 5096 incb rbd,imm4m1 ldd @rs,@rd,rr multl rqd,addr(rs) 5097 ind @rd,@rs,ra lddb @rs,@rd,rr multl rqd,imm32 5098 indb @rd,@rs,rba lddr @rs,@rd,rr multl rqd,rrs 5099 inib @rd,@rs,ra lddrb @rs,@rd,rr neg @rd 5100 inibr @rd,@rs,ra ldi @rd,@rs,rr neg addr 5101 iret ldib @rd,@rs,rr neg addr(rd) 5102 jp cc,@rd ldir @rd,@rs,rr neg rd 5103 jp cc,addr ldirb @rd,@rs,rr negb @rd 5104 jp cc,addr(rd) ldk rd,imm4 negb addr 5105 jr cc,disp8 ldl @rd,rrs negb addr(rd) 5106 ld @rd,imm16 ldl addr(rd),rrs negb rbd 5107 ld @rd,rs ldl addr,rrs nop 5108 ld addr(rd),imm16 ldl rd(imm16),rrs or rd,@rs 5109 ld addr(rd),rs ldl rd(rx),rrs or rd,addr 5110 ld addr,imm16 ldl rrd,@rs or rd,addr(rs) 5111 ld addr,rs ldl rrd,addr or rd,imm16 5112 ld rd(imm16),rs ldl rrd,addr(rs) or rd,rs 5113 ld rd(rx),rs ldl rrd,imm32 orb rbd,@rs 5114 ld rd,@rs ldl rrd,rrs orb rbd,addr 5115 ld rd,addr ldl rrd,rs(imm16) orb rbd,addr(rs) 5116 ld rd,addr(rs) ldl rrd,rs(rx) orb rbd,imm8 5117 ld rd,imm16 ldm @rd,rs,n orb rbd,rbs 5118 ld rd,rs ldm addr(rd),rs,n out @rd,rs 5119 ld rd,rs(imm16) ldm addr,rs,n out imm16,rs 5120 ld rd,rs(rx) ldm rd,@rs,n outb @rd,rbs 5121 lda rd,addr ldm rd,addr(rs),n outb imm16,rbs 5122 lda rd,addr(rs) ldm rd,addr,n outd @rd,@rs,ra 5123 lda rd,rs(imm16) ldps @rs outdb @rd,@rs,rba 5124 lda rd,rs(rx) ldps addr outib @rd,@rs,ra 5125 ldar rd,disp16 ldps addr(rs) outibr @rd,@rs,ra 5126 ldb @rd,imm8 ldr disp16,rs pop @rd,@rs 5127 ldb @rd,rbs ldr rd,disp16 pop addr(rd),@rs 5128 ldb addr(rd),imm8 ldrb disp16,rbs pop addr,@rs 5129 ldb addr(rd),rbs ldrb rbd,disp16 pop rd,@rs 5130 ldb addr,imm8 ldrl disp16,rrs popl @rd,@rs 5131 ldb addr,rbs ldrl rrd,disp16 popl addr(rd),@rs 5132 ldb rbd,@rs mbit popl addr,@rs 5133 ldb rbd,addr mreq rd popl rrd,@rs 5134 ldb rbd,addr(rs) mres push @rd,@rs 5135 ldb rbd,imm8 mset push @rd,addr 5136 ldb rbd,rbs mult rrd,@rs push @rd,addr(rs) 5137 ldb rbd,rs(imm16) mult rrd,addr push @rd,imm16 5138 push @rd,rs set addr,imm4 subl rrd,imm32 5139 pushl @rd,@rs set rd,imm4 subl rrd,rrs 5140 pushl @rd,addr set rd,rs tcc cc,rd 5141 pushl @rd,addr(rs) setb @rd,imm4 tccb cc,rbd 5142 pushl @rd,rrs setb addr(rd),imm4 test @rd 5143 res @rd,imm4 setb addr,imm4 test addr 5144 res addr(rd),imm4 setb rbd,imm4 test addr(rd) 5145 res addr,imm4 setb rbd,rs test rd 5146 res rd,imm4 setflg imm4 testb @rd 5147 res rd,rs sinb rbd,imm16 testb addr 5148 resb @rd,imm4 sinb rd,imm16 testb addr(rd) 5149 resb addr(rd),imm4 sind @rd,@rs,ra testb rbd 5150 resb addr,imm4 sindb @rd,@rs,rba testl @rd 5151 resb rbd,imm4 sinib @rd,@rs,ra testl addr 5152 resb rbd,rs sinibr @rd,@rs,ra testl addr(rd) 5153 resflg imm4 sla rd,imm8 testl rrd 5154 ret cc slab rbd,imm8 trdb @rd,@rs,rba 5155 rl rd,imm1or2 slal rrd,imm8 trdrb @rd,@rs,rba 5156 rlb rbd,imm1or2 sll rd,imm8 trib @rd,@rs,rbr 5157 rlc rd,imm1or2 sllb rbd,imm8 trirb @rd,@rs,rbr 5158 rlcb rbd,imm1or2 slll rrd,imm8 trtdrb @ra,@rb,rbr 5159 rldb rbb,rba sout imm16,rs trtib @ra,@rb,rr 5160 rr rd,imm1or2 soutb imm16,rbs trtirb @ra,@rb,rbr 5161 rrb rbd,imm1or2 soutd @rd,@rs,ra trtrb @ra,@rb,rbr 5162 rrc rd,imm1or2 soutdb @rd,@rs,rba tset @rd 5163 rrcb rbd,imm1or2 soutib @rd,@rs,ra tset addr 5164 rrdb rbb,rba soutibr @rd,@rs,ra tset addr(rd) 5165 rsvd36 sra rd,imm8 tset rd 5166 rsvd38 srab rbd,imm8 tsetb @rd 5167 rsvd78 sral rrd,imm8 tsetb addr 5168 rsvd7e srl rd,imm8 tsetb addr(rd) 5169 rsvd9d srlb rbd,imm8 tsetb rbd 5170 rsvd9f srll rrd,imm8 xor rd,@rs 5171 rsvdb9 sub rd,@rs xor rd,addr 5172 rsvdbf sub rd,addr xor rd,addr(rs) 5173 sbc rd,rs sub rd,addr(rs) xor rd,imm16 5174 sbcb rbd,rbs sub rd,imm16 xor rd,rs 5175 sc imm8 sub rd,rs xorb rbd,@rs 5176 sda rd,rs subb rbd,@rs xorb rbd,addr 5177 sdab rbd,rs subb rbd,addr xorb rbd,addr(rs) 5178 sdal rrd,rs subb rbd,addr(rs) xorb rbd,imm8 5179 sdl rd,rs subb rbd,imm8 xorb rbd,rbs 5180 sdlb rbd,rs subb rbd,rbs xorb rbd,rbs 5181 sdll rrd,rs subl rrd,@rs 5182 set @rd,imm4 subl rrd,addr 5183 set addr(rd),imm4 subl rrd,addr(rs) 5184 5185 5186File: as.info, Node: Vax-Dependent, Prev: Z8000-Dependent, Up: Machine Dependencies 5187 51888.32 VAX Dependent Features 5189=========================== 5190 5191* Menu: 5192 5193* VAX-Opts:: VAX Command-Line Options 5194* VAX-float:: VAX Floating Point 5195* VAX-directives:: Vax Machine Directives 5196* VAX-opcodes:: VAX Opcodes 5197* VAX-branch:: VAX Branch Improvement 5198* VAX-operands:: VAX Operands 5199* VAX-no:: Not Supported on VAX 5200 5201 5202File: as.info, Node: VAX-Opts, Next: VAX-float, Up: Vax-Dependent 5203 52048.32.1 VAX Command-Line Options 5205------------------------------- 5206 5207The Vax version of `as' accepts any of the following options, gives a 5208warning message that the option was ignored and proceeds. These 5209options are for compatibility with scripts designed for other people's 5210assemblers. 5211 5212``-D' (Debug)' 5213``-S' (Symbol Table)' 5214``-T' (Token Trace)' 5215 These are obsolete options used to debug old assemblers. 5216 5217``-d' (Displacement size for JUMPs)' 5218 This option expects a number following the `-d'. Like options 5219 that expect filenames, the number may immediately follow the `-d' 5220 (old standard) or constitute the whole of the command line 5221 argument that follows `-d' (GNU standard). 5222 5223``-V' (Virtualize Interpass Temporary File)' 5224 Some other assemblers use a temporary file. This option commanded 5225 them to keep the information in active memory rather than in a 5226 disk file. `as' always does this, so this option is redundant. 5227 5228``-J' (JUMPify Longer Branches)' 5229 Many 32-bit computers permit a variety of branch instructions to 5230 do the same job. Some of these instructions are short (and fast) 5231 but have a limited range; others are long (and slow) but can 5232 branch anywhere in virtual memory. Often there are 3 flavors of 5233 branch: short, medium and long. Some other assemblers would emit 5234 short and medium branches, unless told by this option to emit 5235 short and long branches. 5236 5237``-t' (Temporary File Directory)' 5238 Some other assemblers may use a temporary file, and this option 5239 takes a filename being the directory to site the temporary file. 5240 Since `as' does not use a temporary disk file, this option makes 5241 no difference. `-t' needs exactly one filename. 5242 5243 The Vax version of the assembler accepts additional options when 5244compiled for VMS: 5245 5246`-h N' 5247 External symbol or section (used for global variables) names are 5248 not case sensitive on VAX/VMS and always mapped to upper case. 5249 This is contrary to the C language definition which explicitly 5250 distinguishes upper and lower case. To implement a standard 5251 conforming C compiler, names must be changed (mapped) to preserve 5252 the case information. The default mapping is to convert all lower 5253 case characters to uppercase and adding an underscore followed by 5254 a 6 digit hex value, representing a 24 digit binary value. The 5255 one digits in the binary value represent which characters are 5256 uppercase in the original symbol name. 5257 5258 The `-h N' option determines how we map names. This takes several 5259 values. No `-h' switch at all allows case hacking as described 5260 above. A value of zero (`-h0') implies names should be upper 5261 case, and inhibits the case hack. A value of 2 (`-h2') implies 5262 names should be all lower case, with no case hack. A value of 3 5263 (`-h3') implies that case should be preserved. The value 1 is 5264 unused. The `-H' option directs `as' to display every mapped 5265 symbol during assembly. 5266 5267 Symbols whose names include a dollar sign `$' are exceptions to the 5268 general name mapping. These symbols are normally only used to 5269 reference VMS library names. Such symbols are always mapped to 5270 upper case. 5271 5272`-+' 5273 The `-+' option causes `as' to truncate any symbol name larger 5274 than 31 characters. The `-+' option also prevents some code 5275 following the `_main' symbol normally added to make the object 5276 file compatible with Vax-11 "C". 5277 5278`-1' 5279 This option is ignored for backward compatibility with `as' 5280 version 1.x. 5281 5282`-H' 5283 The `-H' option causes `as' to print every symbol which was 5284 changed by case mapping. 5285 5286 5287File: as.info, Node: VAX-float, Next: VAX-directives, Prev: VAX-Opts, Up: Vax-Dependent 5288 52898.32.2 VAX Floating Point 5290------------------------- 5291 5292Conversion of flonums to floating point is correct, and compatible with 5293previous assemblers. Rounding is towards zero if the remainder is 5294exactly half the least significant bit. 5295 5296 `D', `F', `G' and `H' floating point formats are understood. 5297 5298 Immediate floating literals (_e.g._ `S`$6.9') are rendered 5299correctly. Again, rounding is towards zero in the boundary case. 5300 5301 The `.float' directive produces `f' format numbers. The `.double' 5302directive produces `d' format numbers. 5303 5304 5305File: as.info, Node: VAX-directives, Next: VAX-opcodes, Prev: VAX-float, Up: Vax-Dependent 5306 53078.32.3 Vax Machine Directives 5308----------------------------- 5309 5310The Vax version of the assembler supports four directives for 5311generating Vax floating point constants. They are described in the 5312table below. 5313 5314`.dfloat' 5315 This expects zero or more flonums, separated by commas, and 5316 assembles Vax `d' format 64-bit floating point constants. 5317 5318`.ffloat' 5319 This expects zero or more flonums, separated by commas, and 5320 assembles Vax `f' format 32-bit floating point constants. 5321 5322`.gfloat' 5323 This expects zero or more flonums, separated by commas, and 5324 assembles Vax `g' format 64-bit floating point constants. 5325 5326`.hfloat' 5327 This expects zero or more flonums, separated by commas, and 5328 assembles Vax `h' format 128-bit floating point constants. 5329 5330 5331 5332File: as.info, Node: VAX-opcodes, Next: VAX-branch, Prev: VAX-directives, Up: Vax-Dependent 5333 53348.32.4 VAX Opcodes 5335------------------ 5336 5337All DEC mnemonics are supported. Beware that `case...' instructions 5338have exactly 3 operands. The dispatch table that follows the `case...' 5339instruction should be made with `.word' statements. This is compatible 5340with all unix assemblers we know of. 5341 5342 5343File: as.info, Node: VAX-branch, Next: VAX-operands, Prev: VAX-opcodes, Up: Vax-Dependent 5344 53458.32.5 VAX Branch Improvement 5346----------------------------- 5347 5348Certain pseudo opcodes are permitted. They are for branch 5349instructions. They expand to the shortest branch instruction that 5350reaches the target. Generally these mnemonics are made by substituting 5351`j' for `b' at the start of a DEC mnemonic. This feature is included 5352both for compatibility and to help compilers. If you do not need this 5353feature, avoid these opcodes. Here are the mnemonics, and the code 5354they can expand into. 5355 5356`jbsb' 5357 `Jsb' is already an instruction mnemonic, so we chose `jbsb'. 5358 (byte displacement) 5359 `bsbb ...' 5360 5361 (word displacement) 5362 `bsbw ...' 5363 5364 (long displacement) 5365 `jsb ...' 5366 5367`jbr' 5368`jr' 5369 Unconditional branch. 5370 (byte displacement) 5371 `brb ...' 5372 5373 (word displacement) 5374 `brw ...' 5375 5376 (long displacement) 5377 `jmp ...' 5378 5379`jCOND' 5380 COND may be any one of the conditional branches `neq', `nequ', 5381 `eql', `eqlu', `gtr', `geq', `lss', `gtru', `lequ', `vc', `vs', 5382 `gequ', `cc', `lssu', `cs'. COND may also be one of the bit tests 5383 `bs', `bc', `bss', `bcs', `bsc', `bcc', `bssi', `bcci', `lbs', 5384 `lbc'. NOTCOND is the opposite condition to COND. 5385 (byte displacement) 5386 `bCOND ...' 5387 5388 (word displacement) 5389 `bNOTCOND foo ; brw ... ; foo:' 5390 5391 (long displacement) 5392 `bNOTCOND foo ; jmp ... ; foo:' 5393 5394`jacbX' 5395 X may be one of `b d f g h l w'. 5396 (word displacement) 5397 `OPCODE ...' 5398 5399 (long displacement) 5400 OPCODE ..., foo ; 5401 brb bar ; 5402 foo: jmp ... ; 5403 bar: 5404 5405`jaobYYY' 5406 YYY may be one of `lss leq'. 5407 5408`jsobZZZ' 5409 ZZZ may be one of `geq gtr'. 5410 (byte displacement) 5411 `OPCODE ...' 5412 5413 (word displacement) 5414 OPCODE ..., foo ; 5415 brb bar ; 5416 foo: brw DESTINATION ; 5417 bar: 5418 5419 (long displacement) 5420 OPCODE ..., foo ; 5421 brb bar ; 5422 foo: jmp DESTINATION ; 5423 bar: 5424 5425`aobleq' 5426`aoblss' 5427`sobgeq' 5428`sobgtr' 5429 5430 (byte displacement) 5431 `OPCODE ...' 5432 5433 (word displacement) 5434 OPCODE ..., foo ; 5435 brb bar ; 5436 foo: brw DESTINATION ; 5437 bar: 5438 5439 (long displacement) 5440 OPCODE ..., foo ; 5441 brb bar ; 5442 foo: jmp DESTINATION ; 5443 bar: 5444 5445 5446File: as.info, Node: VAX-operands, Next: VAX-no, Prev: VAX-branch, Up: Vax-Dependent 5447 54488.32.6 VAX Operands 5449------------------- 5450 5451The immediate character is `$' for Unix compatibility, not `#' as DEC 5452writes it. 5453 5454 The indirect character is `*' for Unix compatibility, not `@' as DEC 5455writes it. 5456 5457 The displacement sizing character is ``' (an accent grave) for Unix 5458compatibility, not `^' as DEC writes it. The letter preceding ``' may 5459have either case. `G' is not understood, but all other letters (`b i l 5460s w') are understood. 5461 5462 Register names understood are `r0 r1 r2 ... r15 ap fp sp pc'. Upper 5463and lower case letters are equivalent. 5464 5465 For instance 5466 tstb *w`$4(r5) 5467 5468 Any expression is permitted in an operand. Operands are comma 5469separated. 5470 5471 5472File: as.info, Node: VAX-no, Prev: VAX-operands, Up: Vax-Dependent 5473 54748.32.7 Not Supported on VAX 5475--------------------------- 5476 5477Vax bit fields can not be assembled with `as'. Someone can add the 5478required code if they really need it. 5479 5480 5481File: as.info, Node: V850-Dependent, Next: Xtensa-Dependent, Prev: TIC54X-Dependent, Up: Machine Dependencies 5482 54838.33 v850 Dependent Features 5484============================ 5485 5486* Menu: 5487 5488* V850 Options:: Options 5489* V850 Syntax:: Syntax 5490* V850 Floating Point:: Floating Point 5491* V850 Directives:: V850 Machine Directives 5492* V850 Opcodes:: Opcodes 5493 5494 5495File: as.info, Node: V850 Options, Next: V850 Syntax, Up: V850-Dependent 5496 54978.33.1 Options 5498-------------- 5499 5500`as' supports the following additional command-line options for the 5501V850 processor family: 5502 5503`-wsigned_overflow' 5504 Causes warnings to be produced when signed immediate values 5505 overflow the space available for then within their opcodes. By 5506 default this option is disabled as it is possible to receive 5507 spurious warnings due to using exact bit patterns as immediate 5508 constants. 5509 5510`-wunsigned_overflow' 5511 Causes warnings to be produced when unsigned immediate values 5512 overflow the space available for then within their opcodes. By 5513 default this option is disabled as it is possible to receive 5514 spurious warnings due to using exact bit patterns as immediate 5515 constants. 5516 5517`-mv850' 5518 Specifies that the assembled code should be marked as being 5519 targeted at the V850 processor. This allows the linker to detect 5520 attempts to link such code with code assembled for other 5521 processors. 5522 5523`-mv850e' 5524 Specifies that the assembled code should be marked as being 5525 targeted at the V850E processor. This allows the linker to detect 5526 attempts to link such code with code assembled for other 5527 processors. 5528 5529`-mv850e1' 5530 Specifies that the assembled code should be marked as being 5531 targeted at the V850E1 processor. This allows the linker to 5532 detect attempts to link such code with code assembled for other 5533 processors. 5534 5535`-mv850any' 5536 Specifies that the assembled code should be marked as being 5537 targeted at the V850 processor but support instructions that are 5538 specific to the extended variants of the process. This allows the 5539 production of binaries that contain target specific code, but 5540 which are also intended to be used in a generic fashion. For 5541 example libgcc.a contains generic routines used by the code 5542 produced by GCC for all versions of the v850 architecture, 5543 together with support routines only used by the V850E architecture. 5544 5545`-mrelax' 5546 Enables relaxation. This allows the .longcall and .longjump pseudo 5547 ops to be used in the assembler source code. These ops label 5548 sections of code which are either a long function call or a long 5549 branch. The assembler will then flag these sections of code and 5550 the linker will attempt to relax them. 5551 5552 5553 5554File: as.info, Node: V850 Syntax, Next: V850 Floating Point, Prev: V850 Options, Up: V850-Dependent 5555 55568.33.2 Syntax 5557------------- 5558 5559* Menu: 5560 5561* V850-Chars:: Special Characters 5562* V850-Regs:: Register Names 5563 5564 5565File: as.info, Node: V850-Chars, Next: V850-Regs, Up: V850 Syntax 5566 55678.33.2.1 Special Characters 5568........................... 5569 5570`#' is the line comment character. 5571 5572 5573File: as.info, Node: V850-Regs, Prev: V850-Chars, Up: V850 Syntax 5574 55758.33.2.2 Register Names 5576....................... 5577 5578`as' supports the following names for registers: 5579`general register 0' 5580 r0, zero 5581 5582`general register 1' 5583 r1 5584 5585`general register 2' 5586 r2, hp 5587 5588`general register 3' 5589 r3, sp 5590 5591`general register 4' 5592 r4, gp 5593 5594`general register 5' 5595 r5, tp 5596 5597`general register 6' 5598 r6 5599 5600`general register 7' 5601 r7 5602 5603`general register 8' 5604 r8 5605 5606`general register 9' 5607 r9 5608 5609`general register 10' 5610 r10 5611 5612`general register 11' 5613 r11 5614 5615`general register 12' 5616 r12 5617 5618`general register 13' 5619 r13 5620 5621`general register 14' 5622 r14 5623 5624`general register 15' 5625 r15 5626 5627`general register 16' 5628 r16 5629 5630`general register 17' 5631 r17 5632 5633`general register 18' 5634 r18 5635 5636`general register 19' 5637 r19 5638 5639`general register 20' 5640 r20 5641 5642`general register 21' 5643 r21 5644 5645`general register 22' 5646 r22 5647 5648`general register 23' 5649 r23 5650 5651`general register 24' 5652 r24 5653 5654`general register 25' 5655 r25 5656 5657`general register 26' 5658 r26 5659 5660`general register 27' 5661 r27 5662 5663`general register 28' 5664 r28 5665 5666`general register 29' 5667 r29 5668 5669`general register 30' 5670 r30, ep 5671 5672`general register 31' 5673 r31, lp 5674 5675`system register 0' 5676 eipc 5677 5678`system register 1' 5679 eipsw 5680 5681`system register 2' 5682 fepc 5683 5684`system register 3' 5685 fepsw 5686 5687`system register 4' 5688 ecr 5689 5690`system register 5' 5691 psw 5692 5693`system register 16' 5694 ctpc 5695 5696`system register 17' 5697 ctpsw 5698 5699`system register 18' 5700 dbpc 5701 5702`system register 19' 5703 dbpsw 5704 5705`system register 20' 5706 ctbp 5707 5708 5709File: as.info, Node: V850 Floating Point, Next: V850 Directives, Prev: V850 Syntax, Up: V850-Dependent 5710 57118.33.3 Floating Point 5712--------------------- 5713 5714The V850 family uses IEEE floating-point numbers. 5715 5716 5717File: as.info, Node: V850 Directives, Next: V850 Opcodes, Prev: V850 Floating Point, Up: V850-Dependent 5718 57198.33.4 V850 Machine Directives 5720------------------------------ 5721 5722`.offset <EXPRESSION>' 5723 Moves the offset into the current section to the specified amount. 5724 5725`.section "name", <type>' 5726 This is an extension to the standard .section directive. It sets 5727 the current section to be <type> and creates an alias for this 5728 section called "name". 5729 5730`.v850' 5731 Specifies that the assembled code should be marked as being 5732 targeted at the V850 processor. This allows the linker to detect 5733 attempts to link such code with code assembled for other 5734 processors. 5735 5736`.v850e' 5737 Specifies that the assembled code should be marked as being 5738 targeted at the V850E processor. This allows the linker to detect 5739 attempts to link such code with code assembled for other 5740 processors. 5741 5742`.v850e1' 5743 Specifies that the assembled code should be marked as being 5744 targeted at the V850E1 processor. This allows the linker to 5745 detect attempts to link such code with code assembled for other 5746 processors. 5747 5748 5749 5750File: as.info, Node: V850 Opcodes, Prev: V850 Directives, Up: V850-Dependent 5751 57528.33.5 Opcodes 5753-------------- 5754 5755`as' implements all the standard V850 opcodes. 5756 5757 `as' also implements the following pseudo ops: 5758 5759`hi0()' 5760 Computes the higher 16 bits of the given expression and stores it 5761 into the immediate operand field of the given instruction. For 5762 example: 5763 5764 `mulhi hi0(here - there), r5, r6' 5765 5766 computes the difference between the address of labels 'here' and 5767 'there', takes the upper 16 bits of this difference, shifts it 5768 down 16 bits and then mutliplies it by the lower 16 bits in 5769 register 5, putting the result into register 6. 5770 5771`lo()' 5772 Computes the lower 16 bits of the given expression and stores it 5773 into the immediate operand field of the given instruction. For 5774 example: 5775 5776 `addi lo(here - there), r5, r6' 5777 5778 computes the difference between the address of labels 'here' and 5779 'there', takes the lower 16 bits of this difference and adds it to 5780 register 5, putting the result into register 6. 5781 5782`hi()' 5783 Computes the higher 16 bits of the given expression and then adds 5784 the value of the most significant bit of the lower 16 bits of the 5785 expression and stores the result into the immediate operand field 5786 of the given instruction. For example the following code can be 5787 used to compute the address of the label 'here' and store it into 5788 register 6: 5789 5790 `movhi hi(here), r0, r6' `movea lo(here), r6, r6' 5791 5792 The reason for this special behaviour is that movea performs a sign 5793 extension on its immediate operand. So for example if the address 5794 of 'here' was 0xFFFFFFFF then without the special behaviour of the 5795 hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6, 5796 then the movea instruction would takes its immediate operand, 5797 0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it 5798 into r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E). 5799 With the hi() pseudo op adding in the top bit of the lo() pseudo 5800 op, the movhi instruction actually stores 0 into r6 (0xFFFF + 1 = 5801 0x0000), so that the movea instruction stores 0xFFFFFFFF into r6 - 5802 the right value. 5803 5804`hilo()' 5805 Computes the 32 bit value of the given expression and stores it 5806 into the immediate operand field of the given instruction (which 5807 must be a mov instruction). For example: 5808 5809 `mov hilo(here), r6' 5810 5811 computes the absolute address of label 'here' and puts the result 5812 into register 6. 5813 5814`sdaoff()' 5815 Computes the offset of the named variable from the start of the 5816 Small Data Area (whoes address is held in register 4, the GP 5817 register) and stores the result as a 16 bit signed value in the 5818 immediate operand field of the given instruction. For example: 5819 5820 `ld.w sdaoff(_a_variable)[gp],r6' 5821 5822 loads the contents of the location pointed to by the label 5823 '_a_variable' into register 6, provided that the label is located 5824 somewhere within +/- 32K of the address held in the GP register. 5825 [Note the linker assumes that the GP register contains a fixed 5826 address set to the address of the label called '__gp'. This can 5827 either be set up automatically by the linker, or specifically set 5828 by using the `--defsym __gp=<value>' command line option]. 5829 5830`tdaoff()' 5831 Computes the offset of the named variable from the start of the 5832 Tiny Data Area (whoes address is held in register 30, the EP 5833 register) and stores the result as a 4,5, 7 or 8 bit unsigned 5834 value in the immediate operand field of the given instruction. 5835 For example: 5836 5837 `sld.w tdaoff(_a_variable)[ep],r6' 5838 5839 loads the contents of the location pointed to by the label 5840 '_a_variable' into register 6, provided that the label is located 5841 somewhere within +256 bytes of the address held in the EP 5842 register. [Note the linker assumes that the EP register contains 5843 a fixed address set to the address of the label called '__ep'. 5844 This can either be set up automatically by the linker, or 5845 specifically set by using the `--defsym __ep=<value>' command line 5846 option]. 5847 5848`zdaoff()' 5849 Computes the offset of the named variable from address 0 and 5850 stores the result as a 16 bit signed value in the immediate 5851 operand field of the given instruction. For example: 5852 5853 `movea zdaoff(_a_variable),zero,r6' 5854 5855 puts the address of the label '_a_variable' into register 6, 5856 assuming that the label is somewhere within the first 32K of 5857 memory. (Strictly speaking it also possible to access the last 5858 32K of memory as well, as the offsets are signed). 5859 5860`ctoff()' 5861 Computes the offset of the named variable from the start of the 5862 Call Table Area (whoes address is helg in system register 20, the 5863 CTBP register) and stores the result a 6 or 16 bit unsigned value 5864 in the immediate field of then given instruction or piece of data. 5865 For example: 5866 5867 `callt ctoff(table_func1)' 5868 5869 will put the call the function whoes address is held in the call 5870 table at the location labeled 'table_func1'. 5871 5872`.longcall `name'' 5873 Indicates that the following sequence of instructions is a long 5874 call to function `name'. The linker will attempt to shorten this 5875 call sequence if `name' is within a 22bit offset of the call. Only 5876 valid if the `-mrelax' command line switch has been enabled. 5877 5878`.longjump `name'' 5879 Indicates that the following sequence of instructions is a long 5880 jump to label `name'. The linker will attempt to shorten this code 5881 sequence if `name' is within a 22bit offset of the jump. Only 5882 valid if the `-mrelax' command line switch has been enabled. 5883 5884 5885 For information on the V850 instruction set, see `V850 Family 588632-/16-Bit single-Chip Microcontroller Architecture Manual' from NEC. 5887Ltd. 5888 5889 5890File: as.info, Node: Xtensa-Dependent, Next: Z8000-Dependent, Prev: V850-Dependent, Up: Machine Dependencies 5891 58928.34 Xtensa Dependent Features 5893============================== 5894 5895 This chapter covers features of the GNU assembler that are specific 5896to the Xtensa architecture. For details about the Xtensa instruction 5897set, please consult the `Xtensa Instruction Set Architecture (ISA) 5898Reference Manual'. 5899 5900* Menu: 5901 5902* Xtensa Options:: Command-line Options. 5903* Xtensa Syntax:: Assembler Syntax for Xtensa Processors. 5904* Xtensa Optimizations:: Assembler Optimizations. 5905* Xtensa Relaxation:: Other Automatic Transformations. 5906* Xtensa Directives:: Directives for Xtensa Processors. 5907 5908 5909File: as.info, Node: Xtensa Options, Next: Xtensa Syntax, Up: Xtensa-Dependent 5910 59118.34.1 Command Line Options 5912--------------------------- 5913 5914The Xtensa version of the GNU assembler supports these special options: 5915 5916`--text-section-literals | --no-text-section-literals' 5917 Control the treatment of literal pools. The default is 5918 `--no-text-section-literals', which places literals in a separate 5919 section in the output file. This allows the literal pool to be 5920 placed in a data RAM/ROM. With `--text-section-literals', the 5921 literals are interspersed in the text section in order to keep 5922 them as close as possible to their references. This may be 5923 necessary for large assembly files, where the literals would 5924 otherwise be out of range of the `L32R' instructions in the text 5925 section. These options only affect literals referenced via 5926 PC-relative `L32R' instructions; literals for absolute mode `L32R' 5927 instructions are handled separately. 5928 5929`--absolute-literals | --no-absolute-literals' 5930 Indicate to the assembler whether `L32R' instructions use absolute 5931 or PC-relative addressing. If the processor includes the absolute 5932 addressing option, the default is to use absolute `L32R' 5933 relocations. Otherwise, only the PC-relative `L32R' relocations 5934 can be used. 5935 5936`--target-align | --no-target-align' 5937 Enable or disable automatic alignment to reduce branch penalties 5938 at some expense in code size. *Note Automatic Instruction 5939 Alignment: Xtensa Automatic Alignment. This optimization is 5940 enabled by default. Note that the assembler will always align 5941 instructions like `LOOP' that have fixed alignment requirements. 5942 5943`--longcalls | --no-longcalls' 5944 Enable or disable transformation of call instructions to allow 5945 calls across a greater range of addresses. *Note Function Call 5946 Relaxation: Xtensa Call Relaxation. This option should be used 5947 when call targets can potentially be out of range. It may degrade 5948 both code size and performance, but the linker can generally 5949 optimize away the unnecessary overhead when a call ends up within 5950 range. The default is `--no-longcalls'. 5951 5952`--transform | --no-transform' 5953 Enable or disable all assembler transformations of Xtensa 5954 instructions, including both relaxation and optimization. The 5955 default is `--transform'; `--no-transform' should only be used in 5956 the rare cases when the instructions must be exactly as specified 5957 in the assembly source. Using `--no-transform' causes out of range 5958 instruction operands to be errors. 5959 5960`--rename-section OLDNAME=NEWNAME' 5961 Rename the OLDNAME section to NEWNAME. This option can be used 5962 multiple times to rename multiple sections. 5963 5964 5965File: as.info, Node: Xtensa Syntax, Next: Xtensa Optimizations, Prev: Xtensa Options, Up: Xtensa-Dependent 5966 59678.34.2 Assembler Syntax 5968----------------------- 5969 5970Block comments are delimited by `/*' and `*/'. End of line comments 5971may be introduced with either `#' or `//'. 5972 5973 Instructions consist of a leading opcode or macro name followed by 5974whitespace and an optional comma-separated list of operands: 5975 5976 OPCODE [OPERAND, ...] 5977 5978 Instructions must be separated by a newline or semicolon. 5979 5980 FLIX instructions, which bundle multiple opcodes together in a single 5981instruction, are specified by enclosing the bundled opcodes inside 5982braces: 5983 5984 { 5985 [FORMAT] 5986 OPCODE0 [OPERANDS] 5987 OPCODE1 [OPERANDS] 5988 OPCODE2 [OPERANDS] 5989 ... 5990 } 5991 5992 The opcodes in a FLIX instruction are listed in the same order as the 5993corresponding instruction slots in the TIE format declaration. 5994Directives and labels are not allowed inside the braces of a FLIX 5995instruction. A particular TIE format name can optionally be specified 5996immediately after the opening brace, but this is usually unnecessary. 5997The assembler will automatically search for a format that can encode the 5998specified opcodes, so the format name need only be specified in rare 5999cases where there is more than one applicable format and where it 6000matters which of those formats is used. A FLIX instruction can also be 6001specified on a single line by separating the opcodes with semicolons: 6002 6003 { [FORMAT;] OPCODE0 [OPERANDS]; OPCODE1 [OPERANDS]; OPCODE2 [OPERANDS]; ... } 6004 6005 The assembler can automatically bundle opcodes into FLIX 6006instructions. It encodes the opcodes in order, one at a time, choosing 6007the smallest format where each opcode can be encoded and filling unused 6008instruction slots with no-ops. 6009 6010* Menu: 6011 6012* Xtensa Opcodes:: Opcode Naming Conventions. 6013* Xtensa Registers:: Register Naming. 6014 6015 6016File: as.info, Node: Xtensa Opcodes, Next: Xtensa Registers, Up: Xtensa Syntax 6017 60188.34.2.1 Opcode Names 6019..................... 6020 6021See the `Xtensa Instruction Set Architecture (ISA) Reference Manual' 6022for a complete list of opcodes and descriptions of their semantics. 6023 6024 If an opcode name is prefixed with an underscore character (`_'), 6025`as' will not transform that instruction in any way. The underscore 6026prefix disables both optimization (*note Xtensa Optimizations: Xtensa 6027Optimizations.) and relaxation (*note Xtensa Relaxation: Xtensa 6028Relaxation.) for that particular instruction. Only use the underscore 6029prefix when it is essential to select the exact opcode produced by the 6030assembler. Using this feature unnecessarily makes the code less 6031efficient by disabling assembler optimization and less flexible by 6032disabling relaxation. 6033 6034 Note that this special handling of underscore prefixes only applies 6035to Xtensa opcodes, not to either built-in macros or user-defined macros. 6036When an underscore prefix is used with a macro (e.g., `_MOV'), it 6037refers to a different macro. The assembler generally provides built-in 6038macros both with and without the underscore prefix, where the underscore 6039versions behave as if the underscore carries through to the instructions 6040in the macros. For example, `_MOV' may expand to `_MOV.N'. 6041 6042 The underscore prefix only applies to individual instructions, not to 6043series of instructions. For example, if a series of instructions have 6044underscore prefixes, the assembler will not transform the individual 6045instructions, but it may insert other instructions between them (e.g., 6046to align a `LOOP' instruction). To prevent the assembler from 6047modifying a series of instructions as a whole, use the `no-transform' 6048directive. *Note transform: Transform Directive. 6049 6050 6051File: as.info, Node: Xtensa Registers, Prev: Xtensa Opcodes, Up: Xtensa Syntax 6052 60538.34.2.2 Register Names 6054....................... 6055 6056The assembly syntax for a register file entry is the "short" name for a 6057TIE register file followed by the index into that register file. For 6058example, the general-purpose `AR' register file has a short name of 6059`a', so these registers are named `a0'...`a15'. As a special feature, 6060`sp' is also supported as a synonym for `a1'. Additional registers may 6061be added by processor configuration options and by designer-defined TIE 6062extensions. An initial `$' character is optional in all register names. 6063 6064 6065File: as.info, Node: Xtensa Optimizations, Next: Xtensa Relaxation, Prev: Xtensa Syntax, Up: Xtensa-Dependent 6066 60678.34.3 Xtensa Optimizations 6068--------------------------- 6069 6070The optimizations currently supported by `as' are generation of density 6071instructions where appropriate and automatic branch target alignment. 6072 6073* Menu: 6074 6075* Density Instructions:: Using Density Instructions. 6076* Xtensa Automatic Alignment:: Automatic Instruction Alignment. 6077 6078 6079File: as.info, Node: Density Instructions, Next: Xtensa Automatic Alignment, Up: Xtensa Optimizations 6080 60818.34.3.1 Using Density Instructions 6082................................... 6083 6084The Xtensa instruction set has a code density option that provides 608516-bit versions of some of the most commonly used opcodes. Use of these 6086opcodes can significantly reduce code size. When possible, the 6087assembler automatically translates instructions from the core Xtensa 6088instruction set into equivalent instructions from the Xtensa code 6089density option. This translation can be disabled by using underscore 6090prefixes (*note Opcode Names: Xtensa Opcodes.), by using the 6091`--no-transform' command-line option (*note Command Line Options: 6092Xtensa Options.), or by using the `no-transform' directive (*note 6093transform: Transform Directive.). 6094 6095 It is a good idea _not_ to use the density instructions directly. 6096The assembler will automatically select dense instructions where 6097possible. If you later need to use an Xtensa processor without the code 6098density option, the same assembly code will then work without 6099modification. 6100 6101 6102File: as.info, Node: Xtensa Automatic Alignment, Prev: Density Instructions, Up: Xtensa Optimizations 6103 61048.34.3.2 Automatic Instruction Alignment 6105........................................ 6106 6107The Xtensa assembler will automatically align certain instructions, both 6108to optimize performance and to satisfy architectural requirements. 6109 6110 As an optimization to improve performance, the assembler attempts to 6111align branch targets so they do not cross instruction fetch boundaries. 6112(Xtensa processors can be configured with either 32-bit or 64-bit 6113instruction fetch widths.) An instruction immediately following a call 6114is treated as a branch target in this context, because it will be the 6115target of a return from the call. This alignment has the potential to 6116reduce branch penalties at some expense in code size. The assembler 6117will not attempt to align labels with the prefixes `.Ln' and `.LM', 6118since these labels are used for debugging information and are not 6119typically branch targets. This optimization is enabled by default. 6120You can disable it with the `--no-target-align' command-line option 6121(*note Command Line Options: Xtensa Options.). 6122 6123 The target alignment optimization is done without adding instructions 6124that could increase the execution time of the program. If there are 6125density instructions in the code preceding a target, the assembler can 6126change the target alignment by widening some of those instructions to 6127the equivalent 24-bit instructions. Extra bytes of padding can be 6128inserted immediately following unconditional jump and return 6129instructions. This approach is usually successful in aligning many, 6130but not all, branch targets. 6131 6132 The `LOOP' family of instructions must be aligned such that the 6133first instruction in the loop body does not cross an instruction fetch 6134boundary (e.g., with a 32-bit fetch width, a `LOOP' instruction must be 6135on either a 1 or 2 mod 4 byte boundary). The assembler knows about 6136this restriction and inserts the minimal number of 2 or 3 byte no-op 6137instructions to satisfy it. When no-op instructions are added, any 6138label immediately preceding the original loop will be moved in order to 6139refer to the loop instruction, not the newly generated no-op 6140instruction. To preserve binary compatibility across processors with 6141different fetch widths, the assembler conservatively assumes a 32-bit 6142fetch width when aligning `LOOP' instructions (except if the first 6143instruction in the loop is a 64-bit instruction). 6144 6145 Similarly, the `ENTRY' instruction must be aligned on a 0 mod 4 byte 6146boundary. The assembler satisfies this requirement by inserting zero 6147bytes when required. In addition, labels immediately preceding the 6148`ENTRY' instruction will be moved to the newly aligned instruction 6149location. 6150 6151 6152File: as.info, Node: Xtensa Relaxation, Next: Xtensa Directives, Prev: Xtensa Optimizations, Up: Xtensa-Dependent 6153 61548.34.4 Xtensa Relaxation 6155------------------------ 6156 6157When an instruction operand is outside the range allowed for that 6158particular instruction field, `as' can transform the code to use a 6159functionally-equivalent instruction or sequence of instructions. This 6160process is known as "relaxation". This is typically done for branch 6161instructions because the distance of the branch targets is not known 6162until assembly-time. The Xtensa assembler offers branch relaxation and 6163also extends this concept to function calls, `MOVI' instructions and 6164other instructions with immediate fields. 6165 6166* Menu: 6167 6168* Xtensa Branch Relaxation:: Relaxation of Branches. 6169* Xtensa Call Relaxation:: Relaxation of Function Calls. 6170* Xtensa Immediate Relaxation:: Relaxation of other Immediate Fields. 6171 6172 6173File: as.info, Node: Xtensa Branch Relaxation, Next: Xtensa Call Relaxation, Up: Xtensa Relaxation 6174 61758.34.4.1 Conditional Branch Relaxation 6176...................................... 6177 6178When the target of a branch is too far away from the branch itself, 6179i.e., when the offset from the branch to the target is too large to fit 6180in the immediate field of the branch instruction, it may be necessary to 6181replace the branch with a branch around a jump. For example, 6182 6183 beqz a2, L 6184 6185 may result in: 6186 6187 bnez.n a2, M 6188 j L 6189 M: 6190 6191 (The `BNEZ.N' instruction would be used in this example only if the 6192density option is available. Otherwise, `BNEZ' would be used.) 6193 6194 This relaxation works well because the unconditional jump instruction 6195has a much larger offset range than the various conditional branches. 6196However, an error will occur if a branch target is beyond the range of a 6197jump instruction. `as' cannot relax unconditional jumps. Similarly, 6198an error will occur if the original input contains an unconditional 6199jump to a target that is out of range. 6200 6201 Branch relaxation is enabled by default. It can be disabled by using 6202underscore prefixes (*note Opcode Names: Xtensa Opcodes.), the 6203`--no-transform' command-line option (*note Command Line Options: 6204Xtensa Options.), or the `no-transform' directive (*note transform: 6205Transform Directive.). 6206 6207 6208File: as.info, Node: Xtensa Call Relaxation, Next: Xtensa Immediate Relaxation, Prev: Xtensa Branch Relaxation, Up: Xtensa Relaxation 6209 62108.34.4.2 Function Call Relaxation 6211................................. 6212 6213Function calls may require relaxation because the Xtensa immediate call 6214instructions (`CALL0', `CALL4', `CALL8' and `CALL12') provide a 6215PC-relative offset of only 512 Kbytes in either direction. For larger 6216programs, it may be necessary to use indirect calls (`CALLX0', 6217`CALLX4', `CALLX8' and `CALLX12') where the target address is specified 6218in a register. The Xtensa assembler can automatically relax immediate 6219call instructions into indirect call instructions. This relaxation is 6220done by loading the address of the called function into the callee's 6221return address register and then using a `CALLX' instruction. So, for 6222example: 6223 6224 call8 func 6225 6226 might be relaxed to: 6227 6228 .literal .L1, func 6229 l32r a8, .L1 6230 callx8 a8 6231 6232 Because the addresses of targets of function calls are not generally 6233known until link-time, the assembler must assume the worst and relax all 6234the calls to functions in other source files, not just those that really 6235will be out of range. The linker can recognize calls that were 6236unnecessarily relaxed, and it will remove the overhead introduced by the 6237assembler for those cases where direct calls are sufficient. 6238 6239 Call relaxation is disabled by default because it can have a negative 6240effect on both code size and performance, although the linker can 6241usually eliminate the unnecessary overhead. If a program is too large 6242and some of the calls are out of range, function call relaxation can be 6243enabled using the `--longcalls' command-line option or the `longcalls' 6244directive (*note longcalls: Longcalls Directive.). 6245 6246 6247File: as.info, Node: Xtensa Immediate Relaxation, Prev: Xtensa Call Relaxation, Up: Xtensa Relaxation 6248 62498.34.4.3 Other Immediate Field Relaxation 6250......................................... 6251 6252The assembler normally performs the following other relaxations. They 6253can be disabled by using underscore prefixes (*note Opcode Names: 6254Xtensa Opcodes.), the `--no-transform' command-line option (*note 6255Command Line Options: Xtensa Options.), or the `no-transform' directive 6256(*note transform: Transform Directive.). 6257 6258 The `MOVI' machine instruction can only materialize values in the 6259range from -2048 to 2047. Values outside this range are best 6260materialized with `L32R' instructions. Thus: 6261 6262 movi a0, 100000 6263 6264 is assembled into the following machine code: 6265 6266 .literal .L1, 100000 6267 l32r a0, .L1 6268 6269 The `L8UI' machine instruction can only be used with immediate 6270offsets in the range from 0 to 255. The `L16SI' and `L16UI' machine 6271instructions can only be used with offsets from 0 to 510. The `L32I' 6272machine instruction can only be used with offsets from 0 to 1020. A 6273load offset outside these ranges can be materalized with an `L32R' 6274instruction if the destination register of the load is different than 6275the source address register. For example: 6276 6277 l32i a1, a0, 2040 6278 6279 is translated to: 6280 6281 .literal .L1, 2040 6282 l32r a1, .L1 6283 addi a1, a0, a1 6284 l32i a1, a1, 0 6285 6286If the load destination and source address register are the same, an 6287out-of-range offset causes an error. 6288 6289 The Xtensa `ADDI' instruction only allows immediate operands in the 6290range from -128 to 127. There are a number of alternate instruction 6291sequences for the `ADDI' operation. First, if the immediate is 0, the 6292`ADDI' will be turned into a `MOV.N' instruction (or the equivalent 6293`OR' instruction if the code density option is not available). If the 6294`ADDI' immediate is outside of the range -128 to 127, but inside the 6295range -32896 to 32639, an `ADDMI' instruction or `ADDMI'/`ADDI' 6296sequence will be used. Finally, if the immediate is outside of this 6297range and a free register is available, an `L32R'/`ADD' sequence will 6298be used with a literal allocated from the literal pool. 6299 6300 For example: 6301 6302 addi a5, a6, 0 6303 addi a5, a6, 512 6304 addi a5, a6, 513 6305 addi a5, a6, 50000 6306 6307 is assembled into the following: 6308 6309 .literal .L1, 50000 6310 mov.n a5, a6 6311 addmi a5, a6, 0x200 6312 addmi a5, a6, 0x200 6313 addi a5, a5, 1 6314 l32r a5, .L1 6315 add a5, a6, a5 6316 6317 6318File: as.info, Node: Xtensa Directives, Prev: Xtensa Relaxation, Up: Xtensa-Dependent 6319 63208.34.5 Directives 6321----------------- 6322 6323The Xtensa assember supports a region-based directive syntax: 6324 6325 .begin DIRECTIVE [OPTIONS] 6326 ... 6327 .end DIRECTIVE 6328 6329 All the Xtensa-specific directives that apply to a region of code use 6330this syntax. 6331 6332 The directive applies to code between the `.begin' and the `.end'. 6333The state of the option after the `.end' reverts to what it was before 6334the `.begin'. A nested `.begin'/`.end' region can further change the 6335state of the directive without having to be aware of its outer state. 6336For example, consider: 6337 6338 .begin no-transform 6339 L: add a0, a1, a2 6340 .begin transform 6341 M: add a0, a1, a2 6342 .end transform 6343 N: add a0, a1, a2 6344 .end no-transform 6345 6346 The `ADD' opcodes at `L' and `N' in the outer `no-transform' region 6347both result in `ADD' machine instructions, but the assembler selects an 6348`ADD.N' instruction for the `ADD' at `M' in the inner `transform' 6349region. 6350 6351 The advantage of this style is that it works well inside macros 6352which can preserve the context of their callers. 6353 6354 The following directives are available: 6355 6356* Menu: 6357 6358* Schedule Directive:: Enable instruction scheduling. 6359* Longcalls Directive:: Use Indirect Calls for Greater Range. 6360* Transform Directive:: Disable All Assembler Transformations. 6361* Literal Directive:: Intermix Literals with Instructions. 6362* Literal Position Directive:: Specify Inline Literal Pool Locations. 6363* Literal Prefix Directive:: Specify Literal Section Name Prefix. 6364* Absolute Literals Directive:: Control PC-Relative vs. Absolute Literals. 6365 6366 6367File: as.info, Node: Schedule Directive, Next: Longcalls Directive, Up: Xtensa Directives 6368 63698.34.5.1 schedule 6370................. 6371 6372The `schedule' directive is recognized only for compatibility with 6373Tensilica's assembler. 6374 6375 .begin [no-]schedule 6376 .end [no-]schedule 6377 6378 This directive is ignored and has no effect on `as'. 6379 6380 6381File: as.info, Node: Longcalls Directive, Next: Transform Directive, Prev: Schedule Directive, Up: Xtensa Directives 6382 63838.34.5.2 longcalls 6384.................. 6385 6386The `longcalls' directive enables or disables function call relaxation. 6387*Note Function Call Relaxation: Xtensa Call Relaxation. 6388 6389 .begin [no-]longcalls 6390 .end [no-]longcalls 6391 6392 Call relaxation is disabled by default unless the `--longcalls' 6393command-line option is specified. The `longcalls' directive overrides 6394the default determined by the command-line options. 6395 6396 6397File: as.info, Node: Transform Directive, Next: Literal Directive, Prev: Longcalls Directive, Up: Xtensa Directives 6398 63998.34.5.3 transform 6400.................. 6401 6402This directive enables or disables all assembler transformation, 6403including relaxation (*note Xtensa Relaxation: Xtensa Relaxation.) and 6404optimization (*note Xtensa Optimizations: Xtensa Optimizations.). 6405 6406 .begin [no-]transform 6407 .end [no-]transform 6408 6409 Transformations are enabled by default unless the `--no-transform' 6410option is used. The `transform' directive overrides the default 6411determined by the command-line options. An underscore opcode prefix, 6412disabling transformation of that opcode, always takes precedence over 6413both directives and command-line flags. 6414 6415 6416File: as.info, Node: Literal Directive, Next: Literal Position Directive, Prev: Transform Directive, Up: Xtensa Directives 6417 64188.34.5.4 literal 6419................ 6420 6421The `.literal' directive is used to define literal pool data, i.e., 6422read-only 32-bit data accessed via `L32R' instructions. 6423 6424 .literal LABEL, VALUE[, VALUE...] 6425 6426 This directive is similar to the standard `.word' directive, except 6427that the actual location of the literal data is determined by the 6428assembler and linker, not by the position of the `.literal' directive. 6429Using this directive gives the assembler freedom to locate the literal 6430data in the most appropriate place and possibly to combine identical 6431literals. For example, the code: 6432 6433 entry sp, 40 6434 .literal .L1, sym 6435 l32r a4, .L1 6436 6437 can be used to load a pointer to the symbol `sym' into register 6438`a4'. The value of `sym' will not be placed between the `ENTRY' and 6439`L32R' instructions; instead, the assembler puts the data in a literal 6440pool. 6441 6442 Literal pools for absolute mode `L32R' instructions (*note Absolute 6443Literals Directive::) are placed in a seperate `.lit4' section. By 6444default literal pools for PC-relative mode `L32R' instructions are 6445placed in a separate `.literal' section; however, when using the 6446`--text-section-literals' option (*note Command Line Options: Xtensa 6447Options.), the literal pools are placed in the current section. These 6448text section literal pools are created automatically before `ENTRY' 6449instructions and manually after `.literal_position' directives (*note 6450literal_position: Literal Position Directive.). If there are no 6451preceding `ENTRY' instructions, explicit `.literal_position' directives 6452must be used to place the text section literal pools; otherwise, `as' 6453will report an error. 6454 6455 6456File: as.info, Node: Literal Position Directive, Next: Literal Prefix Directive, Prev: Literal Directive, Up: Xtensa Directives 6457 64588.34.5.5 literal_position 6459......................... 6460 6461When using `--text-section-literals' to place literals inline in the 6462section being assembled, the `.literal_position' directive can be used 6463to mark a potential location for a literal pool. 6464 6465 .literal_position 6466 6467 The `.literal_position' directive is ignored when the 6468`--text-section-literals' option is not used or when `L32R' 6469instructions use the absolute addressing mode. 6470 6471 The assembler will automatically place text section literal pools 6472before `ENTRY' instructions, so the `.literal_position' directive is 6473only needed to specify some other location for a literal pool. You may 6474need to add an explicit jump instruction to skip over an inline literal 6475pool. 6476 6477 For example, an interrupt vector does not begin with an `ENTRY' 6478instruction so the assembler will be unable to automatically find a good 6479place to put a literal pool. Moreover, the code for the interrupt 6480vector must be at a specific starting address, so the literal pool 6481cannot come before the start of the code. The literal pool for the 6482vector must be explicitly positioned in the middle of the vector (before 6483any uses of the literals, due to the negative offsets used by 6484PC-relative `L32R' instructions). The `.literal_position' directive 6485can be used to do this. In the following code, the literal for `M' 6486will automatically be aligned correctly and is placed after the 6487unconditional jump. 6488 6489 .global M 6490 code_start: 6491 j continue 6492 .literal_position 6493 .align 4 6494 continue: 6495 movi a4, M 6496 6497 6498File: as.info, Node: Literal Prefix Directive, Next: Absolute Literals Directive, Prev: Literal Position Directive, Up: Xtensa Directives 6499 65008.34.5.6 literal_prefix 6501....................... 6502 6503The `literal_prefix' directive allows you to specify different sections 6504to hold literals from different portions of an assembly file. With 6505this directive, a single assembly file can be used to generate code 6506into multiple sections, including literals generated by the assembler. 6507 6508 .begin literal_prefix [NAME] 6509 .end literal_prefix 6510 6511 By default the assembler places literal pools in sections separate 6512from the instructions, using the default literal section names of 6513`.literal' for PC-relative mode `L32R' instructions and `.lit4' for 6514absolute mode `L32R' instructions (*note Absolute Literals 6515Directive::). The `literal_prefix' directive causes different literal 6516sections to be used for the code inside the delimited region. The new 6517literal sections are determined by including NAME as a prefix to the 6518default literal section names. If the NAME argument is omitted, the 6519literal sections revert to the defaults. This directive has no effect 6520when using the `--text-section-literals' option (*note Command Line 6521Options: Xtensa Options.). 6522 6523 Except for two special cases, the assembler determines the new 6524literal sections by simply prepending NAME to the default section names, 6525resulting in `NAME.literal' and `NAME.lit4' sections. The 6526`literal_prefix' directive is often used with the name of the current 6527text section as the prefix argument. To facilitate this usage, the 6528assembler uses special case rules when it recognizes NAME as a text 6529section name. First, if NAME ends with `.text', that suffix is not 6530included in the literal section name. For example, if NAME is 6531`.iram0.text', then the literal sections will be `.iram0.literal' and 6532`.iram0.lit4'. Second, if NAME begins with `.gnu.linkonce.t.', then 6533the literal section names are formed by replacing the `.t' substring 6534with `.literal' and `.lit4'. For example, if NAME is 6535`.gnu.linkonce.t.func', the literal sections will be 6536`.gnu.linkonce.literal.func' and `.gnu.linkonce.lit4.func'. 6537 6538 6539File: as.info, Node: Absolute Literals Directive, Prev: Literal Prefix Directive, Up: Xtensa Directives 6540 65418.34.5.7 absolute-literals 6542.......................... 6543 6544The `absolute-literals' and `no-absolute-literals' directives control 6545the absolute vs. PC-relative mode for `L32R' instructions. These are 6546relevant only for Xtensa configurations that include the absolute 6547addressing option for `L32R' instructions. 6548 6549 .begin [no-]absolute-literals 6550 .end [no-]absolute-literals 6551 6552 These directives do not change the `L32R' mode--they only cause the 6553assembler to emit the appropriate kind of relocation for `L32R' 6554instructions and to place the literal values in the appropriate section. 6555To change the `L32R' mode, the program must write the `LITBASE' special 6556register. It is the programmer's responsibility to keep track of the 6557mode and indicate to the assembler which mode is used in each region of 6558code. 6559 6560 If the Xtensa configuration includes the absolute `L32R' addressing 6561option, the default is to assume absolute `L32R' addressing unless the 6562`--no-absolute-literals' command-line option is specified. Otherwise, 6563the default is to assume PC-relative `L32R' addressing. The 6564`absolute-literals' directive can then be used to override the default 6565determined by the command-line options. 6566 6567 6568File: as.info, Node: Reporting Bugs, Next: Acknowledgements, Prev: Machine Dependencies, Up: Top 6569 65709 Reporting Bugs 6571**************** 6572 6573Your bug reports play an essential role in making `as' reliable. 6574 6575 Reporting a bug may help you by bringing a solution to your problem, 6576or it may not. But in any case the principal function of a bug report 6577is to help the entire community by making the next version of `as' work 6578better. Bug reports are your contribution to the maintenance of `as'. 6579 6580 In order for a bug report to serve its purpose, you must include the 6581information that enables us to fix the bug. 6582 6583* Menu: 6584 6585* Bug Criteria:: Have you found a bug? 6586* Bug Reporting:: How to report bugs 6587 6588 6589File: as.info, Node: Bug Criteria, Next: Bug Reporting, Up: Reporting Bugs 6590 65919.1 Have You Found a Bug? 6592========================= 6593 6594If you are not sure whether you have found a bug, here are some 6595guidelines: 6596 6597 * If the assembler gets a fatal signal, for any input whatever, that 6598 is a `as' bug. Reliable assemblers never crash. 6599 6600 * If `as' produces an error message for valid input, that is a bug. 6601 6602 * If `as' does not produce an error message for invalid input, that 6603 is a bug. However, you should note that your idea of "invalid 6604 input" might be our idea of "an extension" or "support for 6605 traditional practice". 6606 6607 * If you are an experienced user of assemblers, your suggestions for 6608 improvement of `as' are welcome in any case. 6609 6610 6611File: as.info, Node: Bug Reporting, Prev: Bug Criteria, Up: Reporting Bugs 6612 66139.2 How to Report Bugs 6614====================== 6615 6616A number of companies and individuals offer support for GNU products. 6617If you obtained `as' from a support organization, we recommend you 6618contact that organization first. 6619 6620 You can find contact information for many support companies and 6621individuals in the file `etc/SERVICE' in the GNU Emacs distribution. 6622 6623 In any event, we also recommend that you send bug reports for `as' 6624to `bug-binutils@gnu.org'. 6625 6626 The fundamental principle of reporting bugs usefully is this: 6627*report all the facts*. If you are not sure whether to state a fact or 6628leave it out, state it! 6629 6630 Often people omit facts because they think they know what causes the 6631problem and assume that some details do not matter. Thus, you might 6632assume that the name of a symbol you use in an example does not matter. 6633Well, probably it does not, but one cannot be sure. Perhaps the bug 6634is a stray memory reference which happens to fetch from the location 6635where that name is stored in memory; perhaps, if the name were 6636different, the contents of that location would fool the assembler into 6637doing the right thing despite the bug. Play it safe and give a 6638specific, complete example. That is the easiest thing for you to do, 6639and the most helpful. 6640 6641 Keep in mind that the purpose of a bug report is to enable us to fix 6642the bug if it is new to us. Therefore, always write your bug reports 6643on the assumption that the bug has not been reported previously. 6644 6645 Sometimes people give a few sketchy facts and ask, "Does this ring a 6646bell?" This cannot help us fix a bug, so it is basically useless. We 6647respond by asking for enough details to enable us to investigate. You 6648might as well expedite matters by sending them to begin with. 6649 6650 To enable us to fix the bug, you should include all these things: 6651 6652 * The version of `as'. `as' announces it if you start it with the 6653 `--version' argument. 6654 6655 Without this, we will not know whether there is any point in 6656 looking for the bug in the current version of `as'. 6657 6658 * Any patches you may have applied to the `as' source. 6659 6660 * The type of machine you are using, and the operating system name 6661 and version number. 6662 6663 * What compiler (and its version) was used to compile `as'--e.g. 6664 "`gcc-2.7'". 6665 6666 * The command arguments you gave the assembler to assemble your 6667 example and observe the bug. To guarantee you will not omit 6668 something important, list them all. A copy of the Makefile (or 6669 the output from make) is sufficient. 6670 6671 If we were to try to guess the arguments, we would probably guess 6672 wrong and then we might not encounter the bug. 6673 6674 * A complete input file that will reproduce the bug. If the bug is 6675 observed when the assembler is invoked via a compiler, send the 6676 assembler source, not the high level language source. Most 6677 compilers will produce the assembler source when run with the `-S' 6678 option. If you are using `gcc', use the options `-v 6679 --save-temps'; this will save the assembler source in a file with 6680 an extension of `.s', and also show you exactly how `as' is being 6681 run. 6682 6683 * A description of what behavior you observe that you believe is 6684 incorrect. For example, "It gets a fatal signal." 6685 6686 Of course, if the bug is that `as' gets a fatal signal, then we 6687 will certainly notice it. But if the bug is incorrect output, we 6688 might not notice unless it is glaringly wrong. You might as well 6689 not give us a chance to make a mistake. 6690 6691 Even if the problem you experience is a fatal signal, you should 6692 still say so explicitly. Suppose something strange is going on, 6693 such as, your copy of `as' is out of synch, or you have 6694 encountered a bug in the C library on your system. (This has 6695 happened!) Your copy might crash and ours would not. If you told 6696 us to expect a crash, then when ours fails to crash, we would know 6697 that the bug was not happening for us. If you had not told us to 6698 expect a crash, then we would not be able to draw any conclusion 6699 from our observations. 6700 6701 * If you wish to suggest changes to the `as' source, send us context 6702 diffs, as generated by `diff' with the `-u', `-c', or `-p' option. 6703 Always send diffs from the old file to the new file. If you even 6704 discuss something in the `as' source, refer to it by context, not 6705 by line number. 6706 6707 The line numbers in our development sources will not match those 6708 in your sources. Your line numbers would convey no useful 6709 information to us. 6710 6711 Here are some things that are not necessary: 6712 6713 * A description of the envelope of the bug. 6714 6715 Often people who encounter a bug spend a lot of time investigating 6716 which changes to the input file will make the bug go away and which 6717 changes will not affect it. 6718 6719 This is often time consuming and not very useful, because the way 6720 we will find the bug is by running a single example under the 6721 debugger with breakpoints, not by pure deduction from a series of 6722 examples. We recommend that you save your time for something else. 6723 6724 Of course, if you can find a simpler example to report _instead_ 6725 of the original one, that is a convenience for us. Errors in the 6726 output will be easier to spot, running under the debugger will take 6727 less time, and so on. 6728 6729 However, simplification is not vital; if you do not want to do 6730 this, report the bug anyway and send us the entire test case you 6731 used. 6732 6733 * A patch for the bug. 6734 6735 A patch for the bug does help us if it is a good one. But do not 6736 omit the necessary information, such as the test case, on the 6737 assumption that a patch is all we need. We might see problems 6738 with your patch and decide to fix the problem another way, or we 6739 might not understand it at all. 6740 6741 Sometimes with a program as complicated as `as' it is very hard to 6742 construct an example that will make the program follow a certain 6743 path through the code. If you do not send us the example, we will 6744 not be able to construct one, so we will not be able to verify 6745 that the bug is fixed. 6746 6747 And if we cannot understand what bug you are trying to fix, or why 6748 your patch should be an improvement, we will not install it. A 6749 test case will help us to understand. 6750 6751 * A guess about what the bug is or what it depends on. 6752 6753 Such guesses are usually wrong. Even we cannot guess right about 6754 such things without first using the debugger to find the facts. 6755 6756 6757File: as.info, Node: Acknowledgements, Next: GNU Free Documentation License, Prev: Reporting Bugs, Up: Top 6758 675910 Acknowledgements 6760******************* 6761 6762If you have contributed to GAS and your name isn't listed here, it is 6763not meant as a slight. We just don't know about it. Send mail to the 6764maintainer, and we'll correct the situation. Currently the maintainer 6765is Ken Raeburn (email address `raeburn@cygnus.com'). 6766 6767 Dean Elsner wrote the original GNU assembler for the VAX.(1) 6768 6769 Jay Fenlason maintained GAS for a while, adding support for 6770GDB-specific debug information and the 68k series machines, most of the 6771preprocessing pass, and extensive changes in `messages.c', 6772`input-file.c', `write.c'. 6773 6774 K. Richard Pixley maintained GAS for a while, adding various 6775enhancements and many bug fixes, including merging support for several 6776processors, breaking GAS up to handle multiple object file format back 6777ends (including heavy rewrite, testing, an integration of the coff and 6778b.out back ends), adding configuration including heavy testing and 6779verification of cross assemblers and file splits and renaming, 6780converted GAS to strictly ANSI C including full prototypes, added 6781support for m680[34]0 and cpu32, did considerable work on i960 6782including a COFF port (including considerable amounts of reverse 6783engineering), a SPARC opcode file rewrite, DECstation, rs6000, and 6784hp300hpux host ports, updated "know" assertions and made them work, 6785much other reorganization, cleanup, and lint. 6786 6787 Ken Raeburn wrote the high-level BFD interface code to replace most 6788of the code in format-specific I/O modules. 6789 6790 The original VMS support was contributed by David L. Kashtan. Eric 6791Youngdale has done much work with it since. 6792 6793 The Intel 80386 machine description was written by Eliot Dresselhaus. 6794 6795 Minh Tran-Le at IntelliCorp contributed some AIX 386 support. 6796 6797 The Motorola 88k machine description was contributed by Devon Bowen 6798of Buffalo University and Torbjorn Granlund of the Swedish Institute of 6799Computer Science. 6800 6801 Keith Knowles at the Open Software Foundation wrote the original 6802MIPS back end (`tc-mips.c', `tc-mips.h'), and contributed Rose format 6803support (which hasn't been merged in yet). Ralph Campbell worked with 6804the MIPS code to support a.out format. 6805 6806 Support for the Zilog Z8k and Renesas H8/300 and H8/500 processors 6807(tc-z8k, tc-h8300, tc-h8500), and IEEE 695 object file format 6808(obj-ieee), was written by Steve Chamberlain of Cygnus Support. Steve 6809also modified the COFF back end to use BFD for some low-level 6810operations, for use with the H8/300 and AMD 29k targets. 6811 6812 John Gilmore built the AMD 29000 support, added `.include' support, 6813and simplified the configuration of which versions accept which 6814directives. He updated the 68k machine description so that Motorola's 6815opcodes always produced fixed-size instructions (e.g., `jsr'), while 6816synthetic instructions remained shrinkable (`jbsr'). John fixed many 6817bugs, including true tested cross-compilation support, and one bug in 6818relaxation that took a week and required the proverbial one-bit fix. 6819 6820 Ian Lance Taylor of Cygnus Support merged the Motorola and MIT 6821syntax for the 68k, completed support for some COFF targets (68k, i386 6822SVR3, and SCO Unix), added support for MIPS ECOFF and ELF targets, 6823wrote the initial RS/6000 and PowerPC assembler, and made a few other 6824minor patches. 6825 6826 Steve Chamberlain made GAS able to generate listings. 6827 6828 Hewlett-Packard contributed support for the HP9000/300. 6829 6830 Jeff Law wrote GAS and BFD support for the native HPPA object format 6831(SOM) along with a fairly extensive HPPA testsuite (for both SOM and 6832ELF object formats). This work was supported by both the Center for 6833Software Science at the University of Utah and Cygnus Support. 6834 6835 Support for ELF format files has been worked on by Mark Eichin of 6836Cygnus Support (original, incomplete implementation for SPARC), Pete 6837Hoogenboom and Jeff Law at the University of Utah (HPPA mainly), 6838Michael Meissner of the Open Software Foundation (i386 mainly), and Ken 6839Raeburn of Cygnus Support (sparc, and some initial 64-bit support). 6840 6841 Linas Vepstas added GAS support for the ESA/390 "IBM 370" 6842architecture. 6843 6844 Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote 6845GAS and BFD support for openVMS/Alpha. 6846 6847 Timothy Wall, Michael Hayes, and Greg Smart contributed to the 6848various tic* flavors. 6849 6850 David Heine, Sterling Augustine, Bob Wilson and John Ruttenberg from 6851Tensilica, Inc. added support for Xtensa processors. 6852 6853 Several engineers at Cygnus Support have also provided many small 6854bug fixes and configuration enhancements. 6855 6856 Many others have contributed large or small bugfixes and 6857enhancements. If you have contributed significant work and are not 6858mentioned on this list, and want to be, let us know. Some of the 6859history has been lost; we are not intentionally leaving anyone out. 6860 6861 ---------- Footnotes ---------- 6862 6863 (1) Any more details? 6864 6865 6866File: as.info, Node: GNU Free Documentation License, Next: Index, Prev: Acknowledgements, Up: Top 6867 6868Appendix A GNU Free Documentation License 6869***************************************** 6870 6871 Version 1.1, March 2000 6872 6873 Copyright (C) 2000, 2003 Free Software Foundation, Inc. 6874 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 6875 6876 Everyone is permitted to copy and distribute verbatim copies 6877 of this license document, but changing it is not allowed. 6878 6879 6880 0. PREAMBLE 6881 6882 The purpose of this License is to make a manual, textbook, or other 6883 written document "free" in the sense of freedom: to assure everyone 6884 the effective freedom to copy and redistribute it, with or without 6885 modifying it, either commercially or noncommercially. Secondarily, 6886 this License preserves for the author and publisher a way to get 6887 credit for their work, while not being considered responsible for 6888 modifications made by others. 6889 6890 This License is a kind of "copyleft", which means that derivative 6891 works of the document must themselves be free in the same sense. 6892 It complements the GNU General Public License, which is a copyleft 6893 license designed for free software. 6894 6895 We have designed this License in order to use it for manuals for 6896 free software, because free software needs free documentation: a 6897 free program should come with manuals providing the same freedoms 6898 that the software does. But this License is not limited to 6899 software manuals; it can be used for any textual work, regardless 6900 of subject matter or whether it is published as a printed book. 6901 We recommend this License principally for works whose purpose is 6902 instruction or reference. 6903 6904 6905 1. APPLICABILITY AND DEFINITIONS 6906 6907 This License applies to any manual or other work that contains a 6908 notice placed by the copyright holder saying it can be distributed 6909 under the terms of this License. The "Document", below, refers to 6910 any such manual or work. Any member of the public is a licensee, 6911 and is addressed as "you." 6912 6913 A "Modified Version" of the Document means any work containing the 6914 Document or a portion of it, either copied verbatim, or with 6915 modifications and/or translated into another language. 6916 6917 A "Secondary Section" is a named appendix or a front-matter 6918 section of the Document that deals exclusively with the 6919 relationship of the publishers or authors of the Document to the 6920 Document's overall subject (or to related matters) and contains 6921 nothing that could fall directly within that overall subject. 6922 (For example, if the Document is in part a textbook of 6923 mathematics, a Secondary Section may not explain any mathematics.) 6924 The relationship could be a matter of historical connection with 6925 the subject or with related matters, or of legal, commercial, 6926 philosophical, ethical or political position regarding them. 6927 6928 The "Invariant Sections" are certain Secondary Sections whose 6929 titles are designated, as being those of Invariant Sections, in 6930 the notice that says that the Document is released under this 6931 License. 6932 6933 The "Cover Texts" are certain short passages of text that are 6934 listed, as Front-Cover Texts or Back-Cover Texts, in the notice 6935 that says that the Document is released under this License. 6936 6937 A "Transparent" copy of the Document means a machine-readable copy, 6938 represented in a format whose specification is available to the 6939 general public, whose contents can be viewed and edited directly 6940 and straightforwardly with generic text editors or (for images 6941 composed of pixels) generic paint programs or (for drawings) some 6942 widely available drawing editor, and that is suitable for input to 6943 text formatters or for automatic translation to a variety of 6944 formats suitable for input to text formatters. A copy made in an 6945 otherwise Transparent file format whose markup has been designed 6946 to thwart or discourage subsequent modification by readers is not 6947 Transparent. A copy that is not "Transparent" is called "Opaque." 6948 6949 Examples of suitable formats for Transparent copies include plain 6950 ASCII without markup, Texinfo input format, LaTeX input format, 6951 SGML or XML using a publicly available DTD, and 6952 standard-conforming simple HTML designed for human modification. 6953 Opaque formats include PostScript, PDF, proprietary formats that 6954 can be read and edited only by proprietary word processors, SGML 6955 or XML for which the DTD and/or processing tools are not generally 6956 available, and the machine-generated HTML produced by some word 6957 processors for output purposes only. 6958 6959 The "Title Page" means, for a printed book, the title page itself, 6960 plus such following pages as are needed to hold, legibly, the 6961 material this License requires to appear in the title page. For 6962 works in formats which do not have any title page as such, "Title 6963 Page" means the text near the most prominent appearance of the 6964 work's title, preceding the beginning of the body of the text. 6965 6966 2. VERBATIM COPYING 6967 6968 You may copy and distribute the Document in any medium, either 6969 commercially or noncommercially, provided that this License, the 6970 copyright notices, and the license notice saying this License 6971 applies to the Document are reproduced in all copies, and that you 6972 add no other conditions whatsoever to those of this License. You 6973 may not use technical measures to obstruct or control the reading 6974 or further copying of the copies you make or distribute. However, 6975 you may accept compensation in exchange for copies. If you 6976 distribute a large enough number of copies you must also follow 6977 the conditions in section 3. 6978 6979 You may also lend copies, under the same conditions stated above, 6980 and you may publicly display copies. 6981 6982 3. COPYING IN QUANTITY 6983 6984 If you publish printed copies of the Document numbering more than 6985 100, and the Document's license notice requires Cover Texts, you 6986 must enclose the copies in covers that carry, clearly and legibly, 6987 all these Cover Texts: Front-Cover Texts on the front cover, and 6988 Back-Cover Texts on the back cover. Both covers must also clearly 6989 and legibly identify you as the publisher of these copies. The 6990 front cover must present the full title with all words of the 6991 title equally prominent and visible. You may add other material 6992 on the covers in addition. Copying with changes limited to the 6993 covers, as long as they preserve the title of the Document and 6994 satisfy these conditions, can be treated as verbatim copying in 6995 other respects. 6996 6997 If the required texts for either cover are too voluminous to fit 6998 legibly, you should put the first ones listed (as many as fit 6999 reasonably) on the actual cover, and continue the rest onto 7000 adjacent pages. 7001 7002 If you publish or distribute Opaque copies of the Document 7003 numbering more than 100, you must either include a 7004 machine-readable Transparent copy along with each Opaque copy, or 7005 state in or with each Opaque copy a publicly-accessible 7006 computer-network location containing a complete Transparent copy 7007 of the Document, free of added material, which the general 7008 network-using public has access to download anonymously at no 7009 charge using public-standard network protocols. If you use the 7010 latter option, you must take reasonably prudent steps, when you 7011 begin distribution of Opaque copies in quantity, to ensure that 7012 this Transparent copy will remain thus accessible at the stated 7013 location until at least one year after the last time you 7014 distribute an Opaque copy (directly or through your agents or 7015 retailers) of that edition to the public. 7016 7017 It is requested, but not required, that you contact the authors of 7018 the Document well before redistributing any large number of 7019 copies, to give them a chance to provide you with an updated 7020 version of the Document. 7021 7022 4. MODIFICATIONS 7023 7024 You may copy and distribute a Modified Version of the Document 7025 under the conditions of sections 2 and 3 above, provided that you 7026 release the Modified Version under precisely this License, with 7027 the Modified Version filling the role of the Document, thus 7028 licensing distribution and modification of the Modified Version to 7029 whoever possesses a copy of it. In addition, you must do these 7030 things in the Modified Version: 7031 7032 A. Use in the Title Page (and on the covers, if any) a title 7033 distinct from that of the Document, and from those of previous 7034 versions (which should, if there were any, be listed in the 7035 History section of the Document). You may use the same title 7036 as a previous version if the original publisher of that version 7037 gives permission. 7038 B. List on the Title Page, as authors, one or more persons or 7039 entities responsible for authorship of the modifications in the 7040 Modified Version, together with at least five of the principal 7041 authors of the Document (all of its principal authors, if it 7042 has less than five). 7043 C. State on the Title page the name of the publisher of the 7044 Modified Version, as the publisher. 7045 D. Preserve all the copyright notices of the Document. 7046 E. Add an appropriate copyright notice for your modifications 7047 adjacent to the other copyright notices. 7048 F. Include, immediately after the copyright notices, a license 7049 notice giving the public permission to use the Modified Version 7050 under the terms of this License, in the form shown in the 7051 Addendum below. 7052 G. Preserve in that license notice the full lists of Invariant 7053 Sections and required Cover Texts given in the Document's 7054 license notice. 7055 H. Include an unaltered copy of this License. 7056 I. Preserve the section entitled "History", and its title, and add 7057 to it an item stating at least the title, year, new authors, and 7058 publisher of the Modified Version as given on the Title Page. 7059 If there is no section entitled "History" in the Document, 7060 create one stating the title, year, authors, and publisher of 7061 the Document as given on its Title Page, then add an item 7062 describing the Modified Version as stated in the previous 7063 sentence. 7064 J. Preserve the network location, if any, given in the Document for 7065 public access to a Transparent copy of the Document, and 7066 likewise the network locations given in the Document for 7067 previous versions it was based on. These may be placed in the 7068 "History" section. You may omit a network location for a work 7069 that was published at least four years before the Document 7070 itself, or if the original publisher of the version it refers 7071 to gives permission. 7072 K. In any section entitled "Acknowledgements" or "Dedications", 7073 preserve the section's title, and preserve in the section all the 7074 substance and tone of each of the contributor acknowledgements 7075 and/or dedications given therein. 7076 L. Preserve all the Invariant Sections of the Document, 7077 unaltered in their text and in their titles. Section numbers 7078 or the equivalent are not considered part of the section titles. 7079 M. Delete any section entitled "Endorsements." Such a section 7080 may not be included in the Modified Version. 7081 N. Do not retitle any existing section as "Endorsements" or to 7082 conflict in title with any Invariant Section. 7083 7084 If the Modified Version includes new front-matter sections or 7085 appendices that qualify as Secondary Sections and contain no 7086 material copied from the Document, you may at your option 7087 designate some or all of these sections as invariant. To do this, 7088 add their titles to the list of Invariant Sections in the Modified 7089 Version's license notice. These titles must be distinct from any 7090 other section titles. 7091 7092 You may add a section entitled "Endorsements", provided it contains 7093 nothing but endorsements of your Modified Version by various 7094 parties-for example, statements of peer review or that the text has 7095 been approved by an organization as the authoritative definition 7096 of a standard. 7097 7098 You may add a passage of up to five words as a Front-Cover Text, 7099 and a passage of up to 25 words as a Back-Cover Text, to the end 7100 of the list of Cover Texts in the Modified Version. Only one 7101 passage of Front-Cover Text and one of Back-Cover Text may be 7102 added by (or through arrangements made by) any one entity. If the 7103 Document already includes a cover text for the same cover, 7104 previously added by you or by arrangement made by the same entity 7105 you are acting on behalf of, you may not add another; but you may 7106 replace the old one, on explicit permission from the previous 7107 publisher that added the old one. 7108 7109 The author(s) and publisher(s) of the Document do not by this 7110 License give permission to use their names for publicity for or to 7111 assert or imply endorsement of any Modified Version. 7112 7113 5. COMBINING DOCUMENTS 7114 7115 You may combine the Document with other documents released under 7116 this License, under the terms defined in section 4 above for 7117 modified versions, provided that you include in the combination 7118 all of the Invariant Sections of all of the original documents, 7119 unmodified, and list them all as Invariant Sections of your 7120 combined work in its license notice. 7121 7122 The combined work need only contain one copy of this License, and 7123 multiple identical Invariant Sections may be replaced with a single 7124 copy. If there are multiple Invariant Sections with the same name 7125 but different contents, make the title of each such section unique 7126 by adding at the end of it, in parentheses, the name of the 7127 original author or publisher of that section if known, or else a 7128 unique number. Make the same adjustment to the section titles in 7129 the list of Invariant Sections in the license notice of the 7130 combined work. 7131 7132 In the combination, you must combine any sections entitled 7133 "History" in the various original documents, forming one section 7134 entitled "History"; likewise combine any sections entitled 7135 "Acknowledgements", and any sections entitled "Dedications." You 7136 must delete all sections entitled "Endorsements." 7137 7138 6. COLLECTIONS OF DOCUMENTS 7139 7140 You may make a collection consisting of the Document and other 7141 documents released under this License, and replace the individual 7142 copies of this License in the various documents with a single copy 7143 that is included in the collection, provided that you follow the 7144 rules of this License for verbatim copying of each of the 7145 documents in all other respects. 7146 7147 You may extract a single document from such a collection, and 7148 distribute it individually under this License, provided you insert 7149 a copy of this License into the extracted document, and follow 7150 this License in all other respects regarding verbatim copying of 7151 that document. 7152 7153 7. AGGREGATION WITH INDEPENDENT WORKS 7154 7155 A compilation of the Document or its derivatives with other 7156 separate and independent documents or works, in or on a volume of 7157 a storage or distribution medium, does not as a whole count as a 7158 Modified Version of the Document, provided no compilation 7159 copyright is claimed for the compilation. Such a compilation is 7160 called an "aggregate", and this License does not apply to the 7161 other self-contained works thus compiled with the Document, on 7162 account of their being thus compiled, if they are not themselves 7163 derivative works of the Document. 7164 7165 If the Cover Text requirement of section 3 is applicable to these 7166 copies of the Document, then if the Document is less than one 7167 quarter of the entire aggregate, the Document's Cover Texts may be 7168 placed on covers that surround only the Document within the 7169 aggregate. Otherwise they must appear on covers around the whole 7170 aggregate. 7171 7172 8. TRANSLATION 7173 7174 Translation is considered a kind of modification, so you may 7175 distribute translations of the Document under the terms of section 7176 4. Replacing Invariant Sections with translations requires special 7177 permission from their copyright holders, but you may include 7178 translations of some or all Invariant Sections in addition to the 7179 original versions of these Invariant Sections. You may include a 7180 translation of this License provided that you also include the 7181 original English version of this License. In case of a 7182 disagreement between the translation and the original English 7183 version of this License, the original English version will prevail. 7184 7185 9. TERMINATION 7186 7187 You may not copy, modify, sublicense, or distribute the Document 7188 except as expressly provided for under this License. Any other 7189 attempt to copy, modify, sublicense or distribute the Document is 7190 void, and will automatically terminate your rights under this 7191 License. However, parties who have received copies, or rights, 7192 from you under this License will not have their licenses 7193 terminated so long as such parties remain in full compliance. 7194 7195 10. FUTURE REVISIONS OF THIS LICENSE 7196 7197 The Free Software Foundation may publish new, revised versions of 7198 the GNU Free Documentation License from time to time. Such new 7199 versions will be similar in spirit to the present version, but may 7200 differ in detail to address new problems or concerns. See 7201 http://www.gnu.org/copyleft/. 7202 7203 Each version of the License is given a distinguishing version 7204 number. If the Document specifies that a particular numbered 7205 version of this License "or any later version" applies to it, you 7206 have the option of following the terms and conditions either of 7207 that specified version or of any later version that has been 7208 published (not as a draft) by the Free Software Foundation. If 7209 the Document does not specify a version number of this License, 7210 you may choose any version ever published (not as a draft) by the 7211 Free Software Foundation. 7212 7213 7214ADDENDUM: How to use this License for your documents 7215==================================================== 7216 7217To use this License in a document you have written, include a copy of 7218the License in the document and put the following copyright and license 7219notices just after the title page: 7220 7221 Copyright (C) YEAR YOUR NAME. 7222 Permission is granted to copy, distribute and/or modify this document 7223 under the terms of the GNU Free Documentation License, Version 1.1 7224 or any later version published by the Free Software Foundation; 7225 with the Invariant Sections being LIST THEIR TITLES, with the 7226 Front-Cover Texts being LIST, and with the Back-Cover Texts being LIST. 7227 A copy of the license is included in the section entitled "GNU 7228 Free Documentation License." 7229 7230 If you have no Invariant Sections, write "with no Invariant Sections" 7231instead of saying which ones are invariant. If you have no Front-Cover 7232Texts, write "no Front-Cover Texts" instead of "Front-Cover Texts being 7233LIST"; likewise for Back-Cover Texts. 7234 7235 If your document contains nontrivial examples of program code, we 7236recommend releasing these examples in parallel under your choice of 7237free software license, such as the GNU General Public License, to 7238permit their use in free software. 7239 7240