1 /* Opcode table for the ARC.
2 Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2004
3 Free Software Foundation, Inc.
4 Contributed by Doug Evans (dje@cygnus.com).
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software Foundation,
18 Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
19
20 #include "sysdep.h"
21 #include <stdio.h>
22 #include "ansidecl.h"
23 #include "bfd.h"
24 #include "opcode/arc.h"
25
26 #define INSERT_FN(fn) \
27 static arc_insn fn PARAMS ((arc_insn, const struct arc_operand *, \
28 int, const struct arc_operand_value *, long, \
29 const char **))
30 #define EXTRACT_FN(fn) \
31 static long fn PARAMS ((arc_insn *, const struct arc_operand *, \
32 int, const struct arc_operand_value **, int *))
33
34 INSERT_FN (insert_reg);
35 INSERT_FN (insert_shimmfinish);
36 INSERT_FN (insert_limmfinish);
37 INSERT_FN (insert_offset);
38 INSERT_FN (insert_base);
39 INSERT_FN (insert_st_syntax);
40 INSERT_FN (insert_ld_syntax);
41 INSERT_FN (insert_addr_wb);
42 INSERT_FN (insert_flag);
43 INSERT_FN (insert_nullify);
44 INSERT_FN (insert_flagfinish);
45 INSERT_FN (insert_cond);
46 INSERT_FN (insert_forcelimm);
47 INSERT_FN (insert_reladdr);
48 INSERT_FN (insert_absaddr);
49 INSERT_FN (insert_jumpflags);
50 INSERT_FN (insert_unopmacro);
51
52 EXTRACT_FN (extract_reg);
53 EXTRACT_FN (extract_ld_offset);
54 EXTRACT_FN (extract_ld_syntax);
55 EXTRACT_FN (extract_st_offset);
56 EXTRACT_FN (extract_st_syntax);
57 EXTRACT_FN (extract_flag);
58 EXTRACT_FN (extract_cond);
59 EXTRACT_FN (extract_reladdr);
60 EXTRACT_FN (extract_jumpflags);
61 EXTRACT_FN (extract_unopmacro);
62
63 enum operand {OP_NONE,OP_REG,OP_SHIMM,OP_LIMM};
64
65 #define OPERANDS 3
66
67 enum operand ls_operand[OPERANDS];
68
69 struct arc_opcode *arc_ext_opcodes;
70 struct arc_ext_operand_value *arc_ext_operands;
71
72 #define LS_VALUE 0
73 #define LS_DEST 0
74 #define LS_BASE 1
75 #define LS_OFFSET 2
76
77 /* Various types of ARC operands, including insn suffixes. */
78
79 /* Insn format values:
80
81 'a' REGA register A field
82 'b' REGB register B field
83 'c' REGC register C field
84 'S' SHIMMFINISH finish inserting a shimm value
85 'L' LIMMFINISH finish inserting a limm value
86 'o' OFFSET offset in st insns
87 'O' OFFSET offset in ld insns
88 '0' SYNTAX_ST_NE enforce store insn syntax, no errors
89 '1' SYNTAX_LD_NE enforce load insn syntax, no errors
90 '2' SYNTAX_ST enforce store insn syntax, errors, last pattern only
91 '3' SYNTAX_LD enforce load insn syntax, errors, last pattern only
92 's' BASE base in st insn
93 'f' FLAG F flag
94 'F' FLAGFINISH finish inserting the F flag
95 'G' FLAGINSN insert F flag in "flag" insn
96 'n' DELAY N field (nullify field)
97 'q' COND condition code field
98 'Q' FORCELIMM set `cond_p' to 1 to ensure a constant is a limm
99 'B' BRANCH branch address (22 bit pc relative)
100 'J' JUMP jump address (26 bit absolute)
101 'j' JUMPFLAGS optional high order bits of 'J'
102 'z' SIZE1 size field in ld a,[b,c]
103 'Z' SIZE10 size field in ld a,[b,shimm]
104 'y' SIZE22 size field in st c,[b,shimm]
105 'x' SIGN0 sign extend field ld a,[b,c]
106 'X' SIGN9 sign extend field ld a,[b,shimm]
107 'w' ADDRESS3 write-back field in ld a,[b,c]
108 'W' ADDRESS12 write-back field in ld a,[b,shimm]
109 'v' ADDRESS24 write-back field in st c,[b,shimm]
110 'e' CACHEBYPASS5 cache bypass in ld a,[b,c]
111 'E' CACHEBYPASS14 cache bypass in ld a,[b,shimm]
112 'D' CACHEBYPASS26 cache bypass in st c,[b,shimm]
113 'U' UNOPMACRO fake operand to copy REGB to REGC for unop macros
114
115 The following modifiers may appear between the % and char (eg: %.f):
116
117 '.' MODDOT '.' prefix must be present
118 'r' REG generic register value, for register table
119 'A' AUXREG auxiliary register in lr a,[b], sr c,[b]
120
121 Fields are:
122
123 CHAR BITS SHIFT FLAGS INSERT_FN EXTRACT_FN */
124
125 const struct arc_operand arc_operands[] =
126 {
127 /* place holder (??? not sure if needed). */
128 #define UNUSED 0
129 { 0, 0, 0, 0, 0, 0 },
130
131 /* register A or shimm/limm indicator. */
132 #define REGA (UNUSED + 1)
133 { 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg },
134
135 /* register B or shimm/limm indicator. */
136 #define REGB (REGA + 1)
137 { 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg },
138
139 /* register C or shimm/limm indicator. */
140 #define REGC (REGB + 1)
141 { 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED | ARC_OPERAND_ERROR, insert_reg, extract_reg },
142
143 /* fake operand used to insert shimm value into most instructions. */
144 #define SHIMMFINISH (REGC + 1)
145 { 'S', 9, 0, ARC_OPERAND_SIGNED + ARC_OPERAND_FAKE, insert_shimmfinish, 0 },
146
147 /* fake operand used to insert limm value into most instructions. */
148 #define LIMMFINISH (SHIMMFINISH + 1)
149 { 'L', 32, 32, ARC_OPERAND_ADDRESS + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_limmfinish, 0 },
150
151 /* shimm operand when there is no reg indicator (st). */
152 #define ST_OFFSET (LIMMFINISH + 1)
153 { 'o', 9, 0, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_STORE, insert_offset, extract_st_offset },
154
155 /* shimm operand when there is no reg indicator (ld). */
156 #define LD_OFFSET (ST_OFFSET + 1)
157 { 'O', 9, 0,ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | ARC_OPERAND_LOAD, insert_offset, extract_ld_offset },
158
159 /* operand for base. */
160 #define BASE (LD_OFFSET + 1)
161 { 's', 6, ARC_SHIFT_REGB, ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED, insert_base, extract_reg},
162
163 /* 0 enforce syntax for st insns. */
164 #define SYNTAX_ST_NE (BASE + 1)
165 { '0', 9, 0, ARC_OPERAND_FAKE, insert_st_syntax, extract_st_syntax },
166
167 /* 1 enforce syntax for ld insns. */
168 #define SYNTAX_LD_NE (SYNTAX_ST_NE + 1)
169 { '1', 9, 0, ARC_OPERAND_FAKE, insert_ld_syntax, extract_ld_syntax },
170
171 /* 0 enforce syntax for st insns. */
172 #define SYNTAX_ST (SYNTAX_LD_NE + 1)
173 { '2', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_st_syntax, extract_st_syntax },
174
175 /* 0 enforce syntax for ld insns. */
176 #define SYNTAX_LD (SYNTAX_ST + 1)
177 { '3', 9, 0, ARC_OPERAND_FAKE | ARC_OPERAND_ERROR, insert_ld_syntax, extract_ld_syntax },
178
179 /* flag update bit (insertion is defered until we know how). */
180 #define FLAG (SYNTAX_LD + 1)
181 { 'f', 1, 8, ARC_OPERAND_SUFFIX, insert_flag, extract_flag },
182
183 /* fake utility operand to finish 'f' suffix handling. */
184 #define FLAGFINISH (FLAG + 1)
185 { 'F', 1, 8, ARC_OPERAND_FAKE, insert_flagfinish, 0 },
186
187 /* fake utility operand to set the 'f' flag for the "flag" insn. */
188 #define FLAGINSN (FLAGFINISH + 1)
189 { 'G', 1, 8, ARC_OPERAND_FAKE, insert_flag, 0 },
190
191 /* branch delay types. */
192 #define DELAY (FLAGINSN + 1)
193 { 'n', 2, 5, ARC_OPERAND_SUFFIX , insert_nullify, 0 },
194
195 /* conditions. */
196 #define COND (DELAY + 1)
197 { 'q', 5, 0, ARC_OPERAND_SUFFIX, insert_cond, extract_cond },
198
199 /* set `cond_p' to 1 to ensure a constant is treated as a limm. */
200 #define FORCELIMM (COND + 1)
201 { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm, 0 },
202
203 /* branch address; b, bl, and lp insns. */
204 #define BRANCH (FORCELIMM + 1)
205 { 'B', 20, 7, (ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED) | ARC_OPERAND_ERROR, insert_reladdr, extract_reladdr },
206
207 /* jump address; j insn (this is basically the same as 'L' except that the
208 value is right shifted by 2). */
209 #define JUMP (BRANCH + 1)
210 { 'J', 24, 32, ARC_OPERAND_ERROR | (ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE), insert_absaddr, 0 },
211
212 /* jump flags; j{,l} insn value or'ed into 'J' addr for flag values. */
213 #define JUMPFLAGS (JUMP + 1)
214 { 'j', 6, 26, ARC_OPERAND_JUMPFLAGS | ARC_OPERAND_ERROR, insert_jumpflags, extract_jumpflags },
215
216 /* size field, stored in bit 1,2. */
217 #define SIZE1 (JUMPFLAGS + 1)
218 { 'z', 2, 1, ARC_OPERAND_SUFFIX, 0, 0 },
219
220 /* size field, stored in bit 10,11. */
221 #define SIZE10 (SIZE1 + 1)
222 { 'Z', 2, 10, ARC_OPERAND_SUFFIX, 0, 0 },
223
224 /* size field, stored in bit 22,23. */
225 #define SIZE22 (SIZE10 + 1)
226 { 'y', 2, 22, ARC_OPERAND_SUFFIX, 0, 0 },
227
228 /* sign extend field, stored in bit 0. */
229 #define SIGN0 (SIZE22 + 1)
230 { 'x', 1, 0, ARC_OPERAND_SUFFIX, 0, 0 },
231
232 /* sign extend field, stored in bit 9. */
233 #define SIGN9 (SIGN0 + 1)
234 { 'X', 1, 9, ARC_OPERAND_SUFFIX, 0, 0 },
235
236 /* address write back, stored in bit 3. */
237 #define ADDRESS3 (SIGN9 + 1)
238 { 'w', 1, 3, ARC_OPERAND_SUFFIX, insert_addr_wb, 0},
239
240 /* address write back, stored in bit 12. */
241 #define ADDRESS12 (ADDRESS3 + 1)
242 { 'W', 1, 12, ARC_OPERAND_SUFFIX, insert_addr_wb, 0},
243
244 /* address write back, stored in bit 24. */
245 #define ADDRESS24 (ADDRESS12 + 1)
246 { 'v', 1, 24, ARC_OPERAND_SUFFIX, insert_addr_wb, 0},
247
248 /* cache bypass, stored in bit 5. */
249 #define CACHEBYPASS5 (ADDRESS24 + 1)
250 { 'e', 1, 5, ARC_OPERAND_SUFFIX, 0, 0 },
251
252 /* cache bypass, stored in bit 14. */
253 #define CACHEBYPASS14 (CACHEBYPASS5 + 1)
254 { 'E', 1, 14, ARC_OPERAND_SUFFIX, 0, 0 },
255
256 /* cache bypass, stored in bit 26. */
257 #define CACHEBYPASS26 (CACHEBYPASS14 + 1)
258 { 'D', 1, 26, ARC_OPERAND_SUFFIX, 0, 0 },
259
260 /* unop macro, used to copy REGB to REGC. */
261 #define UNOPMACRO (CACHEBYPASS26 + 1)
262 { 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro },
263
264 /* '.' modifier ('.' required). */
265 #define MODDOT (UNOPMACRO + 1)
266 { '.', 1, 0, ARC_MOD_DOT, 0, 0 },
267
268 /* Dummy 'r' modifier for the register table.
269 It's called a "dummy" because there's no point in inserting an 'r' into all
270 the %a/%b/%c occurrences in the insn table. */
271 #define REG (MODDOT + 1)
272 { 'r', 6, 0, ARC_MOD_REG, 0, 0 },
273
274 /* Known auxiliary register modifier (stored in shimm field). */
275 #define AUXREG (REG + 1)
276 { 'A', 9, 0, ARC_MOD_AUXREG, 0, 0 },
277
278 /* end of list place holder. */
279 { 0, 0, 0, 0, 0, 0 }
280 };
281
282 /* Given a format letter, yields the index into `arc_operands'.
283 eg: arc_operand_map['a'] = REGA. */
284 unsigned char arc_operand_map[256];
285
286 /* ARC instructions.
287
288 Longer versions of insns must appear before shorter ones (if gas sees
289 "lsr r2,r3,1" when it's parsing "lsr %a,%b" it will think the ",1" is
290 junk). This isn't necessary for `ld' because of the trailing ']'.
291
292 Instructions that are really macros based on other insns must appear
293 before the real insn so they're chosen when disassembling. Eg: The `mov'
294 insn is really the `and' insn. */
295
296 struct arc_opcode arc_opcodes[] =
297 {
298 /* Base case instruction set (core versions 5-8) */
299
300 /* "mov" is really an "and". */
301 { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12), ARC_MACH_5, 0, 0 },
302 /* "asl" is really an "add". */
303 { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 },
304 /* "lsl" is really an "add". */
305 { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8), ARC_MACH_5, 0, 0 },
306 /* "nop" is really an "xor". */
307 { "nop", 0x7fffffff, 0x7fffffff, ARC_MACH_5, 0, 0 },
308 /* "rlc" is really an "adc". */
309 { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9), ARC_MACH_5, 0, 0 },
310 { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9), ARC_MACH_5, 0, 0 },
311 { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8), ARC_MACH_5, 0, 0 },
312 { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12), ARC_MACH_5, 0, 0 },
313 { "asr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(1), ARC_MACH_5, 0, 0 },
314 { "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14), ARC_MACH_5, 0, 0 },
315 { "b%q%.n %B", I(-1), I(4), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
316 { "bl%q%.n %B", I(-1), I(5), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
317 { "extb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(7), ARC_MACH_5, 0, 0 },
318 { "extw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(8), ARC_MACH_5, 0, 0 },
319 { "flag%.q %b%G%S%L", I(-1)|A(-1)|C(-1), I(3)|A(ARC_REG_SHIMM_UPDATE)|C(0), ARC_MACH_5, 0, 0 },
320 { "brk", 0x1ffffe00, 0x1ffffe00, ARC_MACH_7, 0, 0 },
321 { "sleep", 0x1ffffe01, 0x1ffffe01, ARC_MACH_7, 0, 0 },
322 { "swi", 0x1ffffe02, 0x1ffffe02, ARC_MACH_8, 0, 0 },
323 /* %Q: force cond_p=1 -> no shimm values. This insn allows an
324 optional flags spec. */
325 { "j%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
326 { "j%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1), I(7)|A(0)|C(0)|R(0,7,1), ARC_MACH_5 | ARC_OPCODE_COND_BRANCH, 0, 0 },
327 /* This insn allows an optional flags spec. */
328 { "jl%q%Q%.n%.f %b%F%J,%j", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 },
329 { "jl%q%Q%.n%.f %b%F%J", I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1), I(7)|A(0)|C(0)|R(0,7,1)|R(1,9,1), ARC_MACH_6 | ARC_OPCODE_COND_BRANCH, 0, 0 },
330 /* Put opcode 1 ld insns first so shimm gets prefered over limm.
331 "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */
332 { "ld%Z%.X%.W%.E %a,[%s]%S%L%1", I(-1)|R(-1,13,1)|R(-1,0,511), I(1)|R(0,13,1)|R(0,0,511), ARC_MACH_5, 0, 0 },
333 { "ld%z%.x%.w%.e %a,[%s]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 },
334 { "ld%z%.x%.w%.e %a,[%s,%O]%S%L%1", I(-1)|R(-1,4,1)|R(-1,6,7), I(0)|R(0,4,1)|R(0,6,7), ARC_MACH_5, 0, 0 },
335 { "ld%Z%.X%.W%.E %a,[%s,%O]%S%L%3", I(-1)|R(-1,13,1), I(1)|R(0,13,1), ARC_MACH_5, 0, 0 },
336 { "lp%q%.n %B", I(-1), I(6), ARC_MACH_5, 0, 0 },
337 { "lr %a,[%Ab]%S%L", I(-1)|C(-1), I(1)|C(0x10), ARC_MACH_5, 0, 0 },
338 { "lsr%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(2), ARC_MACH_5, 0, 0 },
339 { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13), ARC_MACH_5, 0, 0 },
340 { "ror%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(3), ARC_MACH_5, 0, 0 },
341 { "rrc%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(4), ARC_MACH_5, 0, 0 },
342 { "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11), ARC_MACH_5, 0, 0 },
343 { "sexb%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(5), ARC_MACH_5, 0, 0 },
344 { "sexw%.q%.f %a,%b%F%S%L", I(-1)|C(-1), I(3)|C(6), ARC_MACH_5, 0, 0 },
345 { "sr %c,[%Ab]%S%L", I(-1)|A(-1), I(2)|A(0x10), ARC_MACH_5, 0, 0 },
346 /* "[%b]" is before "[%b,%o]" so 0 offsets don't get printed. */
347 { "st%y%.v%.D %c,[%s]%L%S%0", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 },
348 { "st%y%.v%.D %c,[%s,%o]%S%L%2", I(-1)|R(-1,25,1)|R(-1,21,1), I(2)|R(0,25,1)|R(0,21,1), ARC_MACH_5, 0, 0 },
349 { "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10), ARC_MACH_5, 0, 0 },
350 { "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15), ARC_MACH_5, 0, 0 }
351 };
352
353 const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]);
354
355 const struct arc_operand_value arc_reg_names[] =
356 {
357 /* Core register set r0-r63. */
358
359 /* r0-r28 - general purpose registers. */
360 { "r0", 0, REG, 0 }, { "r1", 1, REG, 0 }, { "r2", 2, REG, 0 },
361 { "r3", 3, REG, 0 }, { "r4", 4, REG, 0 }, { "r5", 5, REG, 0 },
362 { "r6", 6, REG, 0 }, { "r7", 7, REG, 0 }, { "r8", 8, REG, 0 },
363 { "r9", 9, REG, 0 }, { "r10", 10, REG, 0 }, { "r11", 11, REG, 0 },
364 { "r12", 12, REG, 0 }, { "r13", 13, REG, 0 }, { "r14", 14, REG, 0 },
365 { "r15", 15, REG, 0 }, { "r16", 16, REG, 0 }, { "r17", 17, REG, 0 },
366 { "r18", 18, REG, 0 }, { "r19", 19, REG, 0 }, { "r20", 20, REG, 0 },
367 { "r21", 21, REG, 0 }, { "r22", 22, REG, 0 }, { "r23", 23, REG, 0 },
368 { "r24", 24, REG, 0 }, { "r25", 25, REG, 0 }, { "r26", 26, REG, 0 },
369 { "r27", 27, REG, 0 }, { "r28", 28, REG, 0 },
370 /* Maskable interrupt link register. */
371 { "ilink1", 29, REG, 0 },
372 /* Maskable interrupt link register. */
373 { "ilink2", 30, REG, 0 },
374 /* Branch-link register. */
375 { "blink", 31, REG, 0 },
376
377 /* r32-r59 reserved for extensions. */
378 { "r32", 32, REG, 0 }, { "r33", 33, REG, 0 }, { "r34", 34, REG, 0 },
379 { "r35", 35, REG, 0 }, { "r36", 36, REG, 0 }, { "r37", 37, REG, 0 },
380 { "r38", 38, REG, 0 }, { "r39", 39, REG, 0 }, { "r40", 40, REG, 0 },
381 { "r41", 41, REG, 0 }, { "r42", 42, REG, 0 }, { "r43", 43, REG, 0 },
382 { "r44", 44, REG, 0 }, { "r45", 45, REG, 0 }, { "r46", 46, REG, 0 },
383 { "r47", 47, REG, 0 }, { "r48", 48, REG, 0 }, { "r49", 49, REG, 0 },
384 { "r50", 50, REG, 0 }, { "r51", 51, REG, 0 }, { "r52", 52, REG, 0 },
385 { "r53", 53, REG, 0 }, { "r54", 54, REG, 0 }, { "r55", 55, REG, 0 },
386 { "r56", 56, REG, 0 }, { "r57", 57, REG, 0 }, { "r58", 58, REG, 0 },
387 { "r59", 59, REG, 0 },
388
389 /* Loop count register (24 bits). */
390 { "lp_count", 60, REG, 0 },
391 /* Short immediate data indicator setting flags. */
392 { "r61", 61, REG, ARC_REGISTER_READONLY },
393 /* Long immediate data indicator setting flags. */
394 { "r62", 62, REG, ARC_REGISTER_READONLY },
395 /* Short immediate data indicator not setting flags. */
396 { "r63", 63, REG, ARC_REGISTER_READONLY },
397
398 /* Small-data base register. */
399 { "gp", 26, REG, 0 },
400 /* Frame pointer. */
401 { "fp", 27, REG, 0 },
402 /* Stack pointer. */
403 { "sp", 28, REG, 0 },
404
405 { "r29", 29, REG, 0 },
406 { "r30", 30, REG, 0 },
407 { "r31", 31, REG, 0 },
408 { "r60", 60, REG, 0 },
409
410 /* Auxiliary register set. */
411
412 /* Auxiliary register address map:
413 0xffffffff-0xffffff00 (-1..-256) - customer shimm allocation
414 0xfffffeff-0x80000000 - customer limm allocation
415 0x7fffffff-0x00000100 - ARC limm allocation
416 0x000000ff-0x00000000 - ARC shimm allocation */
417
418 /* Base case auxiliary registers (shimm address). */
419 { "status", 0x00, AUXREG, 0 },
420 { "semaphore", 0x01, AUXREG, 0 },
421 { "lp_start", 0x02, AUXREG, 0 },
422 { "lp_end", 0x03, AUXREG, 0 },
423 { "identity", 0x04, AUXREG, ARC_REGISTER_READONLY },
424 { "debug", 0x05, AUXREG, 0 },
425 };
426
427 const int arc_reg_names_count =
428 sizeof (arc_reg_names) / sizeof (arc_reg_names[0]);
429
430 /* The suffix table.
431 Operands with the same name must be stored together. */
432
433 const struct arc_operand_value arc_suffixes[] =
434 {
435 /* Entry 0 is special, default values aren't printed by the disassembler. */
436 { "", 0, -1, 0 },
437
438 /* Base case condition codes. */
439 { "al", 0, COND, 0 },
440 { "ra", 0, COND, 0 },
441 { "eq", 1, COND, 0 },
442 { "z", 1, COND, 0 },
443 { "ne", 2, COND, 0 },
444 { "nz", 2, COND, 0 },
445 { "pl", 3, COND, 0 },
446 { "p", 3, COND, 0 },
447 { "mi", 4, COND, 0 },
448 { "n", 4, COND, 0 },
449 { "cs", 5, COND, 0 },
450 { "c", 5, COND, 0 },
451 { "lo", 5, COND, 0 },
452 { "cc", 6, COND, 0 },
453 { "nc", 6, COND, 0 },
454 { "hs", 6, COND, 0 },
455 { "vs", 7, COND, 0 },
456 { "v", 7, COND, 0 },
457 { "vc", 8, COND, 0 },
458 { "nv", 8, COND, 0 },
459 { "gt", 9, COND, 0 },
460 { "ge", 10, COND, 0 },
461 { "lt", 11, COND, 0 },
462 { "le", 12, COND, 0 },
463 { "hi", 13, COND, 0 },
464 { "ls", 14, COND, 0 },
465 { "pnz", 15, COND, 0 },
466
467 /* Condition codes 16-31 reserved for extensions. */
468
469 { "f", 1, FLAG, 0 },
470
471 { "nd", ARC_DELAY_NONE, DELAY, 0 },
472 { "d", ARC_DELAY_NORMAL, DELAY, 0 },
473 { "jd", ARC_DELAY_JUMP, DELAY, 0 },
474
475 { "b", 1, SIZE1, 0 },
476 { "b", 1, SIZE10, 0 },
477 { "b", 1, SIZE22, 0 },
478 { "w", 2, SIZE1, 0 },
479 { "w", 2, SIZE10, 0 },
480 { "w", 2, SIZE22, 0 },
481 { "x", 1, SIGN0, 0 },
482 { "x", 1, SIGN9, 0 },
483 { "a", 1, ADDRESS3, 0 },
484 { "a", 1, ADDRESS12, 0 },
485 { "a", 1, ADDRESS24, 0 },
486
487 { "di", 1, CACHEBYPASS5, 0 },
488 { "di", 1, CACHEBYPASS14, 0 },
489 { "di", 1, CACHEBYPASS26, 0 },
490 };
491
492 const int arc_suffixes_count =
493 sizeof (arc_suffixes) / sizeof (arc_suffixes[0]);
494
495 /* Indexed by first letter of opcode. Points to chain of opcodes with same
496 first letter. */
497 static struct arc_opcode *opcode_map[26 + 1];
498
499 /* Indexed by insn code. Points to chain of opcodes with same insn code. */
500 static struct arc_opcode *icode_map[32];
501
502 /* Configuration flags. */
503
504 /* Various ARC_HAVE_XXX bits. */
505 static int cpu_type;
506
507 /* Translate a bfd_mach_arc_xxx value to a ARC_MACH_XXX value. */
508
509 int
arc_get_opcode_mach(bfd_mach,big_p)510 arc_get_opcode_mach (bfd_mach, big_p)
511 int bfd_mach, big_p;
512 {
513 static int mach_type_map[] =
514 {
515 ARC_MACH_5,
516 ARC_MACH_6,
517 ARC_MACH_7,
518 ARC_MACH_8
519 };
520 return mach_type_map[bfd_mach - bfd_mach_arc_5] | (big_p ? ARC_MACH_BIG : 0);
521 }
522
523 /* Initialize any tables that need it.
524 Must be called once at start up (or when first needed).
525
526 FLAGS is a set of bits that say what version of the cpu we have,
527 and in particular at least (one of) ARC_MACH_XXX. */
528
529 void
arc_opcode_init_tables(flags)530 arc_opcode_init_tables (flags)
531 int flags;
532 {
533 static int init_p = 0;
534
535 cpu_type = flags;
536
537 /* We may be intentionally called more than once (for example gdb will call
538 us each time the user switches cpu). These tables only need to be init'd
539 once though. */
540 if (!init_p)
541 {
542 register int i,n;
543
544 memset (arc_operand_map, 0, sizeof (arc_operand_map));
545 n = sizeof (arc_operands) / sizeof (arc_operands[0]);
546 for (i = 0; i < n; ++i)
547 arc_operand_map[arc_operands[i].fmt] = i;
548
549 memset (opcode_map, 0, sizeof (opcode_map));
550 memset (icode_map, 0, sizeof (icode_map));
551 /* Scan the table backwards so macros appear at the front. */
552 for (i = arc_opcodes_count - 1; i >= 0; --i)
553 {
554 int opcode_hash = ARC_HASH_OPCODE (arc_opcodes[i].syntax);
555 int icode_hash = ARC_HASH_ICODE (arc_opcodes[i].value);
556
557 arc_opcodes[i].next_asm = opcode_map[opcode_hash];
558 opcode_map[opcode_hash] = &arc_opcodes[i];
559
560 arc_opcodes[i].next_dis = icode_map[icode_hash];
561 icode_map[icode_hash] = &arc_opcodes[i];
562 }
563
564 init_p = 1;
565 }
566 }
567
568 /* Return non-zero if OPCODE is supported on the specified cpu.
569 Cpu selection is made when calling `arc_opcode_init_tables'. */
570
571 int
arc_opcode_supported(opcode)572 arc_opcode_supported (opcode)
573 const struct arc_opcode *opcode;
574 {
575 if (ARC_OPCODE_CPU (opcode->flags) <= cpu_type)
576 return 1;
577 return 0;
578 }
579
580 /* Return the first insn in the chain for assembling INSN. */
581
582 const struct arc_opcode *
arc_opcode_lookup_asm(insn)583 arc_opcode_lookup_asm (insn)
584 const char *insn;
585 {
586 return opcode_map[ARC_HASH_OPCODE (insn)];
587 }
588
589 /* Return the first insn in the chain for disassembling INSN. */
590
591 const struct arc_opcode *
arc_opcode_lookup_dis(insn)592 arc_opcode_lookup_dis (insn)
593 unsigned int insn;
594 {
595 return icode_map[ARC_HASH_ICODE (insn)];
596 }
597
598 /* Nonzero if we've seen an 'f' suffix (in certain insns). */
599 static int flag_p;
600
601 /* Nonzero if we've finished processing the 'f' suffix. */
602 static int flagshimm_handled_p;
603
604 /* Nonzero if we've seen a 'a' suffix (address writeback). */
605 static int addrwb_p;
606
607 /* Nonzero if we've seen a 'q' suffix (condition code). */
608 static int cond_p;
609
610 /* Nonzero if we've inserted a nullify condition. */
611 static int nullify_p;
612
613 /* The value of the a nullify condition we inserted. */
614 static int nullify;
615
616 /* Nonzero if we've inserted jumpflags. */
617 static int jumpflags_p;
618
619 /* Nonzero if we've inserted a shimm. */
620 static int shimm_p;
621
622 /* The value of the shimm we inserted (each insn only gets one but it can
623 appear multiple times). */
624 static int shimm;
625
626 /* Nonzero if we've inserted a limm (during assembly) or seen a limm
627 (during disassembly). */
628 static int limm_p;
629
630 /* The value of the limm we inserted. Each insn only gets one but it can
631 appear multiple times. */
632 static long limm;
633
634 /* Insertion functions. */
635
636 /* Called by the assembler before parsing an instruction. */
637
638 void
arc_opcode_init_insert()639 arc_opcode_init_insert ()
640 {
641 int i;
642
643 for(i = 0; i < OPERANDS; i++)
644 ls_operand[i] = OP_NONE;
645
646 flag_p = 0;
647 flagshimm_handled_p = 0;
648 cond_p = 0;
649 addrwb_p = 0;
650 shimm_p = 0;
651 limm_p = 0;
652 jumpflags_p = 0;
653 nullify_p = 0;
654 nullify = 0; /* the default is important. */
655 }
656
657 /* Called by the assembler to see if the insn has a limm operand.
658 Also called by the disassembler to see if the insn contains a limm. */
659
660 int
arc_opcode_limm_p(limmp)661 arc_opcode_limm_p (limmp)
662 long *limmp;
663 {
664 if (limmp)
665 *limmp = limm;
666 return limm_p;
667 }
668
669 /* Insert a value into a register field.
670 If REG is NULL, then this is actually a constant.
671
672 We must also handle auxiliary registers for lr/sr insns. */
673
674 static arc_insn
insert_reg(insn,operand,mods,reg,value,errmsg)675 insert_reg (insn, operand, mods, reg, value, errmsg)
676 arc_insn insn;
677 const struct arc_operand *operand;
678 int mods;
679 const struct arc_operand_value *reg;
680 long value;
681 const char **errmsg;
682 {
683 static char buf[100];
684 enum operand op_type = OP_NONE;
685
686 if (reg == NULL)
687 {
688 /* We have a constant that also requires a value stored in a register
689 field. Handle these by updating the register field and saving the
690 value for later handling by either %S (shimm) or %L (limm). */
691
692 /* Try to use a shimm value before a limm one. */
693 if (ARC_SHIMM_CONST_P (value)
694 /* If we've seen a conditional suffix we have to use a limm. */
695 && !cond_p
696 /* If we already have a shimm value that is different than ours
697 we have to use a limm. */
698 && (!shimm_p || shimm == value))
699 {
700 int marker;
701
702 op_type = OP_SHIMM;
703 /* forget about shimm as dest mlm. */
704
705 if ('a' != operand->fmt)
706 {
707 shimm_p = 1;
708 shimm = value;
709 flagshimm_handled_p = 1;
710 marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM;
711 }
712 else
713 {
714 /* don't request flag setting on shimm as dest. */
715 marker = ARC_REG_SHIMM;
716 }
717 insn |= marker << operand->shift;
718 /* insn |= value & 511; - done later. */
719 }
720 /* We have to use a limm. If we've already seen one they must match. */
721 else if (!limm_p || limm == value)
722 {
723 op_type = OP_LIMM;
724 limm_p = 1;
725 limm = value;
726 insn |= ARC_REG_LIMM << operand->shift;
727 /* The constant is stored later. */
728 }
729 else
730 {
731 *errmsg = "unable to fit different valued constants into instruction";
732 }
733 }
734 else
735 {
736 /* We have to handle both normal and auxiliary registers. */
737
738 if (reg->type == AUXREG)
739 {
740 if (!(mods & ARC_MOD_AUXREG))
741 *errmsg = "auxiliary register not allowed here";
742 else
743 {
744 if ((insn & I(-1)) == I(2)) /* check for use validity. */
745 {
746 if (reg->flags & ARC_REGISTER_READONLY)
747 *errmsg = "attempt to set readonly register";
748 }
749 else
750 {
751 if (reg->flags & ARC_REGISTER_WRITEONLY)
752 *errmsg = "attempt to read writeonly register";
753 }
754 insn |= ARC_REG_SHIMM << operand->shift;
755 insn |= reg->value << arc_operands[reg->type].shift;
756 }
757 }
758 else
759 {
760 /* check for use validity. */
761 if ('a' == operand->fmt || ((insn & I(-1)) < I(2)))
762 {
763 if (reg->flags & ARC_REGISTER_READONLY)
764 *errmsg = "attempt to set readonly register";
765 }
766 if ('a' != operand->fmt)
767 {
768 if (reg->flags & ARC_REGISTER_WRITEONLY)
769 *errmsg = "attempt to read writeonly register";
770 }
771 /* We should never get an invalid register number here. */
772 if ((unsigned int) reg->value > 60)
773 {
774 sprintf (buf, "invalid register number `%d'", reg->value);
775 *errmsg = buf;
776 }
777 insn |= reg->value << operand->shift;
778 op_type = OP_REG;
779 }
780 }
781
782 switch (operand->fmt)
783 {
784 case 'a':
785 ls_operand[LS_DEST] = op_type;
786 break;
787 case 's':
788 ls_operand[LS_BASE] = op_type;
789 break;
790 case 'c':
791 if ((insn & I(-1)) == I(2))
792 ls_operand[LS_VALUE] = op_type;
793 else
794 ls_operand[LS_OFFSET] = op_type;
795 break;
796 case 'o': case 'O':
797 ls_operand[LS_OFFSET] = op_type;
798 break;
799 }
800
801 return insn;
802 }
803
804 /* Called when we see an 'f' flag. */
805
806 static arc_insn
insert_flag(insn,operand,mods,reg,value,errmsg)807 insert_flag (insn, operand, mods, reg, value, errmsg)
808 arc_insn insn;
809 const struct arc_operand *operand ATTRIBUTE_UNUSED;
810 int mods ATTRIBUTE_UNUSED;
811 const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
812 long value ATTRIBUTE_UNUSED;
813 const char **errmsg ATTRIBUTE_UNUSED;
814 {
815 /* We can't store anything in the insn until we've parsed the registers.
816 Just record the fact that we've got this flag. `insert_reg' will use it
817 to store the correct value (ARC_REG_SHIMM_UPDATE or bit 0x100). */
818 flag_p = 1;
819 return insn;
820 }
821
822 /* Called when we see an nullify condition. */
823
824 static arc_insn
insert_nullify(insn,operand,mods,reg,value,errmsg)825 insert_nullify (insn, operand, mods, reg, value, errmsg)
826 arc_insn insn;
827 const struct arc_operand *operand;
828 int mods ATTRIBUTE_UNUSED;
829 const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
830 long value;
831 const char **errmsg ATTRIBUTE_UNUSED;
832 {
833 nullify_p = 1;
834 insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
835 nullify = value;
836 return insn;
837 }
838
839 /* Called after completely building an insn to ensure the 'f' flag gets set
840 properly. This is needed because we don't know how to set this flag until
841 we've parsed the registers. */
842
843 static arc_insn
insert_flagfinish(insn,operand,mods,reg,value,errmsg)844 insert_flagfinish (insn, operand, mods, reg, value, errmsg)
845 arc_insn insn;
846 const struct arc_operand *operand;
847 int mods ATTRIBUTE_UNUSED;
848 const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
849 long value ATTRIBUTE_UNUSED;
850 const char **errmsg ATTRIBUTE_UNUSED;
851 {
852 if (flag_p && !flagshimm_handled_p)
853 {
854 if (shimm_p)
855 abort ();
856 flagshimm_handled_p = 1;
857 insn |= (1 << operand->shift);
858 }
859 return insn;
860 }
861
862 /* Called when we see a conditional flag (eg: .eq). */
863
864 static arc_insn
insert_cond(insn,operand,mods,reg,value,errmsg)865 insert_cond (insn, operand, mods, reg, value, errmsg)
866 arc_insn insn;
867 const struct arc_operand *operand;
868 int mods ATTRIBUTE_UNUSED;
869 const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
870 long value;
871 const char **errmsg ATTRIBUTE_UNUSED;
872 {
873 cond_p = 1;
874 insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
875 return insn;
876 }
877
878 /* Used in the "j" instruction to prevent constants from being interpreted as
879 shimm values (which the jump insn doesn't accept). This can also be used
880 to force the use of limm values in other situations (eg: ld r0,[foo] uses
881 this).
882 ??? The mechanism is sound. Access to it is a bit klunky right now. */
883
884 static arc_insn
insert_forcelimm(insn,operand,mods,reg,value,errmsg)885 insert_forcelimm (insn, operand, mods, reg, value, errmsg)
886 arc_insn insn;
887 const struct arc_operand *operand ATTRIBUTE_UNUSED;
888 int mods ATTRIBUTE_UNUSED;
889 const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
890 long value ATTRIBUTE_UNUSED;
891 const char **errmsg ATTRIBUTE_UNUSED;
892 {
893 cond_p = 1;
894 return insn;
895 }
896
897 static arc_insn
insert_addr_wb(insn,operand,mods,reg,value,errmsg)898 insert_addr_wb (insn, operand, mods, reg, value, errmsg)
899 arc_insn insn;
900 const struct arc_operand *operand;
901 int mods ATTRIBUTE_UNUSED;
902 const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
903 long value ATTRIBUTE_UNUSED;
904 const char **errmsg ATTRIBUTE_UNUSED;
905 {
906 addrwb_p = 1 << operand->shift;
907 return insn;
908 }
909
910 static arc_insn
insert_base(insn,operand,mods,reg,value,errmsg)911 insert_base (insn, operand, mods, reg, value, errmsg)
912 arc_insn insn;
913 const struct arc_operand *operand;
914 int mods;
915 const struct arc_operand_value *reg;
916 long value;
917 const char **errmsg;
918 {
919 if (reg != NULL)
920 {
921 arc_insn myinsn;
922 myinsn = insert_reg (0, operand,mods, reg, value, errmsg) >> operand->shift;
923 insn |= B(myinsn);
924 ls_operand[LS_BASE] = OP_REG;
925 }
926 else if (ARC_SHIMM_CONST_P (value) && !cond_p)
927 {
928 if (shimm_p && value != shimm)
929 {
930 /* convert the previous shimm operand to a limm. */
931 limm_p = 1;
932 limm = shimm;
933 insn &= ~C(-1); /* we know where the value is in insn. */
934 insn |= C(ARC_REG_LIMM);
935 ls_operand[LS_VALUE] = OP_LIMM;
936 }
937 insn |= ARC_REG_SHIMM << operand->shift;
938 shimm_p = 1;
939 shimm = value;
940 ls_operand[LS_BASE] = OP_SHIMM;
941 ls_operand[LS_OFFSET] = OP_SHIMM;
942 }
943 else
944 {
945 if (limm_p && value != limm)
946 {
947 *errmsg = "too many long constants";
948 return insn;
949 }
950 limm_p = 1;
951 limm = value;
952 insn |= B(ARC_REG_LIMM);
953 ls_operand[LS_BASE] = OP_LIMM;
954 }
955
956 return insn;
957 }
958
959 /* Used in ld/st insns to handle the offset field. We don't try to
960 match operand syntax here. we catch bad combinations later. */
961
962 static arc_insn
insert_offset(insn,operand,mods,reg,value,errmsg)963 insert_offset (insn, operand, mods, reg, value, errmsg)
964 arc_insn insn;
965 const struct arc_operand *operand;
966 int mods;
967 const struct arc_operand_value *reg;
968 long value;
969 const char **errmsg;
970 {
971 long minval, maxval;
972
973 if (reg != NULL)
974 {
975 arc_insn myinsn;
976 myinsn = insert_reg (0,operand,mods,reg,value,errmsg) >> operand->shift;
977 ls_operand[LS_OFFSET] = OP_REG;
978 if (operand->flags & ARC_OPERAND_LOAD) /* not if store, catch it later. */
979 if ((insn & I(-1)) != I(1)) /* not if opcode == 1, catch it later. */
980 insn |= C(myinsn);
981 }
982 else
983 {
984 /* This is *way* more general than necessary, but maybe some day it'll
985 be useful. */
986 if (operand->flags & ARC_OPERAND_SIGNED)
987 {
988 minval = -(1 << (operand->bits - 1));
989 maxval = (1 << (operand->bits - 1)) - 1;
990 }
991 else
992 {
993 minval = 0;
994 maxval = (1 << operand->bits) - 1;
995 }
996 if ((cond_p && !limm_p) || (value < minval || value > maxval))
997 {
998 if (limm_p && value != limm)
999 {
1000 *errmsg = "too many long constants";
1001 }
1002 else
1003 {
1004 limm_p = 1;
1005 limm = value;
1006 if (operand->flags & ARC_OPERAND_STORE)
1007 insn |= B(ARC_REG_LIMM);
1008 if (operand->flags & ARC_OPERAND_LOAD)
1009 insn |= C(ARC_REG_LIMM);
1010 ls_operand[LS_OFFSET] = OP_LIMM;
1011 }
1012 }
1013 else
1014 {
1015 if ((value < minval || value > maxval))
1016 *errmsg = "need too many limms";
1017 else if (shimm_p && value != shimm)
1018 {
1019 /* check for bad operand combinations before we lose info about them. */
1020 if ((insn & I(-1)) == I(1))
1021 {
1022 *errmsg = "to many shimms in load";
1023 goto out;
1024 }
1025 if (limm_p && operand->flags & ARC_OPERAND_LOAD)
1026 {
1027 *errmsg = "too many long constants";
1028 goto out;
1029 }
1030 /* convert what we thought was a shimm to a limm. */
1031 limm_p = 1;
1032 limm = shimm;
1033 if (ls_operand[LS_VALUE] == OP_SHIMM && operand->flags & ARC_OPERAND_STORE)
1034 {
1035 insn &= ~C(-1);
1036 insn |= C(ARC_REG_LIMM);
1037 ls_operand[LS_VALUE] = OP_LIMM;
1038 }
1039 if (ls_operand[LS_BASE] == OP_SHIMM && operand->flags & ARC_OPERAND_STORE)
1040 {
1041 insn &= ~B(-1);
1042 insn |= B(ARC_REG_LIMM);
1043 ls_operand[LS_BASE] = OP_LIMM;
1044 }
1045 }
1046 shimm = value;
1047 shimm_p = 1;
1048 ls_operand[LS_OFFSET] = OP_SHIMM;
1049 }
1050 }
1051 out:
1052 return insn;
1053 }
1054
1055 /* Used in st insns to do final disasemble syntax check. */
1056
1057 static long
extract_st_syntax(insn,operand,mods,opval,invalid)1058 extract_st_syntax (insn, operand, mods, opval, invalid)
1059 arc_insn *insn;
1060 const struct arc_operand *operand ATTRIBUTE_UNUSED;
1061 int mods ATTRIBUTE_UNUSED;
1062 const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
1063 int *invalid;
1064 {
1065 #define ST_SYNTAX(V,B,O) \
1066 ((ls_operand[LS_VALUE] == (V) && \
1067 ls_operand[LS_BASE] == (B) && \
1068 ls_operand[LS_OFFSET] == (O)))
1069
1070 if (!((ST_SYNTAX(OP_REG,OP_REG,OP_NONE) && (insn[0] & 511) == 0)
1071 || ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE)
1072 || (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0)
1073 || (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (insn[0] & 511) == 0)
1074 || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE)
1075 || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_SHIMM)
1076 || ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM)
1077 || (ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE) && (insn[0] & 511) == 0)
1078 || ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
1079 || ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
1080 || ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM)
1081 || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM)
1082 || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE)
1083 || ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM)))
1084 *invalid = 1;
1085 return 0;
1086 }
1087
1088 int
arc_limm_fixup_adjust(insn)1089 arc_limm_fixup_adjust(insn)
1090 arc_insn insn;
1091 {
1092 int retval = 0;
1093
1094 /* check for st shimm,[limm]. */
1095 if ((insn & (I(-1) | C(-1) | B(-1))) ==
1096 (I(2) | C(ARC_REG_SHIMM) | B(ARC_REG_LIMM)))
1097 {
1098 retval = insn & 0x1ff;
1099 if (retval & 0x100) /* sign extend 9 bit offset. */
1100 retval |= ~0x1ff;
1101 }
1102 return -retval; /* negate offset for return. */
1103 }
1104
1105 /* Used in st insns to do final syntax check. */
1106
1107 static arc_insn
insert_st_syntax(insn,operand,mods,reg,value,errmsg)1108 insert_st_syntax (insn, operand, mods, reg, value, errmsg)
1109 arc_insn insn;
1110 const struct arc_operand *operand ATTRIBUTE_UNUSED;
1111 int mods ATTRIBUTE_UNUSED;
1112 const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
1113 long value ATTRIBUTE_UNUSED;
1114 const char **errmsg;
1115 {
1116 if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm != 0)
1117 {
1118 /* change an illegal insn into a legal one, it's easier to
1119 do it here than to try to handle it during operand scan. */
1120 limm_p = 1;
1121 limm = shimm;
1122 shimm_p = 0;
1123 shimm = 0;
1124 insn = insn & ~(C(-1) | 511);
1125 insn |= ARC_REG_LIMM << ARC_SHIFT_REGC;
1126 ls_operand[LS_VALUE] = OP_LIMM;
1127 }
1128
1129 if (ST_SYNTAX(OP_REG,OP_SHIMM,OP_NONE) || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_NONE))
1130 {
1131 /* try to salvage this syntax. */
1132 if (shimm & 0x1) /* odd shimms won't work. */
1133 {
1134 if (limm_p) /* do we have a limm already? */
1135 {
1136 *errmsg = "impossible store";
1137 }
1138 limm_p = 1;
1139 limm = shimm;
1140 shimm = 0;
1141 shimm_p = 0;
1142 insn = insn & ~(B(-1) | 511);
1143 insn |= B(ARC_REG_LIMM);
1144 ls_operand[LS_BASE] = OP_LIMM;
1145 }
1146 else
1147 {
1148 shimm >>= 1;
1149 insn = insn & ~511;
1150 insn |= shimm;
1151 ls_operand[LS_OFFSET] = OP_SHIMM;
1152 }
1153 }
1154 if (ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE))
1155 {
1156 limm += arc_limm_fixup_adjust(insn);
1157 }
1158 if (!(ST_SYNTAX(OP_REG,OP_REG,OP_NONE)
1159 || ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE)
1160 || ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
1161 || ST_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
1162 || (ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_NONE) && (shimm == 0))
1163 || ST_SYNTAX(OP_SHIMM,OP_LIMM,OP_NONE)
1164 || ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE)
1165 || ST_SYNTAX(OP_SHIMM,OP_REG,OP_SHIMM)
1166 || ST_SYNTAX(OP_SHIMM,OP_SHIMM,OP_SHIMM)
1167 || ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM)
1168 || ST_SYNTAX(OP_LIMM,OP_REG,OP_NONE)
1169 || ST_SYNTAX(OP_LIMM,OP_REG,OP_SHIMM)))
1170 *errmsg = "st operand error";
1171 if (addrwb_p)
1172 {
1173 if (ls_operand[LS_BASE] != OP_REG)
1174 *errmsg = "address writeback not allowed";
1175 insn |= addrwb_p;
1176 }
1177 if (ST_SYNTAX(OP_SHIMM,OP_REG,OP_NONE) && shimm)
1178 *errmsg = "store value must be zero";
1179 return insn;
1180 }
1181
1182 /* Used in ld insns to do final syntax check. */
1183
1184 static arc_insn
insert_ld_syntax(insn,operand,mods,reg,value,errmsg)1185 insert_ld_syntax (insn, operand, mods, reg, value, errmsg)
1186 arc_insn insn;
1187 const struct arc_operand *operand ATTRIBUTE_UNUSED;
1188 int mods ATTRIBUTE_UNUSED;
1189 const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
1190 long value ATTRIBUTE_UNUSED;
1191 const char **errmsg;
1192 {
1193 #define LD_SYNTAX(D,B,O) \
1194 ((ls_operand[LS_DEST] == (D) && \
1195 ls_operand[LS_BASE] == (B) && \
1196 ls_operand[LS_OFFSET] == (O)))
1197
1198 int test = insn & I(-1);
1199
1200 if (!(test == I(1)))
1201 {
1202 if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM
1203 || ls_operand[LS_OFFSET] == OP_SHIMM))
1204 *errmsg = "invalid load/shimm insn";
1205 }
1206 if (!(LD_SYNTAX(OP_REG,OP_REG,OP_NONE)
1207 || LD_SYNTAX(OP_REG,OP_REG,OP_REG)
1208 || LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
1209 || (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1)))
1210 || (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1)))
1211 || LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
1212 || (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1)))))
1213 *errmsg = "ld operand error";
1214 if (addrwb_p)
1215 {
1216 if (ls_operand[LS_BASE] != OP_REG)
1217 *errmsg = "address writeback not allowed";
1218 insn |= addrwb_p;
1219 }
1220 return insn;
1221 }
1222
1223 /* Used in ld insns to do final syntax check. */
1224
1225 static long
extract_ld_syntax(insn,operand,mods,opval,invalid)1226 extract_ld_syntax (insn, operand, mods, opval, invalid)
1227 arc_insn *insn;
1228 const struct arc_operand *operand ATTRIBUTE_UNUSED;
1229 int mods ATTRIBUTE_UNUSED;
1230 const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
1231 int *invalid;
1232 {
1233 int test = insn[0] & I(-1);
1234
1235 if (!(test == I(1)))
1236 {
1237 if ((ls_operand[LS_DEST] == OP_SHIMM || ls_operand[LS_BASE] == OP_SHIMM
1238 || ls_operand[LS_OFFSET] == OP_SHIMM))
1239 *invalid = 1;
1240 }
1241 if (!((LD_SYNTAX(OP_REG,OP_REG,OP_NONE) && (test == I(1)))
1242 || LD_SYNTAX(OP_REG,OP_REG,OP_REG)
1243 || LD_SYNTAX(OP_REG,OP_REG,OP_SHIMM)
1244 || (LD_SYNTAX(OP_REG,OP_REG,OP_LIMM) && !(test == I(1)))
1245 || (LD_SYNTAX(OP_REG,OP_LIMM,OP_REG) && !(test == I(1)))
1246 || (LD_SYNTAX(OP_REG,OP_SHIMM,OP_NONE) && (shimm == 0))
1247 || LD_SYNTAX(OP_REG,OP_SHIMM,OP_SHIMM)
1248 || (LD_SYNTAX(OP_REG,OP_LIMM,OP_NONE) && (test == I(1)))))
1249 *invalid = 1;
1250 return 0;
1251 }
1252
1253 /* Called at the end of processing normal insns (eg: add) to insert a shimm
1254 value (if present) into the insn. */
1255
1256 static arc_insn
insert_shimmfinish(insn,operand,mods,reg,value,errmsg)1257 insert_shimmfinish (insn, operand, mods, reg, value, errmsg)
1258 arc_insn insn;
1259 const struct arc_operand *operand;
1260 int mods ATTRIBUTE_UNUSED;
1261 const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
1262 long value ATTRIBUTE_UNUSED;
1263 const char **errmsg ATTRIBUTE_UNUSED;
1264 {
1265 if (shimm_p)
1266 insn |= (shimm & ((1 << operand->bits) - 1)) << operand->shift;
1267 return insn;
1268 }
1269
1270 /* Called at the end of processing normal insns (eg: add) to insert a limm
1271 value (if present) into the insn.
1272
1273 Note that this function is only intended to handle instructions (with 4 byte
1274 immediate operands). It is not intended to handle data. */
1275
1276 /* ??? Actually, there's nothing for us to do as we can't call frag_more, the
1277 caller must do that. The extract fns take a pointer to two words. The
1278 insert fns could be converted and then we could do something useful, but
1279 then the reloc handlers would have to know to work on the second word of
1280 a 2 word quantity. That's too much so we don't handle them. */
1281
1282 static arc_insn
insert_limmfinish(insn,operand,mods,reg,value,errmsg)1283 insert_limmfinish (insn, operand, mods, reg, value, errmsg)
1284 arc_insn insn;
1285 const struct arc_operand *operand ATTRIBUTE_UNUSED;
1286 int mods ATTRIBUTE_UNUSED;
1287 const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
1288 long value ATTRIBUTE_UNUSED;
1289 const char **errmsg ATTRIBUTE_UNUSED;
1290 {
1291 #if 0
1292 if (limm_p)
1293 ; /* nothing to do, gas does it. */
1294 #endif
1295 return insn;
1296 }
1297
1298 static arc_insn
insert_jumpflags(insn,operand,mods,reg,value,errmsg)1299 insert_jumpflags (insn, operand, mods, reg, value, errmsg)
1300 arc_insn insn;
1301 const struct arc_operand *operand;
1302 int mods ATTRIBUTE_UNUSED;
1303 const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
1304 long value;
1305 const char **errmsg;
1306 {
1307 if (!flag_p)
1308 {
1309 *errmsg = "jump flags, but no .f seen";
1310 }
1311 if (!limm_p)
1312 {
1313 *errmsg = "jump flags, but no limm addr";
1314 }
1315 if (limm & 0xfc000000)
1316 {
1317 *errmsg = "flag bits of jump address limm lost";
1318 }
1319 if (limm & 0x03000000)
1320 {
1321 *errmsg = "attempt to set HR bits";
1322 }
1323 if ((value & ((1 << operand->bits) - 1)) != value)
1324 {
1325 *errmsg = "bad jump flags value";
1326 }
1327 jumpflags_p = 1;
1328 limm = ((limm & ((1 << operand->shift) - 1))
1329 | ((value & ((1 << operand->bits) - 1)) << operand->shift));
1330 return insn;
1331 }
1332
1333 /* Called at the end of unary operand macros to copy the B field to C. */
1334
1335 static arc_insn
insert_unopmacro(insn,operand,mods,reg,value,errmsg)1336 insert_unopmacro (insn, operand, mods, reg, value, errmsg)
1337 arc_insn insn;
1338 const struct arc_operand *operand;
1339 int mods ATTRIBUTE_UNUSED;
1340 const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
1341 long value ATTRIBUTE_UNUSED;
1342 const char **errmsg ATTRIBUTE_UNUSED;
1343 {
1344 insn |= ((insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) << operand->shift;
1345 return insn;
1346 }
1347
1348 /* Insert a relative address for a branch insn (b, bl, or lp). */
1349
1350 static arc_insn
insert_reladdr(insn,operand,mods,reg,value,errmsg)1351 insert_reladdr (insn, operand, mods, reg, value, errmsg)
1352 arc_insn insn;
1353 const struct arc_operand *operand;
1354 int mods ATTRIBUTE_UNUSED;
1355 const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
1356 long value;
1357 const char **errmsg;
1358 {
1359 if (value & 3)
1360 *errmsg = "branch address not on 4 byte boundary";
1361 insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift;
1362 return insn;
1363 }
1364
1365 /* Insert a limm value as a 26 bit address right shifted 2 into the insn.
1366
1367 Note that this function is only intended to handle instructions (with 4 byte
1368 immediate operands). It is not intended to handle data. */
1369
1370 /* ??? Actually, there's little for us to do as we can't call frag_more, the
1371 caller must do that. The extract fns take a pointer to two words. The
1372 insert fns could be converted and then we could do something useful, but
1373 then the reloc handlers would have to know to work on the second word of
1374 a 2 word quantity. That's too much so we don't handle them.
1375
1376 We do check for correct usage of the nullify suffix, or we
1377 set the default correctly, though. */
1378
1379 static arc_insn
insert_absaddr(insn,operand,mods,reg,value,errmsg)1380 insert_absaddr (insn, operand, mods, reg, value, errmsg)
1381 arc_insn insn;
1382 const struct arc_operand *operand ATTRIBUTE_UNUSED;
1383 int mods ATTRIBUTE_UNUSED;
1384 const struct arc_operand_value *reg ATTRIBUTE_UNUSED;
1385 long value ATTRIBUTE_UNUSED;
1386 const char **errmsg;
1387 {
1388 if (limm_p)
1389 {
1390 /* if it is a jump and link, .jd must be specified. */
1391 if (insn & R(-1,9,1))
1392 {
1393 if (!nullify_p)
1394 {
1395 insn |= 0x02 << 5; /* default nullify to .jd. */
1396 }
1397 else
1398 {
1399 if (nullify != 0x02)
1400 {
1401 *errmsg = "must specify .jd or no nullify suffix";
1402 }
1403 }
1404 }
1405 }
1406 return insn;
1407 }
1408
1409 /* Extraction functions.
1410
1411 The suffix extraction functions' return value is redundant since it can be
1412 obtained from (*OPVAL)->value. However, the boolean suffixes don't have
1413 a suffix table entry for the "false" case, so values of zero must be
1414 obtained from the return value (*OPVAL == NULL). */
1415
1416 static const struct arc_operand_value *lookup_register (int type, long regno);
1417
1418 /* Called by the disassembler before printing an instruction. */
1419
1420 void
arc_opcode_init_extract()1421 arc_opcode_init_extract ()
1422 {
1423 arc_opcode_init_insert();
1424 }
1425
1426 /* As we're extracting registers, keep an eye out for the 'f' indicator
1427 (ARC_REG_SHIMM_UPDATE). If we find a register (not a constant marker,
1428 like ARC_REG_SHIMM), set OPVAL so our caller will know this is a register.
1429
1430 We must also handle auxiliary registers for lr/sr insns. They are just
1431 constants with special names. */
1432
1433 static long
extract_reg(insn,operand,mods,opval,invalid)1434 extract_reg (insn, operand, mods, opval, invalid)
1435 arc_insn *insn;
1436 const struct arc_operand *operand;
1437 int mods;
1438 const struct arc_operand_value **opval;
1439 int *invalid ATTRIBUTE_UNUSED;
1440 {
1441 int regno;
1442 long value;
1443 enum operand op_type;
1444
1445 /* Get the register number. */
1446 regno = (*insn >> operand->shift) & ((1 << operand->bits) - 1);
1447
1448 /* Is it a constant marker? */
1449 if (regno == ARC_REG_SHIMM)
1450 {
1451 op_type = OP_SHIMM;
1452 /* always return zero if dest is a shimm mlm. */
1453
1454 if ('a' != operand->fmt)
1455 {
1456 value = *insn & 511;
1457 if ((operand->flags & ARC_OPERAND_SIGNED)
1458 && (value & 256))
1459 value -= 512;
1460 if (!flagshimm_handled_p)
1461 flag_p = 0;
1462 flagshimm_handled_p = 1;
1463 }
1464 else
1465 {
1466 value = 0;
1467 }
1468 }
1469 else if (regno == ARC_REG_SHIMM_UPDATE)
1470 {
1471 op_type = OP_SHIMM;
1472
1473 /* always return zero if dest is a shimm mlm. */
1474
1475 if ('a' != operand->fmt)
1476 {
1477 value = *insn & 511;
1478 if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256))
1479 value -= 512;
1480 }
1481 else
1482 {
1483 value = 0;
1484 }
1485 flag_p = 1;
1486 flagshimm_handled_p = 1;
1487 }
1488 else if (regno == ARC_REG_LIMM)
1489 {
1490 op_type = OP_LIMM;
1491 value = insn[1];
1492 limm_p = 1;
1493 /* if this is a jump instruction (j,jl), show new pc correctly. */
1494 if (0x07 == ((*insn & I(-1)) >> 27))
1495 {
1496 value = (value & 0xffffff);
1497 }
1498 }
1499 /* It's a register, set OPVAL (that's the only way we distinguish registers
1500 from constants here). */
1501 else
1502 {
1503 const struct arc_operand_value *reg = lookup_register (REG, regno);
1504 op_type = OP_REG;
1505
1506 if (reg == NULL)
1507 abort ();
1508 if (opval != NULL)
1509 *opval = reg;
1510 value = regno;
1511 }
1512
1513 /* If this field takes an auxiliary register, see if it's a known one. */
1514 if ((mods & ARC_MOD_AUXREG)
1515 && ARC_REG_CONSTANT_P (regno))
1516 {
1517 const struct arc_operand_value *reg = lookup_register (AUXREG, value);
1518
1519 /* This is really a constant, but tell the caller it has a special
1520 name. */
1521 if (reg != NULL && opval != NULL)
1522 *opval = reg;
1523 }
1524 switch(operand->fmt)
1525 {
1526 case 'a':
1527 ls_operand[LS_DEST] = op_type;
1528 break;
1529 case 's':
1530 ls_operand[LS_BASE] = op_type;
1531 break;
1532 case 'c':
1533 if ((insn[0]& I(-1)) == I(2))
1534 ls_operand[LS_VALUE] = op_type;
1535 else
1536 ls_operand[LS_OFFSET] = op_type;
1537 break;
1538 case 'o': case 'O':
1539 ls_operand[LS_OFFSET] = op_type;
1540 break;
1541 }
1542
1543 return value;
1544 }
1545
1546 /* Return the value of the "flag update" field for shimm insns.
1547 This value is actually stored in the register field. */
1548
1549 static long
extract_flag(insn,operand,mods,opval,invalid)1550 extract_flag (insn, operand, mods, opval, invalid)
1551 arc_insn *insn;
1552 const struct arc_operand *operand;
1553 int mods ATTRIBUTE_UNUSED;
1554 const struct arc_operand_value **opval;
1555 int *invalid ATTRIBUTE_UNUSED;
1556 {
1557 int f;
1558 const struct arc_operand_value *val;
1559
1560 if (flagshimm_handled_p)
1561 f = flag_p != 0;
1562 else
1563 f = (*insn & (1 << operand->shift)) != 0;
1564
1565 /* There is no text for zero values. */
1566 if (f == 0)
1567 return 0;
1568 flag_p = 1;
1569 val = arc_opcode_lookup_suffix (operand, 1);
1570 if (opval != NULL && val != NULL)
1571 *opval = val;
1572 return val->value;
1573 }
1574
1575 /* Extract the condition code (if it exists).
1576 If we've seen a shimm value in this insn (meaning that the insn can't have
1577 a condition code field), then we don't store anything in OPVAL and return
1578 zero. */
1579
1580 static long
extract_cond(insn,operand,mods,opval,invalid)1581 extract_cond (insn, operand, mods, opval, invalid)
1582 arc_insn *insn;
1583 const struct arc_operand *operand;
1584 int mods ATTRIBUTE_UNUSED;
1585 const struct arc_operand_value **opval;
1586 int *invalid ATTRIBUTE_UNUSED;
1587 {
1588 long cond;
1589 const struct arc_operand_value *val;
1590
1591 if (flagshimm_handled_p)
1592 return 0;
1593
1594 cond = (*insn >> operand->shift) & ((1 << operand->bits) - 1);
1595 val = arc_opcode_lookup_suffix (operand, cond);
1596
1597 /* Ignore NULL values of `val'. Several condition code values are
1598 reserved for extensions. */
1599 if (opval != NULL && val != NULL)
1600 *opval = val;
1601 return cond;
1602 }
1603
1604 /* Extract a branch address.
1605 We return the value as a real address (not right shifted by 2). */
1606
1607 static long
extract_reladdr(insn,operand,mods,opval,invalid)1608 extract_reladdr (insn, operand, mods, opval, invalid)
1609 arc_insn *insn;
1610 const struct arc_operand *operand;
1611 int mods ATTRIBUTE_UNUSED;
1612 const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
1613 int *invalid ATTRIBUTE_UNUSED;
1614 {
1615 long addr;
1616
1617 addr = (*insn >> operand->shift) & ((1 << operand->bits) - 1);
1618 if ((operand->flags & ARC_OPERAND_SIGNED)
1619 && (addr & (1 << (operand->bits - 1))))
1620 addr -= 1 << operand->bits;
1621 return addr << 2;
1622 }
1623
1624 /* extract the flags bits from a j or jl long immediate. */
1625 static long
extract_jumpflags(insn,operand,mods,opval,invalid)1626 extract_jumpflags(insn, operand, mods, opval, invalid)
1627 arc_insn *insn;
1628 const struct arc_operand *operand;
1629 int mods ATTRIBUTE_UNUSED;
1630 const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
1631 int *invalid;
1632 {
1633 if (!flag_p || !limm_p)
1634 *invalid = 1;
1635 return ((flag_p && limm_p)
1636 ? (insn[1] >> operand->shift) & ((1 << operand->bits) -1): 0);
1637 }
1638
1639 /* extract st insn's offset. */
1640
1641 static long
extract_st_offset(insn,operand,mods,opval,invalid)1642 extract_st_offset (insn, operand, mods, opval, invalid)
1643 arc_insn *insn;
1644 const struct arc_operand *operand;
1645 int mods ATTRIBUTE_UNUSED;
1646 const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
1647 int *invalid;
1648 {
1649 int value = 0;
1650
1651 if (ls_operand[LS_VALUE] != OP_SHIMM || ls_operand[LS_BASE] != OP_LIMM)
1652 {
1653 value = insn[0] & 511;
1654 if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256))
1655 value -= 512;
1656 if (value)
1657 ls_operand[LS_OFFSET] = OP_SHIMM;
1658 }
1659 else
1660 {
1661 *invalid = 1;
1662 }
1663 return(value);
1664 }
1665
1666 /* extract ld insn's offset. */
1667
1668 static long
extract_ld_offset(insn,operand,mods,opval,invalid)1669 extract_ld_offset (insn, operand, mods, opval, invalid)
1670 arc_insn *insn;
1671 const struct arc_operand *operand;
1672 int mods;
1673 const struct arc_operand_value **opval;
1674 int *invalid;
1675 {
1676 int test = insn[0] & I(-1);
1677 int value;
1678
1679 if (test)
1680 {
1681 value = insn[0] & 511;
1682 if ((operand->flags & ARC_OPERAND_SIGNED) && (value & 256))
1683 value -= 512;
1684 if (value)
1685 ls_operand[LS_OFFSET] = OP_SHIMM;
1686 return(value);
1687 }
1688 /* if it isn't in the insn, it's concealed behind reg 'c'. */
1689 return extract_reg (insn, &arc_operands[arc_operand_map['c']],
1690 mods, opval, invalid);
1691 }
1692
1693 /* The only thing this does is set the `invalid' flag if B != C.
1694 This is needed because the "mov" macro appears before it's real insn "and"
1695 and we don't want the disassembler to confuse them. */
1696
1697 static long
extract_unopmacro(insn,operand,mods,opval,invalid)1698 extract_unopmacro (insn, operand, mods, opval, invalid)
1699 arc_insn *insn;
1700 const struct arc_operand *operand ATTRIBUTE_UNUSED;
1701 int mods ATTRIBUTE_UNUSED;
1702 const struct arc_operand_value **opval ATTRIBUTE_UNUSED;
1703 int *invalid;
1704 {
1705 /* This misses the case where B == ARC_REG_SHIMM_UPDATE &&
1706 C == ARC_REG_SHIMM (or vice versa). No big deal. Those insns will get
1707 printed as "and"s. */
1708 if (((*insn >> ARC_SHIFT_REGB) & ARC_MASK_REG)
1709 != ((*insn >> ARC_SHIFT_REGC) & ARC_MASK_REG))
1710 if (invalid != NULL)
1711 *invalid = 1;
1712 return 0;
1713 }
1714
1715 /* Utility for the extraction functions to return the index into
1716 `arc_suffixes'. */
1717
1718 const struct arc_operand_value *
arc_opcode_lookup_suffix(type,value)1719 arc_opcode_lookup_suffix (type, value)
1720 const struct arc_operand *type;
1721 int value;
1722 {
1723 register const struct arc_operand_value *v,*end;
1724 struct arc_ext_operand_value *ext_oper = arc_ext_operands;
1725
1726 while (ext_oper)
1727 {
1728 if (type == &arc_operands[ext_oper->operand.type]
1729 && value == ext_oper->operand.value)
1730 return (&ext_oper->operand);
1731 ext_oper = ext_oper->next;
1732 }
1733
1734 /* ??? This is a little slow and can be speeded up. */
1735
1736 for (v = arc_suffixes, end = arc_suffixes + arc_suffixes_count; v < end; ++v)
1737 if (type == &arc_operands[v->type]
1738 && value == v->value)
1739 return v;
1740 return 0;
1741 }
1742
1743 static const struct arc_operand_value *
lookup_register(type,regno)1744 lookup_register (type, regno)
1745 int type;
1746 long regno;
1747 {
1748 register const struct arc_operand_value *r,*end;
1749 struct arc_ext_operand_value *ext_oper = arc_ext_operands;
1750
1751 while (ext_oper)
1752 {
1753 if (ext_oper->operand.type == type && ext_oper->operand.value == regno)
1754 return (&ext_oper->operand);
1755 ext_oper = ext_oper->next;
1756 }
1757
1758 if (type == REG)
1759 return &arc_reg_names[regno];
1760
1761 /* ??? This is a little slow and can be speeded up. */
1762
1763 for (r = arc_reg_names, end = arc_reg_names + arc_reg_names_count;
1764 r < end; ++r)
1765 if (type == r->type && regno == r->value)
1766 return r;
1767 return 0;
1768 }
1769
1770 int
arc_insn_is_j(insn)1771 arc_insn_is_j(insn)
1772 arc_insn insn;
1773 {
1774 return (insn & (I(-1))) == I(0x7);
1775 }
1776
1777 int
arc_insn_not_jl(insn)1778 arc_insn_not_jl(insn)
1779 arc_insn insn;
1780 {
1781 return ((insn & (I(-1)|A(-1)|C(-1)|R(-1,7,1)|R(-1,9,1)))
1782 != (I(0x7) | R(-1,9,1)));
1783 }
1784
1785 int
arc_operand_type(int opertype)1786 arc_operand_type(int opertype)
1787 {
1788 switch (opertype)
1789 {
1790 case 0:
1791 return(COND);
1792 break;
1793 case 1:
1794 return(REG);
1795 break;
1796 case 2:
1797 return(AUXREG);
1798 break;
1799 }
1800 return -1;
1801 }
1802
1803 struct arc_operand_value *
get_ext_suffix(s)1804 get_ext_suffix(s)
1805 char *s;
1806 {
1807 struct arc_ext_operand_value *suffix = arc_ext_operands;
1808
1809 while (suffix)
1810 {
1811 if ((COND == suffix->operand.type)
1812 && !strcmp(s,suffix->operand.name))
1813 return(&suffix->operand);
1814 suffix = suffix->next;
1815 }
1816 return NULL;
1817 }
1818
1819 int
arc_get_noshortcut_flag()1820 arc_get_noshortcut_flag()
1821 {
1822 return ARC_REGISTER_NOSHORT_CUT;
1823 }
1824