1 /* Definitions for GCC.  Part of the machine description for CRIS.
2    Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
3    Free Software Foundation, Inc.
4    Contributed by Axis Communications.  Written by Hans-Peter Nilsson.
5 
6 This file is part of GCC.
7 
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12 
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 GNU General Public License for more details.
17 
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING.  If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA.  */
22 
23 #include "config.h"
24 #include "system.h"
25 #include "coretypes.h"
26 #include "tm.h"
27 #include "rtl.h"
28 #include "regs.h"
29 #include "hard-reg-set.h"
30 #include "real.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
34 #include "flags.h"
35 #include "tree.h"
36 #include "expr.h"
37 #include "except.h"
38 #include "function.h"
39 #include "toplev.h"
40 #include "recog.h"
41 #include "reload.h"
42 #include "tm_p.h"
43 #include "debug.h"
44 #include "output.h"
45 #include "target.h"
46 #include "target-def.h"
47 #include "ggc.h"
48 #include "optabs.h"
49 
50 /* Usable when we have an amount to add or subtract, and want the
51    optimal size of the insn.  */
52 #define ADDITIVE_SIZE_MODIFIER(size) \
53  ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d")
54 
55 #define ASSERT_PLT_UNSPEC(x)						\
56   CRIS_ASSERT (XINT (x, 1) == CRIS_UNSPEC_PLT				\
57 	       && ((GET_CODE (XVECEXP (x, 0, 0)) == SYMBOL_REF)		\
58 		   || GET_CODE (XVECEXP (x, 0, 0)) == LABEL_REF))
59 
60 #define LOSE_AND_RETURN(msgid, x)			\
61   do						\
62     {						\
63       cris_operand_lossage (msgid, x);		\
64       return;					\
65     } while (0)
66 
67 enum cris_retinsn_type
68  { CRIS_RETINSN_UNKNOWN = 0, CRIS_RETINSN_RET, CRIS_RETINSN_JUMP };
69 
70 /* Per-function machine data.  */
71 struct machine_function GTY(())
72  {
73    int needs_return_address_on_stack;
74 
75    /* This is the number of registers we save in the prologue due to
76       stdarg.  */
77    int stdarg_regs;
78 
79    enum cris_retinsn_type return_type;
80  };
81 
82 /* This little fix suppresses the 'u' or 's' when '%e' in assembly
83    pattern.  */
84 static char cris_output_insn_is_bound = 0;
85 
86 /* In code for output macros, this is how we know whether e.g. constant
87    goes in code or in a static initializer.  */
88 static int in_code = 0;
89 
90 /* Fix for reg_overlap_mentioned_p.  */
91 static int cris_reg_overlap_mentioned_p (rtx, rtx);
92 
93 static void cris_print_base (rtx, FILE *);
94 
95 static void cris_print_index (rtx, FILE *);
96 
97 static void cris_output_addr_const (FILE *, rtx);
98 
99 static struct machine_function * cris_init_machine_status (void);
100 
101 static rtx cris_struct_value_rtx (tree, int);
102 
103 static void cris_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
104 					 tree type, int *, int);
105 
106 static int cris_initial_frame_pointer_offset (void);
107 
108 static int saved_regs_mentioned (rtx);
109 
110 static void cris_operand_lossage (const char *, rtx);
111 
112 static int cris_reg_saved_in_regsave_area  (unsigned int, bool);
113 
114 static void cris_asm_output_mi_thunk
115   (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
116 
117 static void cris_file_start (void);
118 static void cris_init_libfuncs (void);
119 
120 static bool cris_rtx_costs (rtx, int, int, int *);
121 static int cris_address_cost (rtx);
122 static bool cris_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
123 				    tree, bool);
124 static int cris_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
125 				   tree, bool);
126 static tree cris_md_asm_clobbers (tree, tree, tree);
127 
128 static bool cris_handle_option (size_t, const char *, int);
129 
130 /* This is the parsed result of the "-max-stack-stackframe=" option.  If
131    it (still) is zero, then there was no such option given.  */
132 int cris_max_stackframe = 0;
133 
134 /* This is the parsed result of the "-march=" option, if given.  */
135 int cris_cpu_version = CRIS_DEFAULT_CPU_VERSION;
136 
137 #undef TARGET_ASM_ALIGNED_HI_OP
138 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
139 #undef TARGET_ASM_ALIGNED_SI_OP
140 #define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t"
141 #undef TARGET_ASM_ALIGNED_DI_OP
142 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
143 
144 /* We need to define these, since the 2byte, 4byte, 8byte op:s are only
145    available in ELF.  These "normal" pseudos do not have any alignment
146    constraints or side-effects.  */
147 #undef TARGET_ASM_UNALIGNED_HI_OP
148 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
149 
150 #undef TARGET_ASM_UNALIGNED_SI_OP
151 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
152 
153 #undef TARGET_ASM_UNALIGNED_DI_OP
154 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
155 
156 #undef TARGET_ASM_OUTPUT_MI_THUNK
157 #define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk
158 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
159 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
160 
161 #undef TARGET_ASM_FILE_START
162 #define TARGET_ASM_FILE_START cris_file_start
163 
164 #undef TARGET_INIT_LIBFUNCS
165 #define TARGET_INIT_LIBFUNCS cris_init_libfuncs
166 
167 #undef TARGET_RTX_COSTS
168 #define TARGET_RTX_COSTS cris_rtx_costs
169 #undef TARGET_ADDRESS_COST
170 #define TARGET_ADDRESS_COST cris_address_cost
171 
172 #undef TARGET_PROMOTE_FUNCTION_ARGS
173 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
174 #undef TARGET_STRUCT_VALUE_RTX
175 #define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx
176 #undef TARGET_SETUP_INCOMING_VARARGS
177 #define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs
178 #undef TARGET_PASS_BY_REFERENCE
179 #define TARGET_PASS_BY_REFERENCE cris_pass_by_reference
180 #undef TARGET_ARG_PARTIAL_BYTES
181 #define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes
182 #undef TARGET_MD_ASM_CLOBBERS
183 #define TARGET_MD_ASM_CLOBBERS cris_md_asm_clobbers
184 #undef TARGET_DEFAULT_TARGET_FLAGS
185 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | CRIS_SUBTARGET_DEFAULT)
186 #undef TARGET_HANDLE_OPTION
187 #define TARGET_HANDLE_OPTION cris_handle_option
188 
189 struct gcc_target targetm = TARGET_INITIALIZER;
190 
191 /* Helper for cris_load_multiple_op and cris_ret_movem_op.  */
192 
193 bool
cris_movem_load_rest_p(rtx op,int offs)194 cris_movem_load_rest_p (rtx op, int offs)
195 {
196   unsigned int reg_count = XVECLEN (op, 0) - offs;
197   rtx src_addr;
198   int i;
199   rtx elt;
200   int setno;
201   int regno_dir = 1;
202   unsigned int regno = 0;
203 
204   /* Perform a quick check so we don't blow up below.  FIXME: Adjust for
205      other than (MEM reg).  */
206   if (reg_count <= 1
207       || GET_CODE (XVECEXP (op, 0, offs)) != SET
208       || GET_CODE (SET_DEST (XVECEXP (op, 0, offs))) != REG
209       || GET_CODE (SET_SRC (XVECEXP (op, 0, offs))) != MEM)
210     return false;
211 
212   /* Check a possible post-inc indicator.  */
213   if (GET_CODE (SET_SRC (XVECEXP (op, 0, offs + 1))) == PLUS)
214     {
215       rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 0);
216       rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, offs + 1)), 1);
217 
218       reg_count--;
219 
220       if (reg_count == 1
221 	  || !REG_P (reg)
222 	  || !REG_P (SET_DEST (XVECEXP (op, 0, offs + 1)))
223 	  || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, offs + 1)))
224 	  || GET_CODE (inc) != CONST_INT
225 	  || INTVAL (inc) != (HOST_WIDE_INT) reg_count * 4)
226 	return false;
227       i = offs + 2;
228     }
229   else
230     i = offs + 1;
231 
232   /* FIXME: These two only for pre-v32.  */
233   regno_dir = -1;
234   regno = reg_count - 1;
235 
236   elt = XVECEXP (op, 0, offs);
237   src_addr = XEXP (SET_SRC (elt), 0);
238 
239   if (GET_CODE (elt) != SET
240       || GET_CODE (SET_DEST (elt)) != REG
241       || GET_MODE (SET_DEST (elt)) != SImode
242       || REGNO (SET_DEST (elt)) != regno
243       || GET_CODE (SET_SRC (elt)) != MEM
244       || GET_MODE (SET_SRC (elt)) != SImode
245       || !memory_address_p (SImode, src_addr))
246     return false;
247 
248   for (setno = 1; i < XVECLEN (op, 0); setno++, i++)
249     {
250       rtx elt = XVECEXP (op, 0, i);
251       regno += regno_dir;
252 
253       if (GET_CODE (elt) != SET
254 	  || GET_CODE (SET_DEST (elt)) != REG
255 	  || GET_MODE (SET_DEST (elt)) != SImode
256 	  || REGNO (SET_DEST (elt)) != regno
257 	  || GET_CODE (SET_SRC (elt)) != MEM
258 	  || GET_MODE (SET_SRC (elt)) != SImode
259 	  || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
260 	  || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
261 	  || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
262 	  || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != setno * 4)
263 	return false;
264     }
265 
266   return true;
267 }
268 
269 /* Worker function for predicate for the parallel contents in a movem
270    to-memory.  */
271 
272 bool
cris_store_multiple_op_p(rtx op)273 cris_store_multiple_op_p (rtx op)
274 {
275   int reg_count = XVECLEN (op, 0);
276   rtx dest;
277   rtx dest_addr;
278   rtx dest_base;
279   int i;
280   rtx elt;
281   int setno;
282   int regno_dir = 1;
283   int regno = 0;
284   int offset = 0;
285 
286   /* Perform a quick check so we don't blow up below.  FIXME: Adjust for
287      other than (MEM reg) and (MEM (PLUS reg const)).  */
288   if (reg_count <= 1)
289     return false;
290 
291   elt = XVECEXP (op, 0, 0);
292 
293   if (GET_CODE (elt) != SET)
294     return  false;
295 
296   dest = SET_DEST (elt);
297 
298   if (GET_CODE (SET_SRC (elt)) != REG
299       || GET_CODE (dest) != MEM)
300     return false;
301 
302   dest_addr = XEXP (dest, 0);
303 
304   /* Check a possible post-inc indicator.  */
305   if (GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) == PLUS)
306     {
307       rtx reg = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 0);
308       rtx inc = XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1);
309 
310       reg_count--;
311 
312       if (reg_count == 1
313 	  || !REG_P (reg)
314 	  || !REG_P (SET_DEST (XVECEXP (op, 0, 1)))
315 	  || REGNO (reg) != REGNO (SET_DEST (XVECEXP (op, 0, 1)))
316 	  || GET_CODE (inc) != CONST_INT
317 	  /* Support increment by number of registers, and by the offset
318 	     of the destination, if it has the form (MEM (PLUS reg
319 	     offset)).  */
320 	  || !((REG_P (dest_addr)
321 		&& REGNO (dest_addr) == REGNO (reg)
322 		&& INTVAL (inc) == (HOST_WIDE_INT) reg_count * 4)
323 	       || (GET_CODE (dest_addr) == PLUS
324 		   && REG_P (XEXP (dest_addr, 0))
325 		   && REGNO (XEXP (dest_addr, 0)) == REGNO (reg)
326 		   && GET_CODE (XEXP (dest_addr, 1)) == CONST_INT
327 		   && INTVAL (XEXP (dest_addr, 1)) == INTVAL (inc))))
328 	return false;
329 
330       i = 2;
331     }
332   else
333     i = 1;
334 
335   /* FIXME: These two only for pre-v32.  */
336   regno_dir = -1;
337   regno = reg_count - 1;
338 
339   if (GET_CODE (elt) != SET
340       || GET_CODE (SET_SRC (elt)) != REG
341       || GET_MODE (SET_SRC (elt)) != SImode
342       || REGNO (SET_SRC (elt)) != (unsigned int) regno
343       || GET_CODE (SET_DEST (elt)) != MEM
344       || GET_MODE (SET_DEST (elt)) != SImode)
345     return false;
346 
347   if (REG_P (dest_addr))
348     {
349       dest_base = dest_addr;
350       offset = 0;
351     }
352   else if (GET_CODE (dest_addr) == PLUS
353 	   && REG_P (XEXP (dest_addr, 0))
354 	   && GET_CODE (XEXP (dest_addr, 1)) == CONST_INT)
355     {
356       dest_base = XEXP (dest_addr, 0);
357       offset = INTVAL (XEXP (dest_addr, 1));
358     }
359   else
360     return false;
361 
362   for (setno = 1; i < XVECLEN (op, 0); setno++, i++)
363     {
364       rtx elt = XVECEXP (op, 0, i);
365       regno += regno_dir;
366 
367       if (GET_CODE (elt) != SET
368 	  || GET_CODE (SET_SRC (elt)) != REG
369 	  || GET_MODE (SET_SRC (elt)) != SImode
370 	  || REGNO (SET_SRC (elt)) != (unsigned int) regno
371 	  || GET_CODE (SET_DEST (elt)) != MEM
372 	  || GET_MODE (SET_DEST (elt)) != SImode
373 	  || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
374 	  || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_base)
375 	  || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
376 	  || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != setno * 4 + offset)
377 	return false;
378     }
379 
380   return true;
381 }
382 
383 /* The CONDITIONAL_REGISTER_USAGE worker.  */
384 
385 void
cris_conditional_register_usage(void)386 cris_conditional_register_usage (void)
387 {
388   /* FIXME: This isn't nice.  We should be able to use that register for
389      something else if the PIC table isn't needed.  */
390   if (flag_pic)
391     fixed_regs[PIC_OFFSET_TABLE_REGNUM]
392       = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
393 
394   if (TARGET_HAS_MUL_INSNS)
395     fixed_regs[CRIS_MOF_REGNUM] = 0;
396 
397   /* On early versions, we must use the 16-bit condition-code register,
398      which has another name.  */
399   if (cris_cpu_version < 8)
400     reg_names[CRIS_CC0_REGNUM] = "ccr";
401 }
402 
403 /* Return current_function_uses_pic_offset_table.  For use in cris.md,
404    since some generated files do not include function.h.  */
405 
406 int
cris_cfun_uses_pic_table(void)407 cris_cfun_uses_pic_table (void)
408 {
409   return current_function_uses_pic_offset_table;
410 }
411 
412 /* Given an rtx, return the text string corresponding to the CODE of X.
413    Intended for use in the assembly language output section of a
414    define_insn.  */
415 
416 const char *
cris_op_str(rtx x)417 cris_op_str (rtx x)
418 {
419   cris_output_insn_is_bound = 0;
420   switch (GET_CODE (x))
421     {
422     case PLUS:
423       return "add";
424       break;
425 
426     case MINUS:
427       return "sub";
428       break;
429 
430     case MULT:
431       /* This function is for retrieving a part of an instruction name for
432 	 an operator, for immediate output.  If that ever happens for
433 	 MULT, we need to apply TARGET_MUL_BUG in the caller.  Make sure
434 	 we notice.  */
435       internal_error ("MULT case in cris_op_str");
436       break;
437 
438     case DIV:
439       return "div";
440       break;
441 
442     case AND:
443       return "and";
444       break;
445 
446     case IOR:
447       return "or";
448       break;
449 
450     case XOR:
451       return "xor";
452       break;
453 
454     case NOT:
455       return "not";
456       break;
457 
458     case ASHIFT:
459       return "lsl";
460       break;
461 
462     case LSHIFTRT:
463       return "lsr";
464       break;
465 
466     case ASHIFTRT:
467       return "asr";
468       break;
469 
470     case UMIN:
471       /* Used to control the sign/zero-extend character for the 'E' modifier.
472 	 BOUND has none.  */
473       cris_output_insn_is_bound = 1;
474       return "bound";
475       break;
476 
477     default:
478       return "Unknown operator";
479       break;
480   }
481 }
482 
483 /* Emit an error message when we're in an asm, and a fatal error for
484    "normal" insns.  Formatted output isn't easily implemented, since we
485    use output_operand_lossage to output the actual message and handle the
486    categorization of the error.  */
487 
488 static void
cris_operand_lossage(const char * msgid,rtx op)489 cris_operand_lossage (const char *msgid, rtx op)
490 {
491   debug_rtx (op);
492   output_operand_lossage ("%s", msgid);
493 }
494 
495 /* Print an index part of an address to file.  */
496 
497 static void
cris_print_index(rtx index,FILE * file)498 cris_print_index (rtx index, FILE *file)
499 {
500   rtx inner = XEXP (index, 0);
501 
502   /* Make the index "additive" unless we'll output a negative number, in
503      which case the sign character is free (as in free beer).  */
504   if (GET_CODE (index) != CONST_INT || INTVAL (index) >= 0)
505     putc ('+', file);
506 
507   if (REG_P (index))
508     fprintf (file, "$%s.b", reg_names[REGNO (index)]);
509   else if (CONSTANT_P (index))
510     cris_output_addr_const (file, index);
511   else if (GET_CODE (index) == MULT)
512     {
513       fprintf (file, "$%s.",
514 	       reg_names[REGNO (XEXP (index, 0))]);
515 
516       putc (INTVAL (XEXP (index, 1)) == 2 ? 'w' : 'd', file);
517     }
518   else if (GET_CODE (index) == SIGN_EXTEND &&
519 	   GET_CODE (inner) == MEM)
520     {
521       rtx inner_inner = XEXP (inner, 0);
522 
523       if (GET_CODE (inner_inner) == POST_INC)
524 	{
525 	  fprintf (file, "[$%s+].",
526 		   reg_names[REGNO (XEXP (inner_inner, 0))]);
527 	  putc (GET_MODE (inner) == HImode ? 'w' : 'b', file);
528 	}
529       else
530 	{
531 	  fprintf (file, "[$%s].", reg_names[REGNO (inner_inner)]);
532 
533 	  putc (GET_MODE (inner) == HImode ? 'w' : 'b', file);
534 	}
535     }
536   else if (GET_CODE (index) == MEM)
537     {
538       if (GET_CODE (inner) == POST_INC)
539 	fprintf (file, "[$%s+].d", reg_names[REGNO (XEXP (inner, 0))]);
540       else
541 	fprintf (file, "[$%s].d", reg_names[REGNO (inner)]);
542     }
543   else
544     cris_operand_lossage ("unexpected index-type in cris_print_index",
545 			  index);
546 }
547 
548 /* Print a base rtx of an address to file.  */
549 
550 static void
cris_print_base(rtx base,FILE * file)551 cris_print_base (rtx base, FILE *file)
552 {
553   if (REG_P (base))
554     fprintf (file, "$%s", reg_names[REGNO (base)]);
555   else if (GET_CODE (base) == POST_INC)
556     fprintf (file, "$%s+", reg_names[REGNO (XEXP (base, 0))]);
557   else
558     cris_operand_lossage ("unexpected base-type in cris_print_base",
559 			  base);
560 }
561 
562 /* Usable as a guard in expressions.  */
563 
564 int
cris_fatal(char * arg)565 cris_fatal (char *arg)
566 {
567   internal_error (arg);
568 
569   /* We'll never get here; this is just to appease compilers.  */
570   return 0;
571 }
572 
573 /* Return nonzero if REGNO is an ordinary register that *needs* to be
574    saved together with other registers, possibly by a MOVEM instruction,
575    or is saved for target-independent reasons.  There may be
576    target-dependent reasons to save the register anyway; this is just a
577    wrapper for a complicated conditional.  */
578 
579 static int
cris_reg_saved_in_regsave_area(unsigned int regno,bool got_really_used)580 cris_reg_saved_in_regsave_area (unsigned int regno, bool got_really_used)
581 {
582   return
583     (((regs_ever_live[regno]
584        && !call_used_regs[regno])
585       || (regno == PIC_OFFSET_TABLE_REGNUM
586 	  && (got_really_used
587 	      /* It is saved anyway, if there would be a gap.  */
588 	      || (flag_pic
589 		  && regs_ever_live[regno + 1]
590 		  && !call_used_regs[regno + 1]))))
591      && (regno != FRAME_POINTER_REGNUM || !frame_pointer_needed)
592      && regno != CRIS_SRP_REGNUM)
593     || (current_function_calls_eh_return
594 	&& (regno == EH_RETURN_DATA_REGNO (0)
595 	    || regno == EH_RETURN_DATA_REGNO (1)
596 	    || regno == EH_RETURN_DATA_REGNO (2)
597 	    || regno == EH_RETURN_DATA_REGNO (3)));
598 }
599 
600 /* Return nonzero if there are regs mentioned in the insn that are not all
601    in the call_used regs.  This is part of the decision whether an insn
602    can be put in the epilogue.  */
603 
604 static int
saved_regs_mentioned(rtx x)605 saved_regs_mentioned (rtx x)
606 {
607   int i;
608   const char *fmt;
609   RTX_CODE code;
610 
611   /* Mainly stolen from refers_to_regno_p in rtlanal.c.  */
612 
613   code = GET_CODE (x);
614 
615   switch (code)
616     {
617     case REG:
618       i = REGNO (x);
619       return !call_used_regs[i];
620 
621     case SUBREG:
622       /* If this is a SUBREG of a hard reg, we can see exactly which
623 	 registers are being modified.  Otherwise, handle normally.  */
624       i = REGNO (SUBREG_REG (x));
625       return !call_used_regs[i];
626 
627     default:
628       ;
629     }
630 
631   fmt = GET_RTX_FORMAT (code);
632   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
633     {
634       if (fmt[i] == 'e')
635 	{
636 	  if (saved_regs_mentioned (XEXP (x, i)))
637 	    return 1;
638 	}
639       else if (fmt[i] == 'E')
640 	{
641 	  int j;
642 	  for (j = XVECLEN (x, i) - 1; j >=0; j--)
643 	    if (saved_regs_mentioned (XEXP (x, i)))
644 	      return 1;
645 	}
646     }
647 
648   return 0;
649 }
650 
651 /* The PRINT_OPERAND worker.  */
652 
653 void
cris_print_operand(FILE * file,rtx x,int code)654 cris_print_operand (FILE *file, rtx x, int code)
655 {
656   rtx operand = x;
657 
658   /* Size-strings corresponding to MULT expressions.  */
659   static const char *const mults[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" };
660 
661   /* New code entries should just be added to the switch below.  If
662      handling is finished, just return.  If handling was just a
663      modification of the operand, the modified operand should be put in
664      "operand", and then do a break to let default handling
665      (zero-modifier) output the operand.  */
666 
667   switch (code)
668     {
669     case 'b':
670       /* Print the unsigned supplied integer as if it were signed
671 	 and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc.  */
672       if (GET_CODE (x) != CONST_INT
673 	  || ! CONST_OK_FOR_LETTER_P (INTVAL (x), 'O'))
674 	LOSE_AND_RETURN ("invalid operand for 'b' modifier", x);
675       fprintf (file, HOST_WIDE_INT_PRINT_DEC,
676 	       INTVAL (x)| (INTVAL (x) <= 255 ? ~255 : ~65535));
677       return;
678 
679     case 'x':
680       /* Print assembler code for operator.  */
681       fprintf (file, "%s", cris_op_str (operand));
682       return;
683 
684     case 'o':
685       {
686 	/* A movem modifier working on a parallel; output the register
687 	   name.  */
688 	int regno;
689 
690 	if (GET_CODE (x) != PARALLEL)
691 	  LOSE_AND_RETURN ("invalid operand for 'o' modifier", x);
692 
693 	/* The second item can be (set reg (plus reg const)) to denote a
694 	   postincrement.  */
695 	regno
696 	  = (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS
697 	     ? XVECLEN (x, 0) - 2
698 	     : XVECLEN (x, 0) - 1);
699 
700 	fprintf (file, "$%s", reg_names [regno]);
701       }
702       return;
703 
704     case 'O':
705       {
706 	/* A similar movem modifier; output the memory operand.  */
707 	rtx addr;
708 
709 	if (GET_CODE (x) != PARALLEL)
710 	  LOSE_AND_RETURN ("invalid operand for 'O' modifier", x);
711 
712 	/* The lowest mem operand is in the first item, but perhaps it
713 	   needs to be output as postincremented.  */
714 	addr = GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == MEM
715 	  ? XEXP (SET_SRC (XVECEXP (x, 0, 0)), 0)
716 	  : XEXP (SET_DEST (XVECEXP (x, 0, 0)), 0);
717 
718 	/* The second item can be a (set reg (plus reg const)) to denote
719 	   a modification.  */
720 	if (GET_CODE (SET_SRC (XVECEXP (x, 0, 1))) == PLUS)
721 	  {
722 	    /* It's a post-increment, if the address is a naked (reg).  */
723 	    if (REG_P (addr))
724 	      addr = gen_rtx_POST_INC (SImode, addr);
725 	    else
726 	      {
727 		/* Otherwise, it's a side-effect; RN=RN+M.  */
728 		fprintf (file, "[$%s=$%s%s%d]",
729 			 reg_names [REGNO (SET_DEST (XVECEXP (x, 0, 1)))],
730 			 reg_names [REGNO (XEXP (addr, 0))],
731 			 INTVAL (XEXP (addr, 1)) < 0 ? "" : "+",
732 			 (int) INTVAL (XEXP (addr, 1)));
733 		return;
734 	      }
735 	  }
736 	output_address (addr);
737       }
738       return;
739 
740     case 'p':
741       /* Adjust a power of two to its log2.  */
742       if (GET_CODE (x) != CONST_INT || exact_log2 (INTVAL (x)) < 0 )
743 	LOSE_AND_RETURN ("invalid operand for 'p' modifier", x);
744       fprintf (file, "%d", exact_log2 (INTVAL (x)));
745       return;
746 
747     case 's':
748       /* For an integer, print 'b' or 'w' if <= 255 or <= 65535
749 	 respectively.  This modifier also terminates the inhibiting
750          effects of the 'x' modifier.  */
751       cris_output_insn_is_bound = 0;
752       if (GET_MODE (x) == VOIDmode && GET_CODE (x) == CONST_INT)
753 	{
754 	  if (INTVAL (x) >= 0)
755 	    {
756 	      if (INTVAL (x) <= 255)
757 		putc ('b', file);
758 	      else if (INTVAL (x) <= 65535)
759 		putc ('w', file);
760 	      else
761 		putc ('d', file);
762 	    }
763 	  else
764 	    putc ('d', file);
765 	  return;
766 	}
767 
768       /* For a non-integer, print the size of the operand.  */
769       putc ((GET_MODE (x) == SImode || GET_MODE (x) == SFmode)
770 	    ? 'd' : GET_MODE (x) == HImode ? 'w'
771 	    : GET_MODE (x) == QImode ? 'b'
772 	    /* If none of the above, emit an erroneous size letter.  */
773 	    : 'X',
774 	    file);
775       return;
776 
777     case 'z':
778       /* Const_int: print b for -127 <= x <= 255,
779 	 w for -32768 <= x <= 65535, else die.  */
780       if (GET_CODE (x) != CONST_INT
781 	  || INTVAL (x) < -32768 || INTVAL (x) > 65535)
782 	LOSE_AND_RETURN ("invalid operand for 'z' modifier", x);
783       putc (INTVAL (x) >= -128 && INTVAL (x) <= 255 ? 'b' : 'w', file);
784       return;
785 
786     case '#':
787       /* Output a 'nop' if there's nothing for the delay slot.
788 	 This method stolen from the sparc files.  */
789       if (dbr_sequence_length () == 0)
790 	fputs ("\n\tnop", file);
791       return;
792 
793     case '!':
794       /* Output directive for alignment padded with "nop" insns.
795 	 Optimizing for size, it's plain 4-byte alignment, otherwise we
796 	 align the section to a cache-line (32 bytes) and skip at max 2
797 	 bytes, i.e. we skip if it's the last insn on a cache-line.  The
798 	 latter is faster by a small amount (for two test-programs 99.6%
799 	 and 99.9%) and larger by a small amount (ditto 100.1% and
800 	 100.2%).  This is supposed to be the simplest yet performance-
801 	 wise least intrusive way to make sure the immediately following
802 	 (supposed) muls/mulu insn isn't located at the end of a
803 	 cache-line.  */
804       if (TARGET_MUL_BUG)
805 	fputs (optimize_size
806 	       ? ".p2alignw 2,0x050f\n\t"
807 	       : ".p2alignw 5,0x050f,2\n\t", file);
808       return;
809 
810     case ':':
811       /* The PIC register.  */
812       if (! flag_pic)
813 	internal_error ("invalid use of ':' modifier");
814       fprintf (file, "$%s", reg_names [PIC_OFFSET_TABLE_REGNUM]);
815       return;
816 
817     case 'H':
818       /* Print high (most significant) part of something.  */
819       switch (GET_CODE (operand))
820 	{
821 	case CONST_INT:
822 	  /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode)
823 	     value is kept here, and so may be other than 0 or -1.  */
824 	  fprintf (file, HOST_WIDE_INT_PRINT_DEC,
825 		   INTVAL (operand_subword (operand, 1, 0, DImode)));
826 	  return;
827 
828 	case CONST_DOUBLE:
829 	  /* High part of a long long constant.  */
830 	  if (GET_MODE (operand) == VOIDmode)
831 	    {
832 	      fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_HIGH (x));
833 	      return;
834 	    }
835 	  else
836 	    LOSE_AND_RETURN ("invalid operand for 'H' modifier", x);
837 
838 	case REG:
839 	  /* Print reg + 1.  Check that there's not an attempt to print
840 	     high-parts of registers like stack-pointer or higher.  */
841 	  if (REGNO (operand) > STACK_POINTER_REGNUM - 2)
842 	    LOSE_AND_RETURN ("bad register", operand);
843 	  fprintf (file, "$%s", reg_names[REGNO (operand) + 1]);
844 	  return;
845 
846 	case MEM:
847 	  /* Adjust memory address to high part.  */
848 	  {
849 	    rtx adj_mem = operand;
850 	    int size
851 	      = GET_MODE_BITSIZE (GET_MODE (operand)) / BITS_PER_UNIT;
852 
853 	    /* Adjust so we can use two SImode in DImode.
854 	       Calling adj_offsettable_operand will make sure it is an
855 	       offsettable address.  Don't do this for a postincrement
856 	       though; it should remain as it was.  */
857 	    if (GET_CODE (XEXP (adj_mem, 0)) != POST_INC)
858 	      adj_mem
859 		= adjust_address (adj_mem, GET_MODE (adj_mem), size / 2);
860 
861 	    output_address (XEXP (adj_mem, 0));
862 	    return;
863 	  }
864 
865 	default:
866 	  LOSE_AND_RETURN ("invalid operand for 'H' modifier", x);
867 	}
868 
869     case 'L':
870       /* Strip the MEM expression.  */
871       operand = XEXP (operand, 0);
872       break;
873 
874     case 'e':
875       /* Like 'E', but ignore state set by 'x'.  FIXME: Use code
876 	 iterators ("code macros") and attributes in cris.md to avoid
877 	 the need for %x and %E (and %e) and state passed between
878 	 those modifiers.  */
879       cris_output_insn_is_bound = 0;
880       /* FALL THROUGH.  */
881     case 'E':
882       /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless
883 	 cris_output_insn_is_bound is nonzero.  */
884       if (GET_CODE (operand) != SIGN_EXTEND
885 	  && GET_CODE (operand) != ZERO_EXTEND
886 	  && GET_CODE (operand) != CONST_INT)
887 	LOSE_AND_RETURN ("invalid operand for 'e' modifier", x);
888 
889       if (cris_output_insn_is_bound)
890 	{
891 	  cris_output_insn_is_bound = 0;
892 	  return;
893 	}
894 
895       putc (GET_CODE (operand) == SIGN_EXTEND
896 	    || (GET_CODE (operand) == CONST_INT && INTVAL (operand) < 0)
897 	    ? 's' : 'u', file);
898       return;
899 
900     case 'm':
901       /* Print the size letter of the inner element.  We can do it by
902 	 calling ourselves with the 's' modifier.  */
903       if (GET_CODE (operand) != SIGN_EXTEND && GET_CODE (operand) != ZERO_EXTEND)
904 	LOSE_AND_RETURN ("invalid operand for 'm' modifier", x);
905       cris_print_operand (file, XEXP (operand, 0), 's');
906       return;
907 
908     case 'M':
909       /* Print the least significant part of operand.  */
910       if (GET_CODE (operand) == CONST_DOUBLE)
911 	{
912 	  fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_LOW (x));
913 	  return;
914 	}
915       else if (HOST_BITS_PER_WIDE_INT > 32 && GET_CODE (operand) == CONST_INT)
916 	{
917 	  fprintf (file, HOST_WIDE_INT_PRINT_HEX,
918 		   INTVAL (x) & ((unsigned int) 0x7fffffff * 2 + 1));
919 	  return;
920 	}
921       /* Otherwise the least significant part equals the normal part,
922 	 so handle it normally.  */
923       break;
924 
925     case 'A':
926       /* When emitting an add for the high part of a DImode constant, we
927 	 want to use addq for 0 and adds.w for -1.  */
928       if (GET_CODE (operand) != CONST_INT)
929 	LOSE_AND_RETURN ("invalid operand for 'A' modifier", x);
930       fprintf (file, INTVAL (operand) < 0 ? "adds.w" : "addq");
931       return;
932 
933     case 'd':
934       /* If this is a GOT symbol, force it to be emitted as :GOT and
935 	 :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16).
936 	 Avoid making this too much of a special case.  */
937       if (flag_pic == 1 && CONSTANT_P (operand))
938 	{
939 	  int flag_pic_save = flag_pic;
940 
941 	  flag_pic = 2;
942 	  cris_output_addr_const (file, operand);
943 	  flag_pic = flag_pic_save;
944 	  return;
945 	}
946       break;
947 
948     case 'D':
949       /* When emitting an sub for the high part of a DImode constant, we
950 	 want to use subq for 0 and subs.w for -1.  */
951       if (GET_CODE (operand) != CONST_INT)
952 	LOSE_AND_RETURN ("invalid operand for 'D' modifier", x);
953       fprintf (file, INTVAL (operand) < 0 ? "subs.w" : "subq");
954       return;
955 
956     case 'S':
957       /* Print the operand as the index-part of an address.
958 	 Easiest way out is to use cris_print_index.  */
959       cris_print_index (operand, file);
960       return;
961 
962     case 'T':
963       /* Print the size letter for an operand to a MULT, which must be a
964 	 const_int with a suitable value.  */
965       if (GET_CODE (operand) != CONST_INT || INTVAL (operand) > 4)
966 	LOSE_AND_RETURN ("invalid operand for 'T' modifier", x);
967       fprintf (file, "%s", mults[INTVAL (operand)]);
968       return;
969 
970     case 0:
971       /* No code, print as usual.  */
972       break;
973 
974     default:
975       LOSE_AND_RETURN ("invalid operand modifier letter", x);
976     }
977 
978   /* Print an operand as without a modifier letter.  */
979   switch (GET_CODE (operand))
980     {
981     case REG:
982       if (REGNO (operand) > 15
983 	  && REGNO (operand) != CRIS_MOF_REGNUM
984 	  && REGNO (operand) != CRIS_SRP_REGNUM
985 	  && REGNO (operand) != CRIS_CC0_REGNUM)
986 	internal_error ("internal error: bad register: %d", REGNO (operand));
987       fprintf (file, "$%s", reg_names[REGNO (operand)]);
988       return;
989 
990     case MEM:
991       output_address (XEXP (operand, 0));
992       return;
993 
994     case CONST_DOUBLE:
995       if (GET_MODE (operand) == VOIDmode)
996 	/* A long long constant.  */
997 	output_addr_const (file, operand);
998       else
999 	{
1000 	  /* Only single precision is allowed as plain operands the
1001 	     moment.  FIXME:  REAL_VALUE_FROM_CONST_DOUBLE isn't
1002 	     documented.  */
1003 	  REAL_VALUE_TYPE r;
1004 	  long l;
1005 
1006 	  /* FIXME:  Perhaps check overflow of the "single".  */
1007 	  REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
1008 	  REAL_VALUE_TO_TARGET_SINGLE (r, l);
1009 
1010 	  fprintf (file, "0x%lx", l);
1011 	}
1012       return;
1013 
1014     case UNSPEC:
1015       /* Fall through.  */
1016     case CONST:
1017       cris_output_addr_const (file, operand);
1018       return;
1019 
1020     case MULT:
1021     case ASHIFT:
1022       {
1023 	/* For a (MULT (reg X) const_int) we output "rX.S".  */
1024 	int i = GET_CODE (XEXP (operand, 1)) == CONST_INT
1025 	  ? INTVAL (XEXP (operand, 1)) : INTVAL (XEXP (operand, 0));
1026 	rtx reg = GET_CODE (XEXP (operand, 1)) == CONST_INT
1027 	  ? XEXP (operand, 0) : XEXP (operand, 1);
1028 
1029 	if (GET_CODE (reg) != REG
1030 	    || (GET_CODE (XEXP (operand, 0)) != CONST_INT
1031 		&& GET_CODE (XEXP (operand, 1)) != CONST_INT))
1032 	  LOSE_AND_RETURN ("unexpected multiplicative operand", x);
1033 
1034 	cris_print_base (reg, file);
1035 	fprintf (file, ".%c",
1036 		 i == 0 || (i == 1 && GET_CODE (operand) == MULT) ? 'b'
1037 		 : i == 4 ? 'd'
1038 		 : (i == 2 && GET_CODE (operand) == MULT) || i == 1 ? 'w'
1039 		 : 'd');
1040 	return;
1041       }
1042 
1043     default:
1044       /* No need to handle all strange variants, let output_addr_const
1045 	 do it for us.  */
1046       if (CONSTANT_P (operand))
1047 	{
1048 	  cris_output_addr_const (file, operand);
1049 	  return;
1050 	}
1051 
1052       LOSE_AND_RETURN ("unexpected operand", x);
1053     }
1054 }
1055 
1056 /* The PRINT_OPERAND_ADDRESS worker.  */
1057 
1058 void
cris_print_operand_address(FILE * file,rtx x)1059 cris_print_operand_address (FILE *file, rtx x)
1060 {
1061   /* All these were inside MEM:s so output indirection characters.  */
1062   putc ('[', file);
1063 
1064   if (CONSTANT_ADDRESS_P (x))
1065     cris_output_addr_const (file, x);
1066   else if (BASE_OR_AUTOINCR_P (x))
1067     cris_print_base (x, file);
1068   else if (GET_CODE (x) == PLUS)
1069     {
1070       rtx x1, x2;
1071 
1072       x1 = XEXP (x, 0);
1073       x2 = XEXP (x, 1);
1074       if (BASE_P (x1))
1075 	{
1076 	  cris_print_base (x1, file);
1077 	  cris_print_index (x2, file);
1078 	}
1079       else if (BASE_P (x2))
1080 	{
1081 	  cris_print_base (x2, file);
1082 	  cris_print_index (x1, file);
1083 	}
1084       else
1085 	LOSE_AND_RETURN ("unrecognized address", x);
1086     }
1087   else if (GET_CODE (x) == MEM)
1088     {
1089       /* A DIP.  Output more indirection characters.  */
1090       putc ('[', file);
1091       cris_print_base (XEXP (x, 0), file);
1092       putc (']', file);
1093     }
1094   else
1095     LOSE_AND_RETURN ("unrecognized address", x);
1096 
1097   putc (']', file);
1098 }
1099 
1100 /* The RETURN_ADDR_RTX worker.
1101    We mark that the return address is used, either by EH or
1102    __builtin_return_address, for use by the function prologue and
1103    epilogue.  FIXME: This isn't optimal; we just use the mark in the
1104    prologue and epilogue to say that the return address is to be stored
1105    in the stack frame.  We could return SRP for leaf-functions and use the
1106    initial-value machinery.  */
1107 
1108 rtx
cris_return_addr_rtx(int count,rtx frameaddr ATTRIBUTE_UNUSED)1109 cris_return_addr_rtx (int count, rtx frameaddr ATTRIBUTE_UNUSED)
1110 {
1111   cfun->machine->needs_return_address_on_stack = 1;
1112 
1113   /* The return-address is stored just above the saved frame-pointer (if
1114      present).  Apparently we can't eliminate from the frame-pointer in
1115      that direction, so use the incoming args (maybe pretended) pointer.  */
1116   return count == 0
1117     ? gen_rtx_MEM (Pmode, plus_constant (virtual_incoming_args_rtx, -4))
1118     : NULL_RTX;
1119 }
1120 
1121 /* Accessor used in cris.md:return because cfun->machine isn't available
1122    there.  */
1123 
1124 bool
cris_return_address_on_stack(void)1125 cris_return_address_on_stack (void)
1126 {
1127   return regs_ever_live[CRIS_SRP_REGNUM]
1128     || cfun->machine->needs_return_address_on_stack;
1129 }
1130 
1131 /* Accessor used in cris.md:return because cfun->machine isn't available
1132    there.  */
1133 
1134 bool
cris_return_address_on_stack_for_return(void)1135 cris_return_address_on_stack_for_return (void)
1136 {
1137   return cfun->machine->return_type == CRIS_RETINSN_RET ? false
1138     : cris_return_address_on_stack ();
1139 }
1140 
1141 /* This used to be the INITIAL_FRAME_POINTER_OFFSET worker; now only
1142    handles FP -> SP elimination offset.  */
1143 
1144 static int
cris_initial_frame_pointer_offset(void)1145 cris_initial_frame_pointer_offset (void)
1146 {
1147   int regno;
1148 
1149   /* Initial offset is 0 if we don't have a frame pointer.  */
1150   int offs = 0;
1151   bool got_really_used = false;
1152 
1153   if (current_function_uses_pic_offset_table)
1154     {
1155       push_topmost_sequence ();
1156       got_really_used
1157 	= reg_used_between_p (pic_offset_table_rtx, get_insns (),
1158 			      NULL_RTX);
1159       pop_topmost_sequence ();
1160     }
1161 
1162   /* And 4 for each register pushed.  */
1163   for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1164     if (cris_reg_saved_in_regsave_area (regno, got_really_used))
1165       offs += 4;
1166 
1167   /* And then, last, we add the locals allocated.  */
1168   offs += get_frame_size ();
1169 
1170   /* And more; the accumulated args size.  */
1171   offs += current_function_outgoing_args_size;
1172 
1173   /* Then round it off, in case we use aligned stack.  */
1174   if (TARGET_STACK_ALIGN)
1175     offs = TARGET_ALIGN_BY_32 ? (offs + 3) & ~3 : (offs + 1) & ~1;
1176 
1177   return offs;
1178 }
1179 
1180 /* The INITIAL_ELIMINATION_OFFSET worker.
1181    Calculate the difference between imaginary registers such as frame
1182    pointer and the stack pointer.  Used to eliminate the frame pointer
1183    and imaginary arg pointer.  */
1184 
1185 int
cris_initial_elimination_offset(int fromreg,int toreg)1186 cris_initial_elimination_offset (int fromreg, int toreg)
1187 {
1188   int fp_sp_offset
1189     = cris_initial_frame_pointer_offset ();
1190 
1191   /* We should be able to use regs_ever_live and related prologue
1192      information here, or alpha should not as well.  */
1193   bool return_address_on_stack = cris_return_address_on_stack ();
1194 
1195   /* Here we act as if the frame-pointer were needed.  */
1196   int ap_fp_offset = 4 + (return_address_on_stack ? 4 : 0);
1197 
1198   if (fromreg == ARG_POINTER_REGNUM
1199       && toreg == FRAME_POINTER_REGNUM)
1200     return ap_fp_offset;
1201 
1202   /* Between the frame pointer and the stack are only "normal" stack
1203      variables and saved registers.  */
1204   if (fromreg == FRAME_POINTER_REGNUM
1205       && toreg == STACK_POINTER_REGNUM)
1206     return fp_sp_offset;
1207 
1208   /* We need to balance out the frame pointer here.  */
1209   if (fromreg == ARG_POINTER_REGNUM
1210       && toreg == STACK_POINTER_REGNUM)
1211     return ap_fp_offset + fp_sp_offset - 4;
1212 
1213   gcc_unreachable ();
1214 }
1215 
1216 /* Worker function for LEGITIMIZE_RELOAD_ADDRESS.  */
1217 
1218 bool
cris_reload_address_legitimized(rtx x,enum machine_mode mode ATTRIBUTE_UNUSED,int opnum ATTRIBUTE_UNUSED,int itype,int ind_levels ATTRIBUTE_UNUSED)1219 cris_reload_address_legitimized (rtx x,
1220 				 enum machine_mode mode ATTRIBUTE_UNUSED,
1221 				 int opnum ATTRIBUTE_UNUSED,
1222 				 int itype,
1223 				 int ind_levels ATTRIBUTE_UNUSED)
1224 {
1225   enum reload_type type = itype;
1226   rtx op0, op1;
1227   rtx *op0p;
1228   rtx *op1p;
1229 
1230   if (GET_CODE (x) != PLUS)
1231     return false;
1232 
1233   op0 = XEXP (x, 0);
1234   op0p = &XEXP (x, 0);
1235   op1 = XEXP (x, 1);
1236   op1p = &XEXP (x, 1);
1237 
1238   if (!REG_P (op1))
1239     return false;
1240 
1241   if (GET_CODE (op0) == SIGN_EXTEND
1242       && GET_CODE (XEXP (op0, 0)) == MEM)
1243     {
1244       rtx op00 = XEXP (op0, 0);
1245       rtx op000 = XEXP (op00, 0);
1246       rtx *op000p = &XEXP (op00, 0);
1247 
1248       if ((GET_MODE (op00) == HImode || GET_MODE (op00) == QImode)
1249 	  && (REG_P (op000)
1250 	      || (GET_CODE (op000) == POST_INC && REG_P (XEXP (op000, 0)))))
1251 	{
1252 	  bool something_reloaded = false;
1253 
1254 	  if (GET_CODE (op000) == POST_INC
1255 	      && REG_P (XEXP (op000, 0))
1256 	      && REGNO (XEXP (op000, 0)) > CRIS_LAST_GENERAL_REGISTER)
1257 	    /* No, this gets too complicated and is too rare to care
1258 	       about trying to improve on the general code Here.
1259 	       As the return-value is an all-or-nothing indicator, we
1260 	       punt on the other register too.  */
1261 	    return false;
1262 
1263 	  if ((REG_P (op000)
1264 	       && REGNO (op000) > CRIS_LAST_GENERAL_REGISTER))
1265 	    {
1266 	      /* The address of the inner mem is a pseudo or wrong
1267 		 reg: reload that.  */
1268 	      push_reload (op000, NULL_RTX, op000p, NULL, GENERAL_REGS,
1269 			   GET_MODE (x), VOIDmode, 0, 0, opnum, type);
1270 	      something_reloaded = true;
1271 	    }
1272 
1273 	  if (REGNO (op1) > CRIS_LAST_GENERAL_REGISTER)
1274 	    {
1275 	      /* Base register is a pseudo or wrong reg: reload it.  */
1276 	      push_reload (op1, NULL_RTX, op1p, NULL, GENERAL_REGS,
1277 			   GET_MODE (x), VOIDmode, 0, 0,
1278 			   opnum, type);
1279 	      something_reloaded = true;
1280 	    }
1281 
1282 	  gcc_assert (something_reloaded);
1283 
1284 	  return true;
1285 	}
1286     }
1287 
1288   return false;
1289 }
1290 
1291 /*  This function looks into the pattern to see how this insn affects
1292     condition codes.
1293 
1294     Used when to eliminate test insns before a condition-code user,
1295     such as a "scc" insn or a conditional branch.  This includes
1296     checking if the entities that cc was updated by, are changed by the
1297     operation.
1298 
1299     Currently a jumble of the old peek-inside-the-insn and the newer
1300     check-cc-attribute methods.  */
1301 
1302 void
cris_notice_update_cc(rtx exp,rtx insn)1303 cris_notice_update_cc (rtx exp, rtx insn)
1304 {
1305   /* Check if user specified "-mcc-init" as a bug-workaround.  FIXME:
1306      TARGET_CCINIT does not work; we must set CC_REVERSED as below.
1307      Several testcases will otherwise fail, for example
1308      gcc.c-torture/execute/20000217-1.c -O0 and -O1.  */
1309   if (TARGET_CCINIT)
1310     {
1311       CC_STATUS_INIT;
1312       return;
1313     }
1314 
1315   /* Slowly, we're converting to using attributes to control the setting
1316      of condition-code status.  */
1317   switch (get_attr_cc (insn))
1318     {
1319     case CC_NONE:
1320       /* Even if it is "none", a setting may clobber a previous
1321 	 cc-value, so check.  */
1322       if (GET_CODE (exp) == SET)
1323 	{
1324 	  if (cc_status.value1
1325 	      && modified_in_p (cc_status.value1, insn))
1326 	    cc_status.value1 = 0;
1327 
1328 	  if (cc_status.value2
1329 	      && modified_in_p (cc_status.value2, insn))
1330 	    cc_status.value2 = 0;
1331 	}
1332       return;
1333 
1334     case CC_CLOBBER:
1335       CC_STATUS_INIT;
1336       break;
1337 
1338     case CC_NORMAL:
1339       /* Which means, for:
1340 	 (set (cc0) (...)):
1341 	 CC is (...).
1342 
1343 	 (set (reg) (...)):
1344 	 CC is (reg) and (...) - unless (...) is 0, then CC does not change.
1345 	 CC_NO_OVERFLOW unless (...) is reg or mem.
1346 
1347 	 (set (mem) (...)):
1348 	 CC does not change.
1349 
1350 	 (set (pc) (...)):
1351 	 CC does not change.
1352 
1353 	 (parallel
1354 	  (set (reg1) (mem (bdap/biap)))
1355 	  (set (reg2) (bdap/biap))):
1356 	 CC is (reg1) and (mem (reg2))
1357 
1358 	 (parallel
1359 	  (set (mem (bdap/biap)) (reg1)) [or 0]
1360 	  (set (reg2) (bdap/biap))):
1361 	 CC does not change.
1362 
1363 	 (where reg and mem includes strict_low_parts variants thereof)
1364 
1365 	 For all others, assume CC is clobbered.
1366 	 Note that we do not have to care about setting CC_NO_OVERFLOW,
1367 	 since the overflow flag is set to 0 (i.e. right) for
1368 	 instructions where it does not have any sane sense, but where
1369 	 other flags have meanings.  (This includes shifts; the carry is
1370 	 not set by them).
1371 
1372 	 Note that there are other parallel constructs we could match,
1373 	 but we don't do that yet.  */
1374 
1375       if (GET_CODE (exp) == SET)
1376 	{
1377 	  /* FIXME: Check when this happens.  It looks like we should
1378 	     actually do a CC_STATUS_INIT here to be safe.  */
1379 	  if (SET_DEST (exp) == pc_rtx)
1380 	    return;
1381 
1382 	  /* Record CC0 changes, so we do not have to output multiple
1383 	     test insns.  */
1384 	  if (SET_DEST (exp) == cc0_rtx)
1385 	    {
1386 	      cc_status.value1 = SET_SRC (exp);
1387 	      cc_status.value2 = 0;
1388 
1389 	      /* Handle flags for the special btstq on one bit.  */
1390 	      if (GET_CODE (SET_SRC (exp)) == ZERO_EXTRACT
1391 		  && XEXP (SET_SRC (exp), 1) == const1_rtx)
1392 		{
1393 		  if (GET_CODE (XEXP (SET_SRC (exp), 0)) == CONST_INT)
1394 		    /* Using cmpq.  */
1395 		    cc_status.flags = CC_INVERTED;
1396 		  else
1397 		    /* A one-bit btstq.  */
1398 		    cc_status.flags = CC_Z_IN_NOT_N;
1399 		}
1400 	      else
1401 		cc_status.flags = 0;
1402 
1403 	      if (GET_CODE (SET_SRC (exp)) == COMPARE)
1404 		{
1405 		  if (!REG_P (XEXP (SET_SRC (exp), 0))
1406 		      && XEXP (SET_SRC (exp), 1) != const0_rtx)
1407 		    /* For some reason gcc will not canonicalize compare
1408 		       operations, reversing the sign by itself if
1409 		       operands are in wrong order.  */
1410 		    /* (But NOT inverted; eq is still eq.) */
1411 		    cc_status.flags = CC_REVERSED;
1412 
1413 		  /* This seems to be overlooked by gcc.  FIXME: Check again.
1414 		     FIXME:  Is it really safe?  */
1415 		  cc_status.value2
1416 		    = gen_rtx_MINUS (GET_MODE (SET_SRC (exp)),
1417 				     XEXP (SET_SRC (exp), 0),
1418 				     XEXP (SET_SRC (exp), 1));
1419 		}
1420 	      return;
1421 	    }
1422 	  else if (REG_P (SET_DEST (exp))
1423 		   || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART
1424 		       && REG_P (XEXP (SET_DEST (exp), 0))))
1425 	    {
1426 	      /* A register is set; normally CC is set to show that no
1427 		 test insn is needed.  Catch the exceptions.  */
1428 
1429 	      /* If not to cc0, then no "set"s in non-natural mode give
1430 		 ok cc0...  */
1431 	      if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp))) > UNITS_PER_WORD
1432 		  || GET_MODE_CLASS (GET_MODE (SET_DEST (exp))) == MODE_FLOAT)
1433 		{
1434 		  /* ... except add:s and sub:s in DImode.  */
1435 		  if (GET_MODE (SET_DEST (exp)) == DImode
1436 		      && (GET_CODE (SET_SRC (exp)) == PLUS
1437 			  || GET_CODE (SET_SRC (exp)) == MINUS))
1438 		    {
1439 		      cc_status.flags = 0;
1440 		      cc_status.value1 = SET_DEST (exp);
1441 		      cc_status.value2 = SET_SRC (exp);
1442 
1443 		      if (cris_reg_overlap_mentioned_p (cc_status.value1,
1444 							cc_status.value2))
1445 			cc_status.value2 = 0;
1446 
1447 		      /* Add and sub may set V, which gets us
1448 			 unoptimizable results in "gt" and "le" condition
1449 			 codes.  */
1450 		      cc_status.flags |= CC_NO_OVERFLOW;
1451 
1452 		      return;
1453 		    }
1454 		}
1455 	      else if (SET_SRC (exp) == const0_rtx)
1456 		{
1457 		  /* There's no CC0 change when clearing a register or
1458 		     memory.  Just check for overlap.  */
1459 		  if (cc_status.value1
1460 		      && modified_in_p (cc_status.value1, insn))
1461 		    cc_status.value1 = 0;
1462 
1463 		  if (cc_status.value2
1464 		      && modified_in_p (cc_status.value2, insn))
1465 		    cc_status.value2 = 0;
1466 
1467 		  return;
1468 		}
1469 	      else
1470 		{
1471 		  cc_status.flags = 0;
1472 		  cc_status.value1 = SET_DEST (exp);
1473 		  cc_status.value2 = SET_SRC (exp);
1474 
1475 		  if (cris_reg_overlap_mentioned_p (cc_status.value1,
1476 						    cc_status.value2))
1477 		    cc_status.value2 = 0;
1478 
1479 		  /* Some operations may set V, which gets us
1480 		     unoptimizable results in "gt" and "le" condition
1481 		     codes.  */
1482 		  if (GET_CODE (SET_SRC (exp)) == PLUS
1483 		      || GET_CODE (SET_SRC (exp)) == MINUS
1484 		      || GET_CODE (SET_SRC (exp)) == NEG)
1485 		    cc_status.flags |= CC_NO_OVERFLOW;
1486 
1487 		  return;
1488 		}
1489 	    }
1490 	  else if (GET_CODE (SET_DEST (exp)) == MEM
1491 		   || (GET_CODE (SET_DEST (exp)) == STRICT_LOW_PART
1492 		       && GET_CODE (XEXP (SET_DEST (exp), 0)) == MEM))
1493 	    {
1494 	      /* When SET to MEM, then CC is not changed (except for
1495 		 overlap).  */
1496 	      if (cc_status.value1
1497 		  && modified_in_p (cc_status.value1, insn))
1498 		cc_status.value1 = 0;
1499 
1500 	      if (cc_status.value2
1501 		  && modified_in_p (cc_status.value2, insn))
1502 		cc_status.value2 = 0;
1503 
1504 	      return;
1505 	    }
1506 	}
1507       else if (GET_CODE (exp) == PARALLEL)
1508 	{
1509 	  if (GET_CODE (XVECEXP (exp, 0, 0)) == SET
1510 	      && GET_CODE (XVECEXP (exp, 0, 1)) == SET
1511 	      && REG_P (XEXP (XVECEXP (exp, 0, 1), 0)))
1512 	    {
1513 	      if (REG_P (XEXP (XVECEXP (exp, 0, 0), 0))
1514 		  && GET_CODE (XEXP (XVECEXP (exp, 0, 0), 1)) == MEM)
1515 		{
1516 		  /* For "move.S [rx=ry+o],rz", say CC reflects
1517 		     value1=rz and value2=[rx] */
1518 		  cc_status.value1 = XEXP (XVECEXP (exp, 0, 0), 0);
1519 		  cc_status.value2
1520 		    = replace_equiv_address (XEXP (XVECEXP (exp, 0, 0), 1),
1521 					     XEXP (XVECEXP (exp, 0, 1), 0));
1522 		  cc_status.flags = 0;
1523 
1524 		  /* Huh?  A side-effect cannot change the destination
1525 		     register.  */
1526 		  if (cris_reg_overlap_mentioned_p (cc_status.value1,
1527 						    cc_status.value2))
1528 		    internal_error ("internal error: sideeffect-insn affecting main effect");
1529 		  return;
1530 		}
1531 	      else if ((REG_P (XEXP (XVECEXP (exp, 0, 0), 1))
1532 			|| XEXP (XVECEXP (exp, 0, 0), 1) == const0_rtx)
1533 		       && GET_CODE (XEXP (XVECEXP (exp, 0, 0), 0)) == MEM)
1534 		{
1535 		  /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]",
1536 		     say flags are not changed, except for overlap.  */
1537 		  if (cc_status.value1
1538 		      && modified_in_p (cc_status.value1, insn))
1539 		    cc_status.value1 = 0;
1540 
1541 		  if (cc_status.value2
1542 		      && modified_in_p (cc_status.value2, insn))
1543 		    cc_status.value2 = 0;
1544 
1545 		  return;
1546 		}
1547 	    }
1548 	}
1549       break;
1550 
1551     default:
1552       internal_error ("unknown cc_attr value");
1553     }
1554 
1555   CC_STATUS_INIT;
1556 }
1557 
1558 /* Return != 0 if the return sequence for the current function is short,
1559    like "ret" or "jump [sp+]".  Prior to reloading, we can't tell if
1560    registers must be saved, so return 0 then.  */
1561 
1562 bool
cris_simple_epilogue(void)1563 cris_simple_epilogue (void)
1564 {
1565   unsigned int regno;
1566   unsigned int reglimit = STACK_POINTER_REGNUM;
1567   bool got_really_used = false;
1568 
1569   if (! reload_completed
1570       || frame_pointer_needed
1571       || get_frame_size () != 0
1572       || current_function_pretend_args_size
1573       || current_function_args_size
1574       || current_function_outgoing_args_size
1575       || current_function_calls_eh_return
1576 
1577       /* If we're not supposed to emit prologue and epilogue, we must
1578 	 not emit return-type instructions.  */
1579       || !TARGET_PROLOGUE_EPILOGUE)
1580     return false;
1581 
1582   if (current_function_uses_pic_offset_table)
1583     {
1584       push_topmost_sequence ();
1585       got_really_used
1586 	= reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX);
1587       pop_topmost_sequence ();
1588     }
1589 
1590   /* No simple epilogue if there are saved registers.  */
1591   for (regno = 0; regno < reglimit; regno++)
1592     if (cris_reg_saved_in_regsave_area (regno, got_really_used))
1593       return false;
1594 
1595   return true;
1596 }
1597 
1598 /* Expand a return insn (just one insn) marked as using SRP or stack
1599    slot depending on parameter ON_STACK.  */
1600 
1601 void
cris_expand_return(bool on_stack)1602 cris_expand_return (bool on_stack)
1603 {
1604   /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to
1605      tell "ret" from "jump [sp+]".  Some, but not all, other parts of
1606      GCC expect just (return) to do the right thing when optimizing, so
1607      we do that until they're fixed.  Currently, all return insns in a
1608      function must be the same (not really a limiting factor) so we need
1609      to check that it doesn't change half-way through.  */
1610   emit_jump_insn (gen_rtx_RETURN (VOIDmode));
1611 
1612   CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_RET || !on_stack);
1613   CRIS_ASSERT (cfun->machine->return_type != CRIS_RETINSN_JUMP || on_stack);
1614 
1615   cfun->machine->return_type
1616     = on_stack ? CRIS_RETINSN_JUMP : CRIS_RETINSN_RET;
1617 }
1618 
1619 /* Compute a (partial) cost for rtx X.  Return true if the complete
1620    cost has been computed, and false if subexpressions should be
1621    scanned.  In either case, *TOTAL contains the cost result.  */
1622 
1623 static bool
cris_rtx_costs(rtx x,int code,int outer_code,int * total)1624 cris_rtx_costs (rtx x, int code, int outer_code, int *total)
1625 {
1626   switch (code)
1627     {
1628     case CONST_INT:
1629       {
1630 	HOST_WIDE_INT val = INTVAL (x);
1631 	if (val == 0)
1632 	  *total = 0;
1633 	else if (val < 32 && val >= -32)
1634 	  *total = 1;
1635 	/* Eight or 16 bits are a word and cycle more expensive.  */
1636 	else if (val <= 32767 && val >= -32768)
1637 	  *total = 2;
1638 	/* A 32 bit constant (or very seldom, unsigned 16 bits) costs
1639 	   another word.  FIXME: This isn't linear to 16 bits.  */
1640 	else
1641 	  *total = 4;
1642 	return true;
1643       }
1644 
1645     case LABEL_REF:
1646       *total = 6;
1647       return true;
1648 
1649     case CONST:
1650     case SYMBOL_REF:
1651       *total = 6;
1652       return true;
1653 
1654     case CONST_DOUBLE:
1655       if (x != CONST0_RTX (GET_MODE (x) == VOIDmode ? DImode : GET_MODE (x)))
1656 	*total = 12;
1657       else
1658         /* Make 0.0 cheap, else test-insns will not be used.  */
1659 	*total = 0;
1660       return true;
1661 
1662     case MULT:
1663       /* Identify values that are no powers of two.  Powers of 2 are
1664          taken care of already and those values should not be changed.  */
1665       if (GET_CODE (XEXP (x, 1)) != CONST_INT
1666           || exact_log2 (INTVAL (XEXP (x, 1)) < 0))
1667 	{
1668 	  /* If we have a multiply insn, then the cost is between
1669 	     1 and 2 "fast" instructions.  */
1670 	  if (TARGET_HAS_MUL_INSNS)
1671 	    {
1672 	      *total = COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2;
1673 	      return true;
1674 	    }
1675 
1676 	  /* Estimate as 4 + 4 * #ofbits.  */
1677 	  *total = COSTS_N_INSNS (132);
1678 	  return true;
1679 	}
1680       return false;
1681 
1682     case UDIV:
1683     case MOD:
1684     case UMOD:
1685     case DIV:
1686       if (GET_CODE (XEXP (x, 1)) != CONST_INT
1687           || exact_log2 (INTVAL (XEXP (x, 1)) < 0))
1688 	{
1689 	  /* Estimate this as 4 + 8 * #of bits.  */
1690 	  *total = COSTS_N_INSNS (260);
1691 	  return true;
1692 	}
1693       return false;
1694 
1695     case AND:
1696       if (GET_CODE (XEXP (x, 1)) == CONST_INT
1697           /* Two constants may actually happen before optimization.  */
1698           && GET_CODE (XEXP (x, 0)) != CONST_INT
1699           && !CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
1700 	{
1701 	  *total = (rtx_cost (XEXP (x, 0), outer_code) + 2
1702 		    + 2 * GET_MODE_NUNITS (GET_MODE (XEXP (x, 0))));
1703 	  return true;
1704 	}
1705       return false;
1706 
1707     case ZERO_EXTEND: case SIGN_EXTEND:
1708       *total = rtx_cost (XEXP (x, 0), outer_code);
1709       return true;
1710 
1711     default:
1712       return false;
1713     }
1714 }
1715 
1716 /* The ADDRESS_COST worker.  */
1717 
1718 static int
cris_address_cost(rtx x)1719 cris_address_cost (rtx x)
1720 {
1721   /* The metric to use for the cost-macros is unclear.
1722      The metric used here is (the number of cycles needed) / 2,
1723      where we consider equal a cycle for a word of code and a cycle to
1724      read memory.  */
1725 
1726   /* The cheapest addressing modes get 0, since nothing extra is needed.  */
1727   if (BASE_OR_AUTOINCR_P (x))
1728     return 0;
1729 
1730   /* An indirect mem must be a DIP.  This means two bytes extra for code,
1731      and 4 bytes extra for memory read, i.e.  (2 + 4) / 2.  */
1732   if (GET_CODE (x) == MEM)
1733     return (2 + 4) / 2;
1734 
1735   /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs
1736      an extra DIP prefix and 4 bytes of constant in most cases.  */
1737   if (CONSTANT_P (x))
1738     return (2 + 4) / 2;
1739 
1740   /* Handle BIAP and BDAP prefixes.  */
1741   if (GET_CODE (x) == PLUS)
1742     {
1743       rtx tem1 = XEXP (x, 0);
1744       rtx tem2 = XEXP (x, 1);
1745 
1746     /* A BIAP is 2 extra bytes for the prefix insn, nothing more.  We
1747        recognize the typical MULT which is always in tem1 because of
1748        insn canonicalization.  */
1749     if ((GET_CODE (tem1) == MULT && BIAP_INDEX_P (tem1))
1750 	|| REG_P (tem1))
1751       return 2 / 2;
1752 
1753     /* A BDAP (quick) is 2 extra bytes.  Any constant operand to the
1754        PLUS is always found in tem2.  */
1755     if (GET_CODE (tem2) == CONST_INT
1756 	&& INTVAL (tem2) < 128 && INTVAL (tem2) >= -128)
1757       return 2 / 2;
1758 
1759     /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra
1760        bytes.  */
1761     if (GET_CODE (tem2) == CONST_INT
1762 	&& CONST_OK_FOR_LETTER_P (INTVAL (tem2), 'L'))
1763       return (2 + 2) / 2;
1764 
1765     /* A BDAP with some other constant is 2 bytes extra.  */
1766     if (CONSTANT_P (tem2))
1767       return (2 + 2 + 2) / 2;
1768 
1769     /* BDAP with something indirect should have a higher cost than
1770        BIAP with register.   FIXME: Should it cost like a MEM or more?  */
1771     /* Don't need to check it, it's the only one left.
1772        FIXME:  There was a REG test missing, perhaps there are others.
1773        Think more.  */
1774     return (2 + 2 + 2) / 2;
1775   }
1776 
1777   /* What else?  Return a high cost.  It matters only for valid
1778      addressing modes.  */
1779   return 10;
1780 }
1781 
1782 /* Check various objections to the side-effect.  Used in the test-part
1783    of an anonymous insn describing an insn with a possible side-effect.
1784    Returns nonzero if the implied side-effect is ok.
1785 
1786    code     : PLUS or MULT
1787    ops	    : An array of rtx:es. lreg, rreg, rval,
1788 	      The variables multop and other_op are indexes into this,
1789 	      or -1 if they are not applicable.
1790    lreg     : The register that gets assigned in the side-effect.
1791    rreg     : One register in the side-effect expression
1792    rval     : The other register, or an int.
1793    multop   : An integer to multiply rval with.
1794    other_op : One of the entities of the main effect,
1795 	      whose mode we must consider.  */
1796 
1797 int
cris_side_effect_mode_ok(enum rtx_code code,rtx * ops,int lreg,int rreg,int rval,int multop,int other_op)1798 cris_side_effect_mode_ok (enum rtx_code code, rtx *ops,
1799 			  int lreg, int rreg, int rval,
1800 			  int multop, int other_op)
1801 {
1802   /* Find what value to multiply with, for rx =ry + rz * n.  */
1803   int mult = multop < 0 ? 1 : INTVAL (ops[multop]);
1804 
1805   rtx reg_rtx = ops[rreg];
1806   rtx val_rtx = ops[rval];
1807 
1808   /* The operands may be swapped.  Canonicalize them in reg_rtx and
1809      val_rtx, where reg_rtx always is a reg (for this constraint to
1810      match).  */
1811   if (! BASE_P (reg_rtx))
1812     reg_rtx = val_rtx, val_rtx = ops[rreg];
1813 
1814   /* Don't forget to check that reg_rtx really is a reg.  If it isn't,
1815      we have no business.  */
1816   if (! BASE_P (reg_rtx))
1817     return 0;
1818 
1819   /* Don't do this when -mno-split.  */
1820   if (!TARGET_SIDE_EFFECT_PREFIXES)
1821     return 0;
1822 
1823   /* The mult expression may be hidden in lreg.  FIXME:  Add more
1824      commentary about that.  */
1825   if (GET_CODE (val_rtx) == MULT)
1826     {
1827       mult = INTVAL (XEXP (val_rtx, 1));
1828       val_rtx = XEXP (val_rtx, 0);
1829       code = MULT;
1830     }
1831 
1832   /* First check the "other operand".  */
1833   if (other_op >= 0)
1834     {
1835       if (GET_MODE_SIZE (GET_MODE (ops[other_op])) > UNITS_PER_WORD)
1836 	return 0;
1837 
1838       /* Check if the lvalue register is the same as the "other
1839 	 operand".  If so, the result is undefined and we shouldn't do
1840 	 this.  FIXME:  Check again.  */
1841       if ((BASE_P (ops[lreg])
1842 	   && BASE_P (ops[other_op])
1843 	   && REGNO (ops[lreg]) == REGNO (ops[other_op]))
1844 	  || rtx_equal_p (ops[other_op], ops[lreg]))
1845       return 0;
1846     }
1847 
1848   /* Do not accept frame_pointer_rtx as any operand.  */
1849   if (ops[lreg] == frame_pointer_rtx || ops[rreg] == frame_pointer_rtx
1850       || ops[rval] == frame_pointer_rtx
1851       || (other_op >= 0 && ops[other_op] == frame_pointer_rtx))
1852     return 0;
1853 
1854   if (code == PLUS
1855       && ! BASE_P (val_rtx))
1856     {
1857 
1858       /* Do not allow rx = rx + n if a normal add or sub with same size
1859 	 would do.  */
1860       if (rtx_equal_p (ops[lreg], reg_rtx)
1861 	  && GET_CODE (val_rtx) == CONST_INT
1862 	  && (INTVAL (val_rtx) <= 63 && INTVAL (val_rtx) >= -63))
1863 	return 0;
1864 
1865       /* Check allowed cases, like [r(+)?].[bwd] and const.  */
1866       if (CONSTANT_P (val_rtx))
1867 	return 1;
1868 
1869       if (GET_CODE (val_rtx) == MEM
1870 	  && BASE_OR_AUTOINCR_P (XEXP (val_rtx, 0)))
1871 	return 1;
1872 
1873       if (GET_CODE (val_rtx) == SIGN_EXTEND
1874 	  && GET_CODE (XEXP (val_rtx, 0)) == MEM
1875 	  && BASE_OR_AUTOINCR_P (XEXP (XEXP (val_rtx, 0), 0)))
1876 	return 1;
1877 
1878       /* If we got here, it's not a valid addressing mode.  */
1879       return 0;
1880     }
1881   else if (code == MULT
1882 	   || (code == PLUS && BASE_P (val_rtx)))
1883     {
1884       /* Do not allow rx = rx + ry.S, since it doesn't give better code.  */
1885       if (rtx_equal_p (ops[lreg], reg_rtx)
1886 	  || (mult == 1 && rtx_equal_p (ops[lreg], val_rtx)))
1887 	return 0;
1888 
1889       /* Do not allow bad multiply-values.  */
1890       if (mult != 1 && mult != 2 && mult != 4)
1891 	return 0;
1892 
1893       /* Only allow  r + ...  */
1894       if (! BASE_P (reg_rtx))
1895 	return 0;
1896 
1897       /* If we got here, all seems ok.
1898 	 (All checks need to be done above).  */
1899       return 1;
1900     }
1901 
1902   /* If we get here, the caller got its initial tests wrong.  */
1903   internal_error ("internal error: cris_side_effect_mode_ok with bad operands");
1904 }
1905 
1906 /* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16)
1907    does not handle the case where the IN operand is strict_low_part; it
1908    does handle it for X.  Test-case in Axis-20010516.  This function takes
1909    care of that for THIS port.  FIXME: strict_low_part is going away
1910    anyway.  */
1911 
1912 static int
cris_reg_overlap_mentioned_p(rtx x,rtx in)1913 cris_reg_overlap_mentioned_p (rtx x, rtx in)
1914 {
1915   /* The function reg_overlap_mentioned now handles when X is
1916      strict_low_part, but not when IN is a STRICT_LOW_PART.  */
1917   if (GET_CODE (in) == STRICT_LOW_PART)
1918     in = XEXP (in, 0);
1919 
1920   return reg_overlap_mentioned_p (x, in);
1921 }
1922 
1923 /* The TARGET_ASM_NAMED_SECTION worker.
1924    We just dispatch to the functions for ELF and a.out.  */
1925 
1926 void
cris_target_asm_named_section(const char * name,unsigned int flags,tree decl)1927 cris_target_asm_named_section (const char *name, unsigned int flags,
1928 			       tree decl)
1929 {
1930   if (! TARGET_ELF)
1931     default_no_named_section (name, flags, decl);
1932   else
1933     default_elf_asm_named_section (name, flags, decl);
1934 }
1935 
1936 /* Return TRUE iff X is a CONST valid for e.g. indexing.  */
1937 
1938 bool
cris_valid_pic_const(rtx x)1939 cris_valid_pic_const (rtx x)
1940 {
1941   gcc_assert (flag_pic);
1942 
1943   switch (GET_CODE (x))
1944     {
1945     case CONST_INT:
1946     case CONST_DOUBLE:
1947       return true;
1948     default:
1949       ;
1950     }
1951 
1952   if (GET_CODE (x) != CONST)
1953     return false;
1954 
1955   x = XEXP (x, 0);
1956 
1957   /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))).  */
1958   if (GET_CODE (x) == PLUS
1959       && GET_CODE (XEXP (x, 0)) == UNSPEC
1960       && XINT (XEXP (x, 0), 1) == CRIS_UNSPEC_GOTREL
1961       && GET_CODE (XEXP (x, 1)) == CONST_INT)
1962     x = XEXP (x, 0);
1963 
1964   if (GET_CODE (x) == UNSPEC)
1965     switch (XINT (x, 1))
1966       {
1967       case CRIS_UNSPEC_PLT:
1968       case CRIS_UNSPEC_PLTGOTREAD:
1969       case CRIS_UNSPEC_GOTREAD:
1970       case CRIS_UNSPEC_GOTREL:
1971 	return true;
1972       default:
1973 	gcc_unreachable ();
1974       }
1975 
1976   return cris_pic_symbol_type_of (x) == cris_no_symbol;
1977 }
1978 
1979 /* Helper function to find the right PIC-type symbol to generate,
1980    given the original (non-PIC) representation.  */
1981 
1982 enum cris_pic_symbol_type
cris_pic_symbol_type_of(rtx x)1983 cris_pic_symbol_type_of (rtx x)
1984 {
1985   switch (GET_CODE (x))
1986     {
1987     case SYMBOL_REF:
1988       return SYMBOL_REF_LOCAL_P (x)
1989 	? cris_gotrel_symbol : cris_got_symbol;
1990 
1991     case LABEL_REF:
1992       return cris_gotrel_symbol;
1993 
1994     case CONST:
1995       return cris_pic_symbol_type_of (XEXP (x, 0));
1996 
1997     case PLUS:
1998     case MINUS:
1999       {
2000 	enum cris_pic_symbol_type t1 = cris_pic_symbol_type_of (XEXP (x, 0));
2001 	enum cris_pic_symbol_type t2 = cris_pic_symbol_type_of (XEXP (x, 1));
2002 
2003 	gcc_assert (t1 == cris_no_symbol || t2 == cris_no_symbol);
2004 
2005 	if (t1 == cris_got_symbol || t1 == cris_got_symbol)
2006 	  return cris_got_symbol_needing_fixup;
2007 
2008 	return t1 != cris_no_symbol ? t1 : t2;
2009       }
2010 
2011     case CONST_INT:
2012     case CONST_DOUBLE:
2013       return cris_no_symbol;
2014 
2015     case UNSPEC:
2016       /* Likely an offsettability-test attempting to add a constant to
2017 	 a GOTREAD symbol, which can't be handled.  */
2018       return cris_invalid_pic_symbol;
2019 
2020     default:
2021       fatal_insn ("unrecognized supposed constant", x);
2022     }
2023 
2024   gcc_unreachable ();
2025 }
2026 
2027 /* The LEGITIMATE_PIC_OPERAND_P worker.  */
2028 
2029 int
cris_legitimate_pic_operand(rtx x)2030 cris_legitimate_pic_operand (rtx x)
2031 {
2032   /* Symbols are not valid PIC operands as-is; just constants.  */
2033   return cris_valid_pic_const (x);
2034 }
2035 
2036 /* TARGET_HANDLE_OPTION worker.  We just store the values into local
2037    variables here.  Checks for correct semantics are in
2038    cris_override_options.  */
2039 
2040 static bool
cris_handle_option(size_t code,const char * arg ATTRIBUTE_UNUSED,int value ATTRIBUTE_UNUSED)2041 cris_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED,
2042 		    int value ATTRIBUTE_UNUSED)
2043 {
2044   switch (code)
2045     {
2046     case OPT_metrax100:
2047       target_flags
2048 	|= (MASK_SVINTO
2049 	    + MASK_ETRAX4_ADD
2050 	    + MASK_ALIGN_BY_32);
2051       break;
2052 
2053     case OPT_mno_etrax100:
2054       target_flags
2055 	&= ~(MASK_SVINTO
2056 	     + MASK_ETRAX4_ADD
2057 	     + MASK_ALIGN_BY_32);
2058       break;
2059 
2060     case OPT_m32_bit:
2061     case OPT_m32bit:
2062       target_flags
2063 	|= (MASK_STACK_ALIGN
2064 	    + MASK_CONST_ALIGN
2065 	    + MASK_DATA_ALIGN
2066 	    + MASK_ALIGN_BY_32);
2067       break;
2068 
2069     case OPT_m16_bit:
2070     case OPT_m16bit:
2071       target_flags
2072 	|= (MASK_STACK_ALIGN
2073 	    + MASK_CONST_ALIGN
2074 	    + MASK_DATA_ALIGN);
2075       break;
2076 
2077     case OPT_m8_bit:
2078     case OPT_m8bit:
2079       target_flags
2080 	&= ~(MASK_STACK_ALIGN
2081 	     + MASK_CONST_ALIGN
2082 	     + MASK_DATA_ALIGN);
2083       break;
2084 
2085     default:
2086       break;
2087     }
2088 
2089   CRIS_SUBTARGET_HANDLE_OPTION(code, arg, value);
2090 
2091   return true;
2092 }
2093 
2094 /* The OVERRIDE_OPTIONS worker.
2095    As is the norm, this also parses -mfoo=bar type parameters.  */
2096 
2097 void
cris_override_options(void)2098 cris_override_options (void)
2099 {
2100   if (cris_max_stackframe_str)
2101     {
2102       cris_max_stackframe = atoi (cris_max_stackframe_str);
2103 
2104       /* Do some sanity checking.  */
2105       if (cris_max_stackframe < 0 || cris_max_stackframe > 0x20000000)
2106 	internal_error ("-max-stackframe=%d is not usable, not between 0 and %d",
2107 			cris_max_stackframe, 0x20000000);
2108     }
2109 
2110   /* Let "-metrax4" and "-metrax100" change the cpu version.  */
2111   if (TARGET_SVINTO && cris_cpu_version < CRIS_CPU_SVINTO)
2112     cris_cpu_version = CRIS_CPU_SVINTO;
2113   else if (TARGET_ETRAX4_ADD && cris_cpu_version < CRIS_CPU_ETRAX4)
2114     cris_cpu_version = CRIS_CPU_ETRAX4;
2115 
2116   /* Parse -march=... and its synonym, the deprecated -mcpu=...  */
2117   if (cris_cpu_str)
2118     {
2119       cris_cpu_version
2120 	= (*cris_cpu_str == 'v' ? atoi (cris_cpu_str + 1) : -1);
2121 
2122       if (strcmp ("etrax4", cris_cpu_str) == 0)
2123 	cris_cpu_version = 3;
2124 
2125       if (strcmp ("svinto", cris_cpu_str) == 0
2126 	  || strcmp ("etrax100", cris_cpu_str) == 0)
2127 	cris_cpu_version = 8;
2128 
2129       if (strcmp ("ng", cris_cpu_str) == 0
2130 	  || strcmp ("etrax100lx", cris_cpu_str) == 0)
2131 	cris_cpu_version = 10;
2132 
2133       if (cris_cpu_version < 0 || cris_cpu_version > 10)
2134 	error ("unknown CRIS version specification in -march= or -mcpu= : %s",
2135 	       cris_cpu_str);
2136 
2137       /* Set the target flags.  */
2138       if (cris_cpu_version >= CRIS_CPU_ETRAX4)
2139 	target_flags |= MASK_ETRAX4_ADD;
2140 
2141       /* If this is Svinto or higher, align for 32 bit accesses.  */
2142       if (cris_cpu_version >= CRIS_CPU_SVINTO)
2143 	target_flags
2144 	  |= (MASK_SVINTO | MASK_ALIGN_BY_32
2145 	      | MASK_STACK_ALIGN | MASK_CONST_ALIGN
2146 	      | MASK_DATA_ALIGN);
2147 
2148       /* Note that we do not add new flags when it can be completely
2149 	 described with a macro that uses -mcpu=X.  So
2150 	 TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG).  */
2151     }
2152 
2153   if (cris_tune_str)
2154     {
2155       int cris_tune
2156 	= (*cris_tune_str == 'v' ? atoi (cris_tune_str + 1) : -1);
2157 
2158       if (strcmp ("etrax4", cris_tune_str) == 0)
2159 	cris_tune = 3;
2160 
2161       if (strcmp ("svinto", cris_tune_str) == 0
2162 	  || strcmp ("etrax100", cris_tune_str) == 0)
2163 	cris_tune = 8;
2164 
2165       if (strcmp ("ng", cris_tune_str) == 0
2166 	  || strcmp ("etrax100lx", cris_tune_str) == 0)
2167 	cris_tune = 10;
2168 
2169       if (cris_tune < 0 || cris_tune > 10)
2170 	error ("unknown CRIS cpu version specification in -mtune= : %s",
2171 	       cris_tune_str);
2172 
2173       if (cris_tune >= CRIS_CPU_SVINTO)
2174 	/* We have currently nothing more to tune than alignment for
2175 	   memory accesses.  */
2176 	target_flags
2177 	  |= (MASK_STACK_ALIGN | MASK_CONST_ALIGN
2178 	      | MASK_DATA_ALIGN | MASK_ALIGN_BY_32);
2179     }
2180 
2181   if (flag_pic)
2182     {
2183       /* Use error rather than warning, so invalid use is easily
2184 	 detectable.  Still change to the values we expect, to avoid
2185 	 further errors.  */
2186       if (! TARGET_LINUX)
2187 	{
2188 	  error ("-fPIC and -fpic are not supported in this configuration");
2189 	  flag_pic = 0;
2190 	}
2191 
2192       /* Turn off function CSE.  We need to have the addresses reach the
2193 	 call expanders to get PLT-marked, as they could otherwise be
2194 	 compared against zero directly or indirectly.  After visiting the
2195 	 call expanders they will then be cse:ed, as the call expanders
2196 	 force_reg the addresses, effectively forcing flag_no_function_cse
2197 	 to 0.  */
2198       flag_no_function_cse = 1;
2199     }
2200 
2201   if (write_symbols == DWARF2_DEBUG && ! TARGET_ELF)
2202     {
2203       warning (0, "that particular -g option is invalid with -maout and -melinux");
2204       write_symbols = DBX_DEBUG;
2205     }
2206 
2207   /* Set the per-function-data initializer.  */
2208   init_machine_status = cris_init_machine_status;
2209 }
2210 
2211 /* The TARGET_ASM_OUTPUT_MI_THUNK worker.  */
2212 
2213 static void
cris_asm_output_mi_thunk(FILE * stream,tree thunkdecl ATTRIBUTE_UNUSED,HOST_WIDE_INT delta,HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,tree funcdecl)2214 cris_asm_output_mi_thunk (FILE *stream,
2215 			  tree thunkdecl ATTRIBUTE_UNUSED,
2216 			  HOST_WIDE_INT delta,
2217 			  HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2218 			  tree funcdecl)
2219 {
2220   if (delta > 0)
2221     fprintf (stream, "\tadd%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n",
2222 	     ADDITIVE_SIZE_MODIFIER (delta), delta,
2223 	     reg_names[CRIS_FIRST_ARG_REG]);
2224   else if (delta < 0)
2225     fprintf (stream, "\tsub%s " HOST_WIDE_INT_PRINT_DEC ",$%s\n",
2226 	     ADDITIVE_SIZE_MODIFIER (-delta), -delta,
2227 	     reg_names[CRIS_FIRST_ARG_REG]);
2228 
2229   if (flag_pic)
2230     {
2231       const char *name = XSTR (XEXP (DECL_RTL (funcdecl), 0), 0);
2232 
2233       name = (* targetm.strip_name_encoding) (name);
2234       fprintf (stream, "add.d ");
2235       assemble_name (stream, name);
2236       fprintf (stream, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX);
2237     }
2238   else
2239     {
2240       fprintf (stream, "jump ");
2241       assemble_name (stream, XSTR (XEXP (DECL_RTL (funcdecl), 0), 0));
2242       fprintf (stream, "\n");
2243     }
2244 }
2245 
2246 /* Boilerplate emitted at start of file.
2247 
2248    NO_APP *only at file start* means faster assembly.  It also means
2249    comments are not allowed.  In some cases comments will be output
2250    for debugging purposes.  Make sure they are allowed then.
2251 
2252    We want a .file directive only if TARGET_ELF.  */
2253 static void
cris_file_start(void)2254 cris_file_start (void)
2255 {
2256   /* These expressions can vary at run time, so we cannot put
2257      them into TARGET_INITIALIZER.  */
2258   targetm.file_start_app_off = !(TARGET_PDEBUG || flag_print_asm_name);
2259   targetm.file_start_file_directive = TARGET_ELF;
2260 
2261   default_file_start ();
2262 }
2263 
2264 /* Rename the function calls for integer multiply and divide.  */
2265 static void
cris_init_libfuncs(void)2266 cris_init_libfuncs (void)
2267 {
2268   set_optab_libfunc (smul_optab, SImode, "__Mul");
2269   set_optab_libfunc (sdiv_optab, SImode, "__Div");
2270   set_optab_libfunc (udiv_optab, SImode, "__Udiv");
2271   set_optab_libfunc (smod_optab, SImode, "__Mod");
2272   set_optab_libfunc (umod_optab, SImode, "__Umod");
2273 }
2274 
2275 /* The INIT_EXPANDERS worker sets the per-function-data initializer and
2276    mark functions.  */
2277 
2278 void
cris_init_expanders(void)2279 cris_init_expanders (void)
2280 {
2281   /* Nothing here at the moment.  */
2282 }
2283 
2284 /* Zero initialization is OK for all current fields.  */
2285 
2286 static struct machine_function *
cris_init_machine_status(void)2287 cris_init_machine_status (void)
2288 {
2289   return ggc_alloc_cleared (sizeof (struct machine_function));
2290 }
2291 
2292 /* Split a 2 word move (DI or presumably DF) into component parts.
2293    Originally a copy of gen_split_move_double in m32r.c.  */
2294 
2295 rtx
cris_split_movdx(rtx * operands)2296 cris_split_movdx (rtx *operands)
2297 {
2298   enum machine_mode mode = GET_MODE (operands[0]);
2299   rtx dest = operands[0];
2300   rtx src  = operands[1];
2301   rtx val;
2302 
2303   /* We used to have to handle (SUBREG (MEM)) here, but that should no
2304      longer happen; after reload there are no SUBREGs any more, and we're
2305      only called after reload.  */
2306   CRIS_ASSERT (GET_CODE (dest) != SUBREG && GET_CODE (src) != SUBREG);
2307 
2308   start_sequence ();
2309   if (GET_CODE (dest) == REG)
2310     {
2311       int dregno = REGNO (dest);
2312 
2313       /* Reg-to-reg copy.  */
2314       if (GET_CODE (src) == REG)
2315 	{
2316 	  int sregno = REGNO (src);
2317 
2318 	  int reverse = (dregno == sregno + 1);
2319 
2320 	  /* We normally copy the low-numbered register first.  However, if
2321 	     the first register operand 0 is the same as the second register of
2322 	     operand 1, we must copy in the opposite order.  */
2323 	  emit_insn (gen_rtx_SET (VOIDmode,
2324 				  operand_subword (dest, reverse, TRUE, mode),
2325 				  operand_subword (src, reverse, TRUE, mode)));
2326 
2327 	  emit_insn (gen_rtx_SET (VOIDmode,
2328 				  operand_subword (dest, !reverse, TRUE, mode),
2329 				  operand_subword (src, !reverse, TRUE, mode)));
2330 	}
2331       /* Constant-to-reg copy.  */
2332       else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
2333 	{
2334 	  rtx words[2];
2335 	  split_double (src, &words[0], &words[1]);
2336 	  emit_insn (gen_rtx_SET (VOIDmode,
2337 				  operand_subword (dest, 0, TRUE, mode),
2338 				  words[0]));
2339 
2340 	  emit_insn (gen_rtx_SET (VOIDmode,
2341 				  operand_subword (dest, 1, TRUE, mode),
2342 				  words[1]));
2343 	}
2344       /* Mem-to-reg copy.  */
2345       else if (GET_CODE (src) == MEM)
2346 	{
2347 	  /* If the high-address word is used in the address, we must load it
2348 	     last.  Otherwise, load it first.  */
2349 	  rtx addr = XEXP (src, 0);
2350 	  int reverse
2351 	    = (refers_to_regno_p (dregno, dregno + 1, addr, NULL) != 0);
2352 
2353 	  /* The original code implies that we can't do
2354 	     move.x [rN+],rM  move.x [rN],rM+1
2355 	     when rN is dead, because of REG_NOTES damage.  That is
2356 	     consistent with what I've seen, so don't try it.
2357 
2358              We have two different cases here; if the addr is POST_INC,
2359              just pass it through, otherwise add constants.  */
2360 
2361           if (GET_CODE (addr) == POST_INC)
2362 	    {
2363 	      rtx mem;
2364 	      rtx insn;
2365 
2366 	      /* Whenever we emit insns with post-incremented
2367 		 addresses ourselves, we must add a post-inc note
2368 		 manually.  */
2369 	      mem = change_address (src, SImode, addr);
2370 	      insn
2371 		= gen_rtx_SET (VOIDmode,
2372 			       operand_subword (dest, 0, TRUE, mode), mem);
2373 	      insn = emit_insn (insn);
2374 	      if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2375 		REG_NOTES (insn)
2376 		  = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2377 				     REG_NOTES (insn));
2378 
2379 	      mem = change_address (src, SImode, addr);
2380 	      insn
2381 		= gen_rtx_SET (VOIDmode,
2382 			       operand_subword (dest, 1, TRUE, mode), mem);
2383 	      insn = emit_insn (insn);
2384 	      if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2385 		REG_NOTES (insn)
2386 		  = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2387 				     REG_NOTES (insn));
2388 	    }
2389 	  else
2390 	    {
2391 	      /* Make sure we don't get any other addresses with
2392 		 embedded postincrements.  They should be stopped in
2393 		 GO_IF_LEGITIMATE_ADDRESS, but we're here for your
2394 		 safety.  */
2395 	      if (side_effects_p (addr))
2396 		fatal_insn ("unexpected side-effects in address", addr);
2397 
2398 	      emit_insn (gen_rtx_SET
2399 			 (VOIDmode,
2400 			  operand_subword (dest, reverse, TRUE, mode),
2401 			  change_address
2402 			  (src, SImode,
2403 			   plus_constant (addr,
2404 					  reverse * UNITS_PER_WORD))));
2405 	      emit_insn (gen_rtx_SET
2406 			 (VOIDmode,
2407 			  operand_subword (dest, ! reverse, TRUE, mode),
2408 			  change_address
2409 			  (src, SImode,
2410 			   plus_constant (addr,
2411 					  (! reverse) *
2412 					  UNITS_PER_WORD))));
2413 	    }
2414 	}
2415       else
2416 	internal_error ("Unknown src");
2417     }
2418   /* Reg-to-mem copy or clear mem.  */
2419   else if (GET_CODE (dest) == MEM
2420 	   && (GET_CODE (src) == REG
2421 	       || src == const0_rtx
2422 	       || src == CONST0_RTX (DFmode)))
2423     {
2424       rtx addr = XEXP (dest, 0);
2425 
2426       if (GET_CODE (addr) == POST_INC)
2427 	{
2428 	  rtx mem;
2429 	  rtx insn;
2430 
2431 	  /* Whenever we emit insns with post-incremented addresses
2432 	     ourselves, we must add a post-inc note manually.  */
2433 	  mem = change_address (dest, SImode, addr);
2434 	  insn
2435 	    = gen_rtx_SET (VOIDmode,
2436 			   mem, operand_subword (src, 0, TRUE, mode));
2437 	  insn = emit_insn (insn);
2438 	  if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2439 	    REG_NOTES (insn)
2440 	      = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2441 				 REG_NOTES (insn));
2442 
2443 	  mem = change_address (dest, SImode, addr);
2444 	  insn
2445 	    = gen_rtx_SET (VOIDmode,
2446 			   mem,
2447 			   operand_subword (src, 1, TRUE, mode));
2448 	  insn = emit_insn (insn);
2449 	  if (GET_CODE (XEXP (mem, 0)) == POST_INC)
2450 	    REG_NOTES (insn)
2451 	      = alloc_EXPR_LIST (REG_INC, XEXP (XEXP (mem, 0), 0),
2452 				 REG_NOTES (insn));
2453 	}
2454       else
2455 	{
2456 	  /* Make sure we don't get any other addresses with embedded
2457 	     postincrements.  They should be stopped in
2458 	     GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety.  */
2459 	  if (side_effects_p (addr))
2460 	    fatal_insn ("unexpected side-effects in address", addr);
2461 
2462 	  emit_insn (gen_rtx_SET
2463 		     (VOIDmode,
2464 		      change_address (dest, SImode, addr),
2465 		      operand_subword (src, 0, TRUE, mode)));
2466 
2467 	  emit_insn (gen_rtx_SET
2468 		     (VOIDmode,
2469 		      change_address (dest, SImode,
2470 				      plus_constant (addr,
2471 						     UNITS_PER_WORD)),
2472 		      operand_subword (src, 1, TRUE, mode)));
2473 	}
2474     }
2475 
2476   else
2477     internal_error ("Unknown dest");
2478 
2479   val = get_insns ();
2480   end_sequence ();
2481   return val;
2482 }
2483 
2484 /* The expander for the prologue pattern name.  */
2485 
2486 void
cris_expand_prologue(void)2487 cris_expand_prologue (void)
2488 {
2489   int regno;
2490   int size = get_frame_size ();
2491   /* Shorten the used name for readability.  */
2492   int cfoa_size = current_function_outgoing_args_size;
2493   int last_movem_reg = -1;
2494   int framesize = 0;
2495   rtx mem, insn;
2496   int return_address_on_stack = cris_return_address_on_stack ();
2497   int got_really_used = false;
2498   int n_movem_regs = 0;
2499   int pretend = current_function_pretend_args_size;
2500 
2501   /* Don't do anything if no prologues or epilogues are wanted.  */
2502   if (!TARGET_PROLOGUE_EPILOGUE)
2503     return;
2504 
2505   CRIS_ASSERT (size >= 0);
2506 
2507   if (current_function_uses_pic_offset_table)
2508     {
2509       /* A reference may have been optimized out (like the abort () in
2510 	 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
2511 	 it's still used.  */
2512       push_topmost_sequence ();
2513       got_really_used
2514 	= reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX);
2515       pop_topmost_sequence ();
2516     }
2517 
2518   /* Align the size to what's best for the CPU model.  */
2519   if (TARGET_STACK_ALIGN)
2520     size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1;
2521 
2522   if (pretend)
2523     {
2524       /* See also cris_setup_incoming_varargs where
2525 	 cfun->machine->stdarg_regs is set.  There are other setters of
2526 	 current_function_pretend_args_size than stdarg handling, like
2527 	 for an argument passed with parts in R13 and stack.  We must
2528 	 not store R13 into the pretend-area for that case, as GCC does
2529 	 that itself.  "Our" store would be marked as redundant and GCC
2530 	 will attempt to remove it, which will then be flagged as an
2531 	 internal error; trying to remove a frame-related insn.  */
2532       int stdarg_regs = cfun->machine->stdarg_regs;
2533 
2534       framesize += pretend;
2535 
2536       for (regno = CRIS_FIRST_ARG_REG + CRIS_MAX_ARGS_IN_REGS - 1;
2537 	   stdarg_regs > 0;
2538 	   regno--, pretend -= 4, stdarg_regs--)
2539 	{
2540 	  insn = emit_insn (gen_rtx_SET (VOIDmode,
2541 					 stack_pointer_rtx,
2542 					 plus_constant (stack_pointer_rtx,
2543 							-4)));
2544 	  /* FIXME: When dwarf2 frame output and unless asynchronous
2545 	     exceptions, make dwarf2 bundle together all stack
2546 	     adjustments like it does for registers between stack
2547 	     adjustments.  */
2548 	  RTX_FRAME_RELATED_P (insn) = 1;
2549 
2550 	  mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2551 	  set_mem_alias_set (mem, get_varargs_alias_set ());
2552 	  insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, regno));
2553 
2554 	  /* Note the absence of RTX_FRAME_RELATED_P on the above insn:
2555 	     the value isn't restored, so we don't want to tell dwarf2
2556 	     that it's been stored to stack, else EH handling info would
2557 	     get confused.  */
2558 	}
2559 
2560       /* For other setters of current_function_pretend_args_size, we
2561 	 just adjust the stack by leaving the remaining size in
2562 	 "pretend", handled below.  */
2563     }
2564 
2565   /* Save SRP if not a leaf function.  */
2566   if (return_address_on_stack)
2567     {
2568       insn = emit_insn (gen_rtx_SET (VOIDmode,
2569 				     stack_pointer_rtx,
2570 				     plus_constant (stack_pointer_rtx,
2571 						    -4 - pretend)));
2572       pretend = 0;
2573       RTX_FRAME_RELATED_P (insn) = 1;
2574 
2575       mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2576       set_mem_alias_set (mem, get_frame_alias_set ());
2577       insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM));
2578       RTX_FRAME_RELATED_P (insn) = 1;
2579       framesize += 4;
2580     }
2581 
2582   /* Set up the frame pointer, if needed.  */
2583   if (frame_pointer_needed)
2584     {
2585       insn = emit_insn (gen_rtx_SET (VOIDmode,
2586 				     stack_pointer_rtx,
2587 				     plus_constant (stack_pointer_rtx,
2588 						    -4 - pretend)));
2589       pretend = 0;
2590       RTX_FRAME_RELATED_P (insn) = 1;
2591 
2592       mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2593       set_mem_alias_set (mem, get_frame_alias_set ());
2594       insn = emit_move_insn (mem, frame_pointer_rtx);
2595       RTX_FRAME_RELATED_P (insn) = 1;
2596 
2597       insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
2598       RTX_FRAME_RELATED_P (insn) = 1;
2599 
2600       framesize += 4;
2601     }
2602 
2603   /* Between frame-pointer and saved registers lie the area for local
2604      variables.  If we get here with "pretended" size remaining, count
2605      it into the general stack size.  */
2606   size += pretend;
2607 
2608   /* Get a contiguous sequence of registers, starting with R0, that need
2609      to be saved.  */
2610   for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
2611     {
2612       if (cris_reg_saved_in_regsave_area (regno, got_really_used))
2613 	{
2614 	  n_movem_regs++;
2615 
2616 	  /* Check if movem may be used for registers so far.  */
2617 	  if (regno == last_movem_reg + 1)
2618 	    /* Yes, update next expected register.  */
2619 	    last_movem_reg = regno;
2620 	  else
2621 	    {
2622 	      /* We cannot use movem for all registers.  We have to flush
2623 		 any movem:ed registers we got so far.  */
2624 	      if (last_movem_reg != -1)
2625 		{
2626 		  int n_saved
2627 		    = (n_movem_regs == 1) ? 1 : last_movem_reg + 1;
2628 
2629 		  /* It is a win to use a side-effect assignment for
2630 		     64 <= size <= 128.  But side-effect on movem was
2631 		     not usable for CRIS v0..3.  Also only do it if
2632 		     side-effects insns are allowed.  */
2633 		  if ((last_movem_reg + 1) * 4 + size >= 64
2634 		      && (last_movem_reg + 1) * 4 + size <= 128
2635 		      && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1)
2636 		      && TARGET_SIDE_EFFECT_PREFIXES)
2637 		    {
2638 		      mem
2639 			= gen_rtx_MEM (SImode,
2640 				       plus_constant (stack_pointer_rtx,
2641 						      -(n_saved * 4 + size)));
2642 		      set_mem_alias_set (mem, get_frame_alias_set ());
2643 		      insn
2644 			= cris_emit_movem_store (mem, GEN_INT (n_saved),
2645 						 -(n_saved * 4 + size),
2646 						 true);
2647 		    }
2648 		  else
2649 		    {
2650 		      insn
2651 			= gen_rtx_SET (VOIDmode,
2652 				       stack_pointer_rtx,
2653 				       plus_constant (stack_pointer_rtx,
2654 						      -(n_saved * 4 + size)));
2655 		      insn = emit_insn (insn);
2656 		      RTX_FRAME_RELATED_P (insn) = 1;
2657 
2658 		      mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2659 		      set_mem_alias_set (mem, get_frame_alias_set ());
2660 		      insn = cris_emit_movem_store (mem, GEN_INT (n_saved),
2661 						    0, true);
2662 		    }
2663 
2664 		  framesize += n_saved * 4 + size;
2665 		  last_movem_reg = -1;
2666 		  size = 0;
2667 		}
2668 
2669 	      insn = emit_insn (gen_rtx_SET (VOIDmode,
2670 					     stack_pointer_rtx,
2671 					     plus_constant (stack_pointer_rtx,
2672 							    -4 - size)));
2673 	      RTX_FRAME_RELATED_P (insn) = 1;
2674 
2675 	      mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2676 	      set_mem_alias_set (mem, get_frame_alias_set ());
2677 	      insn = emit_move_insn (mem, gen_rtx_raw_REG (SImode, regno));
2678 	      RTX_FRAME_RELATED_P (insn) = 1;
2679 
2680 	      framesize += 4 + size;
2681 	      size = 0;
2682 	    }
2683 	}
2684     }
2685 
2686   /* Check after, if we could movem all registers.  This is the normal case.  */
2687   if (last_movem_reg != -1)
2688     {
2689       int n_saved
2690 	= (n_movem_regs == 1) ? 1 : last_movem_reg + 1;
2691 
2692       /* Side-effect on movem was not usable for CRIS v0..3.  Also only
2693 	 do it if side-effects insns are allowed.  */
2694       if ((last_movem_reg + 1) * 4 + size >= 64
2695 	  && (last_movem_reg + 1) * 4 + size <= 128
2696 	  && (cris_cpu_version >= CRIS_CPU_SVINTO || n_saved == 1)
2697 	  && TARGET_SIDE_EFFECT_PREFIXES)
2698 	{
2699 	  mem
2700 	    = gen_rtx_MEM (SImode,
2701 			   plus_constant (stack_pointer_rtx,
2702 					  -(n_saved * 4 + size)));
2703 	  set_mem_alias_set (mem, get_frame_alias_set ());
2704 	  insn = cris_emit_movem_store (mem, GEN_INT (n_saved),
2705 					-(n_saved * 4 + size), true);
2706 	}
2707       else
2708 	{
2709 	  insn
2710 	    = gen_rtx_SET (VOIDmode,
2711 			   stack_pointer_rtx,
2712 			   plus_constant (stack_pointer_rtx,
2713 					  -(n_saved * 4 + size)));
2714 	  insn = emit_insn (insn);
2715 	  RTX_FRAME_RELATED_P (insn) = 1;
2716 
2717 	  mem = gen_rtx_MEM (SImode, stack_pointer_rtx);
2718 	  set_mem_alias_set (mem, get_frame_alias_set ());
2719 	  insn = cris_emit_movem_store (mem, GEN_INT (n_saved), 0, true);
2720 	}
2721 
2722       framesize += n_saved * 4 + size;
2723       /* We have to put outgoing argument space after regs.  */
2724       if (cfoa_size)
2725 	{
2726 	  insn = emit_insn (gen_rtx_SET (VOIDmode,
2727 					 stack_pointer_rtx,
2728 					 plus_constant (stack_pointer_rtx,
2729 							-cfoa_size)));
2730 	  RTX_FRAME_RELATED_P (insn) = 1;
2731 	  framesize += cfoa_size;
2732 	}
2733     }
2734   else if ((size + cfoa_size) > 0)
2735     {
2736       insn = emit_insn (gen_rtx_SET (VOIDmode,
2737 				     stack_pointer_rtx,
2738 				     plus_constant (stack_pointer_rtx,
2739 						    -(cfoa_size + size))));
2740       RTX_FRAME_RELATED_P (insn) = 1;
2741       framesize += size + cfoa_size;
2742     }
2743 
2744   /* Set up the PIC register, if it is used.  */
2745   if (got_really_used)
2746     {
2747       rtx got
2748 	= gen_rtx_UNSPEC (SImode, gen_rtvec (1, const0_rtx), CRIS_UNSPEC_GOT);
2749       emit_move_insn (pic_offset_table_rtx, got);
2750 
2751       /* FIXME: This is a cover-up for flow2 messing up; it doesn't
2752 	 follow exceptional paths and tries to delete the GOT load as
2753 	 unused, if it isn't used on the non-exceptional paths.  Other
2754 	 ports have similar or other cover-ups, or plain bugs marking
2755 	 the GOT register load as maybe-dead.  To see this, remove the
2756 	 line below and try libsupc++/vec.cc or a trivial
2757 	 "static void y (); void x () {try {y ();} catch (...) {}}".  */
2758       emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2759     }
2760 
2761   if (cris_max_stackframe && framesize > cris_max_stackframe)
2762     warning (0, "stackframe too big: %d bytes", framesize);
2763 }
2764 
2765 /* The expander for the epilogue pattern.  */
2766 
2767 void
cris_expand_epilogue(void)2768 cris_expand_epilogue (void)
2769 {
2770   int regno;
2771   int size = get_frame_size ();
2772   int last_movem_reg = -1;
2773   int argspace_offset = current_function_outgoing_args_size;
2774   int pretend =	 current_function_pretend_args_size;
2775   rtx mem;
2776   bool return_address_on_stack = cris_return_address_on_stack ();
2777   /* A reference may have been optimized out
2778      (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1)
2779      so check that it's still used.  */
2780   int got_really_used = false;
2781   int n_movem_regs = 0;
2782 
2783   if (!TARGET_PROLOGUE_EPILOGUE)
2784     return;
2785 
2786   if (current_function_uses_pic_offset_table)
2787     {
2788       /* A reference may have been optimized out (like the abort () in
2789 	 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
2790 	 it's still used.  */
2791       push_topmost_sequence ();
2792       got_really_used
2793 	= reg_used_between_p (pic_offset_table_rtx, get_insns (), NULL_RTX);
2794       pop_topmost_sequence ();
2795     }
2796 
2797   /* Align byte count of stack frame.  */
2798   if (TARGET_STACK_ALIGN)
2799     size = TARGET_ALIGN_BY_32 ? (size + 3) & ~3 : (size + 1) & ~1;
2800 
2801   /* Check how many saved regs we can movem.  They start at r0 and must
2802      be contiguous.  */
2803   for (regno = 0;
2804        regno < FIRST_PSEUDO_REGISTER;
2805        regno++)
2806     if (cris_reg_saved_in_regsave_area (regno, got_really_used))
2807       {
2808 	n_movem_regs++;
2809 
2810 	if (regno == last_movem_reg + 1)
2811 	  last_movem_reg = regno;
2812 	else
2813 	  break;
2814       }
2815 
2816   /* If there was only one register that really needed to be saved
2817      through movem, don't use movem.  */
2818   if (n_movem_regs == 1)
2819     last_movem_reg = -1;
2820 
2821   /* Now emit "normal" move insns for all regs higher than the movem
2822      regs.  */
2823   for (regno = FIRST_PSEUDO_REGISTER - 1;
2824        regno > last_movem_reg;
2825        regno--)
2826     if (cris_reg_saved_in_regsave_area (regno, got_really_used))
2827       {
2828 	rtx insn;
2829 
2830 	if (argspace_offset)
2831 	  {
2832 	    /* There is an area for outgoing parameters located before
2833 	       the saved registers.  We have to adjust for that.  */
2834 	    emit_insn (gen_rtx_SET (VOIDmode,
2835 				    stack_pointer_rtx,
2836 				    plus_constant (stack_pointer_rtx,
2837 						   argspace_offset)));
2838 	    /* Make sure we only do this once.  */
2839 	    argspace_offset = 0;
2840 	  }
2841 
2842 	mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode,
2843 						     stack_pointer_rtx));
2844 	set_mem_alias_set (mem, get_frame_alias_set ());
2845 	insn = emit_move_insn (gen_rtx_raw_REG (SImode, regno), mem);
2846 
2847 	/* Whenever we emit insns with post-incremented addresses
2848 	   ourselves, we must add a post-inc note manually.  */
2849 	REG_NOTES (insn)
2850 	  = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
2851       }
2852 
2853   /* If we have any movem-restore, do it now.  */
2854   if (last_movem_reg != -1)
2855     {
2856       rtx insn;
2857 
2858       if (argspace_offset)
2859 	{
2860 	  emit_insn (gen_rtx_SET (VOIDmode,
2861 				  stack_pointer_rtx,
2862 				  plus_constant (stack_pointer_rtx,
2863 						 argspace_offset)));
2864 	  argspace_offset = 0;
2865 	}
2866 
2867       mem = gen_rtx_MEM (SImode,
2868 			 gen_rtx_POST_INC (SImode, stack_pointer_rtx));
2869       set_mem_alias_set (mem, get_frame_alias_set ());
2870       insn
2871 	= emit_insn (cris_gen_movem_load (mem,
2872 					  GEN_INT (last_movem_reg + 1), 0));
2873       /* Whenever we emit insns with post-incremented addresses
2874 	 ourselves, we must add a post-inc note manually.  */
2875       if (side_effects_p (PATTERN (insn)))
2876 	REG_NOTES (insn)
2877 	  = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
2878     }
2879 
2880   /* If we don't clobber all of the allocated stack area (we've already
2881      deallocated saved registers), GCC might want to schedule loads from
2882      the stack to *after* the stack-pointer restore, which introduces an
2883      interrupt race condition.  This happened for the initial-value
2884      SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of
2885      other failure for that test).  It also happened for the stack slot
2886      for the return value in (one version of)
2887      linux/fs/dcache.c:__d_lookup, at least with "-O2
2888      -fno-omit-frame-pointer".  */
2889 
2890   /* Restore frame pointer if necessary.  */
2891   if (frame_pointer_needed)
2892     {
2893       rtx insn;
2894 
2895       emit_insn (gen_cris_frame_deallocated_barrier ());
2896 
2897       emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
2898       mem = gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode,
2899 						   stack_pointer_rtx));
2900       set_mem_alias_set (mem, get_frame_alias_set ());
2901       insn = emit_move_insn (frame_pointer_rtx, mem);
2902 
2903       /* Whenever we emit insns with post-incremented addresses
2904 	 ourselves, we must add a post-inc note manually.  */
2905       REG_NOTES (insn)
2906 	= alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
2907     }
2908   else if ((size + argspace_offset) != 0)
2909     {
2910       emit_insn (gen_cris_frame_deallocated_barrier ());
2911 
2912       /* If there was no frame-pointer to restore sp from, we must
2913 	 explicitly deallocate local variables.  */
2914 
2915       /* Handle space for outgoing parameters that hasn't been handled
2916 	 yet.  */
2917       size += argspace_offset;
2918 
2919       emit_insn (gen_rtx_SET (VOIDmode,
2920 			      stack_pointer_rtx,
2921 			      plus_constant (stack_pointer_rtx, size)));
2922     }
2923 
2924   /* If this function has no pushed register parameters
2925      (stdargs/varargs), and if it is not a leaf function, then we have
2926      the return address on the stack.  */
2927   if (return_address_on_stack && pretend == 0)
2928     {
2929       if (current_function_calls_eh_return)
2930 	{
2931 	  rtx mem;
2932 	  rtx insn;
2933 	  rtx srpreg = gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM);
2934 	  mem = gen_rtx_MEM (SImode,
2935 			     gen_rtx_POST_INC (SImode,
2936 					       stack_pointer_rtx));
2937 	  set_mem_alias_set (mem, get_frame_alias_set ());
2938 	  insn = emit_move_insn (srpreg, mem);
2939 
2940 	  /* Whenever we emit insns with post-incremented addresses
2941 	     ourselves, we must add a post-inc note manually.  */
2942 	  REG_NOTES (insn)
2943 	    = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
2944 
2945 	  emit_insn (gen_addsi3 (stack_pointer_rtx,
2946 				 stack_pointer_rtx,
2947 				 gen_rtx_raw_REG (SImode,
2948 						  CRIS_STACKADJ_REG)));
2949 	  cris_expand_return (false);
2950 	}
2951       else
2952 	cris_expand_return (true);
2953 
2954       return;
2955     }
2956 
2957   /* If we pushed some register parameters, then adjust the stack for
2958      them.  */
2959   if (pretend != 0)
2960     {
2961       /* If SRP is stored on the way, we need to restore it first.  */
2962       if (return_address_on_stack)
2963 	{
2964 	  rtx mem;
2965 	  rtx srpreg = gen_rtx_raw_REG (SImode, CRIS_SRP_REGNUM);
2966 	  rtx insn;
2967 
2968 	  mem = gen_rtx_MEM (SImode,
2969 			     gen_rtx_POST_INC (SImode,
2970 					       stack_pointer_rtx));
2971 	  set_mem_alias_set (mem, get_frame_alias_set ());
2972 	  insn = emit_move_insn (srpreg, mem);
2973 
2974 	  /* Whenever we emit insns with post-incremented addresses
2975 	     ourselves, we must add a post-inc note manually.  */
2976 	  REG_NOTES (insn)
2977 	    = alloc_EXPR_LIST (REG_INC, stack_pointer_rtx, REG_NOTES (insn));
2978 	}
2979 
2980       emit_insn (gen_rtx_SET (VOIDmode,
2981 			      stack_pointer_rtx,
2982 			      plus_constant (stack_pointer_rtx, pretend)));
2983     }
2984 
2985   /* Perform the "physical" unwinding that the EH machinery calculated.  */
2986   if (current_function_calls_eh_return)
2987     emit_insn (gen_addsi3 (stack_pointer_rtx,
2988 			   stack_pointer_rtx,
2989 			   gen_rtx_raw_REG (SImode,
2990 					    CRIS_STACKADJ_REG)));
2991   cris_expand_return (false);
2992 }
2993 
2994 /* Worker function for generating movem from mem for load_multiple.  */
2995 
2996 rtx
cris_gen_movem_load(rtx src,rtx nregs_rtx,int nprefix)2997 cris_gen_movem_load (rtx src, rtx nregs_rtx, int nprefix)
2998 {
2999   int nregs = INTVAL (nregs_rtx);
3000   rtvec vec;
3001   int eltno = 1;
3002   int i;
3003   rtx srcreg = XEXP (src, 0);
3004   unsigned int regno = nregs - 1;
3005   int regno_inc = -1;
3006 
3007   if (GET_CODE (srcreg) == POST_INC)
3008     srcreg = XEXP (srcreg, 0);
3009 
3010   CRIS_ASSERT (REG_P (srcreg));
3011 
3012   /* Don't use movem for just one insn.  The insns are equivalent except
3013      for the pipeline hazard (on v32); movem does not forward the loaded
3014      registers so there's a three cycles penalty for their use.  */
3015   if (nregs == 1)
3016     return gen_movsi (gen_rtx_REG (SImode, 0), src);
3017 
3018   vec = rtvec_alloc (nprefix + nregs
3019 		     + (GET_CODE (XEXP (src, 0)) == POST_INC));
3020 
3021   if (GET_CODE (XEXP (src, 0)) == POST_INC)
3022     {
3023       RTVEC_ELT (vec, nprefix + 1)
3024 	= gen_rtx_SET (VOIDmode, srcreg, plus_constant (srcreg, nregs * 4));
3025       eltno++;
3026     }
3027 
3028   src = replace_equiv_address (src, srcreg);
3029   RTVEC_ELT (vec, nprefix)
3030     = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno), src);
3031   regno += regno_inc;
3032 
3033   for (i = 1; i < nregs; i++, eltno++)
3034     {
3035       RTVEC_ELT (vec, nprefix + eltno)
3036 	= gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno),
3037 		       adjust_address_nv (src, SImode, i * 4));
3038       regno += regno_inc;
3039     }
3040 
3041   return gen_rtx_PARALLEL (VOIDmode, vec);
3042 }
3043 
3044 /* Worker function for generating movem to mem.  If FRAME_RELATED, notes
3045    are added that the dwarf2 machinery understands.  */
3046 
3047 rtx
cris_emit_movem_store(rtx dest,rtx nregs_rtx,int increment,bool frame_related)3048 cris_emit_movem_store (rtx dest, rtx nregs_rtx, int increment,
3049 		       bool frame_related)
3050 {
3051   int nregs = INTVAL (nregs_rtx);
3052   rtvec vec;
3053   int eltno = 1;
3054   int i;
3055   rtx insn;
3056   rtx destreg = XEXP (dest, 0);
3057   unsigned int regno = nregs - 1;
3058   int regno_inc = -1;
3059 
3060   if (GET_CODE (destreg) == POST_INC)
3061     increment += nregs * 4;
3062 
3063   if (GET_CODE (destreg) == POST_INC || GET_CODE (destreg) == PLUS)
3064     destreg = XEXP (destreg, 0);
3065 
3066   CRIS_ASSERT (REG_P (destreg));
3067 
3068   /* Don't use movem for just one insn.  The insns are equivalent except
3069      for the pipeline hazard (on v32); movem does not forward the loaded
3070      registers so there's a three cycles penalty for use.  */
3071   if (nregs == 1)
3072     {
3073       rtx mov = gen_rtx_SET (VOIDmode, dest, gen_rtx_REG (SImode, 0));
3074 
3075       if (increment == 0)
3076 	{
3077 	  insn = emit_insn (mov);
3078 	  if (frame_related)
3079 	    RTX_FRAME_RELATED_P (insn) = 1;
3080 	  return insn;
3081 	}
3082 
3083       /* If there was a request for a side-effect, create the ordinary
3084          parallel.  */
3085       vec = rtvec_alloc (2);
3086 
3087       RTVEC_ELT (vec, 0) = mov;
3088       RTVEC_ELT (vec, 1) = gen_rtx_SET (VOIDmode, destreg,
3089 					plus_constant (destreg, increment));
3090       if (frame_related)
3091 	{
3092 	  RTX_FRAME_RELATED_P (mov) = 1;
3093 	  RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1;
3094 	}
3095     }
3096   else
3097     {
3098       vec = rtvec_alloc (nregs + (increment != 0 ? 1 : 0));
3099       RTVEC_ELT (vec, 0)
3100 	= gen_rtx_SET (VOIDmode,
3101 		       replace_equiv_address (dest,
3102 					      plus_constant (destreg,
3103 							     increment)),
3104 		       gen_rtx_REG (SImode, regno));
3105       regno += regno_inc;
3106 
3107       /* The dwarf2 info wants this mark on each component in a parallel
3108 	 that's part of the prologue (though it's optional on the first
3109 	 component).  */
3110       if (frame_related)
3111 	RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 0)) = 1;
3112 
3113       if (increment != 0)
3114 	{
3115 	  RTVEC_ELT (vec, 1)
3116 	    = gen_rtx_SET (VOIDmode, destreg,
3117 			   plus_constant (destreg,
3118 					  increment != 0
3119 					  ? increment : nregs * 4));
3120 	  eltno++;
3121 
3122 	  if (frame_related)
3123 	    RTX_FRAME_RELATED_P (RTVEC_ELT (vec, 1)) = 1;
3124 
3125 	  /* Don't call adjust_address_nv on a post-incremented address if
3126 	     we can help it.  */
3127 	  if (GET_CODE (XEXP (dest, 0)) == POST_INC)
3128 	    dest = replace_equiv_address (dest, destreg);
3129 	}
3130 
3131       for (i = 1; i < nregs; i++, eltno++)
3132 	{
3133 	  RTVEC_ELT (vec, eltno)
3134 	    = gen_rtx_SET (VOIDmode, adjust_address_nv (dest, SImode, i * 4),
3135 			   gen_rtx_REG (SImode, regno));
3136 	  if (frame_related)
3137 	    RTX_FRAME_RELATED_P (RTVEC_ELT (vec, eltno)) = 1;
3138 	  regno += regno_inc;
3139 	}
3140     }
3141 
3142   insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
3143 
3144   /* Because dwarf2out.c handles the insns in a parallel as a sequence,
3145      we need to keep the stack adjustment separate, after the
3146      MEM-setters.  Else the stack-adjustment in the second component of
3147      the parallel would be mishandled; the offsets for the SETs that
3148      follow it would be wrong.  We prepare for this by adding a
3149      REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE
3150      followed by the increment.  Note that we have FRAME_RELATED_P on
3151      all the SETs, including the original stack adjustment SET in the
3152      parallel.  */
3153   if (frame_related)
3154     {
3155       if (increment != 0)
3156 	{
3157 	  rtx seq = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (nregs + 1));
3158 	  XVECEXP (seq, 0, 0) = XVECEXP (PATTERN (insn), 0, 0);
3159 	  for (i = 1; i < nregs; i++)
3160 	    XVECEXP (seq, 0, i) = XVECEXP (PATTERN (insn), 0, i + 1);
3161 	  XVECEXP (seq, 0, nregs) = XVECEXP (PATTERN (insn), 0, 1);
3162 	  REG_NOTES (insn)
3163 	    = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, seq,
3164 				 REG_NOTES (insn));
3165 	}
3166 
3167       RTX_FRAME_RELATED_P (insn) = 1;
3168     }
3169 
3170   return insn;
3171 }
3172 
3173 /* Worker function for expanding the address for PIC function calls.  */
3174 
3175 void
cris_expand_pic_call_address(rtx * opp)3176 cris_expand_pic_call_address (rtx *opp)
3177 {
3178   rtx op = *opp;
3179 
3180   gcc_assert (MEM_P (op));
3181   op = XEXP (op, 0);
3182 
3183   /* It might be that code can be generated that jumps to 0 (or to a
3184      specific address).  Don't die on that.  (There is a
3185      testcase.)  */
3186   if (CONSTANT_ADDRESS_P (op) && GET_CODE (op) != CONST_INT)
3187     {
3188       enum cris_pic_symbol_type t = cris_pic_symbol_type_of (op);
3189 
3190       CRIS_ASSERT (!no_new_pseudos);
3191 
3192       /* For local symbols (non-PLT), just get the plain symbol
3193 	 reference into a register.  For symbols that can be PLT, make
3194 	 them PLT.  */
3195       if (t == cris_gotrel_symbol)
3196 	op = force_reg (Pmode, op);
3197       else if (t == cris_got_symbol)
3198 	{
3199 	  if (TARGET_AVOID_GOTPLT)
3200 	    {
3201 	      /* Change a "jsr sym" into (allocate register rM, rO)
3202 		 "move.d (const (unspec [sym] CRIS_UNSPEC_PLT)),rM"
3203 		 "add.d rPIC,rM,rO", "jsr rO".  */
3204 	      rtx tem, rm, ro;
3205 	      gcc_assert (! no_new_pseudos);
3206 	      current_function_uses_pic_offset_table = 1;
3207 	      tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op), CRIS_UNSPEC_PLT);
3208 	      rm = gen_reg_rtx (Pmode);
3209 	      emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
3210 	      ro = gen_reg_rtx (Pmode);
3211 	      if (expand_binop (Pmode, add_optab, rm,
3212 				pic_offset_table_rtx,
3213 				ro, 0, OPTAB_LIB_WIDEN) != ro)
3214 		internal_error ("expand_binop failed in movsi got");
3215 	      op = ro;
3216 	    }
3217 	  else
3218 	    {
3219 	      /* Change a "jsr sym" into (allocate register rM, rO)
3220 		 "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOT)),rM"
3221 		 "add.d rPIC,rM,rO" "jsr [rO]" with the memory access
3222 		 marked as not trapping and not aliasing.  No "move.d
3223 		 [rO],rP" as that would invite to re-use of a value
3224 		 that should not be reused.  FIXME: Need a peephole2
3225 		 for cases when this is cse:d from the call, to change
3226 		 back to just get the PLT entry address, so we don't
3227 		 resolve the same symbol over and over (the memory
3228 		 access of the PLTGOT isn't constant).  */
3229 	      rtx tem, mem, rm, ro;
3230 
3231 	      gcc_assert (! no_new_pseudos);
3232 	      current_function_uses_pic_offset_table = 1;
3233 	      tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op),
3234 				    CRIS_UNSPEC_PLTGOTREAD);
3235 	      rm = gen_reg_rtx (Pmode);
3236 	      emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
3237 	      ro = gen_reg_rtx (Pmode);
3238 	      if (expand_binop (Pmode, add_optab, rm,
3239 				pic_offset_table_rtx,
3240 				ro, 0, OPTAB_LIB_WIDEN) != ro)
3241 		internal_error ("expand_binop failed in movsi got");
3242 	      mem = gen_rtx_MEM (Pmode, ro);
3243 
3244 	      /* This MEM doesn't alias anything.  Whether it aliases
3245 		 other same symbols is unimportant.  */
3246 	      set_mem_alias_set (mem, new_alias_set ());
3247 	      MEM_NOTRAP_P (mem) = 1;
3248 	      op = mem;
3249 	    }
3250 	}
3251       else
3252 	/* Can't possibly get a GOT-needing-fixup for a function-call,
3253 	   right?  */
3254 	fatal_insn ("Unidentifiable call op", op);
3255 
3256       *opp = replace_equiv_address (*opp, op);
3257     }
3258 }
3259 
3260 /* Make sure operands are in the right order for an addsi3 insn as
3261    generated by a define_split.  A MEM as the first operand isn't
3262    recognized by addsi3 after reload.  OPERANDS contains the operands,
3263    with the first at OPERANDS[N] and the second at OPERANDS[N+1].  */
3264 
3265 void
cris_order_for_addsi3(rtx * operands,int n)3266 cris_order_for_addsi3 (rtx *operands, int n)
3267 {
3268   if (MEM_P (operands[n]))
3269     {
3270       rtx tem = operands[n];
3271       operands[n] = operands[n + 1];
3272       operands[n + 1] = tem;
3273     }
3274 }
3275 
3276 /* Use from within code, from e.g. PRINT_OPERAND and
3277    PRINT_OPERAND_ADDRESS.  Macros used in output_addr_const need to emit
3278    different things depending on whether code operand or constant is
3279    emitted.  */
3280 
3281 static void
cris_output_addr_const(FILE * file,rtx x)3282 cris_output_addr_const (FILE *file, rtx x)
3283 {
3284   in_code++;
3285   output_addr_const (file, x);
3286   in_code--;
3287 }
3288 
3289 /* Worker function for ASM_OUTPUT_SYMBOL_REF.  */
3290 
3291 void
cris_asm_output_symbol_ref(FILE * file,rtx x)3292 cris_asm_output_symbol_ref (FILE *file, rtx x)
3293 {
3294   gcc_assert (GET_CODE (x) == SYMBOL_REF);
3295 
3296   if (flag_pic && in_code > 0)
3297     {
3298      const char *origstr = XSTR (x, 0);
3299      const char *str;
3300      str = (* targetm.strip_name_encoding) (origstr);
3301      assemble_name (file, str);
3302 
3303      /* Sanity check.  */
3304      if (! current_function_uses_pic_offset_table)
3305        output_operand_lossage ("PIC register isn't set up");
3306     }
3307   else
3308     assemble_name (file, XSTR (x, 0));
3309 }
3310 
3311 /* Worker function for ASM_OUTPUT_LABEL_REF.  */
3312 
3313 void
cris_asm_output_label_ref(FILE * file,char * buf)3314 cris_asm_output_label_ref (FILE *file, char *buf)
3315 {
3316   if (flag_pic && in_code > 0)
3317     {
3318       assemble_name (file, buf);
3319 
3320       /* Sanity check.  */
3321       if (! current_function_uses_pic_offset_table)
3322 	internal_error ("emitting PIC operand, but PIC register isn't set up");
3323     }
3324   else
3325     assemble_name (file, buf);
3326 }
3327 
3328 /* Worker function for OUTPUT_ADDR_CONST_EXTRA.  */
3329 
3330 bool
cris_output_addr_const_extra(FILE * file,rtx xconst)3331 cris_output_addr_const_extra (FILE *file, rtx xconst)
3332 {
3333   switch (GET_CODE (xconst))
3334     {
3335       rtx x;
3336 
3337     case UNSPEC:
3338       x = XVECEXP (xconst, 0, 0);
3339       CRIS_ASSERT (GET_CODE (x) == SYMBOL_REF
3340 		   || GET_CODE (x) == LABEL_REF
3341 		   || GET_CODE (x) == CONST);
3342       output_addr_const (file, x);
3343       switch (XINT (xconst, 1))
3344 	{
3345 	case CRIS_UNSPEC_PLT:
3346 	  fprintf (file, ":PLTG");
3347 	  break;
3348 
3349 	case CRIS_UNSPEC_GOTREL:
3350 	  fprintf (file, ":GOTOFF");
3351 	  break;
3352 
3353 	case CRIS_UNSPEC_GOTREAD:
3354 	  if (flag_pic == 1)
3355 	    fprintf (file, ":GOT16");
3356 	  else
3357 	    fprintf (file, ":GOT");
3358 	  break;
3359 
3360 	case CRIS_UNSPEC_PLTGOTREAD:
3361 	  if (flag_pic == 1)
3362 	    fprintf (file, CRIS_GOTPLT_SUFFIX "16");
3363 	  else
3364 	    fprintf (file, CRIS_GOTPLT_SUFFIX);
3365 	  break;
3366 
3367 	default:
3368 	  gcc_unreachable ();
3369 	}
3370       return true;
3371 
3372     default:
3373       return false;
3374     }
3375 }
3376 
3377 /* Worker function for TARGET_STRUCT_VALUE_RTX.  */
3378 
3379 static rtx
cris_struct_value_rtx(tree fntype ATTRIBUTE_UNUSED,int incoming ATTRIBUTE_UNUSED)3380 cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
3381 		       int incoming ATTRIBUTE_UNUSED)
3382 {
3383   return gen_rtx_REG (Pmode, CRIS_STRUCT_VALUE_REGNUM);
3384 }
3385 
3386 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.  */
3387 
3388 static void
cris_setup_incoming_varargs(CUMULATIVE_ARGS * ca,enum machine_mode mode ATTRIBUTE_UNUSED,tree type ATTRIBUTE_UNUSED,int * pretend_arg_size,int second_time)3389 cris_setup_incoming_varargs (CUMULATIVE_ARGS *ca,
3390 			     enum machine_mode mode ATTRIBUTE_UNUSED,
3391 			     tree type ATTRIBUTE_UNUSED,
3392 			     int *pretend_arg_size,
3393 			     int second_time)
3394 {
3395   if (ca->regs < CRIS_MAX_ARGS_IN_REGS)
3396     {
3397       int stdarg_regs = CRIS_MAX_ARGS_IN_REGS - ca->regs;
3398       cfun->machine->stdarg_regs = stdarg_regs;
3399       *pretend_arg_size = stdarg_regs * 4;
3400     }
3401 
3402   if (TARGET_PDEBUG)
3403     fprintf (asm_out_file,
3404 	     "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n",
3405 	     ca->regs, *pretend_arg_size, second_time);
3406 }
3407 
3408 /* Return true if TYPE must be passed by invisible reference.
3409    For cris, we pass <= 8 bytes by value, others by reference.  */
3410 
3411 static bool
cris_pass_by_reference(CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED,enum machine_mode mode,tree type,bool named ATTRIBUTE_UNUSED)3412 cris_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
3413 			enum machine_mode mode, tree type,
3414 			bool named ATTRIBUTE_UNUSED)
3415 {
3416   return (targetm.calls.must_pass_in_stack (mode, type)
3417 	  || CRIS_FUNCTION_ARG_SIZE (mode, type) > 8);
3418 }
3419 
3420 
3421 static int
cris_arg_partial_bytes(CUMULATIVE_ARGS * ca,enum machine_mode mode,tree type,bool named ATTRIBUTE_UNUSED)3422 cris_arg_partial_bytes (CUMULATIVE_ARGS *ca, enum machine_mode mode,
3423 			tree type, bool named ATTRIBUTE_UNUSED)
3424 {
3425   if (ca->regs == CRIS_MAX_ARGS_IN_REGS - 1
3426       && !targetm.calls.must_pass_in_stack (mode, type)
3427       && CRIS_FUNCTION_ARG_SIZE (mode, type) > 4
3428       && CRIS_FUNCTION_ARG_SIZE (mode, type) <= 8)
3429     return UNITS_PER_WORD;
3430   else
3431     return 0;
3432 }
3433 
3434 /* Worker function for TARGET_MD_ASM_CLOBBERS.  */
3435 
3436 static tree
cris_md_asm_clobbers(tree outputs,tree inputs,tree in_clobbers)3437 cris_md_asm_clobbers (tree outputs, tree inputs, tree in_clobbers)
3438 {
3439   HARD_REG_SET mof_set;
3440   tree clobbers;
3441   tree t;
3442 
3443   CLEAR_HARD_REG_SET (mof_set);
3444   SET_HARD_REG_BIT (mof_set, CRIS_MOF_REGNUM);
3445 
3446   /* For the time being, all asms clobber condition codes.  Revisit when
3447      there's a reasonable use for inputs/outputs that mention condition
3448      codes.  */
3449   clobbers
3450     = tree_cons (NULL_TREE,
3451 		 build_string (strlen (reg_names[CRIS_CC0_REGNUM]),
3452 			       reg_names[CRIS_CC0_REGNUM]),
3453 		 in_clobbers);
3454 
3455   for (t = outputs; t != NULL; t = TREE_CHAIN (t))
3456     {
3457       tree val = TREE_VALUE (t);
3458 
3459       /* The constraint letter for the singleton register class of MOF
3460 	 is 'h'.  If it's mentioned in the constraints, the asm is
3461 	 MOF-aware and adding it to the clobbers would cause it to have
3462 	 impossible constraints.  */
3463       if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t))),
3464 		  'h') != NULL
3465 	  || tree_overlaps_hard_reg_set (val, &mof_set) != NULL_TREE)
3466 	return clobbers;
3467     }
3468 
3469   for (t = inputs; t != NULL; t = TREE_CHAIN (t))
3470     {
3471       tree val = TREE_VALUE (t);
3472 
3473       if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t))),
3474 		  'h') != NULL
3475 	  || tree_overlaps_hard_reg_set (val, &mof_set) != NULL_TREE)
3476 	return clobbers;
3477     }
3478 
3479   return tree_cons (NULL_TREE,
3480 		    build_string (strlen (reg_names[CRIS_MOF_REGNUM]),
3481 				  reg_names[CRIS_MOF_REGNUM]),
3482 		    clobbers);
3483 }
3484 
3485 #if 0
3486 /* Various small functions to replace macros.  Only called from a
3487    debugger.  They might collide with gcc functions or system functions,
3488    so only emit them when '#if 1' above.  */
3489 
3490 enum rtx_code Get_code (rtx);
3491 
3492 enum rtx_code
3493 Get_code (rtx x)
3494 {
3495   return GET_CODE (x);
3496 }
3497 
3498 const char *Get_mode (rtx);
3499 
3500 const char *
3501 Get_mode (rtx x)
3502 {
3503   return GET_MODE_NAME (GET_MODE (x));
3504 }
3505 
3506 rtx Xexp (rtx, int);
3507 
3508 rtx
3509 Xexp (rtx x, int n)
3510 {
3511   return XEXP (x, n);
3512 }
3513 
3514 rtx Xvecexp (rtx, int, int);
3515 
3516 rtx
3517 Xvecexp (rtx x, int n, int m)
3518 {
3519   return XVECEXP (x, n, m);
3520 }
3521 
3522 int Get_rtx_len (rtx);
3523 
3524 int
3525 Get_rtx_len (rtx x)
3526 {
3527   return GET_RTX_LENGTH (GET_CODE (x));
3528 }
3529 
3530 /* Use upper-case to distinguish from local variables that are sometimes
3531    called next_insn and prev_insn.  */
3532 
3533 rtx Next_insn (rtx);
3534 
3535 rtx
3536 Next_insn (rtx insn)
3537 {
3538   return NEXT_INSN (insn);
3539 }
3540 
3541 rtx Prev_insn (rtx);
3542 
3543 rtx
3544 Prev_insn (rtx insn)
3545 {
3546   return PREV_INSN (insn);
3547 }
3548 #endif
3549 
3550 #include "gt-cris.h"
3551 
3552 /*
3553  * Local variables:
3554  * eval: (c-set-style "gnu")
3555  * indent-tabs-mode: t
3556  * End:
3557  */
3558