1 /* Target Definitions for R8C/M16C/M32C 2 Copyright (C) 2005 3 Free Software Foundation, Inc. 4 Contributed by Red Hat. 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify it 9 under the terms of the GNU General Public License as published 10 by the Free Software Foundation; either version 2, or (at your 11 option) any later version. 12 13 GCC is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING. If not, write to the Free 20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 21 02110-1301, USA. */ 22 23 #ifndef GCC_M32C_H 24 #define GCC_M32C_H 25 26 /* Controlling the Compilation Driver, `gcc'. */ 27 28 #undef STARTFILE_SPEC 29 #define STARTFILE_SPEC "crt0.o%s crtbegin.o%s" 30 31 /* There are four CPU series we support, but they basically break down 32 into two families - the R8C/M16C families, with 16 bit address 33 registers and one set of opcodes, and the M32CM/M32C group, with 24 34 bit address registers and a different set of opcodes. The 35 assembler doesn't care except for which opcode set is needed; the 36 big difference is in the memory maps, which we cover in 37 LIB_SPEC. */ 38 39 #undef ASM_SPEC 40 #define ASM_SPEC "\ 41 %{mcpu=r8c:--m16c} \ 42 %{mcpu=m16c:--m16c} \ 43 %{mcpu=m32cm:--m32c} \ 44 %{mcpu=m32c:--m32c} " 45 46 /* The default is R8C hardware. We support a simulator, which has its 47 own libgloss and link map, plus one default link map for each chip 48 family. Most of the logic here is making sure we do the right 49 thing when no CPU is specified, which defaults to R8C. */ 50 #undef LIB_SPEC 51 #define LIB_SPEC "-( -lc %{msim*:-lsim}%{!msim*:-lnosys} -) \ 52 %{msim*:%{!T*: %{mcpu=m32cm:-Tsim24.ld}%{mcpu=m32c:-Tsim24.ld} \ 53 %{!mcpu=m32cm:%{!mcpu=m32c:-Tsim16.ld}}}} \ 54 %{!T*:%{!msim*: %{mcpu=m16c:-Tm16c.ld} \ 55 %{mcpu=m32cm:-Tm32cm.ld} \ 56 %{mcpu=m32c:-Tm32c.ld} \ 57 %{!mcpu=m16c:%{!mcpu=m32cm:%{!mcpu=m32c:-Tr8c.ld}}}}} \ 58 " 59 60 /* Run-time Target Specification */ 61 62 /* Nothing unusual here. */ 63 #define TARGET_CPU_CPP_BUILTINS() \ 64 { \ 65 builtin_assert ("cpu=m32c"); \ 66 builtin_assert ("machine=m32c"); \ 67 builtin_define ("__m32c__=1"); \ 68 if (TARGET_R8C) \ 69 builtin_define ("__r8c_cpu__=1"); \ 70 if (TARGET_M16C) \ 71 builtin_define ("__m16c_cpu__=1"); \ 72 if (TARGET_M32CM) \ 73 builtin_define ("__m32cm_cpu__=1"); \ 74 if (TARGET_M32C) \ 75 builtin_define ("__m32c_cpu__=1"); \ 76 } 77 78 /* The pragma handlers need to know if we've started processing 79 functions yet, as the memregs pragma should only be given at the 80 beginning of the file. This variable starts off TRUE and later 81 becomes FALSE. */ 82 extern int ok_to_change_target_memregs; 83 extern int target_memregs; 84 85 /* TARGET_CPU is a multi-way option set in m32c.opt. While we could 86 use enums or defines for this, this and m32c.opt are the only 87 places that know (or care) what values are being used. */ 88 #define TARGET_R8C (target_cpu == 'r') 89 #define TARGET_M16C (target_cpu == '6') 90 #define TARGET_M32CM (target_cpu == 'm') 91 #define TARGET_M32C (target_cpu == '3') 92 93 /* Address register sizes. Warning: these are used all over the place 94 to select between the two CPU families in general. */ 95 #define TARGET_A16 (TARGET_R8C || TARGET_M16C) 96 #define TARGET_A24 (TARGET_M32CM || TARGET_M32C) 97 98 #define TARGET_VERSION fprintf (stderr, " (m32c)"); 99 100 #define OVERRIDE_OPTIONS m32c_override_options (); 101 102 /* Defining data structures for per-function information */ 103 104 typedef struct machine_function GTY (()) 105 { 106 /* How much we adjust the stack when returning from an exception 107 handler. */ 108 rtx eh_stack_adjust; 109 110 /* TRUE if the current function is an interrupt handler. */ 111 int is_interrupt; 112 113 /* TRUE if the current function is a leaf function. Currently, this 114 only affects saving $a0 in interrupt functions. */ 115 int is_leaf; 116 117 /* Bitmask that keeps track of which registers are used in an 118 interrupt function, so we know which ones need to be saved and 119 restored. */ 120 int intr_pushm; 121 /* Likewise, one element for each memreg that needs to be saved. */ 122 char intr_pushmem[16]; 123 124 /* TRUE if the current function can use a simple RTS to return, instead 125 of the longer ENTER/EXIT pair. */ 126 int use_rts; 127 } 128 machine_function; 129 130 #define INIT_EXPANDERS m32c_init_expanders () 131 132 /* Storage Layout */ 133 134 #define BITS_BIG_ENDIAN 0 135 #define BYTES_BIG_ENDIAN 0 136 #define WORDS_BIG_ENDIAN 0 137 138 /* We can do QI, HI, and SI operations pretty much equally well, but 139 GCC expects us to have a "native" format, so we pick the one that 140 matches "int". Pointers are 16 bits for R8C/M16C (when TARGET_A16 141 is true) and 24 bits for M32CM/M32C (when TARGET_A24 is true), but 142 24 bit pointers are stored in 32 bit words. */ 143 #define BITS_PER_UNIT 8 144 #define UNITS_PER_WORD 2 145 #define POINTER_SIZE (TARGET_A16 ? 16 : 32) 146 #define POINTERS_EXTEND_UNSIGNED 1 147 148 /* These match the alignment enforced by the two types of stack operations. */ 149 #define PARM_BOUNDARY (TARGET_A16 ? 8 : 16) 150 #define STACK_BOUNDARY (TARGET_A16 ? 8 : 16) 151 152 /* We do this because we care more about space than about speed. For 153 the chips with 16 bit busses, we could set these to 16 if 154 desired. */ 155 #define FUNCTION_BOUNDARY 8 156 #define BIGGEST_ALIGNMENT 8 157 158 #define STRICT_ALIGNMENT 0 159 #define SLOW_BYTE_ACCESS 1 160 161 /* Layout of Source Language Data Types */ 162 163 #define INT_TYPE_SIZE 16 164 #define SHORT_TYPE_SIZE 16 165 #define LONG_TYPE_SIZE 32 166 #define LONG_LONG_TYPE_SIZE 64 167 168 #define FLOAT_TYPE_SIZE 32 169 #define DOUBLE_TYPE_SIZE 64 170 #define LONG_DOUBLE_TYPE_SIZE 64 171 172 #define DEFAULT_SIGNED_CHAR 1 173 174 /* REGISTER USAGE */ 175 176 /* Register Basics */ 177 178 /* Register layout: 179 180 [r0h][r0l] $r0 (16 bits, or two 8 bit halves) 181 [--------] $r2 (16 bits) 182 [r1h][r1l] $r1 (16 bits, or two 8 bit halves) 183 [--------] $r3 (16 bits) 184 [---][--------] $a0 (might be 24 bits) 185 [---][--------] $a1 (might be 24 bits) 186 [---][--------] $sb (might be 24 bits) 187 [---][--------] $fb (might be 24 bits) 188 [---][--------] $sp (might be 24 bits) 189 [-------------] $pc (20 or 24 bits) 190 [---] $flg (CPU flags) 191 [---][--------] $argp (virtual) 192 [--------] $mem0 (all 16 bits) 193 . . . 194 [--------] $mem14 195 */ 196 197 #define FIRST_PSEUDO_REGISTER 20 198 199 /* Note that these two tables are modified based on which CPU family 200 you select; see m32c_conditional_register_usage for details. */ 201 202 /* r0 r2 r1 r3 - a0 a1 sb fb - sp pc flg argp - mem0..mem14 */ 203 #define FIXED_REGISTERS { 0, 0, 0, 0, \ 204 0, 0, 1, 0, \ 205 1, 1, 0, 1, \ 206 0, 0, 0, 0, 0, 0, 0, 0 } 207 #define CALL_USED_REGISTERS { 1, 1, 1, 1, \ 208 1, 1, 1, 0, \ 209 1, 1, 1, 1, \ 210 1, 1, 1, 1, 1, 1, 1, 1 } 211 212 #define CONDITIONAL_REGISTER_USAGE m32c_conditional_register_usage (); 213 214 /* The *_REGNO theme matches m32c.md and most register number 215 arguments; the PC_REGNUM is the odd one out. */ 216 #ifndef PC_REGNO 217 #define PC_REGNO 9 218 #endif 219 #define PC_REGNUM PC_REGNO 220 221 /* How Values Fit in Registers */ 222 223 #define HARD_REGNO_NREGS(R,M) m32c_hard_regno_nregs (R, M) 224 #define HARD_REGNO_MODE_OK(R,M) m32c_hard_regno_ok (R, M) 225 #define MODES_TIEABLE_P(M1,M2) m32c_modes_tieable_p (M1, M2) 226 #define AVOID_CCMODE_COPIES 227 228 /* Register Classes */ 229 230 /* Most registers are special purpose in some form or another, so this 231 table is pretty big. Class names are used for constraints also; 232 for example the HL_REGS class (HL below) is "Rhl" in the md files. 233 See m32c_reg_class_from_constraint for the mapping. There's some 234 duplication so that we can better isolate the reason for using 235 constraints in the md files from the actual registers used; for 236 example we may want to exclude a1a0 from SI_REGS in the future, 237 without precluding their use as HImode registers. */ 238 239 /* m7654 - m3210 - argp flg pc sp - fb sb a1 a0 - r3 r1 r2 r0 */ 240 /* mmPAR */ 241 #define REG_CLASS_CONTENTS \ 242 { { 0x00000000 }, /* NO */\ 243 { 0x00000100 }, /* SP - sp */\ 244 { 0x00000080 }, /* FB - fb */\ 245 { 0x00000040 }, /* SB - sb */\ 246 { 0x000001c0 }, /* CR - sb fb sp */\ 247 { 0x00000001 }, /* R0 - r0 */\ 248 { 0x00000004 }, /* R1 - r1 */\ 249 { 0x00000002 }, /* R2 - r2 */\ 250 { 0x00000008 }, /* R3 - r3 */\ 251 { 0x00000003 }, /* R02 - r0r2 */\ 252 { 0x00000005 }, /* HL - r0 r1 */\ 253 { 0x00000005 }, /* QI - r0 r1 */\ 254 { 0x0000000a }, /* R23 - r2 r3 */\ 255 { 0x0000000f }, /* R03 - r0r2 r1r3 */\ 256 { 0x0000000f }, /* DI - r0r2r1r3 + mems */\ 257 { 0x00000030 }, /* A - a0 a1 */\ 258 { 0x000000f0 }, /* AD - a0 a1 sb fp */\ 259 { 0x000001f0 }, /* PS - a0 a1 sb fp sp */\ 260 { 0x0000003f }, /* SI - r0r2 r1r3 a0a1 */\ 261 { 0x0000003f }, /* HI - r0 r1 r2 r3 a0 a1 */\ 262 { 0x0000003f }, /* RA - r0..r3 a0 a1 */\ 263 { 0x0000007f }, /* GENERAL */\ 264 { 0x00000400 }, /* FLG */\ 265 { 0x000001ff }, /* HC - r0l r1 r2 r3 a0 a1 sb fb sp */\ 266 { 0x000ff000 }, /* MEM */\ 267 { 0x000ff003 }, /* R02_A_MEM */\ 268 { 0x000ff005 }, /* A_HL_MEM */\ 269 { 0x000ff00c }, /* R1_R3_A_MEM */\ 270 { 0x000ff00f }, /* R03_MEM */\ 271 { 0x000ff03f }, /* A_HI_MEM */\ 272 { 0x000ff0ff }, /* A_AD_CR_MEM_SI */\ 273 { 0x000ff1ff }, /* ALL */\ 274 } 275 276 enum reg_class 277 { 278 NO_REGS, 279 SP_REGS, 280 FB_REGS, 281 SB_REGS, 282 CR_REGS, 283 R0_REGS, 284 R1_REGS, 285 R2_REGS, 286 R3_REGS, 287 R02_REGS, 288 HL_REGS, 289 QI_REGS, 290 R23_REGS, 291 R03_REGS, 292 DI_REGS, 293 A_REGS, 294 AD_REGS, 295 PS_REGS, 296 SI_REGS, 297 HI_REGS, 298 RA_REGS, 299 GENERAL_REGS, 300 FLG_REGS, 301 HC_REGS, 302 MEM_REGS, 303 R02_A_MEM_REGS, 304 A_HL_MEM_REGS, 305 R1_R3_A_MEM_REGS, 306 R03_MEM_REGS, 307 A_HI_MEM_REGS, 308 A_AD_CR_MEM_SI_REGS, 309 ALL_REGS, 310 LIM_REG_CLASSES 311 }; 312 313 #define N_REG_CLASSES LIM_REG_CLASSES 314 315 #define REG_CLASS_NAMES {\ 316 "NO_REGS", \ 317 "SP_REGS", \ 318 "FB_REGS", \ 319 "SB_REGS", \ 320 "CR_REGS", \ 321 "R0_REGS", \ 322 "R1_REGS", \ 323 "R2_REGS", \ 324 "R3_REGS", \ 325 "R02_REGS", \ 326 "HL_REGS", \ 327 "QI_REGS", \ 328 "R23_REGS", \ 329 "R03_REGS", \ 330 "DI_REGS", \ 331 "A_REGS", \ 332 "AD_REGS", \ 333 "PS_REGS", \ 334 "SI_REGS", \ 335 "HI_REGS", \ 336 "RA_REGS", \ 337 "GENERAL_REGS", \ 338 "FLG_REGS", \ 339 "HC_REGS", \ 340 "MEM_REGS", \ 341 "R02_A_MEM_REGS", \ 342 "A_HL_MEM_REGS", \ 343 "R1_R3_A_MEM_REGS", \ 344 "R03_MEM_REGS", \ 345 "A_HI_MEM_REGS", \ 346 "A_AD_CR_MEM_SI_REGS", \ 347 "ALL_REGS", \ 348 } 349 350 #define REGNO_REG_CLASS(R) m32c_regno_reg_class (R) 351 352 /* We support simple displacements off address registers, nothing else. */ 353 #define BASE_REG_CLASS A_REGS 354 #define INDEX_REG_CLASS NO_REGS 355 356 /* We primarily use the new "long" constraint names, with the initial 357 letter classifying the constraint type and following letters 358 specifying which. The types are: 359 360 I - integer values 361 R - register classes 362 S - memory references (M was used) 363 A - addresses (currently unused) 364 */ 365 366 #define CONSTRAINT_LEN(CHAR,STR) \ 367 ((CHAR) == 'I' ? 3 \ 368 : (CHAR) == 'R' ? 3 \ 369 : (CHAR) == 'S' ? 2 \ 370 : (CHAR) == 'A' ? 2 \ 371 : DEFAULT_CONSTRAINT_LEN(CHAR,STR)) 372 #define REG_CLASS_FROM_CONSTRAINT(CHAR,STR) \ 373 m32c_reg_class_from_constraint (CHAR, STR) 374 375 #define REGNO_OK_FOR_BASE_P(NUM) m32c_regno_ok_for_base_p (NUM) 376 #define REGNO_OK_FOR_INDEX_P(NUM) 0 377 378 #define PREFERRED_RELOAD_CLASS(X,CLASS) m32c_preferred_reload_class (X, CLASS) 379 #define PREFERRED_OUTPUT_RELOAD_CLASS(X,CLASS) m32c_preferred_output_reload_class (X, CLASS) 380 #define LIMIT_RELOAD_CLASS(MODE,CLASS) m32c_limit_reload_class (MODE, CLASS) 381 382 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,X) m32c_secondary_reload_class (CLASS, MODE, X) 383 384 #define SMALL_REGISTER_CLASSES 1 385 386 #define CLASS_LIKELY_SPILLED_P(C) m32c_class_likely_spilled_p (C) 387 388 #define CLASS_MAX_NREGS(C,M) m32c_class_max_nregs (C, M) 389 390 #define CANNOT_CHANGE_MODE_CLASS(F,T,C) m32c_cannot_change_mode_class(F,T,C) 391 392 #define CONST_OK_FOR_CONSTRAINT_P(VALUE,C,STR) \ 393 m32c_const_ok_for_constraint_p (VALUE, C, STR) 394 #define CONST_DOUBLE_OK_FOR_CONSTRAINT_P(VALUE,C,STR) 0 395 #define EXTRA_CONSTRAINT_STR(VALUE,C,STR) \ 396 m32c_extra_constraint_p (VALUE, C, STR) 397 #define EXTRA_MEMORY_CONSTRAINT(C,STR) \ 398 m32c_extra_memory_constraint (C, STR) 399 #define EXTRA_ADDRESS_CONSTRAINT(C,STR) \ 400 m32c_extra_address_constraint (C, STR) 401 402 /* STACK AND CALLING */ 403 404 /* Frame Layout */ 405 406 /* Standard push/pop stack, no surprises here. */ 407 408 #define STACK_GROWS_DOWNWARD 1 409 #define STACK_PUSH_CODE PRE_DEC 410 #define FRAME_GROWS_DOWNWARD 1 411 412 #define STARTING_FRAME_OFFSET 0 413 #define FIRST_PARM_OFFSET(F) 0 414 415 #define RETURN_ADDR_RTX(COUNT,FA) m32c_return_addr_rtx (COUNT) 416 417 #define INCOMING_RETURN_ADDR_RTX m32c_incoming_return_addr_rtx() 418 #define INCOMING_FRAME_SP_OFFSET 3 419 420 /* Exception Handling Support */ 421 422 #define EH_RETURN_DATA_REGNO(N) m32c_eh_return_data_regno (N) 423 #define EH_RETURN_STACKADJ_RTX m32c_eh_return_stackadj_rtx () 424 425 /* Registers That Address the Stack Frame */ 426 427 #ifndef FP_REGNO 428 #define FP_REGNO 7 429 #endif 430 #ifndef SP_REGNO 431 #define SP_REGNO 8 432 #endif 433 #define AP_REGNO 11 434 435 #define STACK_POINTER_REGNUM SP_REGNO 436 #define FRAME_POINTER_REGNUM FP_REGNO 437 #define ARG_POINTER_REGNUM AP_REGNO 438 439 /* The static chain must be pointer-capable. */ 440 #define STATIC_CHAIN_REGNUM A0_REGNO 441 442 #define DWARF_FRAME_REGISTERS 20 443 #define DWARF_FRAME_REGNUM(N) m32c_dwarf_frame_regnum (N) 444 #define DBX_REGISTER_NUMBER(N) m32c_dwarf_frame_regnum (N) 445 446 /* Eliminating Frame Pointer and Arg Pointer */ 447 448 /* If the frame pointer isn't used, we detect it manually. But the 449 stack pointer doesn't have as flexible addressing as the frame 450 pointer, so we always assume we have it. */ 451 #define FRAME_POINTER_REQUIRED 1 452 453 #define ELIMINABLE_REGS \ 454 {{AP_REGNO, SP_REGNO}, \ 455 {AP_REGNO, FB_REGNO}, \ 456 {FB_REGNO, SP_REGNO}} 457 458 #define CAN_ELIMINATE(FROM,TO) 1 459 #define INITIAL_ELIMINATION_OFFSET(FROM,TO,VAR) \ 460 (VAR) = m32c_initial_elimination_offset(FROM,TO) 461 462 /* Passing Function Arguments on the Stack */ 463 464 #define PUSH_ARGS 1 465 #define PUSH_ROUNDING(N) m32c_push_rounding (N) 466 #define RETURN_POPS_ARGS(D,T,S) 0 467 #define CALL_POPS_ARGS(C) 0 468 469 /* Passing Arguments in Registers */ 470 471 #define FUNCTION_ARG(CA,MODE,TYPE,NAMED) \ 472 m32c_function_arg (&(CA),MODE,TYPE,NAMED) 473 474 typedef struct m32c_cumulative_args 475 { 476 /* For address of return value buffer (structures are returned by 477 passing the address of a buffer as an invisible first argument. 478 This identifies it). If set, the current parameter will be put 479 on the stack, regardless of type. */ 480 int force_mem; 481 /* First parm is 1, parm 0 is hidden pointer for returning 482 aggregates. */ 483 int parm_num; 484 } m32c_cumulative_args; 485 486 #define CUMULATIVE_ARGS m32c_cumulative_args 487 #define INIT_CUMULATIVE_ARGS(CA,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \ 488 m32c_init_cumulative_args (&(CA),FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) 489 #define FUNCTION_ARG_ADVANCE(CA,MODE,TYPE,NAMED) \ 490 m32c_function_arg_advance (&(CA),MODE,TYPE,NAMED) 491 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) (TARGET_A16 ? 8 : 16) 492 #define FUNCTION_ARG_REGNO_P(r) m32c_function_arg_regno_p (r) 493 494 /* How Scalar Function Values Are Returned */ 495 496 #define FUNCTION_VALUE(VT,F) m32c_function_value (VT, F) 497 #define LIBCALL_VALUE(MODE) m32c_libcall_value (MODE) 498 499 #define FUNCTION_VALUE_REGNO_P(r) ((r) == R0_REGNO || (r) == MEM0_REGNO) 500 501 /* How Large Values Are Returned */ 502 503 #define DEFAULT_PCC_STRUCT_RETURN 1 504 505 /* Function Entry and Exit */ 506 507 #define EXIT_IGNORE_STACK 0 508 #define EPILOGUE_USES(REGNO) m32c_epilogue_uses(REGNO) 509 #define EH_USES(REGNO) 0 /* FIXME */ 510 511 /* Generating Code for Profiling */ 512 513 #define FUNCTION_PROFILER(FILE,LABELNO) 514 515 /* Implementing the Varargs Macros */ 516 517 /* Trampolines for Nested Functions */ 518 519 #define TRAMPOLINE_SIZE m32c_trampoline_size () 520 #define TRAMPOLINE_ALIGNMENT m32c_trampoline_alignment () 521 #define INITIALIZE_TRAMPOLINE(a,fn,sc) m32c_initialize_trampoline (a, fn, sc) 522 523 /* Addressing Modes */ 524 525 #define HAVE_PRE_DECREMENT 1 526 #define HAVE_POST_INCREMENT 1 527 #define CONSTANT_ADDRESS_P(X) CONSTANT_P(X) 528 #define MAX_REGS_PER_ADDRESS 1 529 530 /* This is passed to the macros below, so that they can be implemented 531 in m32c.c. */ 532 #ifdef REG_OK_STRICT 533 #define REG_OK_STRICT_V 1 534 #else 535 #define REG_OK_STRICT_V 0 536 #endif 537 538 #define GO_IF_LEGITIMATE_ADDRESS(MODE,X,LABEL) \ 539 if (m32c_legitimate_address_p (MODE, X, REG_OK_STRICT_V)) \ 540 goto LABEL; 541 542 #define REG_OK_FOR_BASE_P(X) m32c_reg_ok_for_base_p (X, REG_OK_STRICT_V) 543 #define REG_OK_FOR_INDEX_P(X) 0 544 545 /* #define FIND_BASE_TERM(X) when we do unspecs for symrefs */ 546 547 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 548 if (m32c_legitimize_address(&(X),OLDX,MODE)) \ 549 goto win; 550 551 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 552 if (m32c_legitimize_reload_address(&(X),MODE,OPNUM,TYPE,IND_LEVELS)) \ 553 goto win; 554 555 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 556 if (m32c_mode_dependent_address (ADDR)) \ 557 goto LABEL; 558 559 #define LEGITIMATE_CONSTANT_P(X) m32c_legitimate_constant_p (X) 560 561 /* Condition Code Status */ 562 563 #define REVERSIBLE_CC_MODE(MODE) 1 564 565 /* Describing Relative Costs of Operations */ 566 567 #define REGISTER_MOVE_COST(MODE,FROM,TO) \ 568 m32c_register_move_cost (MODE, FROM, TO) 569 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \ 570 m32c_memory_move_cost (MODE, CLASS, IN) 571 572 /* Dividing the Output into Sections (Texts, Data, ...) */ 573 574 #define TEXT_SECTION_ASM_OP ".text" 575 #define DATA_SECTION_ASM_OP ".data" 576 #define BSS_SECTION_ASM_OP ".bss" 577 578 /* The Overall Framework of an Assembler File */ 579 580 #define ASM_COMMENT_START ";" 581 #define ASM_APP_ON "" 582 #define ASM_APP_OFF "" 583 584 /* Output and Generation of Labels */ 585 586 #define GLOBAL_ASM_OP "\t.global\t" 587 588 /* Output of Assembler Instructions */ 589 590 #define REGISTER_NAMES { \ 591 "r0", "r2", "r1", "r3", \ 592 "a0", "a1", "sb", "fb", "sp", \ 593 "pc", "flg", "argp", \ 594 "mem0", "mem2", "mem4", "mem6", "mem8", "mem10", "mem12", "mem14", \ 595 } 596 597 #define ADDITIONAL_REGISTER_NAMES { \ 598 {"r0l", 0}, \ 599 {"r1l", 2}, \ 600 {"r0r2", 0}, \ 601 {"r1r3", 2}, \ 602 {"a0a1", 4}, \ 603 {"r0r2r1r3", 0} } 604 605 #define PRINT_OPERAND(S,X,C) m32c_print_operand (S, X, C) 606 #define PRINT_OPERAND_PUNCT_VALID_P(C) m32c_print_operand_punct_valid_p (C) 607 #define PRINT_OPERAND_ADDRESS(S,X) m32c_print_operand_address (S, X) 608 609 #undef USER_LABEL_PREFIX 610 #define USER_LABEL_PREFIX "_" 611 612 #define ASM_OUTPUT_REG_PUSH(S,R) m32c_output_reg_push (S, R) 613 #define ASM_OUTPUT_REG_POP(S,R) m32c_output_reg_pop (S, R) 614 615 /* Output of Dispatch Tables */ 616 617 #define ASM_OUTPUT_ADDR_VEC_ELT(S,V) \ 618 fprintf (S, "\t.word L%d\n", V) 619 620 /* Assembler Commands for Exception Regions */ 621 622 #define DWARF_CIE_DATA_ALIGNMENT -1 623 624 /* Assembler Commands for Alignment */ 625 626 #define ASM_OUTPUT_ALIGN(STREAM,POWER) \ 627 fprintf (STREAM, "\t.p2align\t%d\n", POWER); 628 629 /* Controlling Debugging Information Format */ 630 631 #define DWARF2_ADDR_SIZE 4 632 633 /* Miscellaneous Parameters */ 634 635 #define HAS_LONG_COND_BRANCH false 636 #define HAS_LONG_UNCOND_BRANCH true 637 #define CASE_VECTOR_MODE SImode 638 #define LOAD_EXTEND_OP(MEM) ZERO_EXTEND 639 640 #define MOVE_MAX 4 641 #define TRULY_NOOP_TRUNCATION(op,ip) 1 642 643 /* 16 or 24 bit pointers */ 644 #define Pmode (TARGET_A16 ? HImode : PSImode) 645 #define FUNCTION_MODE QImode 646 647 #define REGISTER_TARGET_PRAGMAS() m32c_register_pragmas() 648 649 #endif 650