1;; 2;; DFA-based pipeline description for Broadcom SB-1 3;; 4 5;; The Broadcom SB-1 core is 4-way superscalar, in-order. It has 2 load/store 6;; pipes (one of which can support some ALU operations), 2 alu pipes, 2 FP 7;; pipes, and 1 MDMX pipes. It can issue 2 ls insns and 2 exe/fpu/mdmx insns 8;; each cycle. 9 10;; We model the 4-way issue by ordering unit choices. The possible choices are 11;; {ex1,fp1}|{ex0,fp0}|ls1|ls0. Instructions issue to the first eligible unit 12;; in the list in most cases. Non-indexed load/stores issue to ls0 first. 13;; simple alu operations issue to ls1 if it is still available, and their 14;; operands are ready (no co-issue with loads), otherwise to the first 15;; available ex unit. 16 17;; When exceptions are enabled, can only issue FP insns to fp1. This is 18;; to ensure that instructions complete in order. The -mfp-exceptions option 19;; can be used to specify whether the system has FP exceptions enabled or not. 20 21;; In 32-bit mode, dependent FP can't co-issue with load, and only one FP exe 22;; insn can issue per cycle (fp1). 23 24;; The A1 MDMX pipe is separate from the FP pipes, but uses the same register 25;; file. As a result, once an MDMX insn is issued, no FP insns can be issued 26;; for 3 cycles. When an FP insn is issued, no MDMX insn can be issued for 27;; 5 cycles. This is currently not handled because there is no MDMX insn 28;; support as yet. 29 30;; 31;; We use two automata. sb1_cpu_div is for the integer divides, which are 32;; not pipelined. sb1_cpu is for everything else. 33;; 34(define_automaton "sb1_cpu, sb1_cpu_div") 35 36;; Load/store function units. 37(define_cpu_unit "sb1_ls0" "sb1_cpu") 38(define_cpu_unit "sb1_ls1" "sb1_cpu") 39 40;; CPU function units. 41(define_cpu_unit "sb1_ex0" "sb1_cpu") 42(define_cpu_unit "sb1_ex1" "sb1_cpu") 43 44;; The divide unit is not pipelined, and blocks hi/lo reads and writes. 45(define_cpu_unit "sb1_div" "sb1_cpu_div") 46;; DMULT block any multiply from issuing in the next cycle. 47(define_cpu_unit "sb1_mul" "sb1_cpu") 48 49;; Floating-point units. 50(define_cpu_unit "sb1_fp0" "sb1_cpu") 51(define_cpu_unit "sb1_fp1" "sb1_cpu") 52 53;; Can only issue to one of the ex and fp pipes at a time. 54(exclusion_set "sb1_ex0" "sb1_fp0") 55(exclusion_set "sb1_ex1" "sb1_fp1") 56 57;; Define an SB-1 specific attribute to simplify some FP descriptions. 58;; We can use 2 FP pipes only if we have 64-bit FP code, and exceptions are 59;; disabled. 60 61(define_attr "sb1_fp_pipes" "one,two" 62 (cond [(and (ne (symbol_ref "TARGET_FLOAT64") (const_int 0)) 63 (eq (symbol_ref "TARGET_FP_EXCEPTIONS") (const_int 0))) 64 (const_string "two")] 65 (const_string "one"))) 66 67;; Define reservations for common combinations. 68 69;; For long cycle operations, the FPU has a 4 cycle pipeline that repeats, 70;; effectively re-issuing the operation every 4 cycles. This means that we 71;; can have at most 4 long-cycle operations per pipe. 72 73;; ??? The fdiv operations should be e.g. 74;; sb1_fp1_4cycles*7" | "sb1_fp0_4cycle*7 75;; but the DFA is too large when we do that. Perhaps have to use scheduler 76;; hooks here. 77 78;; ??? Try limiting scheduler to 2 long latency operations, and see if this 79;; results in a usable DFA, and whether it helps code performance. 80 81;;(define_reservation "sb1_fp0_4cycles" "sb1_fp0, nothing*3") 82;;(define_reservation "sb1_fp1_4cycles" "sb1_fp1, nothing*3") 83 84;; 85;; The ordering of the instruction-execution-path/resource-usage 86;; descriptions (also known as reservation RTL) is roughly ordered 87;; based on the define attribute RTL for the "type" classification. 88;; When modifying, remember that the first test that matches is the 89;; reservation used! 90;; 91 92(define_insn_reservation "ir_sb1_unknown" 1 93 (and (eq_attr "cpu" "sb1") 94 (eq_attr "type" "unknown,multi")) 95 "sb1_ls0+sb1_ls1+sb1_ex0+sb1_ex1+sb1_fp0+sb1_fp1") 96 97;; predicted taken branch causes 2 cycle ifetch bubble. predicted not 98;; taken branch causes 0 cycle ifetch bubble. mispredicted branch causes 8 99;; cycle ifetch bubble. We assume all branches predicted not taken. 100 101;; ??? This assumption that branches are predicated not taken should be 102;; investigated. Maybe using 2 here will give better results. 103 104(define_insn_reservation "ir_sb1_branch" 0 105 (and (eq_attr "cpu" "sb1") 106 (eq_attr "type" "branch,jump,call")) 107 "sb1_ex0") 108 109;; ??? This is 1 cycle for ldl/ldr to ldl/ldr when they use the same data 110;; register as destination. 111 112;; ??? Can co-issue a load with a dependent arith insn if it executes on an EX 113;; unit. Can not co-issue if the dependent insn executes on an LS unit. 114 115;; A load normally has a latency of zero cycles. In some cases, dependent 116;; insns can be issued in the same cycle. However, a value of 1 gives 117;; better performance in empirical testing. 118 119(define_insn_reservation "ir_sb1_load" 1 120 (and (eq_attr "cpu" "sb1") 121 (eq_attr "type" "load,prefetch")) 122 "sb1_ls0 | sb1_ls1") 123 124;; Can not co-issue fpload with fp exe when in 32-bit mode. 125 126(define_insn_reservation "ir_sb1_fpload" 0 127 (and (eq_attr "cpu" "sb1") 128 (and (eq_attr "type" "fpload") 129 (ne (symbol_ref "TARGET_FLOAT64") 130 (const_int 0)))) 131 "sb1_ls0 | sb1_ls1") 132 133(define_insn_reservation "ir_sb1_fpload_32bitfp" 1 134 (and (eq_attr "cpu" "sb1") 135 (and (eq_attr "type" "fpload") 136 (eq (symbol_ref "TARGET_FLOAT64") 137 (const_int 0)))) 138 "sb1_ls0 | sb1_ls1") 139 140;; Indexed loads can only execute on LS1 pipe. 141 142(define_insn_reservation "ir_sb1_fpidxload" 0 143 (and (eq_attr "cpu" "sb1") 144 (and (eq_attr "type" "fpidxload") 145 (ne (symbol_ref "TARGET_FLOAT64") 146 (const_int 0)))) 147 "sb1_ls1") 148 149(define_insn_reservation "ir_sb1_fpidxload_32bitfp" 1 150 (and (eq_attr "cpu" "sb1") 151 (and (eq_attr "type" "fpidxload") 152 (eq (symbol_ref "TARGET_FLOAT64") 153 (const_int 0)))) 154 "sb1_ls1") 155 156;; prefx can only execute on the ls1 pipe. 157 158(define_insn_reservation "ir_sb1_prefetchx" 0 159 (and (eq_attr "cpu" "sb1") 160 (eq_attr "type" "prefetchx")) 161 "sb1_ls1") 162 163;; ??? There is a 4.5 cycle latency if a store is followed by a load, and 164;; there is a RAW dependency. 165 166(define_insn_reservation "ir_sb1_store" 1 167 (and (eq_attr "cpu" "sb1") 168 (eq_attr "type" "store")) 169 "sb1_ls0+sb1_ex1 | sb1_ls0+sb1_ex0 | sb1_ls1+sb1_ex1 | sb1_ls1+sb1_ex0") 170 171(define_insn_reservation "ir_sb1_fpstore" 1 172 (and (eq_attr "cpu" "sb1") 173 (eq_attr "type" "fpstore")) 174 "sb1_ls0+sb1_fp1 | sb1_ls0+sb1_fp0 | sb1_ls1+sb1_fp1 | sb1_ls1+sb1_fp0") 175 176;; Indexed stores can only execute on LS1 pipe. 177 178(define_insn_reservation "ir_sb1_fpidxstore" 1 179 (and (eq_attr "cpu" "sb1") 180 (eq_attr "type" "fpidxstore")) 181 "sb1_ls1+sb1_fp1 | sb1_ls1+sb1_fp0") 182 183;; Load latencies are 3 cycles for one load to another load or store (address 184;; only). This is 0 cycles for one load to a store using it as the data 185;; written. 186 187;; This assumes that if a load is dependent on a previous insn, then it must 188;; be an address dependence. 189 190(define_bypass 3 191 "ir_sb1_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,ir_sb1_fpidxload, 192 ir_sb1_fpidxload_32bitfp" 193 "ir_sb1_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,ir_sb1_fpidxload, 194 ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx") 195 196(define_bypass 3 197 "ir_sb1_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,ir_sb1_fpidxload, 198 ir_sb1_fpidxload_32bitfp" 199 "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore" 200 "store_data_bypass_p") 201 202;; Simple alu instructions can execute on the LS1 unit. 203 204;; ??? A simple alu insn issued on an LS unit has 0 cycle latency to an EX 205;; insn, to a store (for data), and to an xfer insn. It has 1 cycle latency to 206;; another LS insn (excluding store data). A simple alu insn issued on an EX 207;; unit has a latency of 5 cycles when the results goes to a LS unit (excluding 208;; store data), otherwise a latency of 1 cycle. 209 210;; ??? We cannot handle latencies properly for simple alu instructions 211;; within the DFA pipeline model. Latencies can be defined only from one 212;; insn reservation to another. We can't make them depend on which function 213;; unit was used. This isn't a DFA flaw. There is a conflict here, as we 214;; need to know the latency before we can determine which unit will be 215;; available, but we need to know which unit it is issued to before we can 216;; compute the latency. Perhaps this can be handled via scheduler hooks. 217;; This needs to be investigated. 218 219;; ??? Optimal scheduling taking the LS units into account seems to require 220;; a pre-scheduling pass. We need to determine which instructions feed results 221;; into store/load addresses, and thus benefit most from being issued to the 222;; LS unit. Also, we need to prune the list to ensure we don't overschedule 223;; insns to the LS unit, and that we don't conflict with insns that need LS1 224;; such as indexed loads. We then need to emit nops to ensure that simple 225;; alu instructions that are not supposed to be scheduled to LS1 don't 226;; accidentally end up there because LS1 is free when they are issued. This 227;; will be a lot of work, and it isn't clear how useful it will be. 228 229;; Empirical testing shows that 2 gives the best result. 230 231(define_insn_reservation "ir_sb1_simple_alu" 2 232 (and (eq_attr "cpu" "sb1") 233 (eq_attr "type" "const,arith")) 234 "sb1_ls1 | sb1_ex1 | sb1_ex0") 235 236;; ??? condmove also includes some FP instructions that execute on the FP 237;; units. This needs to be clarified. 238 239(define_insn_reservation "ir_sb1_alu" 1 240 (and (eq_attr "cpu" "sb1") 241 (eq_attr "type" "condmove,nop,shift")) 242 "sb1_ex1 | sb1_ex0") 243 244;; These are type arith/darith that only execute on the EX0 unit. 245 246(define_insn_reservation "ir_sb1_alu_0" 1 247 (and (eq_attr "cpu" "sb1") 248 (eq_attr "type" "slt,clz,trap")) 249 "sb1_ex0") 250 251;; An alu insn issued on an EX unit has a latency of 5 cycles when the 252;; result goes to a LS unit (excluding store data). 253 254;; This assumes that if a load is dependent on a previous insn, then it must 255;; be an address dependence. 256 257(define_bypass 5 258 "ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo" 259 "ir_sb1_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,ir_sb1_fpidxload, 260 ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx") 261 262(define_bypass 5 263 "ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo" 264 "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore" 265 "store_data_bypass_p") 266 267;; mf{hi,lo} is 1 cycle. 268 269(define_insn_reservation "ir_sb1_mfhi" 1 270 (and (eq_attr "cpu" "sb1") 271 (and (eq_attr "type" "mfhilo") 272 (not (match_operand 1 "lo_operand")))) 273 "sb1_ex1") 274 275(define_insn_reservation "ir_sb1_mflo" 1 276 (and (eq_attr "cpu" "sb1") 277 (and (eq_attr "type" "mfhilo") 278 (match_operand 1 "lo_operand"))) 279 "sb1_ex1") 280 281;; mt{hi,lo} to mul/div is 4 cycles. 282 283(define_insn_reservation "ir_sb1_mthilo" 4 284 (and (eq_attr "cpu" "sb1") 285 (eq_attr "type" "mthilo")) 286 "sb1_ex1") 287 288;; mt{hi,lo} to mf{hi,lo} is 3 cycles. 289 290(define_bypass 3 "ir_sb1_mthilo" "ir_sb1_mfhi,ir_sb1_mflo") 291 292;; multiply latency to an EX operation is 3 cycles. 293 294;; ??? Should check whether we need to make multiply conflict with moves 295;; to/from hilo registers. 296 297(define_insn_reservation "ir_sb1_mulsi" 3 298 (and (eq_attr "cpu" "sb1") 299 (and (eq_attr "type" "imul,imul3,imadd") 300 (eq_attr "mode" "SI"))) 301 "sb1_ex1+sb1_mul") 302 303;; muldi to mfhi is 4 cycles. 304;; Blocks any other multiply insn issue for 1 cycle. 305 306(define_insn_reservation "ir_sb1_muldi" 4 307 (and (eq_attr "cpu" "sb1") 308 (and (eq_attr "type" "imul,imul3") 309 (eq_attr "mode" "DI"))) 310 "sb1_ex1+sb1_mul, sb1_mul") 311 312;; muldi to mflo is 3 cycles. 313 314(define_bypass 3 "ir_sb1_muldi" "ir_sb1_mflo") 315 316;; mul latency is 7 cycles if the result is used by any LS insn. 317 318;; This assumes that if a load is dependent on a previous insn, then it must 319;; be an address dependence. 320 321(define_bypass 7 322 "ir_sb1_mulsi,ir_sb1_muldi" 323 "ir_sb1_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,ir_sb1_fpidxload, 324 ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx") 325 326(define_bypass 7 327 "ir_sb1_mulsi,ir_sb1_muldi" 328 "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore" 329 "store_data_bypass_p") 330 331;; The divide unit is not pipelined. Divide busy is asserted in the 4th 332;; cycle, and then deasserted on the latency cycle. So only one divide at 333;; a time, but the first/last 4 cycles can overlap. 334 335;; ??? All divides block writes to hi/lo regs. hi/lo regs are written 4 cycles 336;; after the latency cycle for divides (e.g. 40/72). dmult writes lo in 337;; cycle 7, and hi in cycle 8. All other insns write hi/lo regs in cycle 7. 338;; Default for output dependencies is the difference in latencies, which is 339;; only 1 cycle off here, e.g. div to mtlo stalls for 32 cycles, but should 340;; stall for 33 cycles. This does not seem significant enough to worry about. 341 342(define_insn_reservation "ir_sb1_divsi" 36 343 (and (eq_attr "cpu" "sb1") 344 (and (eq_attr "type" "idiv") 345 (eq_attr "mode" "SI"))) 346 "sb1_ex1, nothing*3, sb1_div*32") 347 348(define_insn_reservation "ir_sb1_divdi" 68 349 (and (eq_attr "cpu" "sb1") 350 (and (eq_attr "type" "idiv") 351 (eq_attr "mode" "DI"))) 352 "sb1_ex1, nothing*3, sb1_div*64") 353 354(define_insn_reservation "ir_sb1_fpu_2pipes" 4 355 (and (eq_attr "cpu" "sb1") 356 (and (eq_attr "type" "fmove,fadd,fmul,fabs,fneg,fcvt,frdiv1,frsqrt1") 357 (eq_attr "sb1_fp_pipes" "two"))) 358 "sb1_fp1 | sb1_fp0") 359 360(define_insn_reservation "ir_sb1_fpu_1pipe" 4 361 (and (eq_attr "cpu" "sb1") 362 (and (eq_attr "type" "fmove,fadd,fmul,fabs,fneg,fcvt,frdiv1,frsqrt1") 363 (eq_attr "sb1_fp_pipes" "one"))) 364 "sb1_fp1") 365 366(define_insn_reservation "ir_sb1_fpu_step2_2pipes" 8 367 (and (eq_attr "cpu" "sb1") 368 (and (eq_attr "type" "frdiv2,frsqrt2") 369 (eq_attr "sb1_fp_pipes" "two"))) 370 "sb1_fp1 | sb1_fp0") 371 372(define_insn_reservation "ir_sb1_fpu_step2_1pipe" 8 373 (and (eq_attr "cpu" "sb1") 374 (and (eq_attr "type" "frdiv2,frsqrt2") 375 (eq_attr "sb1_fp_pipes" "one"))) 376 "sb1_fp1") 377 378;; ??? madd/msub 4-cycle latency to itself (same fr?), but 8 cycle latency 379;; otherwise. 380 381;; ??? Blocks issue of another non-madd/msub after 4 cycles. 382 383(define_insn_reservation "ir_sb1_fmadd_2pipes" 8 384 (and (eq_attr "cpu" "sb1") 385 (and (eq_attr "type" "fmadd") 386 (eq_attr "sb1_fp_pipes" "two"))) 387 "sb1_fp1 | sb1_fp0") 388 389(define_insn_reservation "ir_sb1_fmadd_1pipe" 8 390 (and (eq_attr "cpu" "sb1") 391 (and (eq_attr "type" "fmadd") 392 (eq_attr "sb1_fp_pipes" "one"))) 393 "sb1_fp1") 394 395(define_insn_reservation "ir_sb1_fcmp" 4 396 (and (eq_attr "cpu" "sb1") 397 (eq_attr "type" "fcmp")) 398 "sb1_fp1") 399 400;; mtc1 latency 5 cycles. 401 402(define_insn_reservation "ir_sb1_mtxfer" 5 403 (and (eq_attr "cpu" "sb1") 404 (and (eq_attr "type" "xfer") 405 (match_operand 0 "fpr_operand"))) 406 "sb1_fp0") 407 408;; mfc1 latency 1 cycle. 409 410(define_insn_reservation "ir_sb1_mfxfer" 1 411 (and (eq_attr "cpu" "sb1") 412 (and (eq_attr "type" "xfer") 413 (not (match_operand 0 "fpr_operand")))) 414 "sb1_fp0") 415 416;; ??? Can deliver at most 1 result per every 6 cycles because of issue 417;; restrictions. 418 419(define_insn_reservation "ir_sb1_divsf_2pipes" 24 420 (and (eq_attr "cpu" "sb1") 421 (and (eq_attr "type" "fdiv") 422 (and (eq_attr "mode" "SF") 423 (eq_attr "sb1_fp_pipes" "two")))) 424 "sb1_fp1 | sb1_fp0") 425 426(define_insn_reservation "ir_sb1_divsf_1pipe" 24 427 (and (eq_attr "cpu" "sb1") 428 (and (eq_attr "type" "fdiv") 429 (and (eq_attr "mode" "SF") 430 (eq_attr "sb1_fp_pipes" "one")))) 431 "sb1_fp1") 432 433;; ??? Can deliver at most 1 result per every 8 cycles because of issue 434;; restrictions. 435 436(define_insn_reservation "ir_sb1_divdf_2pipes" 32 437 (and (eq_attr "cpu" "sb1") 438 (and (eq_attr "type" "fdiv") 439 (and (eq_attr "mode" "DF") 440 (eq_attr "sb1_fp_pipes" "two")))) 441 "sb1_fp1 | sb1_fp0") 442 443(define_insn_reservation "ir_sb1_divdf_1pipe" 32 444 (and (eq_attr "cpu" "sb1") 445 (and (eq_attr "type" "fdiv") 446 (and (eq_attr "mode" "DF") 447 (eq_attr "sb1_fp_pipes" "one")))) 448 "sb1_fp1") 449 450;; ??? Can deliver at most 1 result per every 3 cycles because of issue 451;; restrictions. 452 453(define_insn_reservation "ir_sb1_recipsf_2pipes" 12 454 (and (eq_attr "cpu" "sb1") 455 (and (eq_attr "type" "frdiv") 456 (and (eq_attr "mode" "SF") 457 (eq_attr "sb1_fp_pipes" "two")))) 458 "sb1_fp1 | sb1_fp0") 459 460(define_insn_reservation "ir_sb1_recipsf_1pipe" 12 461 (and (eq_attr "cpu" "sb1") 462 (and (eq_attr "type" "frdiv") 463 (and (eq_attr "mode" "SF") 464 (eq_attr "sb1_fp_pipes" "one")))) 465 "sb1_fp1") 466 467;; ??? Can deliver at most 1 result per every 5 cycles because of issue 468;; restrictions. 469 470(define_insn_reservation "ir_sb1_recipdf_2pipes" 20 471 (and (eq_attr "cpu" "sb1") 472 (and (eq_attr "type" "frdiv") 473 (and (eq_attr "mode" "DF") 474 (eq_attr "sb1_fp_pipes" "two")))) 475 "sb1_fp1 | sb1_fp0") 476 477(define_insn_reservation "ir_sb1_recipdf_1pipe" 20 478 (and (eq_attr "cpu" "sb1") 479 (and (eq_attr "type" "frdiv") 480 (and (eq_attr "mode" "DF") 481 (eq_attr "sb1_fp_pipes" "one")))) 482 "sb1_fp1") 483 484;; ??? Can deliver at most 1 result per every 7 cycles because of issue 485;; restrictions. 486 487(define_insn_reservation "ir_sb1_sqrtsf_2pipes" 28 488 (and (eq_attr "cpu" "sb1") 489 (and (eq_attr "type" "fsqrt") 490 (and (eq_attr "mode" "SF") 491 (eq_attr "sb1_fp_pipes" "two")))) 492 "sb1_fp1 | sb1_fp0") 493 494(define_insn_reservation "ir_sb1_sqrtsf_1pipe" 28 495 (and (eq_attr "cpu" "sb1") 496 (and (eq_attr "type" "fsqrt") 497 (and (eq_attr "mode" "SF") 498 (eq_attr "sb1_fp_pipes" "one")))) 499 "sb1_fp1") 500 501;; ??? Can deliver at most 1 result per every 10 cycles because of issue 502;; restrictions. 503 504(define_insn_reservation "ir_sb1_sqrtdf_2pipes" 40 505 (and (eq_attr "cpu" "sb1") 506 (and (eq_attr "type" "fsqrt") 507 (and (eq_attr "mode" "DF") 508 (eq_attr "sb1_fp_pipes" "two")))) 509 "sb1_fp1 | sb1_fp0") 510 511(define_insn_reservation "ir_sb1_sqrtdf_1pipe" 40 512 (and (eq_attr "cpu" "sb1") 513 (and (eq_attr "type" "fsqrt") 514 (and (eq_attr "mode" "DF") 515 (eq_attr "sb1_fp_pipes" "one")))) 516 "sb1_fp1") 517 518;; ??? Can deliver at most 1 result per every 4 cycles because of issue 519;; restrictions. 520 521(define_insn_reservation "ir_sb1_rsqrtsf_2pipes" 16 522 (and (eq_attr "cpu" "sb1") 523 (and (eq_attr "type" "frsqrt") 524 (and (eq_attr "mode" "SF") 525 (eq_attr "sb1_fp_pipes" "two")))) 526 "sb1_fp1 | sb1_fp0") 527 528(define_insn_reservation "ir_sb1_rsqrtsf_1pipe" 16 529 (and (eq_attr "cpu" "sb1") 530 (and (eq_attr "type" "frsqrt") 531 (and (eq_attr "mode" "SF") 532 (eq_attr "sb1_fp_pipes" "one")))) 533 "sb1_fp1") 534 535;; ??? Can deliver at most 1 result per every 7 cycles because of issue 536;; restrictions. 537 538(define_insn_reservation "ir_sb1_rsqrtdf_2pipes" 28 539 (and (eq_attr "cpu" "sb1") 540 (and (eq_attr "type" "frsqrt") 541 (and (eq_attr "mode" "DF") 542 (eq_attr "sb1_fp_pipes" "two")))) 543 "sb1_fp1 | sb1_fp0") 544 545(define_insn_reservation "ir_sb1_rsqrtdf_1pipe" 28 546 (and (eq_attr "cpu" "sb1") 547 (and (eq_attr "type" "frsqrt") 548 (and (eq_attr "mode" "DF") 549 (eq_attr "sb1_fp_pipes" "one")))) 550 "sb1_fp1") 551