1 /**************************************************************************//** 2 * @file ARMSC000.h 3 * @brief CMSIS Core Peripheral Access Layer Header File for 4 * ARMSC000 Device Series 5 * @version V3.00 6 * @date 16. October 2015 7 ******************************************************************************/ 8 /* Copyright (c) 2011 - 2015 ARM LIMITED 9 10 All rights reserved. 11 Redistribution and use in source and binary forms, with or without 12 modification, are permitted provided that the following conditions are met: 13 - Redistributions of source code must retain the above copyright 14 notice, this list of conditions and the following disclaimer. 15 - Redistributions in binary form must reproduce the above copyright 16 notice, this list of conditions and the following disclaimer in the 17 documentation and/or other materials provided with the distribution. 18 - Neither the name of ARM nor the names of its contributors may be used 19 to endorse or promote products derived from this software without 20 specific prior written permission. 21 * 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 POSSIBILITY OF SUCH DAMAGE. 33 ---------------------------------------------------------------------------*/ 34 35 36 #ifndef ARMSC000_H 37 #define ARMSC000_H 38 39 #ifdef __cplusplus 40 extern "C" { 41 #endif 42 43 44 /* ------------------------- Interrupt Number Definition ------------------------ */ 45 46 typedef enum IRQn 47 { 48 /* --------------------- SC000 Processor Exceptions Numbers --------------------- */ 49 NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ 50 HardFault_IRQn = -13, /* 3 HardFault Interrupt */ 51 52 53 54 SVCall_IRQn = -5, /* 11 SV Call Interrupt */ 55 56 PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ 57 SysTick_IRQn = -1, /* 15 System Tick Interrupt */ 58 59 /* ---------------------- ARMSC000 Specific Interrupt Numbers ------------------- */ 60 WDT_IRQn = 0, /* Watchdog Timer Interrupt */ 61 RTC_IRQn = 1, /* Real Time Clock Interrupt */ 62 TIM0_IRQn = 2, /* Timer0 / Timer1 Interrupt */ 63 TIM2_IRQn = 3, /* Timer2 / Timer3 Interrupt */ 64 MCIA_IRQn = 4, /* MCIa Interrupt */ 65 MCIB_IRQn = 5, /* MCIb Interrupt */ 66 UART0_IRQn = 6, /* UART0 Interrupt */ 67 UART1_IRQn = 7, /* UART1 Interrupt */ 68 UART2_IRQn = 8, /* UART2 Interrupt */ 69 UART4_IRQn = 9, /* UART4 Interrupt */ 70 AACI_IRQn = 10, /* AACI / AC97 Interrupt */ 71 CLCD_IRQn = 11, /* CLCD Combined Interrupt */ 72 ENET_IRQn = 12, /* Ethernet Interrupt */ 73 USBDC_IRQn = 13, /* USB Device Interrupt */ 74 USBHC_IRQn = 14, /* USB Host Controller Interrupt */ 75 CHLCD_IRQn = 15, /* Character LCD Interrupt */ 76 FLEXRAY_IRQn = 16, /* Flexray Interrupt */ 77 CAN_IRQn = 17, /* CAN Interrupt */ 78 LIN_IRQn = 18, /* LIN Interrupt */ 79 I2C_IRQn = 19, /* I2C ADC/DAC Interrupt */ 80 CPU_CLCD_IRQn = 28, /* CPU CLCD Combined Interrupt */ 81 UART3_IRQn = 30, /* UART3 Interrupt */ 82 SPI_IRQn = 31 /* SPI Touchscreen Interrupt */ 83 } IRQn_Type; 84 85 86 /* ================================================================================ */ 87 /* ================ Processor and Core Peripheral Section ================ */ 88 /* ================================================================================ */ 89 90 /* ------- Start of section using anonymous unions and disabling warnings ------- */ 91 #if defined (__CC_ARM) 92 #pragma push 93 #pragma anon_unions 94 #elif defined (__ICCARM__) 95 #pragma language=extended 96 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 97 #pragma clang diagnostic push 98 #pragma clang diagnostic ignored "-Wc11-extensions" 99 #pragma clang diagnostic ignored "-Wreserved-id-macro" 100 #elif defined (__GNUC__) 101 /* anonymous unions are enabled by default */ 102 #elif defined (__TMS470__) 103 /* anonymous unions are enabled by default */ 104 #elif defined (__TASKING__) 105 #pragma warning 586 106 #elif defined (__CSMC__) 107 /* anonymous unions are enabled by default */ 108 #else 109 #warning Not supported compiler type 110 #endif 111 112 113 /* -------- Configuration of the SC000 Processor and Core Peripherals ----------- */ 114 #define __SC000_REV 0x0000U /* Core revision r0p0 */ 115 #define __MPU_PRESENT 1 /* MPU present */ 116 #define __VTOR_PRESENT 0 /* no VTOR present*/ 117 #define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */ 118 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ 119 120 #include "core_SC000.h" /* Processor and core peripherals */ 121 #include "system_ARMSC000.h" /* System Header */ 122 123 124 /* ================================================================================ */ 125 /* ================ Device Specific Peripheral Section ================ */ 126 /* ================================================================================ */ 127 128 129 /* ================================================================================ */ 130 /* ================ CPU FPGA System (CPU_SYS) ================ */ 131 /* ================================================================================ */ 132 typedef struct 133 { 134 __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */ 135 __IOM uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */ 136 __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */ 137 __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */ 138 __IM uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */ 139 __IOM uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */ 140 uint32_t RESERVED0[2]; 141 __IOM uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */ 142 __IOM uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */ 143 __IOM uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */ 144 uint32_t RESERVED1[3]; 145 __IOM uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */ 146 __IOM uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */ 147 } ARM_CPU_SYS_TypeDef; 148 149 150 /* ================================================================================ */ 151 /* ================ DUT FPGA System (DUT_SYS) ================ */ 152 /* ================================================================================ */ 153 typedef struct 154 { 155 __IM uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */ 156 __IOM uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */ 157 __IM uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */ 158 __IOM uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */ 159 __IOM uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */ 160 __IM uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */ 161 __IM uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */ 162 } ARM_DUT_SYS_TypeDef; 163 164 165 /* ================================================================================ */ 166 /* ================ Timer (TIM) ================ */ 167 /* ================================================================================ */ 168 typedef struct 169 { 170 __IOM uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */ 171 __IM uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */ 172 __IOM uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */ 173 __OM uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */ 174 __IM uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */ 175 __IM uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */ 176 __IOM uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */ 177 uint32_t RESERVED0[1]; 178 __IOM uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */ 179 __IM uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */ 180 __IOM uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */ 181 __OM uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */ 182 __IM uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */ 183 __IM uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */ 184 __IOM uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */ 185 } ARM_TIM_TypeDef; 186 187 188 /* ================================================================================ */ 189 /* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */ 190 /* ================================================================================ */ 191 typedef struct 192 { 193 __IOM uint32_t DR; /* Offset: 0x000 (R/W) Data */ 194 union { 195 __IM uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */ 196 __OM uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */ 197 }; 198 uint32_t RESERVED0[4]; 199 __IOM uint32_t FR; /* Offset: 0x018 (R/W) Flags */ 200 uint32_t RESERVED1[1]; 201 __IOM uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */ 202 __IOM uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */ 203 __IOM uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */ 204 __IOM uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */ 205 __IOM uint32_t CR; /* Offset: 0x030 (R/W) Control */ 206 __IOM uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */ 207 __IOM uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */ 208 __IOM uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */ 209 __IOM uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */ 210 __OM uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */ 211 __IOM uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */ 212 } ARM_UART_TypeDef; 213 214 215 /* -------- End of section using anonymous unions and disabling warnings -------- */ 216 #if defined (__CC_ARM) 217 #pragma pop 218 #elif defined (__ICCARM__) 219 /* leave anonymous unions enabled */ 220 #elif (__ARMCC_VERSION >= 6010050) 221 #pragma clang diagnostic pop 222 #elif defined (__GNUC__) 223 /* anonymous unions are enabled by default */ 224 #elif defined (__TMS470__) 225 /* anonymous unions are enabled by default */ 226 #elif defined (__TASKING__) 227 #pragma warning restore 228 #elif defined (__CSMC__) 229 /* anonymous unions are enabled by default */ 230 #else 231 #warning Not supported compiler type 232 #endif 233 234 235 236 237 /* ================================================================================ */ 238 /* ================ Peripheral memory map ================ */ 239 /* ================================================================================ */ 240 /* -------------------------- CPU FPGA memory map ------------------------------- */ 241 #define ARM_FLASH_BASE (0x00000000UL) 242 #define ARM_RAM_BASE (0x20000000UL) 243 #define ARM_RAM_FPGA_BASE (0x1EFF0000UL) 244 #define ARM_CPU_CFG_BASE (0xDFFF0000UL) 245 246 #define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000UL) 247 #define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000UL) 248 249 /* -------------------------- DUT FPGA memory map ------------------------------- */ 250 #define ARM_APB_BASE (0x40000000UL) 251 #define ARM_AHB_BASE (0x4FF00000UL) 252 #define ARM_DMC_BASE (0x60000000UL) 253 #define ARM_SMC_BASE (0xA0000000UL) 254 255 #define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000UL) 256 #define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000UL) 257 #define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000UL) 258 #define ARM_UART0_BASE (ARM_APB_BASE + 0x06000UL) 259 #define ARM_UART1_BASE (ARM_APB_BASE + 0x07000UL) 260 #define ARM_UART2_BASE (ARM_APB_BASE + 0x08000UL) 261 #define ARM_UART4_BASE (ARM_APB_BASE + 0x09000UL) 262 263 264 /* ================================================================================ */ 265 /* ================ Peripheral declaration ================ */ 266 /* ================================================================================ */ 267 /* -------------------------- CPU FPGA Peripherals ------------------------------ */ 268 #define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE) 269 #define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE) 270 271 /* -------------------------- DUT FPGA Peripherals ------------------------------ */ 272 #define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE) 273 #define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE) 274 #define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE) 275 #define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE) 276 #define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE) 277 #define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE) 278 #define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE) 279 280 281 #ifdef __cplusplus 282 } 283 #endif 284 285 #endif /* ARMSC000_H */ 286