1 /* 2 * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * 1. Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * 3. Neither the name of Nordic Semiconductor ASA nor the names of its 15 * contributors may be used to endorse or promote products derived from this 16 * software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 * 30 * @file nrf52840.h 31 * @brief CMSIS HeaderFile 32 * @version 1 33 * @date 06. June 2018 34 * @note Generated by SVDConv V3.3.18 on Wednesday, 06.06.2018 15:21:39 35 * from File 'nrf52840.svd', 36 * last modified on Wednesday, 06.06.2018 13:21:35 37 */ 38 39 40 41 /** @addtogroup Nordic Semiconductor 42 * @{ 43 */ 44 45 46 /** @addtogroup nrf52840 47 * @{ 48 */ 49 50 51 #ifndef NRF52840_H 52 #define NRF52840_H 53 54 #ifdef __cplusplus 55 extern "C" { 56 #endif 57 58 59 /** @addtogroup Configuration_of_CMSIS 60 * @{ 61 */ 62 63 64 65 /* =========================================================================================================================== */ 66 /* ================ Interrupt Number Definition ================ */ 67 /* =========================================================================================================================== */ 68 69 typedef enum { 70 /* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ 71 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 72 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 73 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 74 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 75 and No Match */ 76 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 77 related Fault */ 78 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 79 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 80 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 81 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 82 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 83 /* ========================================== nrf52840 Specific Interrupt Numbers ========================================== */ 84 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ 85 RADIO_IRQn = 1, /*!< 1 RADIO */ 86 UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ 87 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ 88 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ 89 NFCT_IRQn = 5, /*!< 5 NFCT */ 90 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ 91 SAADC_IRQn = 7, /*!< 7 SAADC */ 92 TIMER0_IRQn = 8, /*!< 8 TIMER0 */ 93 TIMER1_IRQn = 9, /*!< 9 TIMER1 */ 94 TIMER2_IRQn = 10, /*!< 10 TIMER2 */ 95 RTC0_IRQn = 11, /*!< 11 RTC0 */ 96 TEMP_IRQn = 12, /*!< 12 TEMP */ 97 RNG_IRQn = 13, /*!< 13 RNG */ 98 ECB_IRQn = 14, /*!< 14 ECB */ 99 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ 100 WDT_IRQn = 16, /*!< 16 WDT */ 101 RTC1_IRQn = 17, /*!< 17 RTC1 */ 102 QDEC_IRQn = 18, /*!< 18 QDEC */ 103 COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ 104 SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ 105 SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ 106 SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ 107 SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ 108 SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ 109 SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ 110 TIMER3_IRQn = 26, /*!< 26 TIMER3 */ 111 TIMER4_IRQn = 27, /*!< 27 TIMER4 */ 112 PWM0_IRQn = 28, /*!< 28 PWM0 */ 113 PDM_IRQn = 29, /*!< 29 PDM */ 114 MWU_IRQn = 32, /*!< 32 MWU */ 115 PWM1_IRQn = 33, /*!< 33 PWM1 */ 116 PWM2_IRQn = 34, /*!< 34 PWM2 */ 117 SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ 118 RTC2_IRQn = 36, /*!< 36 RTC2 */ 119 I2S_IRQn = 37, /*!< 37 I2S */ 120 FPU_IRQn = 38, /*!< 38 FPU */ 121 USBD_IRQn = 39, /*!< 39 USBD */ 122 UARTE1_IRQn = 40, /*!< 40 UARTE1 */ 123 QSPI_IRQn = 41, /*!< 41 QSPI */ 124 CRYPTOCELL_IRQn = 42, /*!< 42 CRYPTOCELL */ 125 PWM3_IRQn = 45, /*!< 45 PWM3 */ 126 SPIM3_IRQn = 47 /*!< 47 SPIM3 */ 127 } IRQn_Type; 128 129 130 131 /* =========================================================================================================================== */ 132 /* ================ Processor and Core Peripheral Section ================ */ 133 /* =========================================================================================================================== */ 134 135 /* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ 136 #define __CM4_REV 0x0001U /*!< CM4 Core Revision */ 137 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 138 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 139 #define __MPU_PRESENT 1 /*!< MPU present or not */ 140 #define __FPU_PRESENT 1 /*!< FPU present or not */ 141 142 143 /** @} */ /* End of group Configuration_of_CMSIS */ 144 145 #include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ 146 #include "system_nrf52840.h" /*!< nrf52840 System */ 147 148 #ifndef __IM /*!< Fallback for older CMSIS versions */ 149 #define __IM __I 150 #endif 151 #ifndef __OM /*!< Fallback for older CMSIS versions */ 152 #define __OM __O 153 #endif 154 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 155 #define __IOM __IO 156 #endif 157 158 159 /* ======================================== Start of section using anonymous unions ======================================== */ 160 #if defined (__CC_ARM) 161 #pragma push 162 #pragma anon_unions 163 #elif defined (__ICCARM__) 164 #pragma language=extended 165 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 166 #pragma clang diagnostic push 167 #pragma clang diagnostic ignored "-Wc11-extensions" 168 #pragma clang diagnostic ignored "-Wreserved-id-macro" 169 #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" 170 #pragma clang diagnostic ignored "-Wnested-anon-types" 171 #elif defined (__GNUC__) 172 /* anonymous unions are enabled by default */ 173 #elif defined (__TMS470__) 174 /* anonymous unions are enabled by default */ 175 #elif defined (__TASKING__) 176 #pragma warning 586 177 #elif defined (__CSMC__) 178 /* anonymous unions are enabled by default */ 179 #else 180 #warning Not supported compiler type 181 #endif 182 183 184 /* =========================================================================================================================== */ 185 /* ================ Device Specific Cluster Section ================ */ 186 /* =========================================================================================================================== */ 187 188 189 /** @addtogroup Device_Peripheral_clusters 190 * @{ 191 */ 192 193 194 /** 195 * @brief FICR_INFO [INFO] (Device info) 196 */ 197 typedef struct { 198 __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ 199 __IM uint32_t VARIANT; /*!< (@ 0x00000004) Build code (hardware version and production configuration) */ 200 __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ 201 __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ 202 __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ 203 __IOM uint32_t UNUSED8[3]; /*!< (@ 0x00000014) Unspecified */ 204 } FICR_INFO_Type; /*!< Size = 32 (0x20) */ 205 206 207 /** 208 * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) 209 */ 210 typedef struct { 211 __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0 */ 212 __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1 */ 213 __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2 */ 214 __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3 */ 215 __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4 */ 216 __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5 */ 217 __IM uint32_t B0; /*!< (@ 0x00000018) Y-intercept B0 */ 218 __IM uint32_t B1; /*!< (@ 0x0000001C) Y-intercept B1 */ 219 __IM uint32_t B2; /*!< (@ 0x00000020) Y-intercept B2 */ 220 __IM uint32_t B3; /*!< (@ 0x00000024) Y-intercept B3 */ 221 __IM uint32_t B4; /*!< (@ 0x00000028) Y-intercept B4 */ 222 __IM uint32_t B5; /*!< (@ 0x0000002C) Y-intercept B5 */ 223 __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0 */ 224 __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1 */ 225 __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2 */ 226 __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3 */ 227 __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4 */ 228 } FICR_TEMP_Type; /*!< Size = 68 (0x44) */ 229 230 231 /** 232 * @brief FICR_NFC [NFC] (Unspecified) 233 */ 234 typedef struct { 235 __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC tag. Software can read 236 these values to populate NFCID1_3RD_LAST, 237 NFCID1_2ND_LAST and NFCID1_LAST. */ 238 __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC tag. Software can read 239 these values to populate NFCID1_3RD_LAST, 240 NFCID1_2ND_LAST and NFCID1_LAST. */ 241 __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC tag. Software can read 242 these values to populate NFCID1_3RD_LAST, 243 NFCID1_2ND_LAST and NFCID1_LAST. */ 244 __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC tag. Software can read 245 these values to populate NFCID1_3RD_LAST, 246 NFCID1_2ND_LAST and NFCID1_LAST. */ 247 } FICR_NFC_Type; /*!< Size = 16 (0x10) */ 248 249 250 /** 251 * @brief FICR_TRNG90B [TRNG90B] (NIST800-90B RNG calibration data) 252 */ 253 typedef struct { 254 __IM uint32_t BYTES; /*!< (@ 0x00000000) Amount of bytes for the required entropy bits */ 255 __IM uint32_t RCCUTOFF; /*!< (@ 0x00000004) Repetition counter cutoff */ 256 __IM uint32_t APCUTOFF; /*!< (@ 0x00000008) Adaptive proportion cutoff */ 257 __IM uint32_t STARTUP; /*!< (@ 0x0000000C) Amount of bytes for the startup tests */ 258 __IM uint32_t ROSC1; /*!< (@ 0x00000010) Sample count for ring oscillator 1 */ 259 __IM uint32_t ROSC2; /*!< (@ 0x00000014) Sample count for ring oscillator 2 */ 260 __IM uint32_t ROSC3; /*!< (@ 0x00000018) Sample count for ring oscillator 3 */ 261 __IM uint32_t ROSC4; /*!< (@ 0x0000001C) Sample count for ring oscillator 4 */ 262 } FICR_TRNG90B_Type; /*!< Size = 32 (0x20) */ 263 264 265 /** 266 * @brief POWER_RAM [RAM] (Unspecified) 267 */ 268 typedef struct { 269 __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster[n]: RAMn power control register */ 270 __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster[n]: RAMn power control set 271 register */ 272 __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster[n]: RAMn power control clear 273 register */ 274 __IM uint32_t RESERVED; 275 } POWER_RAM_Type; /*!< Size = 16 (0x10) */ 276 277 278 /** 279 * @brief UART_PSEL [PSEL] (Unspecified) 280 */ 281 typedef struct { 282 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS */ 283 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD */ 284 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS */ 285 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD */ 286 } UART_PSEL_Type; /*!< Size = 16 (0x10) */ 287 288 289 /** 290 * @brief UARTE_PSEL [PSEL] (Unspecified) 291 */ 292 typedef struct { 293 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 294 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 295 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 296 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 297 } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 298 299 300 /** 301 * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 302 */ 303 typedef struct { 304 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 305 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 306 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 307 } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 308 309 310 /** 311 * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 312 */ 313 typedef struct { 314 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 315 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 316 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 317 } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 318 319 320 /** 321 * @brief SPI_PSEL [PSEL] (Unspecified) 322 */ 323 typedef struct { 324 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 325 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 326 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 327 } SPI_PSEL_Type; /*!< Size = 12 (0xc) */ 328 329 330 /** 331 * @brief SPIM_PSEL [PSEL] (Unspecified) 332 */ 333 typedef struct { 334 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 335 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 336 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 337 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN */ 338 } SPIM_PSEL_Type; /*!< Size = 16 (0x10) */ 339 340 341 /** 342 * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 343 */ 344 typedef struct { 345 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 346 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 347 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 348 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 349 } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 350 351 352 /** 353 * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 354 */ 355 typedef struct { 356 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 357 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of bytes in transmit buffer */ 358 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 359 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 360 } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 361 362 363 /** 364 * @brief SPIM_IFTIMING [IFTIMING] (Unspecified) 365 */ 366 typedef struct { 367 __IOM uint32_t RXDELAY; /*!< (@ 0x00000000) Sample delay for input serial data on MISO */ 368 __IOM uint32_t CSNDUR; /*!< (@ 0x00000004) Minimum duration between edge of CSN and edge 369 of SCK and minimum duration CSN must stay 370 high between transactions */ 371 } SPIM_IFTIMING_Type; /*!< Size = 8 (0x8) */ 372 373 374 /** 375 * @brief SPIS_PSEL [PSEL] (Unspecified) 376 */ 377 typedef struct { 378 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 379 __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 380 __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 381 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 382 } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 383 384 385 /** 386 * @brief SPIS_RXD [RXD] (Unspecified) 387 */ 388 typedef struct { 389 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 390 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 391 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 392 } SPIS_RXD_Type; /*!< Size = 12 (0xc) */ 393 394 395 /** 396 * @brief SPIS_TXD [TXD] (Unspecified) 397 */ 398 typedef struct { 399 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 400 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 401 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 402 } SPIS_TXD_Type; /*!< Size = 12 (0xc) */ 403 404 405 /** 406 * @brief TWI_PSEL [PSEL] (Unspecified) 407 */ 408 typedef struct { 409 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL */ 410 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA */ 411 } TWI_PSEL_Type; /*!< Size = 8 (0x8) */ 412 413 414 /** 415 * @brief TWIM_PSEL [PSEL] (Unspecified) 416 */ 417 typedef struct { 418 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 419 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 420 } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 421 422 423 /** 424 * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 425 */ 426 typedef struct { 427 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 428 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 429 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 430 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 431 } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 432 433 434 /** 435 * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 436 */ 437 typedef struct { 438 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 439 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 440 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 441 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 442 } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 443 444 445 /** 446 * @brief TWIS_PSEL [PSEL] (Unspecified) 447 */ 448 typedef struct { 449 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 450 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 451 } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 452 453 454 /** 455 * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 456 */ 457 typedef struct { 458 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 459 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 460 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 461 } TWIS_RXD_Type; /*!< Size = 12 (0xc) */ 462 463 464 /** 465 * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 466 */ 467 typedef struct { 468 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 469 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 470 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 471 } TWIS_TXD_Type; /*!< Size = 12 (0xc) */ 472 473 474 /** 475 * @brief NFCT_FRAMESTATUS [FRAMESTATUS] (Unspecified) 476 */ 477 typedef struct { 478 __IOM uint32_t RX; /*!< (@ 0x00000000) Result of last incoming frame */ 479 } NFCT_FRAMESTATUS_Type; /*!< Size = 4 (0x4) */ 480 481 482 /** 483 * @brief NFCT_TXD [TXD] (Unspecified) 484 */ 485 typedef struct { 486 __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of outgoing frames */ 487 __IOM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of outgoing frame */ 488 } NFCT_TXD_Type; /*!< Size = 8 (0x8) */ 489 490 491 /** 492 * @brief NFCT_RXD [RXD] (Unspecified) 493 */ 494 typedef struct { 495 __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of incoming frames */ 496 __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of last incoming frame */ 497 } NFCT_RXD_Type; /*!< Size = 8 (0x8) */ 498 499 500 /** 501 * @brief SAADC_EVENTS_CH [EVENTS_CH] (Unspecified) 502 */ 503 typedef struct { 504 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster[n]: Last result is equal 505 or above CH[n].LIMIT.HIGH */ 506 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster[n]: Last result is equal 507 or below CH[n].LIMIT.LOW */ 508 } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ 509 510 511 /** 512 * @brief SAADC_CH [CH] (Unspecified) 513 */ 514 typedef struct { 515 __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster[n]: Input positive pin selection 516 for CH[n] */ 517 __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster[n]: Input negative pin selection 518 for CH[n] */ 519 __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster[n]: Input configuration for 520 CH[n] */ 521 __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster[n]: High/low limits for event 522 monitoring of a channel */ 523 } SAADC_CH_Type; /*!< Size = 16 (0x10) */ 524 525 526 /** 527 * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) 528 */ 529 typedef struct { 530 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 531 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of 16-bit samples to be written 532 to output RAM buffer */ 533 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of 16-bit samples written to output RAM 534 buffer since the previous START task */ 535 } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ 536 537 538 /** 539 * @brief QDEC_PSEL [PSEL] (Unspecified) 540 */ 541 typedef struct { 542 __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ 543 __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ 544 __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ 545 } QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ 546 547 548 /** 549 * @brief PWM_SEQ [SEQ] (Unspecified) 550 */ 551 typedef struct { 552 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Beginning address in 553 RAM of this sequence */ 554 __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster[n]: Number of values (duty 555 cycles) in this sequence */ 556 __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster[n]: Number of additional 557 PWM periods between samples loaded into 558 compare register */ 559 __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster[n]: Time added after the 560 sequence */ 561 __IM uint32_t RESERVED[4]; 562 } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ 563 564 565 /** 566 * @brief PWM_PSEL [PSEL] (Unspecified) 567 */ 568 typedef struct { 569 __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection[n]: Output pin select 570 for PWM channel n */ 571 } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ 572 573 574 /** 575 * @brief PDM_PSEL [PSEL] (Unspecified) 576 */ 577 typedef struct { 578 __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ 579 __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ 580 } PDM_PSEL_Type; /*!< Size = 8 (0x8) */ 581 582 583 /** 584 * @brief PDM_SAMPLE [SAMPLE] (Unspecified) 585 */ 586 typedef struct { 587 __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with 588 EasyDMA */ 589 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA 590 mode */ 591 } PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ 592 593 594 /** 595 * @brief ACL_ACL [ACL] (Unspecified) 596 */ 597 typedef struct { 598 __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster[n]: Configure the word-aligned 599 start address of region n to protect */ 600 __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster[n]: Size of region to protect 601 counting from address ACL[n].ADDR. Write 602 '0' as no effect. */ 603 __IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster[n]: Access permissions for 604 region n as defined by start address ACL[n].ADDR 605 and size ACL[n].SIZE */ 606 __IOM uint32_t UNUSED0; /*!< (@ 0x0000000C) Unspecified */ 607 } ACL_ACL_Type; /*!< Size = 16 (0x10) */ 608 609 610 /** 611 * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) 612 */ 613 typedef struct { 614 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster[n]: Enable channel group 615 n */ 616 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster[n]: Disable channel group 617 n */ 618 } PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 619 620 621 /** 622 * @brief PPI_CH [CH] (PPI Channel) 623 */ 624 typedef struct { 625 __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster[n]: Channel n event end-point */ 626 __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster[n]: Channel n task end-point */ 627 } PPI_CH_Type; /*!< Size = 8 (0x8) */ 628 629 630 /** 631 * @brief PPI_FORK [FORK] (Fork) 632 */ 633 typedef struct { 634 __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster[n]: Channel n task end-point */ 635 } PPI_FORK_Type; /*!< Size = 4 (0x4) */ 636 637 638 /** 639 * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Unspecified) 640 */ 641 typedef struct { 642 __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[n]: Write access to region 643 n detected */ 644 __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[n]: Read access to region 645 n detected */ 646 } MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */ 647 648 649 /** 650 * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Unspecified) 651 */ 652 typedef struct { 653 __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[n]: Write access to peripheral 654 region n detected */ 655 __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[n]: Read access to peripheral 656 region n detected */ 657 } MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */ 658 659 660 /** 661 * @brief MWU_PERREGION [PERREGION] (Unspecified) 662 */ 663 typedef struct { 664 __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster[n]: Source of event/interrupt 665 in region n, write access detected while 666 corresponding subregion was enabled for 667 watching */ 668 __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster[n]: Source of event/interrupt 669 in region n, read access detected while 670 corresponding subregion was enabled for 671 watching */ 672 } MWU_PERREGION_Type; /*!< Size = 8 (0x8) */ 673 674 675 /** 676 * @brief MWU_REGION [REGION] (Unspecified) 677 */ 678 typedef struct { 679 __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster[n]: Start address for region 680 n */ 681 __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster[n]: End address of region 682 n */ 683 __IM uint32_t RESERVED[2]; 684 } MWU_REGION_Type; /*!< Size = 16 (0x10) */ 685 686 687 /** 688 * @brief MWU_PREGION [PREGION] (Unspecified) 689 */ 690 typedef struct { 691 __IM uint32_t START; /*!< (@ 0x00000000) Description cluster[n]: Reserved for future use */ 692 __IM uint32_t END; /*!< (@ 0x00000004) Description cluster[n]: Reserved for future use */ 693 __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster[n]: Subregions of region 694 n */ 695 __IM uint32_t RESERVED; 696 } MWU_PREGION_Type; /*!< Size = 16 (0x10) */ 697 698 699 /** 700 * @brief I2S_CONFIG [CONFIG] (Unspecified) 701 */ 702 typedef struct { 703 __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ 704 __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ 705 __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ 706 __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ 707 __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ 708 __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ 709 __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ 710 __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ 711 __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ 712 __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ 713 } I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ 714 715 716 /** 717 * @brief I2S_RXD [RXD] (Unspecified) 718 */ 719 typedef struct { 720 __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ 721 } I2S_RXD_Type; /*!< Size = 4 (0x4) */ 722 723 724 /** 725 * @brief I2S_TXD [TXD] (Unspecified) 726 */ 727 typedef struct { 728 __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ 729 } I2S_TXD_Type; /*!< Size = 4 (0x4) */ 730 731 732 /** 733 * @brief I2S_RXTXD [RXTXD] (Unspecified) 734 */ 735 typedef struct { 736 __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ 737 } I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ 738 739 740 /** 741 * @brief I2S_PSEL [PSEL] (Unspecified) 742 */ 743 typedef struct { 744 __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ 745 __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ 746 __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ 747 __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ 748 __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ 749 } I2S_PSEL_Type; /*!< Size = 20 (0x14) */ 750 751 752 /** 753 * @brief USBD_HALTED [HALTED] (Unspecified) 754 */ 755 typedef struct { 756 __IM uint32_t EPIN[8]; /*!< (@ 0x00000000) Description collection[n]: IN endpoint halted 757 status. Can be used as is as response to 758 a GetStatus() request to endpoint. */ 759 __IM uint32_t RESERVED; 760 __IM uint32_t EPOUT[8]; /*!< (@ 0x00000024) Description collection[n]: OUT endpoint halted 761 status. Can be used as is as response to 762 a GetStatus() request to endpoint. */ 763 } USBD_HALTED_Type; /*!< Size = 68 (0x44) */ 764 765 766 /** 767 * @brief USBD_SIZE [SIZE] (Unspecified) 768 */ 769 typedef struct { 770 __IOM uint32_t EPOUT[8]; /*!< (@ 0x00000000) Description collection[n]: Number of bytes received 771 last in the data stage of this OUT endpoint */ 772 __IM uint32_t ISOOUT; /*!< (@ 0x00000020) Number of bytes received last on this ISO OUT 773 data endpoint */ 774 } USBD_SIZE_Type; /*!< Size = 36 (0x24) */ 775 776 777 /** 778 * @brief USBD_EPIN [EPIN] (Unspecified) 779 */ 780 typedef struct { 781 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Data pointer */ 782 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster[n]: Maximum number of bytes 783 to transfer */ 784 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster[n]: Number of bytes transferred 785 in the last transaction */ 786 __IM uint32_t RESERVED[2]; 787 } USBD_EPIN_Type; /*!< Size = 20 (0x14) */ 788 789 790 /** 791 * @brief USBD_ISOIN [ISOIN] (Unspecified) 792 */ 793 typedef struct { 794 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 795 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ 796 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 797 } USBD_ISOIN_Type; /*!< Size = 12 (0xc) */ 798 799 800 /** 801 * @brief USBD_EPOUT [EPOUT] (Unspecified) 802 */ 803 typedef struct { 804 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[n]: Data pointer */ 805 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster[n]: Maximum number of bytes 806 to transfer */ 807 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster[n]: Number of bytes transferred 808 in the last transaction */ 809 __IM uint32_t RESERVED[2]; 810 } USBD_EPOUT_Type; /*!< Size = 20 (0x14) */ 811 812 813 /** 814 * @brief USBD_ISOOUT [ISOOUT] (Unspecified) 815 */ 816 typedef struct { 817 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 818 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ 819 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 820 } USBD_ISOOUT_Type; /*!< Size = 12 (0xc) */ 821 822 823 /** 824 * @brief QSPI_READ [READ] (Unspecified) 825 */ 826 typedef struct { 827 __IOM uint32_t SRC; /*!< (@ 0x00000000) Flash memory source address */ 828 __IOM uint32_t DST; /*!< (@ 0x00000004) RAM destination address */ 829 __IOM uint32_t CNT; /*!< (@ 0x00000008) Read transfer length */ 830 } QSPI_READ_Type; /*!< Size = 12 (0xc) */ 831 832 833 /** 834 * @brief QSPI_WRITE [WRITE] (Unspecified) 835 */ 836 typedef struct { 837 __IOM uint32_t DST; /*!< (@ 0x00000000) Flash destination address */ 838 __IOM uint32_t SRC; /*!< (@ 0x00000004) RAM source address */ 839 __IOM uint32_t CNT; /*!< (@ 0x00000008) Write transfer length */ 840 } QSPI_WRITE_Type; /*!< Size = 12 (0xc) */ 841 842 843 /** 844 * @brief QSPI_ERASE [ERASE] (Unspecified) 845 */ 846 typedef struct { 847 __IOM uint32_t PTR; /*!< (@ 0x00000000) Start address of flash block to be erased */ 848 __IOM uint32_t LEN; /*!< (@ 0x00000004) Size of block to be erased. */ 849 } QSPI_ERASE_Type; /*!< Size = 8 (0x8) */ 850 851 852 /** 853 * @brief QSPI_PSEL [PSEL] (Unspecified) 854 */ 855 typedef struct { 856 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for serial clock SCK */ 857 __IOM uint32_t CSN; /*!< (@ 0x00000004) Pin select for chip select signal CSN. */ 858 __IM uint32_t RESERVED; 859 __IOM uint32_t IO0; /*!< (@ 0x0000000C) Pin select for serial data MOSI/IO0. */ 860 __IOM uint32_t IO1; /*!< (@ 0x00000010) Pin select for serial data MISO/IO1. */ 861 __IOM uint32_t IO2; /*!< (@ 0x00000014) Pin select for serial data IO2. */ 862 __IOM uint32_t IO3; /*!< (@ 0x00000018) Pin select for serial data IO3. */ 863 } QSPI_PSEL_Type; /*!< Size = 28 (0x1c) */ 864 865 866 /** @} */ /* End of group Device_Peripheral_clusters */ 867 868 869 /* =========================================================================================================================== */ 870 /* ================ Device Specific Peripheral Section ================ */ 871 /* =========================================================================================================================== */ 872 873 874 /** @addtogroup Device_Peripheral_peripherals 875 * @{ 876 */ 877 878 879 880 /* =========================================================================================================================== */ 881 /* ================ FICR ================ */ 882 /* =========================================================================================================================== */ 883 884 885 /** 886 * @brief Factory information configuration registers (FICR) 887 */ 888 889 typedef struct { /*!< (@ 0x10000000) FICR Structure */ 890 __IM uint32_t RESERVED[4]; 891 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ 892 __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ 893 __IM uint32_t RESERVED1[18]; 894 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection[n]: Device identifier */ 895 __IM uint32_t RESERVED2[6]; 896 __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection[n]: Encryption root, word 897 n */ 898 __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection[n]: Identity Root, word 899 n */ 900 __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ 901 __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection[n]: Device address n */ 902 __IM uint32_t RESERVED3[21]; 903 __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ 904 __IM uint32_t RESERVED4[140]; 905 __IM uint32_t PRODTEST[3]; /*!< (@ 0x00000350) Description collection[n]: Production test signature 906 n */ 907 __IM uint32_t RESERVED5[42]; 908 __IOM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization 909 coefficients */ 910 __IM uint32_t RESERVED6[2]; 911 __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ 912 __IM uint32_t RESERVED7[488]; 913 __IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */ 914 } NRF_FICR_Type; /*!< Size = 3104 (0xc20) */ 915 916 917 918 /* =========================================================================================================================== */ 919 /* ================ UICR ================ */ 920 /* =========================================================================================================================== */ 921 922 923 /** 924 * @brief User information configuration registers (UICR) 925 */ 926 927 typedef struct { /*!< (@ 0x10001000) UICR Structure */ 928 __IOM uint32_t UNUSED0; /*!< (@ 0x00000000) Unspecified */ 929 __IOM uint32_t UNUSED1; /*!< (@ 0x00000004) Unspecified */ 930 __IOM uint32_t UNUSED2; /*!< (@ 0x00000008) Unspecified */ 931 __IM uint32_t RESERVED; 932 __IOM uint32_t UNUSED3; /*!< (@ 0x00000010) Unspecified */ 933 __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection[n]: Reserved for Nordic 934 firmware design */ 935 __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection[n]: Reserved for Nordic 936 hardware design */ 937 __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection[n]: Reserved for customer */ 938 __IM uint32_t RESERVED1[64]; 939 __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection[n]: Mapping of the nRESET 940 function */ 941 __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ 942 __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality: 943 NFC antenna or GPIO */ 944 __IOM uint32_t DEBUGCTRL; /*!< (@ 0x00000210) Processor debug control */ 945 __IM uint32_t RESERVED2[60]; 946 __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) GPIO reference voltage / external output supply 947 voltage in high voltage mode */ 948 } NRF_UICR_Type; /*!< Size = 776 (0x308) */ 949 950 951 952 /* =========================================================================================================================== */ 953 /* ================ CLOCK ================ */ 954 /* =========================================================================================================================== */ 955 956 957 /** 958 * @brief Clock control (CLOCK) 959 */ 960 961 typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ 962 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFXO crystal oscillator */ 963 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFXO crystal oscillator */ 964 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK */ 965 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK */ 966 __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC */ 967 __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ 968 __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ 969 __IM uint32_t RESERVED[57]; 970 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFXO crystal oscillator started */ 971 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ 972 __IM uint32_t RESERVED1; 973 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFRC completed */ 974 __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ 975 __IM uint32_t RESERVED2[5]; 976 __IOM uint32_t EVENTS_CTSTARTED; /*!< (@ 0x00000128) Calibration timer has been started and is ready 977 to process new tasks */ 978 __IOM uint32_t EVENTS_CTSTOPPED; /*!< (@ 0x0000012C) Calibration timer has been stopped and is ready 979 to process new tasks */ 980 __IM uint32_t RESERVED3[117]; 981 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 982 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 983 __IM uint32_t RESERVED4[63]; 984 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 985 triggered */ 986 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ 987 __IM uint32_t RESERVED5; 988 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 989 triggered */ 990 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ 991 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART 992 task was triggered */ 993 __IM uint32_t RESERVED6[62]; 994 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ 995 __IM uint32_t RESERVED7[3]; 996 __IOM uint32_t HFXODEBOUNCE; /*!< (@ 0x00000528) HFXO debounce time. The HFXO is started by triggering 997 the TASKS_HFCLKSTART task. */ 998 __IM uint32_t RESERVED8[3]; 999 __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ 1000 __IM uint32_t RESERVED9[8]; 1001 __IOM uint32_t TRACECONFIG; /*!< (@ 0x0000055C) Clocking options for the trace port debug interface */ 1002 __IM uint32_t RESERVED10[21]; 1003 __IOM uint32_t LFRCMODE; /*!< (@ 0x000005B4) LFRC mode configuration */ 1004 } NRF_CLOCK_Type; /*!< Size = 1464 (0x5b8) */ 1005 1006 1007 1008 /* =========================================================================================================================== */ 1009 /* ================ POWER ================ */ 1010 /* =========================================================================================================================== */ 1011 1012 1013 /** 1014 * @brief Power control (POWER) 1015 */ 1016 1017 typedef struct { /*!< (@ 0x40000000) POWER Structure */ 1018 __IM uint32_t RESERVED[30]; 1019 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */ 1020 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ 1021 __IM uint32_t RESERVED1[34]; 1022 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 1023 __IM uint32_t RESERVED2[2]; 1024 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 1025 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 1026 __IOM uint32_t EVENTS_USBDETECTED; /*!< (@ 0x0000011C) Voltage supply detected on VBUS */ 1027 __IOM uint32_t EVENTS_USBREMOVED; /*!< (@ 0x00000120) Voltage supply removed from VBUS */ 1028 __IOM uint32_t EVENTS_USBPWRRDY; /*!< (@ 0x00000124) USB 3.3 V supply ready */ 1029 __IM uint32_t RESERVED3[119]; 1030 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1031 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1032 __IM uint32_t RESERVED4[61]; 1033 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 1034 __IM uint32_t RESERVED5[9]; 1035 __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Deprecated register - RAM status register */ 1036 __IM uint32_t RESERVED6[3]; 1037 __IM uint32_t USBREGSTATUS; /*!< (@ 0x00000438) USB supply status */ 1038 __IM uint32_t RESERVED7[49]; 1039 __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 1040 __IM uint32_t RESERVED8[3]; 1041 __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power-fail comparator configuration */ 1042 __IM uint32_t RESERVED9[2]; 1043 __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ 1044 __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ 1045 __IM uint32_t RESERVED10[21]; 1046 __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC converter for REG1 stage. */ 1047 __IM uint32_t RESERVED11; 1048 __IOM uint32_t DCDCEN0; /*!< (@ 0x00000580) Enable DC/DC converter for REG0 stage. */ 1049 __IM uint32_t RESERVED12[47]; 1050 __IM uint32_t MAINREGSTATUS; /*!< (@ 0x00000640) Main supply status */ 1051 __IM uint32_t RESERVED13[175]; 1052 __IOM POWER_RAM_Type RAM[9]; /*!< (@ 0x00000900) Unspecified */ 1053 } NRF_POWER_Type; /*!< Size = 2448 (0x990) */ 1054 1055 1056 1057 /* =========================================================================================================================== */ 1058 /* ================ RADIO ================ */ 1059 /* =========================================================================================================================== */ 1060 1061 1062 /** 1063 * @brief 2.4 GHz radio (RADIO) 1064 */ 1065 1066 typedef struct { /*!< (@ 0x40001000) RADIO Structure */ 1067 __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ 1068 __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ 1069 __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ 1070 __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ 1071 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ 1072 __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of 1073 the receive signal strength */ 1074 __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ 1075 __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ 1076 __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ 1077 __OM uint32_t TASKS_EDSTART; /*!< (@ 0x00000024) Start the energy detect measurement used in IEEE 1078 802.15.4 mode */ 1079 __OM uint32_t TASKS_EDSTOP; /*!< (@ 0x00000028) Stop the energy detect measurement */ 1080 __OM uint32_t TASKS_CCASTART; /*!< (@ 0x0000002C) Start the clear channel assessment used in IEEE 1081 802.15.4 mode */ 1082 __OM uint32_t TASKS_CCASTOP; /*!< (@ 0x00000030) Stop the clear channel assessment */ 1083 __IM uint32_t RESERVED[51]; 1084 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ 1085 __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ 1086 __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ 1087 __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ 1088 __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ 1089 __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received 1090 packet */ 1091 __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last 1092 received packet */ 1093 __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete */ 1094 __IM uint32_t RESERVED1[2]; 1095 __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value */ 1096 __IM uint32_t RESERVED2; 1097 __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ 1098 __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ 1099 __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */ 1100 __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new 1101 ED sample is ready for readout from the 1102 RADIO.EDSAMPLE register. */ 1103 __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */ 1104 __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */ 1105 __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */ 1106 __IOM uint32_t EVENTS_CCASTOPPED; /*!< (@ 0x0000014C) The CCA has stopped */ 1107 __IOM uint32_t EVENTS_RATEBOOST; /*!< (@ 0x00000150) Ble_LR CI field received, receive mode is changed 1108 from Ble_LR125Kbit to Ble_LR500Kbit. */ 1109 __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000154) RADIO has ramped up and is ready to be started 1110 TX path */ 1111 __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started 1112 RX path */ 1113 __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ 1114 __IM uint32_t RESERVED3[3]; 1115 __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated in Ble_LR125Kbit, Ble_LR500Kbit and 1116 BleIeee802154_250Kbit modes when last bit 1117 is sent on air. */ 1118 __IM uint32_t RESERVED4[36]; 1119 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1120 __IM uint32_t RESERVED5[64]; 1121 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1122 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1123 __IM uint32_t RESERVED6[61]; 1124 __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ 1125 __IM uint32_t RESERVED7; 1126 __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ 1127 __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ 1128 __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ 1129 __IM uint32_t PDUSTAT; /*!< (@ 0x00000414) Payload status */ 1130 __IM uint32_t RESERVED8[59]; 1131 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ 1132 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ 1133 __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ 1134 __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ 1135 __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ 1136 __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ 1137 __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ 1138 __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ 1139 __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ 1140 __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ 1141 __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ 1142 __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ 1143 __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ 1144 __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ 1145 __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ 1146 __IM uint32_t RESERVED9; 1147 __IOM uint32_t TIFS; /*!< (@ 0x00000544) Interframe spacing in us */ 1148 __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ 1149 __IM uint32_t RESERVED10; 1150 __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ 1151 __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ 1152 __IM uint32_t RESERVED11[2]; 1153 __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ 1154 __IM uint32_t RESERVED12[39]; 1155 __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection[n]: Device address base 1156 segment n */ 1157 __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection[n]: Device address prefix 1158 n */ 1159 __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ 1160 __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */ 1161 __IOM uint32_t MHRMATCHMAS; /*!< (@ 0x00000648) Pattern mask */ 1162 __IM uint32_t RESERVED13; 1163 __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ 1164 __IM uint32_t RESERVED14[3]; 1165 __IOM uint32_t SFD; /*!< (@ 0x00000660) IEEE 802.15.4 start of frame delimiter */ 1166 __IOM uint32_t EDCNT; /*!< (@ 0x00000664) IEEE 802.15.4 energy detect loop count */ 1167 __IOM uint32_t EDSAMPLE; /*!< (@ 0x00000668) IEEE 802.15.4 energy detect level */ 1168 __IOM uint32_t CCACTRL; /*!< (@ 0x0000066C) IEEE 802.15.4 clear channel assessment control */ 1169 __IM uint32_t RESERVED15[611]; 1170 __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ 1171 } NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ 1172 1173 1174 1175 /* =========================================================================================================================== */ 1176 /* ================ UART0 ================ */ 1177 /* =========================================================================================================================== */ 1178 1179 1180 /** 1181 * @brief Universal Asynchronous Receiver/Transmitter (UART0) 1182 */ 1183 1184 typedef struct { /*!< (@ 0x40002000) UART0 Structure */ 1185 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1186 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1187 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1188 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1189 __IM uint32_t RESERVED[3]; 1190 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ 1191 __IM uint32_t RESERVED1[56]; 1192 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1193 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1194 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ 1195 __IM uint32_t RESERVED2[4]; 1196 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1197 __IM uint32_t RESERVED3; 1198 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1199 __IM uint32_t RESERVED4[7]; 1200 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1201 __IM uint32_t RESERVED5[46]; 1202 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1203 __IM uint32_t RESERVED6[64]; 1204 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1205 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1206 __IM uint32_t RESERVED7[93]; 1207 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ 1208 __IM uint32_t RESERVED8[31]; 1209 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1210 __IM uint32_t RESERVED9; 1211 __IOM UART_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1212 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1213 __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1214 __IM uint32_t RESERVED10; 1215 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1216 selected. */ 1217 __IM uint32_t RESERVED11[17]; 1218 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1219 } NRF_UART_Type; /*!< Size = 1392 (0x570) */ 1220 1221 1222 1223 /* =========================================================================================================================== */ 1224 /* ================ UARTE0 ================ */ 1225 /* =========================================================================================================================== */ 1226 1227 1228 /** 1229 * @brief UART with EasyDMA 0 (UARTE0) 1230 */ 1231 1232 typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ 1233 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1234 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1235 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1236 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1237 __IM uint32_t RESERVED[7]; 1238 __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 1239 __IM uint32_t RESERVED1[52]; 1240 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1241 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1242 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 1243 transferred to Data RAM) */ 1244 __IM uint32_t RESERVED2; 1245 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 1246 __IM uint32_t RESERVED3[2]; 1247 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1248 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 1249 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1250 __IM uint32_t RESERVED4[7]; 1251 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1252 __IM uint32_t RESERVED5; 1253 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 1254 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 1255 __IM uint32_t RESERVED6; 1256 __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 1257 __IM uint32_t RESERVED7[41]; 1258 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1259 __IM uint32_t RESERVED8[63]; 1260 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1261 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1262 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1263 __IM uint32_t RESERVED9[93]; 1264 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write 1265 one to clear. */ 1266 __IM uint32_t RESERVED10[31]; 1267 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1268 __IM uint32_t RESERVED11; 1269 __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1270 __IM uint32_t RESERVED12[3]; 1271 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1272 selected. */ 1273 __IM uint32_t RESERVED13[3]; 1274 __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1275 __IM uint32_t RESERVED14; 1276 __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1277 __IM uint32_t RESERVED15[7]; 1278 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1279 } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 1280 1281 1282 1283 /* =========================================================================================================================== */ 1284 /* ================ SPI0 ================ */ 1285 /* =========================================================================================================================== */ 1286 1287 1288 /** 1289 * @brief Serial Peripheral Interface 0 (SPI0) 1290 */ 1291 1292 typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ 1293 __IM uint32_t RESERVED[66]; 1294 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ 1295 __IM uint32_t RESERVED1[126]; 1296 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1297 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1298 __IM uint32_t RESERVED2[125]; 1299 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ 1300 __IM uint32_t RESERVED3; 1301 __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1302 __IM uint32_t RESERVED4; 1303 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1304 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1305 __IM uint32_t RESERVED5; 1306 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1307 source selected. */ 1308 __IM uint32_t RESERVED6[11]; 1309 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1310 } NRF_SPI_Type; /*!< Size = 1368 (0x558) */ 1311 1312 1313 1314 /* =========================================================================================================================== */ 1315 /* ================ SPIM0 ================ */ 1316 /* =========================================================================================================================== */ 1317 1318 1319 /** 1320 * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0) 1321 */ 1322 1323 typedef struct { /*!< (@ 0x40003000) SPIM0 Structure */ 1324 __IM uint32_t RESERVED[4]; 1325 __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 1326 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 1327 __IM uint32_t RESERVED1; 1328 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 1329 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 1330 __IM uint32_t RESERVED2[56]; 1331 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 1332 __IM uint32_t RESERVED3[2]; 1333 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1334 __IM uint32_t RESERVED4; 1335 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 1336 __IM uint32_t RESERVED5; 1337 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 1338 __IM uint32_t RESERVED6[10]; 1339 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 1340 __IM uint32_t RESERVED7[44]; 1341 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1342 __IM uint32_t RESERVED8[64]; 1343 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1344 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1345 __IM uint32_t RESERVED9[61]; 1346 __IOM uint32_t STALLSTAT; /*!< (@ 0x00000400) Stall status for EasyDMA RAM accesses. The fields 1347 in this register is set to STALL by hardware 1348 whenever a stall occurres and can be cleared 1349 (set to NOSTALL) by the CPU. */ 1350 __IM uint32_t RESERVED10[63]; 1351 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 1352 __IM uint32_t RESERVED11; 1353 __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1354 __IM uint32_t RESERVED12[3]; 1355 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1356 source selected. */ 1357 __IM uint32_t RESERVED13[3]; 1358 __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1359 __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1360 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1361 __IM uint32_t RESERVED14[2]; 1362 __IOM SPIM_IFTIMING_Type IFTIMING; /*!< (@ 0x00000560) Unspecified */ 1363 __IOM uint32_t CSNPOL; /*!< (@ 0x00000568) Polarity of CSN output */ 1364 __IOM uint32_t PSELDCX; /*!< (@ 0x0000056C) Pin select for DCX signal */ 1365 __IOM uint32_t DCXCNT; /*!< (@ 0x00000570) DCX configuration */ 1366 __IM uint32_t RESERVED15[19]; 1367 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Byte transmitted after TXD.MAXCNT bytes have 1368 been transmitted in the case when RXD.MAXCNT 1369 is greater than TXD.MAXCNT */ 1370 } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1371 1372 1373 1374 /* =========================================================================================================================== */ 1375 /* ================ SPIS0 ================ */ 1376 /* =========================================================================================================================== */ 1377 1378 1379 /** 1380 * @brief SPI Slave 0 (SPIS0) 1381 */ 1382 1383 typedef struct { /*!< (@ 0x40003000) SPIS0 Structure */ 1384 __IM uint32_t RESERVED[9]; 1385 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1386 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1387 to acquire it */ 1388 __IM uint32_t RESERVED1[54]; 1389 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1390 __IM uint32_t RESERVED2[2]; 1391 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1392 __IM uint32_t RESERVED3[5]; 1393 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1394 __IM uint32_t RESERVED4[53]; 1395 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1396 __IM uint32_t RESERVED5[64]; 1397 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1398 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1399 __IM uint32_t RESERVED6[61]; 1400 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1401 __IM uint32_t RESERVED7[15]; 1402 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1403 __IM uint32_t RESERVED8[47]; 1404 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1405 __IM uint32_t RESERVED9; 1406 __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1407 __IM uint32_t RESERVED10[7]; 1408 __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1409 __IM uint32_t RESERVED11; 1410 __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1411 __IM uint32_t RESERVED12; 1412 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1413 __IM uint32_t RESERVED13; 1414 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1415 of an ignored transaction. */ 1416 __IM uint32_t RESERVED14[24]; 1417 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1418 } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1419 1420 1421 1422 /* =========================================================================================================================== */ 1423 /* ================ TWI0 ================ */ 1424 /* =========================================================================================================================== */ 1425 1426 1427 /** 1428 * @brief I2C compatible Two-Wire Interface 0 (TWI0) 1429 */ 1430 1431 typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ 1432 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1433 __IM uint32_t RESERVED; 1434 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1435 __IM uint32_t RESERVED1[2]; 1436 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1437 __IM uint32_t RESERVED2; 1438 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1439 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1440 __IM uint32_t RESERVED3[56]; 1441 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1442 __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ 1443 __IM uint32_t RESERVED4[4]; 1444 __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ 1445 __IM uint32_t RESERVED5; 1446 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1447 __IM uint32_t RESERVED6[4]; 1448 __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte 1449 that is sent or received */ 1450 __IM uint32_t RESERVED7[3]; 1451 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ 1452 __IM uint32_t RESERVED8[45]; 1453 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1454 __IM uint32_t RESERVED9[64]; 1455 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1456 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1457 __IM uint32_t RESERVED10[110]; 1458 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1459 __IM uint32_t RESERVED11[14]; 1460 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ 1461 __IM uint32_t RESERVED12; 1462 __IOM TWI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1463 __IM uint32_t RESERVED13[2]; 1464 __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ 1465 __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ 1466 __IM uint32_t RESERVED14; 1467 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1468 source selected. */ 1469 __IM uint32_t RESERVED15[24]; 1470 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1471 } NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ 1472 1473 1474 1475 /* =========================================================================================================================== */ 1476 /* ================ TWIM0 ================ */ 1477 /* =========================================================================================================================== */ 1478 1479 1480 /** 1481 * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0) 1482 */ 1483 1484 typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ 1485 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1486 __IM uint32_t RESERVED; 1487 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1488 __IM uint32_t RESERVED1[2]; 1489 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 1490 TWI master is not suspended. */ 1491 __IM uint32_t RESERVED2; 1492 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1493 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1494 __IM uint32_t RESERVED3[56]; 1495 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1496 __IM uint32_t RESERVED4[7]; 1497 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1498 __IM uint32_t RESERVED5[8]; 1499 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND 1500 task has been issued, TWI traffic is now 1501 suspended. */ 1502 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1503 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1504 __IM uint32_t RESERVED6[2]; 1505 __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 1506 __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 1507 byte */ 1508 __IM uint32_t RESERVED7[39]; 1509 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1510 __IM uint32_t RESERVED8[63]; 1511 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1512 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1513 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1514 __IM uint32_t RESERVED9[110]; 1515 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1516 __IM uint32_t RESERVED10[14]; 1517 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 1518 __IM uint32_t RESERVED11; 1519 __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1520 __IM uint32_t RESERVED12[5]; 1521 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1522 source selected. */ 1523 __IM uint32_t RESERVED13[3]; 1524 __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1525 __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1526 __IM uint32_t RESERVED14[13]; 1527 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1528 } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 1529 1530 1531 1532 /* =========================================================================================================================== */ 1533 /* ================ TWIS0 ================ */ 1534 /* =========================================================================================================================== */ 1535 1536 1537 /** 1538 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0) 1539 */ 1540 1541 typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ 1542 __IM uint32_t RESERVED[5]; 1543 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1544 __IM uint32_t RESERVED1; 1545 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1546 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1547 __IM uint32_t RESERVED2[3]; 1548 __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1549 __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1550 __IM uint32_t RESERVED3[51]; 1551 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1552 __IM uint32_t RESERVED4[7]; 1553 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1554 __IM uint32_t RESERVED5[9]; 1555 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1556 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1557 __IM uint32_t RESERVED6[4]; 1558 __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1559 __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1560 __IM uint32_t RESERVED7[37]; 1561 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1562 __IM uint32_t RESERVED8[63]; 1563 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1564 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1565 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1566 __IM uint32_t RESERVED9[113]; 1567 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1568 __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1569 a match */ 1570 __IM uint32_t RESERVED10[10]; 1571 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1572 __IM uint32_t RESERVED11; 1573 __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1574 __IM uint32_t RESERVED12[9]; 1575 __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1576 __IM uint32_t RESERVED13; 1577 __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1578 __IM uint32_t RESERVED14[14]; 1579 __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection[n]: TWI slave address 1580 n */ 1581 __IM uint32_t RESERVED15; 1582 __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1583 mechanism */ 1584 __IM uint32_t RESERVED16[10]; 1585 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1586 of an over-read of the transmit buffer. */ 1587 } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1588 1589 1590 1591 /* =========================================================================================================================== */ 1592 /* ================ NFCT ================ */ 1593 /* =========================================================================================================================== */ 1594 1595 1596 /** 1597 * @brief NFC-A compatible radio (NFCT) 1598 */ 1599 1600 typedef struct { /*!< (@ 0x40005000) NFCT Structure */ 1601 __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate NFCT peripheral for incoming and outgoing 1602 frames, change state to activated */ 1603 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000004) Disable NFCT peripheral */ 1604 __OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, change state to 1605 sense mode */ 1606 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x0000000C) Start transmission of an outgoing frame, change 1607 state to transmit */ 1608 __IM uint32_t RESERVED[3]; 1609 __OM uint32_t TASKS_ENABLERXDATA; /*!< (@ 0x0000001C) Initializes the EasyDMA for receive. */ 1610 __IM uint32_t RESERVED1; 1611 __OM uint32_t TASKS_GOIDLE; /*!< (@ 0x00000024) Force state machine to IDLE state */ 1612 __OM uint32_t TASKS_GOSLEEP; /*!< (@ 0x00000028) Force state machine to SLEEP_A state */ 1613 __IM uint32_t RESERVED2[53]; 1614 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) The NFCT peripheral is ready to receive and send 1615 frames */ 1616 __IOM uint32_t EVENTS_FIELDDETECTED; /*!< (@ 0x00000104) Remote NFC field detected */ 1617 __IOM uint32_t EVENTS_FIELDLOST; /*!< (@ 0x00000108) Remote NFC field lost */ 1618 __IOM uint32_t EVENTS_TXFRAMESTART; /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted 1619 frame */ 1620 __IOM uint32_t EVENTS_TXFRAMEEND; /*!< (@ 0x00000110) Marks the end of the last transmitted on-air 1621 symbol of a frame */ 1622 __IOM uint32_t EVENTS_RXFRAMESTART; /*!< (@ 0x00000114) Marks the end of the first symbol of a received 1623 frame */ 1624 __IOM uint32_t EVENTS_RXFRAMEEND; /*!< (@ 0x00000118) Received data has been checked (CRC, parity) 1625 and transferred to RAM, and EasyDMA has 1626 ended accessing the RX buffer */ 1627 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register 1628 contains details on the source of the error. */ 1629 __IM uint32_t RESERVED3[2]; 1630 __IOM uint32_t EVENTS_RXERROR; /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX 1631 register contains details on the source 1632 of the error. */ 1633 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN) 1634 in Data RAM full. */ 1635 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA 1636 has ended accessing the TX buffer */ 1637 __IM uint32_t RESERVED4; 1638 __IOM uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< (@ 0x00000138) Auto collision resolution process has started */ 1639 __IM uint32_t RESERVED5[3]; 1640 __IOM uint32_t EVENTS_COLLISION; /*!< (@ 0x00000148) NFC auto collision resolution error reported. */ 1641 __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC auto collision resolution successfully completed */ 1642 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */ 1643 __IM uint32_t RESERVED6[43]; 1644 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1645 __IM uint32_t RESERVED7[63]; 1646 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1647 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1648 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1649 __IM uint32_t RESERVED8[62]; 1650 __IOM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) NFC Error Status register */ 1651 __IM uint32_t RESERVED9; 1652 __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< (@ 0x0000040C) Unspecified */ 1653 __IM uint32_t NFCTAGSTATE; /*!< (@ 0x00000410) NfcTag state register */ 1654 __IM uint32_t RESERVED10[3]; 1655 __IM uint32_t SLEEPSTATE; /*!< (@ 0x00000420) Sleep state during automatic collision resolution */ 1656 __IM uint32_t RESERVED11[6]; 1657 __IM uint32_t FIELDPRESENT; /*!< (@ 0x0000043C) Indicates the presence or not of a valid field */ 1658 __IM uint32_t RESERVED12[49]; 1659 __IOM uint32_t FRAMEDELAYMIN; /*!< (@ 0x00000504) Minimum frame delay */ 1660 __IOM uint32_t FRAMEDELAYMAX; /*!< (@ 0x00000508) Maximum frame delay */ 1661 __IOM uint32_t FRAMEDELAYMODE; /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer */ 1662 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in 1663 Data RAM */ 1664 __IOM uint32_t MAXLEN; /*!< (@ 0x00000514) Size of the RAM buffer allocated to TXD and RXD 1665 data storage each */ 1666 __IOM NFCT_TXD_Type TXD; /*!< (@ 0x00000518) Unspecified */ 1667 __IOM NFCT_RXD_Type RXD; /*!< (@ 0x00000520) Unspecified */ 1668 __IM uint32_t RESERVED13[26]; 1669 __IOM uint32_t NFCID1_LAST; /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID) */ 1670 __IOM uint32_t NFCID1_2ND_LAST; /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID) */ 1671 __IOM uint32_t NFCID1_3RD_LAST; /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID) */ 1672 __IOM uint32_t AUTOCOLRESCONFIG; /*!< (@ 0x0000059C) Controls the auto collision resolution function. 1673 This setting must be done before the NFCT 1674 peripheral is enabled. */ 1675 __IOM uint32_t SENSRES; /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings */ 1676 __IOM uint32_t SELRES; /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings */ 1677 } NRF_NFCT_Type; /*!< Size = 1448 (0x5a8) */ 1678 1679 1680 1681 /* =========================================================================================================================== */ 1682 /* ================ GPIOTE ================ */ 1683 /* =========================================================================================================================== */ 1684 1685 1686 /** 1687 * @brief GPIO Tasks and Events (GPIOTE) 1688 */ 1689 1690 typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ 1691 __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection[n]: Task for writing to 1692 pin specified in CONFIG[n].PSEL. Action 1693 on pin is configured in CONFIG[n].POLARITY. */ 1694 __IM uint32_t RESERVED[4]; 1695 __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection[n]: Task for writing to 1696 pin specified in CONFIG[n].PSEL. Action 1697 on pin is to set it high. */ 1698 __IM uint32_t RESERVED1[4]; 1699 __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection[n]: Task for writing to 1700 pin specified in CONFIG[n].PSEL. Action 1701 on pin is to set it low. */ 1702 __IM uint32_t RESERVED2[32]; 1703 __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection[n]: Event generated from 1704 pin specified in CONFIG[n].PSEL */ 1705 __IM uint32_t RESERVED3[23]; 1706 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 1707 with SENSE mechanism enabled */ 1708 __IM uint32_t RESERVED4[97]; 1709 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1710 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1711 __IM uint32_t RESERVED5[129]; 1712 __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection[n]: Configuration for 1713 OUT[n], SET[n] and CLR[n] tasks and IN[n] 1714 event */ 1715 } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 1716 1717 1718 1719 /* =========================================================================================================================== */ 1720 /* ================ SAADC ================ */ 1721 /* =========================================================================================================================== */ 1722 1723 1724 /** 1725 * @brief Successive approximation register (SAR) analog-to-digital converter (SAADC) 1726 */ 1727 1728 typedef struct { /*!< (@ 0x40007000) SAADC Structure */ 1729 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts the SAADC and prepares the result buffer 1730 in RAM */ 1731 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Takes one SAADC sample */ 1732 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stops the SAADC and terminates all on-going conversions */ 1733 __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ 1734 __IM uint32_t RESERVED[60]; 1735 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The SAADC has started */ 1736 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The SAADC has filled up the result buffer */ 1737 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending 1738 on the configuration, multiple conversions 1739 might be needed for a result to be transferred 1740 to RAM. */ 1741 __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) Result ready for transfer to RAM */ 1742 __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ 1743 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The SAADC has stopped */ 1744 __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Unspecified */ 1745 __IM uint32_t RESERVED1[106]; 1746 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1747 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1748 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1749 __IM uint32_t RESERVED2[61]; 1750 __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ 1751 __IM uint32_t RESERVED3[63]; 1752 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable SAADC */ 1753 __IM uint32_t RESERVED4[3]; 1754 __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ 1755 __IM uint32_t RESERVED5[24]; 1756 __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ 1757 __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. The RESOLUTION is 1758 applied before averaging, thus for high 1759 OVERSAMPLE a higher RESOLUTION should be 1760 used. */ 1761 __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ 1762 __IM uint32_t RESERVED6[12]; 1763 __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ 1764 } NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ 1765 1766 1767 1768 /* =========================================================================================================================== */ 1769 /* ================ TIMER0 ================ */ 1770 /* =========================================================================================================================== */ 1771 1772 1773 /** 1774 * @brief Timer/Counter 0 (TIMER0) 1775 */ 1776 1777 typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ 1778 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 1779 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 1780 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 1781 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 1782 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 1783 __IM uint32_t RESERVED[11]; 1784 __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection[n]: Capture Timer value 1785 to CC[n] register */ 1786 __IM uint32_t RESERVED1[58]; 1787 __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection[n]: Compare event on CC[n] 1788 match */ 1789 __IM uint32_t RESERVED2[42]; 1790 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1791 __IM uint32_t RESERVED3[64]; 1792 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1793 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1794 __IM uint32_t RESERVED4[126]; 1795 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 1796 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 1797 __IM uint32_t RESERVED5; 1798 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 1799 __IM uint32_t RESERVED6[11]; 1800 __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection[n]: Capture/Compare register 1801 n */ 1802 } NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ 1803 1804 1805 1806 /* =========================================================================================================================== */ 1807 /* ================ RTC0 ================ */ 1808 /* =========================================================================================================================== */ 1809 1810 1811 /** 1812 * @brief Real time counter 0 (RTC0) 1813 */ 1814 1815 typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ 1816 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ 1817 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ 1818 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ 1819 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ 1820 __IM uint32_t RESERVED[60]; 1821 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ 1822 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ 1823 __IM uint32_t RESERVED1[14]; 1824 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection[n]: Compare event on CC[n] 1825 match */ 1826 __IM uint32_t RESERVED2[109]; 1827 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1828 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1829 __IM uint32_t RESERVED3[13]; 1830 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 1831 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 1832 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 1833 __IM uint32_t RESERVED4[110]; 1834 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ 1835 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu 1836 t be written when RTC is stopped */ 1837 __IM uint32_t RESERVED5[13]; 1838 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection[n]: Compare register n */ 1839 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 1840 1841 1842 1843 /* =========================================================================================================================== */ 1844 /* ================ TEMP ================ */ 1845 /* =========================================================================================================================== */ 1846 1847 1848 /** 1849 * @brief Temperature Sensor (TEMP) 1850 */ 1851 1852 typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ 1853 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ 1854 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ 1855 __IM uint32_t RESERVED[62]; 1856 __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ 1857 __IM uint32_t RESERVED1[128]; 1858 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1859 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1860 __IM uint32_t RESERVED2[127]; 1861 __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ 1862 __IM uint32_t RESERVED3[5]; 1863 __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ 1864 __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ 1865 __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ 1866 __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ 1867 __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ 1868 __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ 1869 __IM uint32_t RESERVED4[2]; 1870 __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ 1871 __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ 1872 __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ 1873 __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ 1874 __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ 1875 __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ 1876 __IM uint32_t RESERVED5[2]; 1877 __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ 1878 __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ 1879 __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ 1880 __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ 1881 __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ 1882 } NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ 1883 1884 1885 1886 /* =========================================================================================================================== */ 1887 /* ================ RNG ================ */ 1888 /* =========================================================================================================================== */ 1889 1890 1891 /** 1892 * @brief Random Number Generator (RNG) 1893 */ 1894 1895 typedef struct { /*!< (@ 0x4000D000) RNG Structure */ 1896 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ 1897 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ 1898 __IM uint32_t RESERVED[62]; 1899 __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number 1900 written to the VALUE register */ 1901 __IM uint32_t RESERVED1[63]; 1902 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1903 __IM uint32_t RESERVED2[64]; 1904 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1905 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1906 __IM uint32_t RESERVED3[126]; 1907 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 1908 __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ 1909 } NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ 1910 1911 1912 1913 /* =========================================================================================================================== */ 1914 /* ================ ECB ================ */ 1915 /* =========================================================================================================================== */ 1916 1917 1918 /** 1919 * @brief AES ECB Mode Encryption (ECB) 1920 */ 1921 1922 typedef struct { /*!< (@ 0x4000E000) ECB Structure */ 1923 __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ 1924 __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ 1925 __IM uint32_t RESERVED[62]; 1926 __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ 1927 __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB 1928 task or due to an error */ 1929 __IM uint32_t RESERVED1[127]; 1930 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1931 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1932 __IM uint32_t RESERVED2[126]; 1933 __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ 1934 } NRF_ECB_Type; /*!< Size = 1288 (0x508) */ 1935 1936 1937 1938 /* =========================================================================================================================== */ 1939 /* ================ AAR ================ */ 1940 /* =========================================================================================================================== */ 1941 1942 1943 /** 1944 * @brief Accelerated Address Resolver (AAR) 1945 */ 1946 1947 typedef struct { /*!< (@ 0x4000F000) AAR Structure */ 1948 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified 1949 in the IRK data structure */ 1950 __IM uint32_t RESERVED; 1951 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ 1952 __IM uint32_t RESERVED1[61]; 1953 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ 1954 __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ 1955 __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ 1956 __IM uint32_t RESERVED2[126]; 1957 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1958 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1959 __IM uint32_t RESERVED3[61]; 1960 __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ 1961 __IM uint32_t RESERVED4[63]; 1962 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ 1963 __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ 1964 __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ 1965 __IM uint32_t RESERVED5; 1966 __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ 1967 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 1968 } NRF_AAR_Type; /*!< Size = 1304 (0x518) */ 1969 1970 1971 1972 /* =========================================================================================================================== */ 1973 /* ================ CCM ================ */ 1974 /* =========================================================================================================================== */ 1975 1976 1977 /** 1978 * @brief AES CCM Mode Encryption (CCM) 1979 */ 1980 1981 typedef struct { /*!< (@ 0x4000F000) CCM Structure */ 1982 __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation 1983 will stop by itself when completed. */ 1984 __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will 1985 stop by itself when completed. */ 1986 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ 1987 __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with 1988 the contents of the RATEOVERRIDE register 1989 for any ongoing encryption/decryption */ 1990 __IM uint32_t RESERVED[60]; 1991 __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ 1992 __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ 1993 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ 1994 __IM uint32_t RESERVED1[61]; 1995 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 1996 __IM uint32_t RESERVED2[64]; 1997 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1998 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1999 __IM uint32_t RESERVED3[61]; 2000 __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ 2001 __IM uint32_t RESERVED4[63]; 2002 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ 2003 __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ 2004 __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and 2005 NONCE vector */ 2006 __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ 2007 __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ 2008 __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ 2009 __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of key-stream generated when MODE.LENGTH 2010 = Extended. */ 2011 __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ 2012 } NRF_CCM_Type; /*!< Size = 1312 (0x520) */ 2013 2014 2015 2016 /* =========================================================================================================================== */ 2017 /* ================ WDT ================ */ 2018 /* =========================================================================================================================== */ 2019 2020 2021 /** 2022 * @brief Watchdog Timer (WDT) 2023 */ 2024 2025 typedef struct { /*!< (@ 0x40010000) WDT Structure */ 2026 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ 2027 __IM uint32_t RESERVED[63]; 2028 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 2029 __IM uint32_t RESERVED1[128]; 2030 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2031 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2032 __IM uint32_t RESERVED2[61]; 2033 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 2034 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 2035 __IM uint32_t RESERVED3[63]; 2036 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 2037 __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 2038 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 2039 __IM uint32_t RESERVED4[60]; 2040 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection[n]: Reload request n */ 2041 } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 2042 2043 2044 2045 /* =========================================================================================================================== */ 2046 /* ================ QDEC ================ */ 2047 /* =========================================================================================================================== */ 2048 2049 2050 /** 2051 * @brief Quadrature Decoder (QDEC) 2052 */ 2053 2054 typedef struct { /*!< (@ 0x40012000) QDEC Structure */ 2055 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ 2056 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ 2057 __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ 2058 __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ 2059 __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ 2060 __IM uint32_t RESERVED[59]; 2061 __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value 2062 written to the SAMPLE register */ 2063 __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ 2064 __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ 2065 __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ 2066 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ 2067 __IM uint32_t RESERVED1[59]; 2068 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 2069 __IM uint32_t RESERVED2[64]; 2070 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2071 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2072 __IM uint32_t RESERVED3[125]; 2073 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ 2074 __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ 2075 __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ 2076 __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ 2077 __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY 2078 and DBLRDY events can be generated */ 2079 __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ 2080 __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the 2081 READCLRACC or RDCLRACC task */ 2082 __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ 2083 __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ 2084 __IM uint32_t RESERVED4[5]; 2085 __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ 2086 __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected 2087 double transitions */ 2088 __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC 2089 or RDCLRDBL task */ 2090 } NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ 2091 2092 2093 2094 /* =========================================================================================================================== */ 2095 /* ================ COMP ================ */ 2096 /* =========================================================================================================================== */ 2097 2098 2099 /** 2100 * @brief Comparator (COMP) 2101 */ 2102 2103 typedef struct { /*!< (@ 0x40013000) COMP Structure */ 2104 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 2105 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 2106 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 2107 __IM uint32_t RESERVED[61]; 2108 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ 2109 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 2110 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 2111 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 2112 __IM uint32_t RESERVED1[60]; 2113 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 2114 __IM uint32_t RESERVED2[63]; 2115 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2116 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2117 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2118 __IM uint32_t RESERVED3[61]; 2119 __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 2120 __IM uint32_t RESERVED4[63]; 2121 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ 2122 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ 2123 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ 2124 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 2125 __IM uint32_t RESERVED5[8]; 2126 __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ 2127 __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ 2128 __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 2129 } NRF_COMP_Type; /*!< Size = 1340 (0x53c) */ 2130 2131 2132 2133 /* =========================================================================================================================== */ 2134 /* ================ LPCOMP ================ */ 2135 /* =========================================================================================================================== */ 2136 2137 2138 /** 2139 * @brief Low Power Comparator (LPCOMP) 2140 */ 2141 2142 typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */ 2143 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 2144 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 2145 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 2146 __IM uint32_t RESERVED[61]; 2147 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid */ 2148 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 2149 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 2150 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 2151 __IM uint32_t RESERVED1[60]; 2152 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 2153 __IM uint32_t RESERVED2[64]; 2154 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2155 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2156 __IM uint32_t RESERVED3[61]; 2157 __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 2158 __IM uint32_t RESERVED4[63]; 2159 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable LPCOMP */ 2160 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select */ 2161 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select */ 2162 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 2163 __IM uint32_t RESERVED5[4]; 2164 __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration */ 2165 __IM uint32_t RESERVED6[5]; 2166 __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 2167 } NRF_LPCOMP_Type; /*!< Size = 1340 (0x53c) */ 2168 2169 2170 2171 /* =========================================================================================================================== */ 2172 /* ================ EGU0 ================ */ 2173 /* =========================================================================================================================== */ 2174 2175 2176 /** 2177 * @brief Event Generator Unit 0 (EGU0) 2178 */ 2179 2180 typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ 2181 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection[n]: Trigger n for triggering 2182 the corresponding TRIGGERED[n] event */ 2183 __IM uint32_t RESERVED[48]; 2184 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection[n]: Event number n generated 2185 by triggering the corresponding TRIGGER[n] 2186 task */ 2187 __IM uint32_t RESERVED1[112]; 2188 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2189 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2190 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2191 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 2192 2193 2194 2195 /* =========================================================================================================================== */ 2196 /* ================ SWI0 ================ */ 2197 /* =========================================================================================================================== */ 2198 2199 2200 /** 2201 * @brief Software interrupt 0 (SWI0) 2202 */ 2203 2204 typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ 2205 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 2206 } NRF_SWI_Type; /*!< Size = 4 (0x4) */ 2207 2208 2209 2210 /* =========================================================================================================================== */ 2211 /* ================ PWM0 ================ */ 2212 /* =========================================================================================================================== */ 2213 2214 2215 /** 2216 * @brief Pulse width modulation unit 0 (PWM0) 2217 */ 2218 2219 typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */ 2220 __IM uint32_t RESERVED; 2221 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at 2222 the end of current PWM period, and stops 2223 sequence playback */ 2224 __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection[n]: Loads the first PWM 2225 value on all enabled channels from sequence 2226 n, and starts playing that sequence at the 2227 rate defined in SEQ[n]REFRESH and/or DECODER.MODE. 2228 Causes PWM generation to start if not running. */ 2229 __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on 2230 all enabled channels if DECODER.MODE=NextStep. 2231 Does not cause PWM generation to start if 2232 not running. */ 2233 __IM uint32_t RESERVED1[60]; 2234 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses 2235 are no longer generated */ 2236 __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection[n]: First PWM period started 2237 on sequence n */ 2238 __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection[n]: Emitted at end of 2239 every sequence n, when last value from RAM 2240 has been applied to wave counter */ 2241 __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ 2242 __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount 2243 of times defined in LOOP.CNT */ 2244 __IM uint32_t RESERVED2[56]; 2245 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 2246 __IM uint32_t RESERVED3[63]; 2247 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2248 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2249 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2250 __IM uint32_t RESERVED4[125]; 2251 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ 2252 __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ 2253 __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter 2254 counts */ 2255 __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ 2256 __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ 2257 __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ 2258 __IM uint32_t RESERVED5[2]; 2259 __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ 2260 __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2261 } NRF_PWM_Type; /*!< Size = 1392 (0x570) */ 2262 2263 2264 2265 /* =========================================================================================================================== */ 2266 /* ================ PDM ================ */ 2267 /* =========================================================================================================================== */ 2268 2269 2270 /** 2271 * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) 2272 */ 2273 2274 typedef struct { /*!< (@ 0x4001D000) PDM Structure */ 2275 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ 2276 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ 2277 __IM uint32_t RESERVED[62]; 2278 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ 2279 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ 2280 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified 2281 by SAMPLE.MAXCNT (or the last sample after 2282 a STOP task has been received) to Data RAM */ 2283 __IM uint32_t RESERVED1[125]; 2284 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2285 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2286 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2287 __IM uint32_t RESERVED2[125]; 2288 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ 2289 __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ 2290 __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' 2291 signals */ 2292 __IM uint32_t RESERVED3[3]; 2293 __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ 2294 __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ 2295 __IOM uint32_t RATIO; /*!< (@ 0x00000520) Selects the ratio between PDM_CLK and output 2296 sample rate. Change PDMCLKCTRL accordingly. */ 2297 __IM uint32_t RESERVED4[7]; 2298 __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ 2299 __IM uint32_t RESERVED5[6]; 2300 __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ 2301 } NRF_PDM_Type; /*!< Size = 1384 (0x568) */ 2302 2303 2304 2305 /* =========================================================================================================================== */ 2306 /* ================ ACL ================ */ 2307 /* =========================================================================================================================== */ 2308 2309 2310 /** 2311 * @brief Access control lists (ACL) 2312 */ 2313 2314 typedef struct { /*!< (@ 0x4001E000) ACL Structure */ 2315 __IM uint32_t RESERVED[512]; 2316 __IOM ACL_ACL_Type ACL[8]; /*!< (@ 0x00000800) Unspecified */ 2317 } NRF_ACL_Type; /*!< Size = 2176 (0x880) */ 2318 2319 2320 2321 /* =========================================================================================================================== */ 2322 /* ================ NVMC ================ */ 2323 /* =========================================================================================================================== */ 2324 2325 2326 /** 2327 * @brief Non Volatile Memory Controller (NVMC) 2328 */ 2329 2330 typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ 2331 __IM uint32_t RESERVED[256]; 2332 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 2333 __IM uint32_t RESERVED1; 2334 __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ 2335 __IM uint32_t RESERVED2[62]; 2336 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 2337 2338 union { 2339 __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */ 2340 __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a 2341 page in code area. Equivalent to ERASEPAGE. */ 2342 }; 2343 __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 2344 __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a 2345 page in code area. Equivalent to ERASEPAGE. */ 2346 __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration 2347 registers */ 2348 __IOM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code 2349 area */ 2350 __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 2351 __IM uint32_t RESERVED3[8]; 2352 __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register. */ 2353 __IM uint32_t RESERVED4; 2354 __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter. */ 2355 __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter. */ 2356 } NRF_NVMC_Type; /*!< Size = 1360 (0x550) */ 2357 2358 2359 2360 /* =========================================================================================================================== */ 2361 /* ================ PPI ================ */ 2362 /* =========================================================================================================================== */ 2363 2364 2365 /** 2366 * @brief Programmable Peripheral Interconnect (PPI) 2367 */ 2368 2369 typedef struct { /*!< (@ 0x4001F000) PPI Structure */ 2370 __IOM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 2371 __IM uint32_t RESERVED[308]; 2372 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 2373 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 2374 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 2375 __IM uint32_t RESERVED1; 2376 __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ 2377 __IM uint32_t RESERVED2[148]; 2378 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection[n]: Channel group n */ 2379 __IM uint32_t RESERVED3[62]; 2380 __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ 2381 } NRF_PPI_Type; /*!< Size = 2448 (0x990) */ 2382 2383 2384 2385 /* =========================================================================================================================== */ 2386 /* ================ MWU ================ */ 2387 /* =========================================================================================================================== */ 2388 2389 2390 /** 2391 * @brief Memory Watch Unit (MWU) 2392 */ 2393 2394 typedef struct { /*!< (@ 0x40020000) MWU Structure */ 2395 __IM uint32_t RESERVED[64]; 2396 __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Unspecified */ 2397 __IM uint32_t RESERVED1[16]; 2398 __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Unspecified */ 2399 __IM uint32_t RESERVED2[100]; 2400 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2401 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2402 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2403 __IM uint32_t RESERVED3[5]; 2404 __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable non-maskable interrupt */ 2405 __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable non-maskable interrupt */ 2406 __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable non-maskable interrupt */ 2407 __IM uint32_t RESERVED4[53]; 2408 __IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */ 2409 __IM uint32_t RESERVED5[64]; 2410 __IOM uint32_t REGIONEN; /*!< (@ 0x00000510) Enable/disable regions watch */ 2411 __IOM uint32_t REGIONENSET; /*!< (@ 0x00000514) Enable regions watch */ 2412 __IOM uint32_t REGIONENCLR; /*!< (@ 0x00000518) Disable regions watch */ 2413 __IM uint32_t RESERVED6[57]; 2414 __IOM MWU_REGION_Type REGION[4]; /*!< (@ 0x00000600) Unspecified */ 2415 __IM uint32_t RESERVED7[32]; 2416 __IOM MWU_PREGION_Type PREGION[2]; /*!< (@ 0x000006C0) Unspecified */ 2417 } NRF_MWU_Type; /*!< Size = 1760 (0x6e0) */ 2418 2419 2420 2421 /* =========================================================================================================================== */ 2422 /* ================ I2S ================ */ 2423 /* =========================================================================================================================== */ 2424 2425 2426 /** 2427 * @brief Inter-IC Sound (I2S) 2428 */ 2429 2430 typedef struct { /*!< (@ 0x40025000) I2S Structure */ 2431 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK 2432 generator when this is enabled. */ 2433 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. 2434 Triggering this task will cause the {event:STOPPED} 2435 event to be generated. */ 2436 __IM uint32_t RESERVED[63]; 2437 __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal 2438 double-buffers. When the I2S module is started 2439 and RX is enabled, this event will be generated 2440 for every RXTXD.MAXCNT words that are received 2441 on the SDIN pin. */ 2442 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ 2443 __IM uint32_t RESERVED1[2]; 2444 __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal 2445 double-buffers. When the I2S module is started 2446 and TX is enabled, this event will be generated 2447 for every RXTXD.MAXCNT words that are sent 2448 on the SDOUT pin. */ 2449 __IM uint32_t RESERVED2[122]; 2450 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2451 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2452 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2453 __IM uint32_t RESERVED3[125]; 2454 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ 2455 __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ 2456 __IM uint32_t RESERVED4[3]; 2457 __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ 2458 __IM uint32_t RESERVED5; 2459 __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ 2460 __IM uint32_t RESERVED6[3]; 2461 __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ 2462 __IM uint32_t RESERVED7[3]; 2463 __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2464 } NRF_I2S_Type; /*!< Size = 1396 (0x574) */ 2465 2466 2467 2468 /* =========================================================================================================================== */ 2469 /* ================ FPU ================ */ 2470 /* =========================================================================================================================== */ 2471 2472 2473 /** 2474 * @brief FPU (FPU) 2475 */ 2476 2477 typedef struct { /*!< (@ 0x40026000) FPU Structure */ 2478 __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ 2479 } NRF_FPU_Type; /*!< Size = 4 (0x4) */ 2480 2481 2482 2483 /* =========================================================================================================================== */ 2484 /* ================ USBD ================ */ 2485 /* =========================================================================================================================== */ 2486 2487 2488 /** 2489 * @brief Universal serial bus device (USBD) 2490 */ 2491 2492 typedef struct { /*!< (@ 0x40027000) USBD Structure */ 2493 __IM uint32_t RESERVED; 2494 __OM uint32_t TASKS_STARTEPIN[8]; /*!< (@ 0x00000004) Description collection[n]: Captures the EPIN[n].PTR 2495 and EPIN[n].MAXCNT registers values, and 2496 enables endpoint IN n to respond to traffic 2497 from host */ 2498 __OM uint32_t TASKS_STARTISOIN; /*!< (@ 0x00000024) Captures the ISOIN.PTR and ISOIN.MAXCNT registers 2499 values, and enables sending data on ISO 2500 endpoint */ 2501 __OM uint32_t TASKS_STARTEPOUT[8]; /*!< (@ 0x00000028) Description collection[n]: Captures the EPOUT[n].PTR 2502 and EPOUT[n].MAXCNT registers values, and 2503 enables endpoint n to respond to traffic 2504 from host */ 2505 __OM uint32_t TASKS_STARTISOOUT; /*!< (@ 0x00000048) Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers 2506 values, and enables receiving of data on 2507 ISO endpoint */ 2508 __OM uint32_t TASKS_EP0RCVOUT; /*!< (@ 0x0000004C) Allows OUT data stage on control endpoint 0 */ 2509 __OM uint32_t TASKS_EP0STATUS; /*!< (@ 0x00000050) Allows status stage on control endpoint 0 */ 2510 __OM uint32_t TASKS_EP0STALL; /*!< (@ 0x00000054) Stalls data and status stage on control endpoint 2511 0 */ 2512 __OM uint32_t TASKS_DPDMDRIVE; /*!< (@ 0x00000058) Forces D+ and D- lines into the state defined 2513 in the DPDMVALUE register */ 2514 __OM uint32_t TASKS_DPDMNODRIVE; /*!< (@ 0x0000005C) Stops forcing D+ and D- lines into any state 2515 (USB engine takes control) */ 2516 __IM uint32_t RESERVED1[40]; 2517 __IOM uint32_t EVENTS_USBRESET; /*!< (@ 0x00000100) Signals that a USB reset condition has been detected 2518 on USB lines */ 2519 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000104) Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, 2520 or EPOUT[n].PTR and EPOUT[n].MAXCNT registers 2521 have been captured on all endpoints reported 2522 in the EPSTATUS register */ 2523 __IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection[n]: The whole EPIN[n] 2524 buffer has been consumed. The RAM buffer 2525 can be accessed safely by software. */ 2526 __IOM uint32_t EVENTS_EP0DATADONE; /*!< (@ 0x00000128) An acknowledged data transfer has taken place 2527 on the control endpoint */ 2528 __IOM uint32_t EVENTS_ENDISOIN; /*!< (@ 0x0000012C) The whole ISOIN buffer has been consumed. The 2529 RAM buffer can be accessed safely by software. */ 2530 __IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection[n]: The whole EPOUT[n] 2531 buffer has been consumed. The RAM buffer 2532 can be accessed safely by software. */ 2533 __IOM uint32_t EVENTS_ENDISOOUT; /*!< (@ 0x00000150) The whole ISOOUT buffer has been consumed. The 2534 RAM buffer can be accessed safely by software. */ 2535 __IOM uint32_t EVENTS_SOF; /*!< (@ 0x00000154) Signals that a SOF (start of frame) condition 2536 has been detected on USB lines */ 2537 __IOM uint32_t EVENTS_USBEVENT; /*!< (@ 0x00000158) An event or an error not covered by specific 2538 events has occurred. Check EVENTCAUSE register 2539 to find the cause. */ 2540 __IOM uint32_t EVENTS_EP0SETUP; /*!< (@ 0x0000015C) A valid SETUP token has been received (and acknowledged) 2541 on the control endpoint */ 2542 __IOM uint32_t EVENTS_EPDATA; /*!< (@ 0x00000160) A data transfer has occurred on a data endpoint, 2543 indicated by the EPDATASTATUS register */ 2544 __IM uint32_t RESERVED2[39]; 2545 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ 2546 __IM uint32_t RESERVED3[63]; 2547 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2548 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2549 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2550 __IM uint32_t RESERVED4[61]; 2551 __IOM uint32_t EVENTCAUSE; /*!< (@ 0x00000400) Details on what caused the USBEVENT event */ 2552 __IM uint32_t RESERVED5[7]; 2553 __IOM USBD_HALTED_Type HALTED; /*!< (@ 0x00000420) Unspecified */ 2554 __IM uint32_t RESERVED6; 2555 __IOM uint32_t EPSTATUS; /*!< (@ 0x00000468) Provides information on which endpoint's EasyDMA 2556 registers have been captured */ 2557 __IOM uint32_t EPDATASTATUS; /*!< (@ 0x0000046C) Provides information on which endpoint(s) an 2558 acknowledged data transfer has occurred 2559 (EPDATA event) */ 2560 __IM uint32_t USBADDR; /*!< (@ 0x00000470) Device USB address */ 2561 __IM uint32_t RESERVED7[3]; 2562 __IM uint32_t BMREQUESTTYPE; /*!< (@ 0x00000480) SETUP data, byte 0, bmRequestType */ 2563 __IM uint32_t BREQUEST; /*!< (@ 0x00000484) SETUP data, byte 1, bRequest */ 2564 __IM uint32_t WVALUEL; /*!< (@ 0x00000488) SETUP data, byte 2, LSB of wValue */ 2565 __IM uint32_t WVALUEH; /*!< (@ 0x0000048C) SETUP data, byte 3, MSB of wValue */ 2566 __IM uint32_t WINDEXL; /*!< (@ 0x00000490) SETUP data, byte 4, LSB of wIndex */ 2567 __IM uint32_t WINDEXH; /*!< (@ 0x00000494) SETUP data, byte 5, MSB of wIndex */ 2568 __IM uint32_t WLENGTHL; /*!< (@ 0x00000498) SETUP data, byte 6, LSB of wLength */ 2569 __IM uint32_t WLENGTHH; /*!< (@ 0x0000049C) SETUP data, byte 7, MSB of wLength */ 2570 __IOM USBD_SIZE_Type SIZE; /*!< (@ 0x000004A0) Unspecified */ 2571 __IM uint32_t RESERVED8[15]; 2572 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable USB */ 2573 __IOM uint32_t USBPULLUP; /*!< (@ 0x00000504) Control of the USB pull-up */ 2574 __IOM uint32_t DPDMVALUE; /*!< (@ 0x00000508) State D+ and D- lines will be forced into by 2575 the DPDMDRIVE task. The DPDMNODRIVE task 2576 reverts the control of the lines to MAC 2577 IP (no forcing). */ 2578 __IOM uint32_t DTOGGLE; /*!< (@ 0x0000050C) Data toggle control and status */ 2579 __IOM uint32_t EPINEN; /*!< (@ 0x00000510) Endpoint IN enable */ 2580 __IOM uint32_t EPOUTEN; /*!< (@ 0x00000514) Endpoint OUT enable */ 2581 __OM uint32_t EPSTALL; /*!< (@ 0x00000518) STALL endpoints */ 2582 __IOM uint32_t ISOSPLIT; /*!< (@ 0x0000051C) Controls the split of ISO buffers */ 2583 __IM uint32_t FRAMECNTR; /*!< (@ 0x00000520) Returns the current value of the start of frame 2584 counter */ 2585 __IM uint32_t RESERVED9[2]; 2586 __IOM uint32_t LOWPOWER; /*!< (@ 0x0000052C) Controls USBD peripheral low power mode during 2587 USB suspend */ 2588 __IOM uint32_t ISOINCONFIG; /*!< (@ 0x00000530) Controls the response of the ISO IN endpoint 2589 to an IN token when no data is ready to 2590 be sent */ 2591 __IM uint32_t RESERVED10[51]; 2592 __IOM USBD_EPIN_Type EPIN[8]; /*!< (@ 0x00000600) Unspecified */ 2593 __IOM USBD_ISOIN_Type ISOIN; /*!< (@ 0x000006A0) Unspecified */ 2594 __IM uint32_t RESERVED11[21]; 2595 __IOM USBD_EPOUT_Type EPOUT[8]; /*!< (@ 0x00000700) Unspecified */ 2596 __IOM USBD_ISOOUT_Type ISOOUT; /*!< (@ 0x000007A0) Unspecified */ 2597 } NRF_USBD_Type; /*!< Size = 1964 (0x7ac) */ 2598 2599 2600 2601 /* =========================================================================================================================== */ 2602 /* ================ QSPI ================ */ 2603 /* =========================================================================================================================== */ 2604 2605 2606 /** 2607 * @brief External flash interface (QSPI) 2608 */ 2609 2610 typedef struct { /*!< (@ 0x40029000) QSPI Structure */ 2611 __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate QSPI interface */ 2612 __OM uint32_t TASKS_READSTART; /*!< (@ 0x00000004) Start transfer from external flash memory to 2613 internal RAM */ 2614 __OM uint32_t TASKS_WRITESTART; /*!< (@ 0x00000008) Start transfer from internal RAM to external 2615 flash memory */ 2616 __OM uint32_t TASKS_ERASESTART; /*!< (@ 0x0000000C) Start external flash memory erase operation */ 2617 __OM uint32_t TASKS_DEACTIVATE; /*!< (@ 0x00000010) Deactivate QSPI interface */ 2618 __IM uint32_t RESERVED[59]; 2619 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) QSPI peripheral is ready. This event will be 2620 generated as a response to any QSPI task. */ 2621 __IM uint32_t RESERVED1[127]; 2622 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2623 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2624 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2625 __IM uint32_t RESERVED2[125]; 2626 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable QSPI peripheral and acquire the pins selected 2627 in PSELn registers */ 2628 __IOM QSPI_READ_Type READ; /*!< (@ 0x00000504) Unspecified */ 2629 __IOM QSPI_WRITE_Type WRITE; /*!< (@ 0x00000510) Unspecified */ 2630 __IOM QSPI_ERASE_Type ERASE; /*!< (@ 0x0000051C) Unspecified */ 2631 __IOM QSPI_PSEL_Type PSEL; /*!< (@ 0x00000524) Unspecified */ 2632 __IOM uint32_t XIPOFFSET; /*!< (@ 0x00000540) Address offset into the external memory for Execute 2633 in Place operation. */ 2634 __IOM uint32_t IFCONFIG0; /*!< (@ 0x00000544) Interface configuration. */ 2635 __IM uint32_t RESERVED3[46]; 2636 __IOM uint32_t IFCONFIG1; /*!< (@ 0x00000600) Interface configuration. */ 2637 __IM uint32_t STATUS; /*!< (@ 0x00000604) Status register. */ 2638 __IM uint32_t RESERVED4[3]; 2639 __IOM uint32_t DPMDUR; /*!< (@ 0x00000614) Set the duration required to enter/exit deep 2640 power-down mode (DPM). */ 2641 __IM uint32_t RESERVED5[3]; 2642 __IOM uint32_t ADDRCONF; /*!< (@ 0x00000624) Extended address configuration. */ 2643 __IM uint32_t RESERVED6[3]; 2644 __IOM uint32_t CINSTRCONF; /*!< (@ 0x00000634) Custom instruction configuration register. */ 2645 __IOM uint32_t CINSTRDAT0; /*!< (@ 0x00000638) Custom instruction data register 0. */ 2646 __IOM uint32_t CINSTRDAT1; /*!< (@ 0x0000063C) Custom instruction data register 1. */ 2647 __IOM uint32_t IFTIMING; /*!< (@ 0x00000640) SPI interface timing. */ 2648 } NRF_QSPI_Type; /*!< Size = 1604 (0x644) */ 2649 2650 2651 2652 /* =========================================================================================================================== */ 2653 /* ================ P0 ================ */ 2654 /* =========================================================================================================================== */ 2655 2656 2657 /** 2658 * @brief GPIO Port 1 (P0) 2659 */ 2660 2661 typedef struct { /*!< (@ 0x50000000) P0 Structure */ 2662 __IM uint32_t RESERVED[321]; 2663 __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ 2664 __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ 2665 __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ 2666 __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ 2667 __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ 2668 __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ 2669 __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ 2670 __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that 2671 have met the criteria set in the PIN_CNF[n].SENSE 2672 registers */ 2673 __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour 2674 and LDETECT mode */ 2675 __IM uint32_t RESERVED1[118]; 2676 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection[n]: Configuration of GPIO 2677 pins */ 2678 } NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ 2679 2680 2681 2682 /* =========================================================================================================================== */ 2683 /* ================ CC_HOST_RGF ================ */ 2684 /* =========================================================================================================================== */ 2685 2686 2687 /** 2688 * @brief CRYPTOCELL HOST_RGF interface (CC_HOST_RGF) 2689 */ 2690 2691 typedef struct { /*!< (@ 0x5002A000) CC_HOST_RGF Structure */ 2692 __IM uint32_t RESERVED[1678]; 2693 __IOM uint32_t HOST_CRYPTOKEY_SEL; /*!< (@ 0x00001A38) AES hardware key select */ 2694 __IM uint32_t RESERVED1[4]; 2695 __IOM uint32_t HOST_IOT_KPRTL_LOCK; /*!< (@ 0x00001A4C) This write-once register is the K_PRTL lock register. 2696 When this register is set, K_PRTL can not 2697 be used and a zeroed key will be used instead. 2698 The value of this register is saved in the 2699 CRYPTOCELL AO power domain. */ 2700 __IOM uint32_t HOST_IOT_KDR0; /*!< (@ 0x00001A50) This register holds bits 31:0 of K_DR. The value 2701 of this register is saved in the CRYPTOCELL 2702 AO power domain. Reading from this address 2703 returns the K_DR valid status indicating 2704 if K_DR is successfully retained. */ 2705 __OM uint32_t HOST_IOT_KDR1; /*!< (@ 0x00001A54) This register holds bits 63:32 of K_DR. The value 2706 of this register is saved in the CRYPTOCELL 2707 AO power domain. */ 2708 __OM uint32_t HOST_IOT_KDR2; /*!< (@ 0x00001A58) This register holds bits 95:64 of K_DR. The value 2709 of this register is saved in the CRYPTOCELL 2710 AO power domain. */ 2711 __OM uint32_t HOST_IOT_KDR3; /*!< (@ 0x00001A5C) This register holds bits 127:96 of K_DR. The 2712 value of this register is saved in the CRYPTOCELL 2713 AO power domain. */ 2714 __IOM uint32_t HOST_IOT_LCS; /*!< (@ 0x00001A60) Controls lifecycle state (LCS) for CRYPTOCELL 2715 subsystem */ 2716 } NRF_CC_HOST_RGF_Type; /*!< Size = 6756 (0x1a64) */ 2717 2718 2719 2720 /* =========================================================================================================================== */ 2721 /* ================ CRYPTOCELL ================ */ 2722 /* =========================================================================================================================== */ 2723 2724 2725 /** 2726 * @brief ARM TrustZone CryptoCell register interface (CRYPTOCELL) 2727 */ 2728 2729 typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL Structure */ 2730 __IM uint32_t RESERVED[320]; 2731 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable CRYPTOCELL subsystem */ 2732 } NRF_CRYPTOCELL_Type; /*!< Size = 1284 (0x504) */ 2733 2734 2735 /** @} */ /* End of group Device_Peripheral_peripherals */ 2736 2737 2738 /* =========================================================================================================================== */ 2739 /* ================ Device Specific Peripheral Address Map ================ */ 2740 /* =========================================================================================================================== */ 2741 2742 2743 /** @addtogroup Device_Peripheral_peripheralAddr 2744 * @{ 2745 */ 2746 2747 #define NRF_FICR_BASE 0x10000000UL 2748 #define NRF_UICR_BASE 0x10001000UL 2749 #define NRF_CLOCK_BASE 0x40000000UL 2750 #define NRF_POWER_BASE 0x40000000UL 2751 #define NRF_RADIO_BASE 0x40001000UL 2752 #define NRF_UART0_BASE 0x40002000UL 2753 #define NRF_UARTE0_BASE 0x40002000UL 2754 #define NRF_SPI0_BASE 0x40003000UL 2755 #define NRF_SPIM0_BASE 0x40003000UL 2756 #define NRF_SPIS0_BASE 0x40003000UL 2757 #define NRF_TWI0_BASE 0x40003000UL 2758 #define NRF_TWIM0_BASE 0x40003000UL 2759 #define NRF_TWIS0_BASE 0x40003000UL 2760 #define NRF_SPI1_BASE 0x40004000UL 2761 #define NRF_SPIM1_BASE 0x40004000UL 2762 #define NRF_SPIS1_BASE 0x40004000UL 2763 #define NRF_TWI1_BASE 0x40004000UL 2764 #define NRF_TWIM1_BASE 0x40004000UL 2765 #define NRF_TWIS1_BASE 0x40004000UL 2766 #define NRF_NFCT_BASE 0x40005000UL 2767 #define NRF_GPIOTE_BASE 0x40006000UL 2768 #define NRF_SAADC_BASE 0x40007000UL 2769 #define NRF_TIMER0_BASE 0x40008000UL 2770 #define NRF_TIMER1_BASE 0x40009000UL 2771 #define NRF_TIMER2_BASE 0x4000A000UL 2772 #define NRF_RTC0_BASE 0x4000B000UL 2773 #define NRF_TEMP_BASE 0x4000C000UL 2774 #define NRF_RNG_BASE 0x4000D000UL 2775 #define NRF_ECB_BASE 0x4000E000UL 2776 #define NRF_AAR_BASE 0x4000F000UL 2777 #define NRF_CCM_BASE 0x4000F000UL 2778 #define NRF_WDT_BASE 0x40010000UL 2779 #define NRF_RTC1_BASE 0x40011000UL 2780 #define NRF_QDEC_BASE 0x40012000UL 2781 #define NRF_COMP_BASE 0x40013000UL 2782 #define NRF_LPCOMP_BASE 0x40013000UL 2783 #define NRF_EGU0_BASE 0x40014000UL 2784 #define NRF_SWI0_BASE 0x40014000UL 2785 #define NRF_EGU1_BASE 0x40015000UL 2786 #define NRF_SWI1_BASE 0x40015000UL 2787 #define NRF_EGU2_BASE 0x40016000UL 2788 #define NRF_SWI2_BASE 0x40016000UL 2789 #define NRF_EGU3_BASE 0x40017000UL 2790 #define NRF_SWI3_BASE 0x40017000UL 2791 #define NRF_EGU4_BASE 0x40018000UL 2792 #define NRF_SWI4_BASE 0x40018000UL 2793 #define NRF_EGU5_BASE 0x40019000UL 2794 #define NRF_SWI5_BASE 0x40019000UL 2795 #define NRF_TIMER3_BASE 0x4001A000UL 2796 #define NRF_TIMER4_BASE 0x4001B000UL 2797 #define NRF_PWM0_BASE 0x4001C000UL 2798 #define NRF_PDM_BASE 0x4001D000UL 2799 #define NRF_ACL_BASE 0x4001E000UL 2800 #define NRF_NVMC_BASE 0x4001E000UL 2801 #define NRF_PPI_BASE 0x4001F000UL 2802 #define NRF_MWU_BASE 0x40020000UL 2803 #define NRF_PWM1_BASE 0x40021000UL 2804 #define NRF_PWM2_BASE 0x40022000UL 2805 #define NRF_SPI2_BASE 0x40023000UL 2806 #define NRF_SPIM2_BASE 0x40023000UL 2807 #define NRF_SPIS2_BASE 0x40023000UL 2808 #define NRF_RTC2_BASE 0x40024000UL 2809 #define NRF_I2S_BASE 0x40025000UL 2810 #define NRF_FPU_BASE 0x40026000UL 2811 #define NRF_USBD_BASE 0x40027000UL 2812 #define NRF_UARTE1_BASE 0x40028000UL 2813 #define NRF_QSPI_BASE 0x40029000UL 2814 #define NRF_PWM3_BASE 0x4002D000UL 2815 #define NRF_SPIM3_BASE 0x4002F000UL 2816 #define NRF_P0_BASE 0x50000000UL 2817 #define NRF_P1_BASE 0x50000300UL 2818 #define NRF_CC_HOST_RGF_BASE 0x5002A000UL 2819 #define NRF_CRYPTOCELL_BASE 0x5002A000UL 2820 2821 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 2822 2823 2824 /* =========================================================================================================================== */ 2825 /* ================ Peripheral declaration ================ */ 2826 /* =========================================================================================================================== */ 2827 2828 2829 /** @addtogroup Device_Peripheral_declaration 2830 * @{ 2831 */ 2832 2833 #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) 2834 #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) 2835 #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) 2836 #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) 2837 #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) 2838 #define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) 2839 #define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) 2840 #define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) 2841 #define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) 2842 #define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) 2843 #define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) 2844 #define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) 2845 #define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) 2846 #define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) 2847 #define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE) 2848 #define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) 2849 #define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) 2850 #define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE) 2851 #define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE) 2852 #define NRF_NFCT ((NRF_NFCT_Type*) NRF_NFCT_BASE) 2853 #define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) 2854 #define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) 2855 #define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) 2856 #define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) 2857 #define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) 2858 #define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) 2859 #define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) 2860 #define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) 2861 #define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) 2862 #define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) 2863 #define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) 2864 #define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) 2865 #define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) 2866 #define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) 2867 #define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) 2868 #define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE) 2869 #define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) 2870 #define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) 2871 #define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) 2872 #define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) 2873 #define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE) 2874 #define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) 2875 #define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE) 2876 #define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) 2877 #define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE) 2878 #define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) 2879 #define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE) 2880 #define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) 2881 #define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE) 2882 #define NRF_TIMER4 ((NRF_TIMER_Type*) NRF_TIMER4_BASE) 2883 #define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) 2884 #define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) 2885 #define NRF_ACL ((NRF_ACL_Type*) NRF_ACL_BASE) 2886 #define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) 2887 #define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) 2888 #define NRF_MWU ((NRF_MWU_Type*) NRF_MWU_BASE) 2889 #define NRF_PWM1 ((NRF_PWM_Type*) NRF_PWM1_BASE) 2890 #define NRF_PWM2 ((NRF_PWM_Type*) NRF_PWM2_BASE) 2891 #define NRF_SPI2 ((NRF_SPI_Type*) NRF_SPI2_BASE) 2892 #define NRF_SPIM2 ((NRF_SPIM_Type*) NRF_SPIM2_BASE) 2893 #define NRF_SPIS2 ((NRF_SPIS_Type*) NRF_SPIS2_BASE) 2894 #define NRF_RTC2 ((NRF_RTC_Type*) NRF_RTC2_BASE) 2895 #define NRF_I2S ((NRF_I2S_Type*) NRF_I2S_BASE) 2896 #define NRF_FPU ((NRF_FPU_Type*) NRF_FPU_BASE) 2897 #define NRF_USBD ((NRF_USBD_Type*) NRF_USBD_BASE) 2898 #define NRF_UARTE1 ((NRF_UARTE_Type*) NRF_UARTE1_BASE) 2899 #define NRF_QSPI ((NRF_QSPI_Type*) NRF_QSPI_BASE) 2900 #define NRF_PWM3 ((NRF_PWM_Type*) NRF_PWM3_BASE) 2901 #define NRF_SPIM3 ((NRF_SPIM_Type*) NRF_SPIM3_BASE) 2902 #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) 2903 #define NRF_P1 ((NRF_GPIO_Type*) NRF_P1_BASE) 2904 #define NRF_CC_HOST_RGF ((NRF_CC_HOST_RGF_Type*) NRF_CC_HOST_RGF_BASE) 2905 #define NRF_CRYPTOCELL ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_BASE) 2906 2907 /** @} */ /* End of group Device_Peripheral_declaration */ 2908 2909 2910 /* ========================================= End of section using anonymous unions ========================================= */ 2911 #if defined (__CC_ARM) 2912 #pragma pop 2913 #elif defined (__ICCARM__) 2914 /* leave anonymous unions enabled */ 2915 #elif (__ARMCC_VERSION >= 6010050) 2916 #pragma clang diagnostic pop 2917 #elif defined (__GNUC__) 2918 /* anonymous unions are enabled by default */ 2919 #elif defined (__TMS470__) 2920 /* anonymous unions are enabled by default */ 2921 #elif defined (__TASKING__) 2922 #pragma warning restore 2923 #elif defined (__CSMC__) 2924 /* anonymous unions are enabled by default */ 2925 #endif 2926 2927 2928 #ifdef __cplusplus 2929 } 2930 #endif 2931 2932 #endif /* NRF52840_H */ 2933 2934 2935 /** @} */ /* End of group nrf52840 */ 2936 2937 /** @} */ /* End of group Nordic Semiconductor */ 2938