1; NOTE: This test ensures that for both Big and Little Endian cases a set of 2; NOTE: 4 floats is gathered into a v4f32 register using xxmrghw and xxmrgld 3; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \ 4; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu < %s \ 5; RUN: | FileCheck %s -check-prefix=CHECK-LE 6; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \ 7; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64-unknown-linux-gnu < %s \ 8; RUN: | FileCheck %s -check-prefix=CHECK-BE 9define dso_local <4 x float> @vector_gatherf(float* nocapture readonly %a, 10float* nocapture readonly %b, float* nocapture readonly %c, 11float* nocapture readonly %d) { 12; C code from which this IR test case was generated: 13; vector float test(float *a, float *b, float *c, float *d) { 14; return (vector float) { *a, *b, *c, *d }; 15; } 16; CHECK-LE-LABEL: vector_gatherf: 17; CHECK-LE: # %bb.0: # %entry 18; CHECK-LE-DAG: lfiwzx f[[REG0:[0-9]+]], 0, r6 19; CHECK-LE-DAG: lfiwzx f[[REG1:[0-9]+]], 0, r5 20; CHECK-LE-DAG: lfiwzx f[[REG2:[0-9]+]], 0, r4 21; CHECK-LE-DAG: lfiwzx f[[REG3:[0-9]+]], 0, r3 22; CHECK-LE-DAG: xxmrghw vs[[REG0]], vs[[REG0]], vs[[REG1]] 23; CHECK-LE-DAG: xxmrghw vs[[REG4:[0-9]+]], vs[[REG2]], vs[[REG3]] 24; CHECK-LE-NEXT: xxmrgld v[[REG:[0-9]+]], vs[[REG0]], vs[[REG4]] 25; CHECK-LE-NEXT: blr 26 27; CHECK-BE-LABEL: vector_gatherf: 28; CHECK-BE: # %bb.0: # %entry 29; CHECK-BE-DAG: lfiwzx f[[REG0:[0-9]+]], 0, r3 30; CHECK-BE-DAG: lfiwzx f[[REG1:[0-9]+]], 0, r4 31; CHECK-BE-DAG: lfiwzx f[[REG2:[0-9]+]], 0, r5 32; CHECK-BE-DAG: lfiwzx f[[REG3:[0-9]+]], 0, r6 33; CHECK-BE-DAG: xxmrghw vs[[REG0]], vs[[REG0]], vs[[REG1]] 34; CHECK-BE-DAG: xxmrghw vs[[REG4:[0-9]+]], vs[[REG2]], vs[[REG3]] 35; CHECK-BE-NEXT: xxmrgld v[[REG:[0-9]+]], vs[[REG0]], vs[[REG4]] 36; CHECK-BE-NEXT: blr 37entry: 38 %0 = load float, float* %a, align 4 39 %vecinit = insertelement <4 x float> undef, float %0, i32 0 40 %1 = load float, float* %b, align 4 41 %vecinit1 = insertelement <4 x float> %vecinit, float %1, i32 1 42 %2 = load float, float* %c, align 4 43 %vecinit2 = insertelement <4 x float> %vecinit1, float %2, i32 2 44 %3 = load float, float* %d, align 4 45 %vecinit3 = insertelement <4 x float> %vecinit2, float %3, i32 3 46 ret <4 x float> %vecinit3 47} 48 49