1; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s
2; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-infs-fp-math -enable-no-nans-fp-math -mattr=-vsx | FileCheck -check-prefix=CHECK-FM %s
3; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-infs-fp-math -enable-no-nans-fp-math -mattr=+vsx | FileCheck -check-prefix=CHECK-FM-VSX %s
4target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
5target triple = "powerpc64-unknown-linux-gnu"
6
7define double @zerocmp1(double %a, double %y, double %z) #0 {
8entry:
9  %cmp = fcmp ult double %a, 0.000000e+00
10  %z.y = select i1 %cmp, double %z, double %y
11  ret double %z.y
12
13; CHECK: @zerocmp1
14; CHECK-NOT: fsel
15; CHECK: blr
16
17; CHECK-FM: @zerocmp1
18; CHECK-FM: fsel 1, 1, 2, 3
19; CHECK-FM: blr
20
21; CHECK-FM-VSX: @zerocmp1
22; CHECK-FM-VSX: fsel 1, 1, 2, 3
23; CHECK-FM-VSX: blr
24}
25
26define double @zerocmp2(double %a, double %y, double %z) #0 {
27entry:
28  %cmp = fcmp ogt double %a, 0.000000e+00
29  %y.z = select i1 %cmp, double %y, double %z
30  ret double %y.z
31
32; CHECK: @zerocmp2
33; CHECK-NOT: fsel
34; CHECK: blr
35
36; CHECK-FM: @zerocmp2
37; CHECK-FM: fneg [[REG:[0-9]+]], 1
38; CHECK-FM: fsel 1, [[REG]], 3, 2
39; CHECK-FM: blr
40
41; CHECK-FM-VSX: @zerocmp2
42; CHECK-FM-VSX: xsnegdp [[REG:[0-9]+]], 1
43; CHECK-FM-VSX: fsel 1, [[REG]], 3, 2
44; CHECK-FM-VSX: blr
45}
46
47define double @zerocmp3(double %a, double %y, double %z) #0 {
48entry:
49  %cmp = fcmp oeq double %a, 0.000000e+00
50  %y.z = select i1 %cmp, double %y, double %z
51  ret double %y.z
52
53; CHECK: @zerocmp3
54; CHECK-NOT: fsel
55; CHECK: blr
56
57; CHECK-FM: @zerocmp3
58; CHECK-FM: fsel [[REG:[0-9]+]], 1, 2, 3
59; CHECK-FM: fneg [[REG2:[0-9]+]], 1
60; CHECK-FM: fsel 1, [[REG2]], [[REG]], 3
61; CHECK-FM: blr
62
63; CHECK-FM-VSX: @zerocmp3
64; CHECK-FM-VSX: xsnegdp [[REG2:[0-9]+]], 1
65; CHECK-FM-VSX: fsel [[REG:[0-9]+]], 1, 2, 3
66; CHECK-FM-VSX: fsel 1, [[REG2]], [[REG]], 3
67; CHECK-FM-VSX: blr
68}
69
70define double @min1(double %a, double %b) #0 {
71entry:
72  %cmp = fcmp ole double %a, %b
73  %cond = select i1 %cmp, double %a, double %b
74  ret double %cond
75
76; CHECK: @min1
77; CHECK-NOT: fsel
78; CHECK: blr
79
80; CHECK-FM: @min1
81; CHECK-FM: fsub [[REG:[0-9]+]], 2, 1
82; CHECK-FM: fsel 1, [[REG]], 1, 2
83; CHECK-FM: blr
84
85; CHECK-FM-VSX: @min1
86; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 2, 1
87; CHECK-FM-VSX: fsel 1, [[REG]], 1, 2
88; CHECK-FM-VSX: blr
89}
90
91define double @max1(double %a, double %b) #0 {
92entry:
93  %cmp = fcmp oge double %a, %b
94  %cond = select i1 %cmp, double %a, double %b
95  ret double %cond
96
97; CHECK: @max1
98; CHECK-NOT: fsel
99; CHECK: blr
100
101; CHECK-FM: @max1
102; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2
103; CHECK-FM: fsel 1, [[REG]], 1, 2
104; CHECK-FM: blr
105
106; CHECK-FM-VSX: @max1
107; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2
108; CHECK-FM-VSX: fsel 1, [[REG]], 1, 2
109; CHECK-FM-VSX: blr
110}
111
112define double @cmp1(double %a, double %b, double %y, double %z) #0 {
113entry:
114  %cmp = fcmp ult double %a, %b
115  %z.y = select i1 %cmp, double %z, double %y
116  ret double %z.y
117
118; CHECK: @cmp1
119; CHECK-NOT: fsel
120; CHECK: blr
121
122; CHECK-FM: @cmp1
123; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2
124; CHECK-FM: fsel 1, [[REG]], 3, 4
125; CHECK-FM: blr
126
127; CHECK-FM-VSX: @cmp1
128; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2
129; CHECK-FM-VSX: fsel 1, [[REG]], 3, 4
130; CHECK-FM-VSX: blr
131}
132
133define double @cmp2(double %a, double %b, double %y, double %z) #0 {
134entry:
135  %cmp = fcmp ogt double %a, %b
136  %y.z = select i1 %cmp, double %y, double %z
137  ret double %y.z
138
139; CHECK: @cmp2
140; CHECK-NOT: fsel
141; CHECK: blr
142
143; CHECK-FM: @cmp2
144; CHECK-FM: fsub [[REG:[0-9]+]], 2, 1
145; CHECK-FM: fsel 1, [[REG]], 4, 3
146; CHECK-FM: blr
147
148; CHECK-FM-VSX: @cmp2
149; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 2, 1
150; CHECK-FM-VSX: fsel 1, [[REG]], 4, 3
151; CHECK-FM-VSX: blr
152}
153
154define double @cmp3(double %a, double %b, double %y, double %z) #0 {
155entry:
156  %cmp = fcmp oeq double %a, %b
157  %y.z = select i1 %cmp, double %y, double %z
158  ret double %y.z
159
160; CHECK: @cmp3
161; CHECK-NOT: fsel
162; CHECK: blr
163
164; CHECK-FM: @cmp3
165; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2
166; CHECK-FM: fsel [[REG2:[0-9]+]], [[REG]], 3, 4
167; CHECK-FM: fneg [[REG3:[0-9]+]], [[REG]]
168; CHECK-FM: fsel 1, [[REG3]], [[REG2]], 4
169; CHECK-FM: blr
170
171; CHECK-FM-VSX: @cmp3
172; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2
173; CHECK-FM-VSX: xsnegdp [[REG3:[0-9]+]], [[REG]]
174; CHECK-FM-VSX: fsel [[REG2:[0-9]+]], [[REG]], 3, 4
175; CHECK-FM-VSX: fsel 1, [[REG3]], [[REG2]], 4
176; CHECK-FM-VSX: blr
177}
178
179attributes #0 = { nounwind readnone }
180
181