1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
4; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
7; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
8@glob = local_unnamed_addr global i64 0, align 8
9
10define signext i32 @test_igesll(i64 %a, i64 %b) {
11; CHECK-LABEL: test_igesll:
12; CHECK:       # %bb.0: # %entry
13; CHECK-NEXT:    sradi r5, r3, 63
14; CHECK-NEXT:    rldicl r6, r4, 1, 63
15; CHECK-NEXT:    subfc r3, r4, r3
16; CHECK-NEXT:    adde r3, r5, r6
17; CHECK-NEXT:    blr
18; CHECK-BE-LABEL: test_igesll:
19; CHECK-BE:       # %bb.0: # %entry
20; CHECK-BE-NEXT:    sradi r5, r3, 63
21; CHECK-BE-NEXT:    rldicl r6, r4, 1, 63
22; CHECK-BE-NEXT:    subfc r3, r4, r3
23; CHECK-BE-NEXT:    adde r3, r5, r6
24; CHECK-BE-NEXT:    blr
25;
26; CHECK-LE-LABEL: test_igesll:
27; CHECK-LE:       # %bb.0: # %entry
28; CHECK-LE-NEXT:    sradi r5, r3, 63
29; CHECK-LE-NEXT:    rldicl r6, r4, 1, 63
30; CHECK-LE-NEXT:    subfc r3, r4, r3
31; CHECK-LE-NEXT:    adde r3, r5, r6
32; CHECK-LE-NEXT:    blr
33entry:
34  %cmp = icmp sge i64 %a, %b
35  %conv = zext i1 %cmp to i32
36  ret i32 %conv
37}
38
39define signext i32 @test_igesll_sext(i64 %a, i64 %b) {
40; CHECK-LABEL: test_igesll_sext:
41; CHECK:       # %bb.0: # %entry
42; CHECK-NEXT:    sradi r5, r3, 63
43; CHECK-NEXT:    rldicl r6, r4, 1, 63
44; CHECK-NEXT:    subfc r3, r4, r3
45; CHECK-NEXT:    adde r3, r5, r6
46; CHECK-NEXT:    neg r3, r3
47; CHECK-NEXT:    blr
48; CHECK-BE-LABEL: test_igesll_sext:
49; CHECK-BE:       # %bb.0: # %entry
50; CHECK-BE-NEXT:    sradi r5, r3, 63
51; CHECK-BE-NEXT:    rldicl r6, r4, 1, 63
52; CHECK-BE-NEXT:    subfc r3, r4, r3
53; CHECK-BE-NEXT:    adde r3, r5, r6
54; CHECK-BE-NEXT:    neg r3, r3
55; CHECK-BE-NEXT:    blr
56;
57; CHECK-LE-LABEL: test_igesll_sext:
58; CHECK-LE:       # %bb.0: # %entry
59; CHECK-LE-NEXT:    sradi r5, r3, 63
60; CHECK-LE-NEXT:    rldicl r6, r4, 1, 63
61; CHECK-LE-NEXT:    subfc r3, r4, r3
62; CHECK-LE-NEXT:    adde r3, r5, r6
63; CHECK-LE-NEXT:    neg r3, r3
64; CHECK-LE-NEXT:    blr
65entry:
66  %cmp = icmp sge i64 %a, %b
67  %sub = sext i1 %cmp to i32
68  ret i32 %sub
69}
70
71define signext i32 @test_igesll_z(i64 %a) {
72; CHECK-LABEL: test_igesll_z:
73; CHECK:       # %bb.0: # %entry
74; CHECK-NEXT:    not r3, r3
75; CHECK-NEXT:    rldicl r3, r3, 1, 63
76; CHECK-NEXT:    blr
77; CHECK-BE-LABEL: test_igesll_z:
78; CHECK-BE:       # %bb.0: # %entry
79; CHECK-BE-NEXT:    not r3, r3
80; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
81; CHECK-BE-NEXT:    blr
82;
83; CHECK-LE-LABEL: test_igesll_z:
84; CHECK-LE:       # %bb.0: # %entry
85; CHECK-LE-NEXT:    not r3, r3
86; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
87; CHECK-LE-NEXT:    blr
88entry:
89  %cmp = icmp sgt i64 %a, -1
90  %conv = zext i1 %cmp to i32
91  ret i32 %conv
92}
93
94define signext i32 @test_igesll_sext_z(i64 %a) {
95; CHECK-LABEL: test_igesll_sext_z:
96; CHECK:       # %bb.0: # %entry
97; CHECK-NEXT:    sradi r3, r3, 63
98; CHECK-NEXT:    not r3, r3
99; CHECK-NEXT:    blr
100; CHECK-BE-LABEL: test_igesll_sext_z:
101; CHECK-BE:       # %bb.0: # %entry
102; CHECK-BE-NEXT:    not r3, r3
103; CHECK-BE-NEXT:    sradi r3, r3, 63
104; CHECK-BE-NEXT:    blr
105;
106; CHECK-LE-LABEL: test_igesll_sext_z:
107; CHECK-LE:       # %bb.0: # %entry
108; CHECK-LE-NEXT:    not r3, r3
109; CHECK-LE-NEXT:    sradi r3, r3, 63
110; CHECK-LE-NEXT:    blr
111entry:
112  %cmp = icmp sgt i64 %a, -1
113  %sub = sext i1 %cmp to i32
114  ret i32 %sub
115}
116
117define void @test_igesll_store(i64 %a, i64 %b) {
118; CHECK-LABEL: test_igesll_store:
119; CHECK:       # %bb.0: # %entry
120; CHECK-NEXT:    sradi r6, r3, 63
121; CHECK-NEXT:    addis r5, r2, glob@toc@ha
122; CHECK-NEXT:    subfc r3, r4, r3
123; CHECK-NEXT:    rldicl r3, r4, 1, 63
124; CHECK-NEXT:    adde r3, r6, r3
125; CHECK-NEXT:    std r3, glob@toc@l(r5)
126; CHECK-NEXT:    blr
127; CHECK-BE-LABEL: test_igesll_store:
128; CHECK-BE:       # %bb.0: # %entry
129; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
130; CHECK-BE-NEXT:    sradi r6, r3, 63
131; CHECK-BE-NEXT:    ld r5, .LC0@toc@l(r5)
132; CHECK-BE-NEXT:    subfc r3, r4, r3
133; CHECK-BE-NEXT:    rldicl r3, r4, 1, 63
134; CHECK-BE-NEXT:    adde r3, r6, r3
135; CHECK-BE-NEXT:    std r3, 0(r5)
136; CHECK-BE-NEXT:    blr
137;
138; CHECK-LE-LABEL: test_igesll_store:
139; CHECK-LE:       # %bb.0: # %entry
140; CHECK-LE-NEXT:    sradi r6, r3, 63
141; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
142; CHECK-LE-NEXT:    subfc r3, r4, r3
143; CHECK-LE-NEXT:    rldicl r3, r4, 1, 63
144; CHECK-LE-NEXT:    adde r3, r6, r3
145; CHECK-LE-NEXT:    std r3, glob@toc@l(r5)
146; CHECK-LE-NEXT:    blr
147entry:
148  %cmp = icmp sge i64 %a, %b
149  %conv1 = zext i1 %cmp to i64
150  store i64 %conv1, i64* @glob, align 8
151  ret void
152}
153
154define void @test_igesll_sext_store(i64 %a, i64 %b) {
155; CHECK-LABEL: test_igesll_sext_store:
156; CHECK:       # %bb.0: # %entry
157; CHECK-NEXT:    sradi r6, r3, 63
158; CHECK-NEXT:    addis r5, r2, glob@toc@ha
159; CHECK-NEXT:    subfc r3, r4, r3
160; CHECK-NEXT:    rldicl r3, r4, 1, 63
161; CHECK-NEXT:    adde r3, r6, r3
162; CHECK-NEXT:    neg r3, r3
163; CHECK-NEXT:    std r3, glob@toc@l(r5)
164; CHECK-NEXT:    blr
165; CHECK-BE-LABEL: test_igesll_sext_store:
166; CHECK-BE:       # %bb.0: # %entry
167; CHECK-BE-NEXT:    sradi r6, r3, 63
168; CHECK-BE-NEXT:    addis r5, r2, .LC0@toc@ha
169; CHECK-BE-NEXT:    subfc r3, r4, r3
170; CHECK-BE-NEXT:    rldicl r3, r4, 1, 63
171; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r5)
172; CHECK-BE-NEXT:    adde r3, r6, r3
173; CHECK-BE-NEXT:    neg r3, r3
174; CHECK-BE-NEXT:    std r3, 0(r4)
175; CHECK-BE-NEXT:    blr
176;
177; CHECK-LE-LABEL: test_igesll_sext_store:
178; CHECK-LE:       # %bb.0: # %entry
179; CHECK-LE-NEXT:    sradi r6, r3, 63
180; CHECK-LE-NEXT:    addis r5, r2, glob@toc@ha
181; CHECK-LE-NEXT:    subfc r3, r4, r3
182; CHECK-LE-NEXT:    rldicl r3, r4, 1, 63
183; CHECK-LE-NEXT:    adde r3, r6, r3
184; CHECK-LE-NEXT:    neg r3, r3
185; CHECK-LE-NEXT:    std r3, glob@toc@l(r5)
186; CHECK-LE-NEXT:    blr
187entry:
188  %cmp = icmp sge i64 %a, %b
189  %conv1 = sext i1 %cmp to i64
190  store i64 %conv1, i64* @glob, align 8
191  ret void
192}
193
194define void @test_igesll_z_store(i64 %a) {
195; CHECK-LABEL: test_igesll_z_store:
196; CHECK:       # %bb.0: # %entry
197; CHECK-NEXT:    not r3, r3
198; CHECK-NEXT:    addis r4, r2, glob@toc@ha
199; CHECK-NEXT:    rldicl r3, r3, 1, 63
200; CHECK-NEXT:    std r3, glob@toc@l(r4)
201; CHECK-NEXT:    blr
202; CHECK-BE-LABEL: test_igesll_z_store:
203; CHECK-BE:       # %bb.0: # %entry
204; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
205; CHECK-BE-NEXT:    not r3, r3
206; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
207; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
208; CHECK-BE-NEXT:    std r3, 0(r4)
209; CHECK-BE-NEXT:    blr
210;
211; CHECK-LE-LABEL: test_igesll_z_store:
212; CHECK-LE:       # %bb.0: # %entry
213; CHECK-LE-NEXT:    not r3, r3
214; CHECK-LE-NEXT:    addis r4, r2, glob@toc@ha
215; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
216; CHECK-LE-NEXT:    std r3, glob@toc@l(r4)
217; CHECK-LE-NEXT:    blr
218entry:
219  %cmp = icmp sgt i64 %a, -1
220  %conv1 = zext i1 %cmp to i64
221  store i64 %conv1, i64* @glob, align 8
222  ret void
223}
224
225define void @test_igesll_sext_z_store(i64 %a) {
226; CHECK-LABEL: test_igesll_sext_z_store:
227; CHECK:       # %bb.0: # %entry
228; CHECK-NEXT:    not r3, r3
229; CHECK-NEXT:    addis r4, r2, glob@toc@ha
230; CHECK-NEXT:    sradi r3, r3, 63
231; CHECK-NEXT:    std r3, glob@toc@l(r4)
232; CHECK-NEXT:    blr
233; CHECK-BE-LABEL: test_igesll_sext_z_store:
234; CHECK-BE:       # %bb.0: # %entry
235; CHECK-BE-NEXT:    addis r4, r2, .LC0@toc@ha
236; CHECK-BE-NEXT:    not r3, r3
237; CHECK-BE-NEXT:    ld r4, .LC0@toc@l(r4)
238; CHECK-BE-NEXT:    sradi r3, r3, 63
239; CHECK-BE-NEXT:    std r3, 0(r4)
240; CHECK-BE-NEXT:    blr
241;
242; CHECK-LE-LABEL: test_igesll_sext_z_store:
243; CHECK-LE:       # %bb.0: # %entry
244; CHECK-LE-NEXT:    not r3, r3
245; CHECK-LE-NEXT:    addis r4, r2, glob@toc@ha
246; CHECK-LE-NEXT:    sradi r3, r3, 63
247; CHECK-LE-NEXT:    std r3, glob@toc@l(r4)
248; CHECK-LE-NEXT:    blr
249entry:
250  %cmp = icmp sgt i64 %a, -1
251  %conv1 = sext i1 %cmp to i64
252  store i64 %conv1, i64* @glob, align 8
253  ret void
254}
255