1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown | FileCheck %s
3
4; First, check the generic pattern for any 2 vector constants. Then, check special cases where
5; the constants are all off-by-one. Finally, check the extra special cases where the constants
6; include 0 or -1.
7; Each minimal select test is repeated with a more typical pattern that includes a compare to
8; generate the condition value.
9
10define <4 x i32> @sel_C1_or_C2_vec(<4 x i1> %cond) {
11; CHECK-LABEL: sel_C1_or_C2_vec:
12; CHECK:       # %bb.0:
13; CHECK-NEXT:    vspltisw 3, -16
14; CHECK-NEXT:    vspltisw 4, 15
15; CHECK-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
16; CHECK-NEXT:    addis 4, 2, .LCPI0_1@toc@ha
17; CHECK-NEXT:    addi 3, 3, .LCPI0_0@toc@l
18; CHECK-NEXT:    addi 4, 4, .LCPI0_1@toc@l
19; CHECK-NEXT:    vsubuwm 3, 4, 3
20; CHECK-NEXT:    lvx 4, 0, 4
21; CHECK-NEXT:    vslw 2, 2, 3
22; CHECK-NEXT:    vsraw 2, 2, 3
23; CHECK-NEXT:    lvx 3, 0, 3
24; CHECK-NEXT:    xxsel 34, 36, 35, 34
25; CHECK-NEXT:    blr
26  %add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
27  ret <4 x i32> %add
28}
29
30define <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) {
31; CHECK-LABEL: cmp_sel_C1_or_C2_vec:
32; CHECK:       # %bb.0:
33; CHECK-NEXT:    vcmpequw 2, 2, 3
34; CHECK-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
35; CHECK-NEXT:    addis 4, 2, .LCPI1_1@toc@ha
36; CHECK-NEXT:    addi 3, 3, .LCPI1_0@toc@l
37; CHECK-NEXT:    addi 4, 4, .LCPI1_1@toc@l
38; CHECK-NEXT:    lvx 3, 0, 3
39; CHECK-NEXT:    lvx 4, 0, 4
40; CHECK-NEXT:    xxsel 34, 36, 35, 34
41; CHECK-NEXT:    blr
42  %cond = icmp eq <4 x i32> %x, %y
43  %add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
44  ret <4 x i32> %add
45}
46
47define <4 x i32> @sel_Cplus1_or_C_vec(<4 x i1> %cond) {
48; CHECK-LABEL: sel_Cplus1_or_C_vec:
49; CHECK:       # %bb.0:
50; CHECK-NEXT:    vspltisw 3, 1
51; CHECK-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
52; CHECK-NEXT:    addi 3, 3, .LCPI2_0@toc@l
53; CHECK-NEXT:    xxland 34, 34, 35
54; CHECK-NEXT:    lvx 3, 0, 3
55; CHECK-NEXT:    vadduwm 2, 2, 3
56; CHECK-NEXT:    blr
57  %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
58  ret <4 x i32> %add
59}
60
61define <4 x i32> @cmp_sel_Cplus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {
62; CHECK-LABEL: cmp_sel_Cplus1_or_C_vec:
63; CHECK:       # %bb.0:
64; CHECK-NEXT:    vcmpequw 2, 2, 3
65; CHECK-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
66; CHECK-NEXT:    addi 3, 3, .LCPI3_0@toc@l
67; CHECK-NEXT:    lvx 3, 0, 3
68; CHECK-NEXT:    vsubuwm 2, 3, 2
69; CHECK-NEXT:    blr
70  %cond = icmp eq <4 x i32> %x, %y
71  %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1>
72  ret <4 x i32> %add
73}
74
75define <4 x i32> @sel_Cminus1_or_C_vec(<4 x i1> %cond) {
76; CHECK-LABEL: sel_Cminus1_or_C_vec:
77; CHECK:       # %bb.0:
78; CHECK-NEXT:    vspltisw 3, -16
79; CHECK-NEXT:    vspltisw 4, 15
80; CHECK-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
81; CHECK-NEXT:    addi 3, 3, .LCPI4_0@toc@l
82; CHECK-NEXT:    vsubuwm 3, 4, 3
83; CHECK-NEXT:    vslw 2, 2, 3
84; CHECK-NEXT:    vsraw 2, 2, 3
85; CHECK-NEXT:    lvx 3, 0, 3
86; CHECK-NEXT:    vadduwm 2, 2, 3
87; CHECK-NEXT:    blr
88  %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>
89  ret <4 x i32> %add
90}
91
92define <4 x i32> @cmp_sel_Cminus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) {
93; CHECK-LABEL: cmp_sel_Cminus1_or_C_vec:
94; CHECK:       # %bb.0:
95; CHECK-NEXT:    vcmpequw 2, 2, 3
96; CHECK-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
97; CHECK-NEXT:    addi 3, 3, .LCPI5_0@toc@l
98; CHECK-NEXT:    lvx 3, 0, 3
99; CHECK-NEXT:    vadduwm 2, 2, 3
100; CHECK-NEXT:    blr
101  %cond = icmp eq <4 x i32> %x, %y
102  %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1>
103  ret <4 x i32> %add
104}
105
106define <4 x i32> @sel_minus1_or_0_vec(<4 x i1> %cond) {
107; CHECK-LABEL: sel_minus1_or_0_vec:
108; CHECK:       # %bb.0:
109; CHECK-NEXT:    vspltisw 3, -16
110; CHECK-NEXT:    vspltisw 4, 15
111; CHECK-NEXT:    vsubuwm 3, 4, 3
112; CHECK-NEXT:    vslw 2, 2, 3
113; CHECK-NEXT:    vsraw 2, 2, 3
114; CHECK-NEXT:    blr
115  %add = select <4 x i1> %cond, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
116  ret <4 x i32> %add
117}
118
119define <4 x i32> @cmp_sel_minus1_or_0_vec(<4 x i32> %x, <4 x i32> %y) {
120; CHECK-LABEL: cmp_sel_minus1_or_0_vec:
121; CHECK:       # %bb.0:
122; CHECK-NEXT:    vcmpequw 2, 2, 3
123; CHECK-NEXT:    blr
124  %cond = icmp eq <4 x i32> %x, %y
125  %add = select <4 x i1> %cond, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
126  ret <4 x i32> %add
127}
128
129define <4 x i32> @sel_0_or_minus1_vec(<4 x i1> %cond) {
130; CHECK-LABEL: sel_0_or_minus1_vec:
131; CHECK:       # %bb.0:
132; CHECK-NEXT:    vspltisw 3, 1
133; CHECK-NEXT:    xxland 34, 34, 35
134; CHECK-NEXT:    xxleqv 35, 35, 35
135; CHECK-NEXT:    vadduwm 2, 2, 3
136; CHECK-NEXT:    blr
137  %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
138  ret <4 x i32> %add
139}
140
141define <4 x i32> @cmp_sel_0_or_minus1_vec(<4 x i32> %x, <4 x i32> %y) {
142; CHECK-LABEL: cmp_sel_0_or_minus1_vec:
143; CHECK:       # %bb.0:
144; CHECK-NEXT:    vcmpequw 2, 2, 3
145; CHECK-NEXT:    xxlnor 34, 34, 34
146; CHECK-NEXT:    blr
147  %cond = icmp eq <4 x i32> %x, %y
148  %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
149  ret <4 x i32> %add
150}
151
152define <4 x i32> @sel_1_or_0_vec(<4 x i1> %cond) {
153; CHECK-LABEL: sel_1_or_0_vec:
154; CHECK:       # %bb.0:
155; CHECK-NEXT:    vspltisw 3, 1
156; CHECK-NEXT:    xxland 34, 34, 35
157; CHECK-NEXT:    blr
158  %add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
159  ret <4 x i32> %add
160}
161
162define <4 x i32> @cmp_sel_1_or_0_vec(<4 x i32> %x, <4 x i32> %y) {
163; CHECK-LABEL: cmp_sel_1_or_0_vec:
164; CHECK:       # %bb.0:
165; CHECK-NEXT:    vcmpequw 2, 2, 3
166; CHECK-NEXT:    vspltisw 3, 1
167; CHECK-NEXT:    xxland 34, 34, 35
168; CHECK-NEXT:    blr
169  %cond = icmp eq <4 x i32> %x, %y
170  %add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
171  ret <4 x i32> %add
172}
173
174define <4 x i32> @sel_0_or_1_vec(<4 x i1> %cond) {
175; CHECK-LABEL: sel_0_or_1_vec:
176; CHECK:       # %bb.0:
177; CHECK-NEXT:    vspltisw 3, 1
178; CHECK-NEXT:    xxlandc 34, 35, 34
179; CHECK-NEXT:    blr
180  %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
181  ret <4 x i32> %add
182}
183
184define <4 x i32> @cmp_sel_0_or_1_vec(<4 x i32> %x, <4 x i32> %y) {
185; CHECK-LABEL: cmp_sel_0_or_1_vec:
186; CHECK:       # %bb.0:
187; CHECK-NEXT:    vcmpequw 2, 2, 3
188; CHECK-NEXT:    vspltisw 3, 1
189; CHECK-NEXT:    xxlnor 0, 34, 34
190; CHECK-NEXT:    xxland 34, 0, 35
191; CHECK-NEXT:    blr
192  %cond = icmp eq <4 x i32> %x, %y
193  %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
194  ret <4 x i32> %add
195}
196
197