1; Test LOCFHR and LOCHHI.
2; See comments in asm-18.ll about testing high-word operations.
3;
4; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu -mcpu=z13 \
5; RUN:   -no-integrated-as | FileCheck %s
6;
7; Run the test again to make sure it still works the same even
8; in the presence of the select instructions.
9; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu -mcpu=z15 \
10; RUN:   -no-integrated-as | FileCheck %s
11
12define void @f1(i32 %limit) {
13; CHECK-LABEL: f1:
14; CHECK-DAG: stepa [[REG1:%r[0-5]]]
15; CHECK-DAG: stepb [[REG2:%r[0-5]]]
16; CHECK-DAG: clfi %r2, 42
17; CHECK: locfhrhe [[REG1]], [[REG2]]
18; CHECK: stepc [[REG1]]
19; CHECK: br %r14
20  %a = call i32 asm sideeffect "stepa $0", "=h"()
21  %b = call i32 asm sideeffect "stepb $0", "=h"()
22  %cond = icmp ult i32 %limit, 42
23  %res = select i1 %cond, i32 %a, i32 %b
24  call void asm sideeffect "stepc $0", "h"(i32 %res)
25  call void asm sideeffect "use $0", "h"(i32 %b)
26  ret void
27}
28
29define void @f2(i32 %limit) {
30; CHECK-LABEL: f2:
31; CHECK-DAG: stepa [[REG1:%r[0-5]]]
32; CHECK-DAG: stepb [[REG2:%r[0-5]]]
33; CHECK-DAG: clijl %r2, 42, [[LABEL:.LBB[0-9_]+]]
34; CHECK: risbhg [[REG1]], [[REG2]], 0, 159, 32
35; CHECK: [[LABEL]]
36; CHECK: stepc [[REG1]]
37; CHECK: br %r14
38  %dummy = call i32 asm sideeffect "dummy $0", "=h"()
39  %a = call i32 asm sideeffect "stepa $0", "=h"()
40  %b = call i32 asm sideeffect "stepb $0", "=r"()
41  %cond = icmp ult i32 %limit, 42
42  %res = select i1 %cond, i32 %a, i32 %b
43  call void asm sideeffect "stepc $0", "h"(i32 %res)
44  call void asm sideeffect "dummy $0", "h"(i32 %dummy)
45  call void asm sideeffect "use $0", "r"(i32 %b)
46  ret void
47}
48
49define void @f3(i32 %limit) {
50; CHECK-LABEL: f3:
51; CHECK-DAG: stepa [[REG1:%r[0-5]]]
52; CHECK-DAG: stepb [[REG2:%r[0-5]]]
53; CHECK-DAG: clijhe %r2, 42, [[LABEL:.LBB[0-9_]+]]
54; CHECK: risbhg [[REG2]], [[REG1]], 0, 159, 32
55; CHECK: [[LABEL]]
56; CHECK: stepc [[REG2]]
57; CHECK: br %r14
58  %dummy = call i32 asm sideeffect "dummy $0", "=h"()
59  %a = call i32 asm sideeffect "stepa $0", "=r"()
60  %b = call i32 asm sideeffect "stepb $0", "=h"()
61  %cond = icmp ult i32 %limit, 42
62  %res = select i1 %cond, i32 %a, i32 %b
63  call void asm sideeffect "stepc $0", "h"(i32 %res)
64  call void asm sideeffect "dummy $0", "h"(i32 %dummy)
65  call void asm sideeffect "use $0", "r"(i32 %a)
66  ret void
67}
68
69define void @f4(i32 %limit) {
70; CHECK-LABEL: f4:
71; CHECK-DAG: stepa [[REG1:%r[0-5]]]
72; CHECK-DAG: stepb [[REG2:%r[0-5]]]
73; CHECK-DAG: clijl %r2, 42, [[LABEL:.LBB[0-9_]+]]
74; CHECK: risblg [[REG1]], [[REG2]], 0, 159, 32
75; CHECK: [[LABEL]]
76; CHECK: stepc [[REG1]]
77; CHECK: br %r14
78  %dummy = call i32 asm sideeffect "dummy $0", "=h"()
79  %a = call i32 asm sideeffect "stepa $0", "=r"()
80  %b = call i32 asm sideeffect "stepb $0", "=h"()
81  %cond = icmp ult i32 %limit, 42
82  %res = select i1 %cond, i32 %a, i32 %b
83  call void asm sideeffect "stepc $0", "r"(i32 %res)
84  call void asm sideeffect "dummy $0", "h"(i32 %dummy)
85  call void asm sideeffect "use $0", "h"(i32 %b)
86  ret void
87}
88
89define void @f5(i32 %limit) {
90; CHECK-LABEL: f5:
91; CHECK-DAG: stepa [[REG2:%r[0-5]]]
92; CHECK-DAG: stepb [[REG1:%r[0-5]]]
93; CHECK-DAG: clijhe %r2, 42, [[LABEL:.LBB[0-9_]+]]
94; CHECK: risblg [[REG1]], [[REG2]], 0, 159, 32
95; CHECK: [[LABEL]]
96; CHECK: stepc [[REG1]]
97; CHECK: br %r14
98  %dummy = call i32 asm sideeffect "dummy $0", "=h"()
99  %a = call i32 asm sideeffect "stepa $0", "=h"()
100  %b = call i32 asm sideeffect "stepb $0", "=r"()
101  %cond = icmp ult i32 %limit, 42
102  %res = select i1 %cond, i32 %a, i32 %b
103  call void asm sideeffect "stepc $0", "r"(i32 %res)
104  call void asm sideeffect "dummy $0", "h"(i32 %dummy)
105  ret void
106}
107
108; Check that we also get LOCFHR as a result of early if-conversion.
109define void @f6(i32 %limit) {
110; CHECK-LABEL: f6:
111; CHECK-DAG: stepa [[REG1:%r[0-5]]]
112; CHECK-DAG: stepb [[REG2:%r[0-5]]]
113; CHECK-DAG: clfi %r2, 41
114; CHECK: locfhrh [[REG1]], [[REG2]]
115; CHECK: stepc [[REG1]]
116; CHECK: br %r14
117entry:
118  %a = call i32 asm sideeffect "stepa $0", "=h"()
119  %b = call i32 asm sideeffect "stepb $0", "=h"()
120  %cond = icmp ult i32 %limit, 42
121  br i1 %cond, label %if.then, label %return
122
123if.then:
124  br label %return
125
126return:
127  %res = phi i32 [ %a, %if.then ], [ %b, %entry ]
128  call void asm sideeffect "stepc $0", "h"(i32 %res)
129  call void asm sideeffect "use $0", "h"(i32 %b)
130  ret void
131}
132
133; Check that inverting the condition works as well.
134define void @f7(i32 %limit) {
135; CHECK-LABEL: f7:
136; CHECK-DAG: stepa [[REG1:%r[0-5]]]
137; CHECK-DAG: stepb [[REG2:%r[0-5]]]
138; CHECK-DAG: clfi %r2, 41
139; CHECK: locfhrle [[REG1]], [[REG2]]
140; CHECK: stepc [[REG1]]
141; CHECK: br %r14
142entry:
143  %a = call i32 asm sideeffect "stepa $0", "=h"()
144  %b = call i32 asm sideeffect "stepb $0", "=h"()
145  %cond = icmp ult i32 %limit, 42
146  br i1 %cond, label %if.then, label %return
147
148if.then:
149  br label %return
150
151return:
152  %res = phi i32 [ %b, %if.then ], [ %a, %entry ]
153  call void asm sideeffect "stepc $0", "h"(i32 %res)
154  call void asm sideeffect "use $0", "h"(i32 %b)
155  ret void
156}
157
158define void @f8(i32 %limit) {
159; CHECK-LABEL: f8:
160; CHECK: clfi %r2, 42
161; CHECK: lochhil [[REG:%r[0-5]]], 32767
162; CHECK: stepa [[REG]]
163; CHECK: br %r14
164  %cond = icmp ult i32 %limit, 42
165  %res = select i1 %cond, i32 32767, i32 0
166  call void asm sideeffect "stepa $0", "h"(i32 %res)
167  ret void
168}
169
170define void @f9(i32 %limit) {
171; CHECK-LABEL: f9:
172; CHECK: clfi %r2, 42
173; CHECK: lochhil [[REG:%r[0-5]]], -32768
174; CHECK: stepa [[REG]]
175; CHECK: br %r14
176  %cond = icmp ult i32 %limit, 42
177  %res = select i1 %cond, i32 -32768, i32 0
178  call void asm sideeffect "stepa $0", "h"(i32 %res)
179  ret void
180}
181
182; Check that we also get LOCHHI as a result of early if-conversion.
183define void @f10(i32 %limit) {
184; CHECK-LABEL: f10:
185; CHECK-DAG: stepa [[REG:%r[0-5]]]
186; CHECK-DAG: clfi %r2, 41
187; CHECK: lochhile [[REG]], 123
188; CHECK: stepb [[REG]]
189; CHECK: br %r14
190entry:
191  %a = call i32 asm sideeffect "stepa $0", "=h"()
192  %cond = icmp ult i32 %limit, 42
193  br i1 %cond, label %if.then, label %return
194
195if.then:
196  br label %return
197
198return:
199  %res = phi i32 [ 123, %if.then ], [ %a, %entry ]
200  call void asm sideeffect "stepb $0", "h"(i32 %res)
201  ret void
202}
203
204; Check that inverting the condition works as well.
205define void @f11(i32 %limit) {
206; CHECK-LABEL: f11:
207; CHECK-DAG: stepa [[REG:%r[0-5]]]
208; CHECK-DAG: clfi %r2, 41
209; CHECK: lochhih [[REG]], 123
210; CHECK: stepb [[REG]]
211; CHECK: br %r14
212entry:
213  %a = call i32 asm sideeffect "stepa $0", "=h"()
214  %cond = icmp ult i32 %limit, 42
215  br i1 %cond, label %if.then, label %return
216
217if.then:
218  br label %return
219
220return:
221  %res = phi i32 [ %a, %if.then ], [ 123, %entry ]
222  call void asm sideeffect "stepb $0", "h"(i32 %res)
223  ret void
224}
225