1-- Taken from a comment https://github.com/universal-ctags/ctags/issues/2678
2-- submitted by @pidgeon777
3library ieee;
4use ieee.std_logic_1164.all;
5
6entity ENTITY_TOP is
7  generic (
8    GEN : integer := 0
9  );
10  port (
11    INP : in std_logic
12  );
13end entity;
14
15architecture arch of ENTITY_TOP is
16  signal sig : std_logic := '0';
17
18  component ENTITY_1
19    generic (
20      GEN : integer := 0
21    );
22    port (
23      INP : in std_logic
24    );
25  end component;
26
27  component ENTITY_2
28    generic (
29      GEN : integer := 0
30    );
31    port (
32      INP : in std_logic
33    );
34  end component;
35
36begin
37
38  ENTITY_1_i : ENTITY_1
39  generic map(
40    GEN => 0
41  )
42  port map(
43    INP => '0'
44  );
45
46  ENTITY_2_i : ENTITY_2
47  generic map(
48    GEN => 0
49  )
50  port map(
51    INP => '0'
52  );
53
54end architecture;
55