1//===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the target-independent interfaces used by SelectionDAG 10// instruction selection generators. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Selection DAG Type Constraint definitions. 16// 17// Note that the semantics of these constraints are hard coded into tblgen. To 18// modify or add constraints, you have to hack tblgen. 19// 20 21class SDTypeConstraint<int opnum> { 22 int OperandNum = opnum; 23} 24 25// SDTCisVT - The specified operand has exactly this VT. 26class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 27 ValueType VT = vt; 28} 29 30class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>; 31 32// SDTCisInt - The specified operand has integer type. 33class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>; 34 35// SDTCisFP - The specified operand has floating-point type. 36class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>; 37 38// SDTCisVec - The specified operand has a vector type. 39class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>; 40 41// SDTCisSameAs - The two specified operands have identical types. 42class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 43 int OtherOperandNum = OtherOp; 44} 45 46// SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is 47// smaller than the 'Other' operand. 48class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 49 int OtherOperandNum = OtherOp; 50} 51 52class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{ 53 int BigOperandNum = BigOp; 54} 55 56/// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same 57/// type as the element type of OtherOp, which is a vector type. 58class SDTCisEltOfVec<int ThisOp, int OtherOp> 59 : SDTypeConstraint<ThisOp> { 60 int OtherOpNum = OtherOp; 61} 62 63/// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type 64/// with length less that of OtherOp, which is a vector type. 65class SDTCisSubVecOfVec<int ThisOp, int OtherOp> 66 : SDTypeConstraint<ThisOp> { 67 int OtherOpNum = OtherOp; 68} 69 70// SDTCVecEltisVT - The specified operand is vector type with element type 71// of VT. 72class SDTCVecEltisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 73 ValueType VT = vt; 74} 75 76// SDTCisSameNumEltsAs - The two specified operands have identical number 77// of elements. 78class SDTCisSameNumEltsAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 79 int OtherOperandNum = OtherOp; 80} 81 82// SDTCisSameSizeAs - The two specified operands have identical size. 83class SDTCisSameSizeAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 84 int OtherOperandNum = OtherOp; 85} 86 87//===----------------------------------------------------------------------===// 88// Selection DAG Type Profile definitions. 89// 90// These use the constraints defined above to describe the type requirements of 91// the various nodes. These are not hard coded into tblgen, allowing targets to 92// add their own if needed. 93// 94 95// SDTypeProfile - This profile describes the type requirements of a Selection 96// DAG node. 97class SDTypeProfile<int numresults, int numoperands, 98 list<SDTypeConstraint> constraints> { 99 int NumResults = numresults; 100 int NumOperands = numoperands; 101 list<SDTypeConstraint> Constraints = constraints; 102} 103 104// Builtin profiles. 105def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. 106def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'. 107def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. 108def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. 109def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. 110def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert. 111 112def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. 113 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> 114]>; 115def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl 116 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2> 117]>; 118def SDTIntShiftDOp: SDTypeProfile<1, 3, [ // fshl, fshr 119 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3> 120]>; 121def SDTIntSatNoShOp : SDTypeProfile<1, 2, [ // ssat with no shift 122 SDTCisSameAs<0, 1>, SDTCisInt<2> 123]>; 124def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem 125 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0> 126]>; 127def SDTIntScaledBinOp : SDTypeProfile<1, 3, [ // smulfix, sdivfix, etc 128 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3> 129]>; 130 131def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. 132 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 133]>; 134def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign. 135 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2> 136]>; 137def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc. 138 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0> 139]>; 140def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // bitreverse 141 SDTCisSameAs<0, 1>, SDTCisInt<0> 142]>; 143def SDTIntBitCountUnaryOp : SDTypeProfile<1, 1, [ // ctlz, cttz 144 SDTCisInt<0>, SDTCisInt<1> 145]>; 146def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext 147 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1> 148]>; 149def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc 150 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1> 151]>; 152def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc 153 SDTCisSameAs<0, 1>, SDTCisFP<0> 154]>; 155def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround 156 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1> 157]>; 158def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend 159 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1> 160]>; 161def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp 162 SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1> 163]>; 164def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int 165 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1> 166]>; 167def SDTFPToIntSatOp : SDTypeProfile<1, 2, [ // fp_to_[su]int_sat 168 SDTCisInt<0>, SDTCisFP<1>, SDTCisInt<2>, SDTCisSameNumEltsAs<0, 1> 169]>; 170def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg 171 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, 172 SDTCisVTSmallerThanOp<2, 1> 173]>; 174def SDTExtInvec : SDTypeProfile<1, 1, [ // sext_invec 175 SDTCisInt<0>, SDTCisVec<0>, SDTCisInt<1>, SDTCisVec<1>, 176 SDTCisOpSmallerThanOp<1, 0> 177]>; 178 179def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 180 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 181]>; 182 183def SDTSelect : SDTypeProfile<1, 3, [ // select 184 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 185]>; 186 187def SDTVSelect : SDTypeProfile<1, 3, [ // vselect 188 SDTCisVec<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>, SDTCisSameNumEltsAs<0, 1> 189]>; 190 191def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc 192 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>, 193 SDTCisVT<5, OtherVT> 194]>; 195 196def SDTBr : SDTypeProfile<0, 1, [ // br 197 SDTCisVT<0, OtherVT> 198]>; 199 200def SDTBrCC : SDTypeProfile<0, 4, [ // brcc 201 SDTCisVT<0, OtherVT>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 202]>; 203 204def SDTBrcond : SDTypeProfile<0, 2, [ // brcond 205 SDTCisInt<0>, SDTCisVT<1, OtherVT> 206]>; 207 208def SDTBrind : SDTypeProfile<0, 1, [ // brind 209 SDTCisPtrTy<0> 210]>; 211 212def SDTCatchret : SDTypeProfile<0, 2, [ // catchret 213 SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT> 214]>; 215 216def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap 217 218def SDTUBSANTrap : SDTypeProfile<0, 1, []>; // ubsantrap 219 220def SDTLoad : SDTypeProfile<1, 1, [ // load 221 SDTCisPtrTy<1> 222]>; 223 224def SDTStore : SDTypeProfile<0, 2, [ // store 225 SDTCisPtrTy<1> 226]>; 227 228def SDTIStore : SDTypeProfile<1, 3, [ // indexed store 229 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3> 230]>; 231 232def SDTMaskedStore: SDTypeProfile<0, 4, [ // masked store 233 SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisPtrTy<2>, SDTCisVec<3>, SDTCisSameNumEltsAs<0, 3> 234]>; 235 236def SDTMaskedLoad: SDTypeProfile<1, 4, [ // masked load 237 SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisPtrTy<2>, SDTCisVec<3>, SDTCisSameAs<0, 4>, 238 SDTCisSameNumEltsAs<0, 3> 239]>; 240 241def SDTVecShuffle : SDTypeProfile<1, 2, [ 242 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> 243]>; 244def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract 245 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2> 246]>; 247def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert 248 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3> 249]>; 250def SDTVecReduce : SDTypeProfile<1, 1, [ // vector reduction 251 SDTCisInt<0>, SDTCisVec<1> 252]>; 253def SDTFPVecReduce : SDTypeProfile<1, 1, [ // FP vector reduction 254 SDTCisFP<0>, SDTCisVec<1> 255]>; 256 257 258def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract 259 SDTCisSubVecOfVec<0,1>, SDTCisInt<2> 260]>; 261def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert 262 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3> 263]>; 264 265def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch 266 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1> 267]>; 268 269def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barrier 270 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>, 271 SDTCisInt<0> 272]>; 273def SDTAtomicFence : SDTypeProfile<0, 2, [ 274 SDTCisSameAs<0,1>, SDTCisPtrTy<0> 275]>; 276def SDTAtomic3 : SDTypeProfile<1, 3, [ 277 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1> 278]>; 279def SDTAtomic2 : SDTypeProfile<1, 2, [ 280 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> 281]>; 282 283def SDTFPAtomic2 : SDTypeProfile<1, 2, [ 284 SDTCisSameAs<0,2>, SDTCisFP<0>, SDTCisPtrTy<1> 285]>; 286 287def SDTAtomicStore : SDTypeProfile<0, 2, [ 288 SDTCisPtrTy<0>, SDTCisInt<1> 289]>; 290def SDTAtomicLoad : SDTypeProfile<1, 1, [ 291 SDTCisInt<0>, SDTCisPtrTy<1> 292]>; 293 294def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su 295 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5> 296]>; 297 298class SDCallSeqStart<list<SDTypeConstraint> constraints> : 299 SDTypeProfile<0, 2, constraints>; 300class SDCallSeqEnd<list<SDTypeConstraint> constraints> : 301 SDTypeProfile<0, 2, constraints>; 302 303//===----------------------------------------------------------------------===// 304// Selection DAG Node definitions. 305// 306class SDNode<string opcode, SDTypeProfile typeprof, 307 list<SDNodeProperty> props = [], string sdclass = "SDNode"> 308 : SDPatternOperator { 309 string Opcode = opcode; 310 string SDClass = sdclass; 311 let Properties = props; 312 SDTypeProfile TypeProfile = typeprof; 313} 314 315// Special TableGen-recognized dag nodes 316def set; 317def implicit; 318def node; 319def srcvalue; 320 321def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; 322def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">; 323def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">; 324def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; 325def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; 326def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; 327def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; 328def vscale : SDNode<"ISD::VSCALE" , SDTIntUnaryOp, []>; 329def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], 330 "GlobalAddressSDNode">; 331def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], 332 "GlobalAddressSDNode">; 333def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [], 334 "GlobalAddressSDNode">; 335def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [], 336 "GlobalAddressSDNode">; 337def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [], 338 "ConstantPoolSDNode">; 339def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], 340 "ConstantPoolSDNode">; 341def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [], 342 "JumpTableSDNode">; 343def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [], 344 "JumpTableSDNode">; 345def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], 346 "FrameIndexSDNode">; 347def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [], 348 "FrameIndexSDNode">; 349def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], 350 "ExternalSymbolSDNode">; 351def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [], 352 "ExternalSymbolSDNode">; 353def mcsym: SDNode<"ISD::MCSymbol", SDTPtrLeaf, [], "MCSymbolSDNode">; 354def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [], 355 "BlockAddressSDNode">; 356def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [], 357 "BlockAddressSDNode">; 358 359def add : SDNode<"ISD::ADD" , SDTIntBinOp , 360 [SDNPCommutative, SDNPAssociative]>; 361def sub : SDNode<"ISD::SUB" , SDTIntBinOp>; 362def mul : SDNode<"ISD::MUL" , SDTIntBinOp, 363 [SDNPCommutative, SDNPAssociative]>; 364def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>; 365def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>; 366def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 367def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 368def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>; 369def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; 370def srem : SDNode<"ISD::SREM" , SDTIntBinOp>; 371def urem : SDNode<"ISD::UREM" , SDTIntBinOp>; 372def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>; 373def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>; 374def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>; 375def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>; 376def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>; 377def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>; 378def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>; 379def fshl : SDNode<"ISD::FSHL" , SDTIntShiftDOp>; 380def fshr : SDNode<"ISD::FSHR" , SDTIntShiftDOp>; 381def and : SDNode<"ISD::AND" , SDTIntBinOp, 382 [SDNPCommutative, SDNPAssociative]>; 383def or : SDNode<"ISD::OR" , SDTIntBinOp, 384 [SDNPCommutative, SDNPAssociative]>; 385def xor : SDNode<"ISD::XOR" , SDTIntBinOp, 386 [SDNPCommutative, SDNPAssociative]>; 387def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, 388 [SDNPCommutative, SDNPOutGlue]>; 389def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, 390 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>; 391def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, 392 [SDNPOutGlue]>; 393def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, 394 [SDNPOutGlue, SDNPInGlue]>; 395def smin : SDNode<"ISD::SMIN" , SDTIntBinOp, 396 [SDNPCommutative, SDNPAssociative]>; 397def smax : SDNode<"ISD::SMAX" , SDTIntBinOp, 398 [SDNPCommutative, SDNPAssociative]>; 399def umin : SDNode<"ISD::UMIN" , SDTIntBinOp, 400 [SDNPCommutative, SDNPAssociative]>; 401def umax : SDNode<"ISD::UMAX" , SDTIntBinOp, 402 [SDNPCommutative, SDNPAssociative]>; 403 404def saddsat : SDNode<"ISD::SADDSAT" , SDTIntBinOp, [SDNPCommutative]>; 405def uaddsat : SDNode<"ISD::UADDSAT" , SDTIntBinOp, [SDNPCommutative]>; 406def ssubsat : SDNode<"ISD::SSUBSAT" , SDTIntBinOp>; 407def usubsat : SDNode<"ISD::USUBSAT" , SDTIntBinOp>; 408def sshlsat : SDNode<"ISD::SSHLSAT" , SDTIntBinOp>; 409def ushlsat : SDNode<"ISD::USHLSAT" , SDTIntBinOp>; 410 411def smulfix : SDNode<"ISD::SMULFIX" , SDTIntScaledBinOp, [SDNPCommutative]>; 412def smulfixsat : SDNode<"ISD::SMULFIXSAT", SDTIntScaledBinOp, [SDNPCommutative]>; 413def umulfix : SDNode<"ISD::UMULFIX" , SDTIntScaledBinOp, [SDNPCommutative]>; 414def umulfixsat : SDNode<"ISD::UMULFIXSAT", SDTIntScaledBinOp, [SDNPCommutative]>; 415def sdivfix : SDNode<"ISD::SDIVFIX" , SDTIntScaledBinOp>; 416def sdivfixsat : SDNode<"ISD::SDIVFIXSAT", SDTIntScaledBinOp>; 417def udivfix : SDNode<"ISD::UDIVFIX" , SDTIntScaledBinOp>; 418def udivfixsat : SDNode<"ISD::UDIVFIXSAT", SDTIntScaledBinOp>; 419 420def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; 421def sext_invec : SDNode<"ISD::SIGN_EXTEND_VECTOR_INREG", SDTExtInvec>; 422def zext_invec : SDNode<"ISD::ZERO_EXTEND_VECTOR_INREG", SDTExtInvec>; 423 424def abs : SDNode<"ISD::ABS" , SDTIntUnaryOp>; 425def bitreverse : SDNode<"ISD::BITREVERSE" , SDTIntUnaryOp>; 426def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; 427def ctlz : SDNode<"ISD::CTLZ" , SDTIntBitCountUnaryOp>; 428def cttz : SDNode<"ISD::CTTZ" , SDTIntBitCountUnaryOp>; 429def ctpop : SDNode<"ISD::CTPOP" , SDTIntBitCountUnaryOp>; 430def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntBitCountUnaryOp>; 431def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntBitCountUnaryOp>; 432def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>; 433def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; 434def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; 435def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; 436def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>; 437def addrspacecast : SDNode<"ISD::ADDRSPACECAST", SDTUnaryOp>; 438def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; 439def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; 440 441def vecreduce_add : SDNode<"ISD::VECREDUCE_ADD", SDTVecReduce>; 442def vecreduce_smax : SDNode<"ISD::VECREDUCE_SMAX", SDTVecReduce>; 443def vecreduce_umax : SDNode<"ISD::VECREDUCE_UMAX", SDTVecReduce>; 444def vecreduce_smin : SDNode<"ISD::VECREDUCE_SMIN", SDTVecReduce>; 445def vecreduce_umin : SDNode<"ISD::VECREDUCE_UMIN", SDTVecReduce>; 446def vecreduce_fadd : SDNode<"ISD::VECREDUCE_FADD", SDTFPVecReduce>; 447 448def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; 449def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; 450def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; 451def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; 452def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; 453def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp, [SDNPCommutative]>; 454def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp, [SDNPCommutative]>; 455def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; 456def fminnum : SDNode<"ISD::FMINNUM" , SDTFPBinOp, 457 [SDNPCommutative, SDNPAssociative]>; 458def fmaxnum : SDNode<"ISD::FMAXNUM" , SDTFPBinOp, 459 [SDNPCommutative, SDNPAssociative]>; 460def fminnum_ieee : SDNode<"ISD::FMINNUM_IEEE", SDTFPBinOp, 461 [SDNPCommutative]>; 462def fmaxnum_ieee : SDNode<"ISD::FMAXNUM_IEEE", SDTFPBinOp, 463 [SDNPCommutative]>; 464def fminimum : SDNode<"ISD::FMINIMUM" , SDTFPBinOp, 465 [SDNPCommutative, SDNPAssociative]>; 466def fmaximum : SDNode<"ISD::FMAXIMUM" , SDTFPBinOp, 467 [SDNPCommutative, SDNPAssociative]>; 468def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>; 469def fcanonicalize : SDNode<"ISD::FCANONICALIZE", SDTFPUnaryOp>; 470def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; 471def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; 472def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; 473def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>; 474def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>; 475def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>; 476def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>; 477def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>; 478def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>; 479def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>; 480def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>; 481def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>; 482def fround : SDNode<"ISD::FROUND" , SDTFPUnaryOp>; 483 484def lround : SDNode<"ISD::LROUND" , SDTFPToIntOp>; 485def llround : SDNode<"ISD::LLROUND" , SDTFPToIntOp>; 486def lrint : SDNode<"ISD::LRINT" , SDTFPToIntOp>; 487def llrint : SDNode<"ISD::LLRINT" , SDTFPToIntOp>; 488 489def fpround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; 490def fpextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; 491def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>; 492 493def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; 494def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; 495def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>; 496def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; 497def fp_to_sint_sat : SDNode<"ISD::FP_TO_SINT_SAT" , SDTFPToIntSatOp>; 498def fp_to_uint_sat : SDNode<"ISD::FP_TO_UINT_SAT" , SDTFPToIntSatOp>; 499def f16_to_fp : SDNode<"ISD::FP16_TO_FP" , SDTIntToFPOp>; 500def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>; 501 502def strict_fadd : SDNode<"ISD::STRICT_FADD", 503 SDTFPBinOp, [SDNPHasChain, SDNPCommutative]>; 504def strict_fsub : SDNode<"ISD::STRICT_FSUB", 505 SDTFPBinOp, [SDNPHasChain]>; 506def strict_fmul : SDNode<"ISD::STRICT_FMUL", 507 SDTFPBinOp, [SDNPHasChain, SDNPCommutative]>; 508def strict_fdiv : SDNode<"ISD::STRICT_FDIV", 509 SDTFPBinOp, [SDNPHasChain]>; 510def strict_frem : SDNode<"ISD::STRICT_FREM", 511 SDTFPBinOp, [SDNPHasChain]>; 512def strict_fma : SDNode<"ISD::STRICT_FMA", 513 SDTFPTernaryOp, [SDNPHasChain, SDNPCommutative]>; 514def strict_fsqrt : SDNode<"ISD::STRICT_FSQRT", 515 SDTFPUnaryOp, [SDNPHasChain]>; 516def strict_fsin : SDNode<"ISD::STRICT_FSIN", 517 SDTFPUnaryOp, [SDNPHasChain]>; 518def strict_fcos : SDNode<"ISD::STRICT_FCOS", 519 SDTFPUnaryOp, [SDNPHasChain]>; 520def strict_fexp2 : SDNode<"ISD::STRICT_FEXP2", 521 SDTFPUnaryOp, [SDNPHasChain]>; 522def strict_fpow : SDNode<"ISD::STRICT_FPOW", 523 SDTFPBinOp, [SDNPHasChain]>; 524def strict_flog2 : SDNode<"ISD::STRICT_FLOG2", 525 SDTFPUnaryOp, [SDNPHasChain]>; 526def strict_frint : SDNode<"ISD::STRICT_FRINT", 527 SDTFPUnaryOp, [SDNPHasChain]>; 528def strict_lrint : SDNode<"ISD::STRICT_LRINT", 529 SDTFPToIntOp, [SDNPHasChain]>; 530def strict_llrint : SDNode<"ISD::STRICT_LLRINT", 531 SDTFPToIntOp, [SDNPHasChain]>; 532def strict_fnearbyint : SDNode<"ISD::STRICT_FNEARBYINT", 533 SDTFPUnaryOp, [SDNPHasChain]>; 534def strict_fceil : SDNode<"ISD::STRICT_FCEIL", 535 SDTFPUnaryOp, [SDNPHasChain]>; 536def strict_ffloor : SDNode<"ISD::STRICT_FFLOOR", 537 SDTFPUnaryOp, [SDNPHasChain]>; 538def strict_lround : SDNode<"ISD::STRICT_LROUND", 539 SDTFPToIntOp, [SDNPHasChain]>; 540def strict_llround : SDNode<"ISD::STRICT_LLROUND", 541 SDTFPToIntOp, [SDNPHasChain]>; 542def strict_fround : SDNode<"ISD::STRICT_FROUND", 543 SDTFPUnaryOp, [SDNPHasChain]>; 544def strict_ftrunc : SDNode<"ISD::STRICT_FTRUNC", 545 SDTFPUnaryOp, [SDNPHasChain]>; 546def strict_fminnum : SDNode<"ISD::STRICT_FMINNUM", 547 SDTFPBinOp, [SDNPHasChain, 548 SDNPCommutative, SDNPAssociative]>; 549def strict_fmaxnum : SDNode<"ISD::STRICT_FMAXNUM", 550 SDTFPBinOp, [SDNPHasChain, 551 SDNPCommutative, SDNPAssociative]>; 552def strict_fminimum : SDNode<"ISD::STRICT_FMINIMUM", 553 SDTFPBinOp, [SDNPHasChain, 554 SDNPCommutative, SDNPAssociative]>; 555def strict_fmaximum : SDNode<"ISD::STRICT_FMAXIMUM", 556 SDTFPBinOp, [SDNPHasChain, 557 SDNPCommutative, SDNPAssociative]>; 558def strict_fpround : SDNode<"ISD::STRICT_FP_ROUND", 559 SDTFPRoundOp, [SDNPHasChain]>; 560def strict_fpextend : SDNode<"ISD::STRICT_FP_EXTEND", 561 SDTFPExtendOp, [SDNPHasChain]>; 562def strict_fp_to_sint : SDNode<"ISD::STRICT_FP_TO_SINT", 563 SDTFPToIntOp, [SDNPHasChain]>; 564def strict_fp_to_uint : SDNode<"ISD::STRICT_FP_TO_UINT", 565 SDTFPToIntOp, [SDNPHasChain]>; 566def strict_sint_to_fp : SDNode<"ISD::STRICT_SINT_TO_FP", 567 SDTIntToFPOp, [SDNPHasChain]>; 568def strict_uint_to_fp : SDNode<"ISD::STRICT_UINT_TO_FP", 569 SDTIntToFPOp, [SDNPHasChain]>; 570def strict_fsetcc : SDNode<"ISD::STRICT_FSETCC", SDTSetCC, [SDNPHasChain]>; 571def strict_fsetccs : SDNode<"ISD::STRICT_FSETCCS", SDTSetCC, [SDNPHasChain]>; 572 573def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 574def select : SDNode<"ISD::SELECT" , SDTSelect>; 575def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>; 576def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; 577 578def brcc : SDNode<"ISD::BR_CC" , SDTBrCC, [SDNPHasChain]>; 579def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; 580def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; 581def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; 582def catchret : SDNode<"ISD::CATCHRET" , SDTCatchret, 583 [SDNPHasChain, SDNPSideEffect]>; 584def cleanupret : SDNode<"ISD::CLEANUPRET" , SDTNone, [SDNPHasChain]>; 585 586def trap : SDNode<"ISD::TRAP" , SDTNone, 587 [SDNPHasChain, SDNPSideEffect]>; 588def debugtrap : SDNode<"ISD::DEBUGTRAP" , SDTNone, 589 [SDNPHasChain, SDNPSideEffect]>; 590def ubsantrap : SDNode<"ISD::UBSANTRAP" , SDTUBSANTrap, 591 [SDNPHasChain, SDNPSideEffect]>; 592 593def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch, 594 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 595 SDNPMemOperand]>; 596 597def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf, 598 [SDNPHasChain, SDNPSideEffect]>; 599 600def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence, 601 [SDNPHasChain, SDNPSideEffect]>; 602 603def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3, 604 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 605def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2, 606 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 607def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2, 608 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 609def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2, 610 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 611def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2, 612 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 613def atomic_load_clr : SDNode<"ISD::ATOMIC_LOAD_CLR" , SDTAtomic2, 614 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 615def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2, 616 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 617def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2, 618 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 619def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2, 620 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 621def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2, 622 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 623def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2, 624 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 625def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2, 626 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 627def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2, 628 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 629def atomic_load_fadd : SDNode<"ISD::ATOMIC_LOAD_FADD" , SDTFPAtomic2, 630 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 631def atomic_load_fsub : SDNode<"ISD::ATOMIC_LOAD_FSUB" , SDTFPAtomic2, 632 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 633 634def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad, 635 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 636def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore, 637 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 638 639def masked_st : SDNode<"ISD::MSTORE", SDTMaskedStore, 640 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 641def masked_ld : SDNode<"ISD::MLOAD", SDTMaskedLoad, 642 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 643 644// Do not use ld, st directly. Use load, extload, sextload, zextload, store, 645// and truncst (see below). 646def ld : SDNode<"ISD::LOAD" , SDTLoad, 647 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 648def st : SDNode<"ISD::STORE" , SDTStore, 649 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 650def ist : SDNode<"ISD::STORE" , SDTIStore, 651 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 652 653def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; 654def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>; 655def splat_vector : SDNode<"ISD::SPLAT_VECTOR", SDTypeProfile<1, 1, []>, []>; 656def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, 657 []>; 658 659// vector_extract/vector_insert are deprecated. extractelt/insertelt 660// are preferred. 661def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 662 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; 663def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 664 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; 665def concat_vectors : SDNode<"ISD::CONCAT_VECTORS", 666 SDTypeProfile<1, 2, [SDTCisSubVecOfVec<1, 0>, SDTCisSameAs<1, 2>]>,[]>; 667 668// This operator does not do subvector type checking. The ARM 669// backend, at least, needs it. 670def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR", 671 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>, 672 []>; 673 674// This operator does subvector type checking. 675def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>; 676def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>; 677 678// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use 679// these internally. Don't reference these directly. 680def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 681 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 682 [SDNPHasChain]>; 683def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 684 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, 685 [SDNPHasChain]>; 686def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 687 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>; 688 689def SDT_assert : SDTypeProfile<1, 1, 690 [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>; 691def assertsext : SDNode<"ISD::AssertSext", SDT_assert>; 692def assertzext : SDNode<"ISD::AssertZext", SDT_assert>; 693def assertalign : SDNode<"ISD::AssertAlign", SDT_assert>; 694 695 696//===----------------------------------------------------------------------===// 697// Selection DAG Condition Codes 698 699class CondCode<string fcmpName = "", string icmpName = ""> { 700 string ICmpPredicate = icmpName; 701 string FCmpPredicate = fcmpName; 702} 703 704// ISD::CondCode enums, and mapping to CmpInst::Predicate names 705def SETOEQ : CondCode<"FCMP_OEQ">; 706def SETOGT : CondCode<"FCMP_OGT">; 707def SETOGE : CondCode<"FCMP_OGE">; 708def SETOLT : CondCode<"FCMP_OLT">; 709def SETOLE : CondCode<"FCMP_OLE">; 710def SETONE : CondCode<"FCMP_ONE">; 711def SETO : CondCode<"FCMP_ORD">; 712def SETUO : CondCode<"FCMP_UNO">; 713def SETUEQ : CondCode<"FCMP_UEQ">; 714def SETUGT : CondCode<"FCMP_UGT", "ICMP_UGT">; 715def SETUGE : CondCode<"FCMP_UGE", "ICMP_UGE">; 716def SETULT : CondCode<"FCMP_ULT", "ICMP_ULT">; 717def SETULE : CondCode<"FCMP_ULE", "ICMP_ULE">; 718def SETUNE : CondCode<"FCMP_UNE">; 719def SETEQ : CondCode<"", "ICMP_EQ">; 720def SETGT : CondCode<"", "ICMP_SGT">; 721def SETGE : CondCode<"", "ICMP_SGE">; 722def SETLT : CondCode<"", "ICMP_SLT">; 723def SETLE : CondCode<"", "ICMP_SLE">; 724def SETNE : CondCode<"", "ICMP_NE">; 725 726//===----------------------------------------------------------------------===// 727// Selection DAG Node Transformation Functions. 728// 729// This mechanism allows targets to manipulate nodes in the output DAG once a 730// match has been formed. This is typically used to manipulate immediate 731// values. 732// 733class SDNodeXForm<SDNode opc, code xformFunction> { 734 SDNode Opcode = opc; 735 code XFormFunction = xformFunction; 736} 737 738def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>; 739 740//===----------------------------------------------------------------------===// 741// Selection DAG Pattern Fragments. 742// 743// Pattern fragments are reusable chunks of dags that match specific things. 744// They can take arguments and have C++ predicates that control whether they 745// match. They are intended to make the patterns for common instructions more 746// compact and readable. 747// 748 749/// PatFrags - Represents a set of pattern fragments. Each single fragment 750/// can match something on the DAG, from a single node to multiple nested other 751/// fragments. The whole set of fragments matches if any of the single 752/// fragments match. This allows e.g. matching and "add with overflow" and 753/// a regular "add" with the same fragment set. 754/// 755class PatFrags<dag ops, list<dag> frags, code pred = [{}], 756 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator { 757 dag Operands = ops; 758 list<dag> Fragments = frags; 759 code PredicateCode = pred; 760 code GISelPredicateCode = [{}]; 761 code ImmediateCode = [{}]; 762 SDNodeXForm OperandTransform = xform; 763 764 // When this is set, the PredicateCode may refer to a constant Operands 765 // vector which contains the captured nodes of the DAG, in the order listed 766 // by the Operands field above. 767 // 768 // This is useful when Fragments involves associative / commutative 769 // operators: a single piece of code can easily refer to all operands even 770 // when re-associated / commuted variants of the fragment are matched. 771 bit PredicateCodeUsesOperands = false; 772 773 // Define a few pre-packaged predicates. This helps GlobalISel import 774 // existing rules from SelectionDAG for many common cases. 775 // They will be tested prior to the code in pred and must not be used in 776 // ImmLeaf and its subclasses. 777 778 // Is the desired pre-packaged predicate for a load? 779 bit IsLoad = ?; 780 // Is the desired pre-packaged predicate for a store? 781 bit IsStore = ?; 782 // Is the desired pre-packaged predicate for an atomic? 783 bit IsAtomic = ?; 784 785 // cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 786 // cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 787 bit IsUnindexed = ?; 788 789 // cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD 790 bit IsNonExtLoad = ?; 791 // cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD; 792 bit IsAnyExtLoad = ?; 793 // cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; 794 bit IsSignExtLoad = ?; 795 // cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD; 796 bit IsZeroExtLoad = ?; 797 // !cast<StoreSDNode>(N)->isTruncatingStore(); 798 // cast<StoreSDNode>(N)->isTruncatingStore(); 799 bit IsTruncStore = ?; 800 801 // cast<MemSDNode>(N)->getAddressSpace() == 802 // If this empty, accept any address space. 803 list<int> AddressSpaces = ?; 804 805 // cast<MemSDNode>(N)->getAlignment() >= 806 // If this is empty, accept any alignment. 807 int MinAlignment = ?; 808 809 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Monotonic 810 bit IsAtomicOrderingMonotonic = ?; 811 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Acquire 812 bit IsAtomicOrderingAcquire = ?; 813 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::Release 814 bit IsAtomicOrderingRelease = ?; 815 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::AcquireRelease 816 bit IsAtomicOrderingAcquireRelease = ?; 817 // cast<AtomicSDNode>(N)->getOrdering() == AtomicOrdering::SequentiallyConsistent 818 bit IsAtomicOrderingSequentiallyConsistent = ?; 819 820 // isAcquireOrStronger(cast<AtomicSDNode>(N)->getOrdering()) 821 // !isAcquireOrStronger(cast<AtomicSDNode>(N)->getOrdering()) 822 bit IsAtomicOrderingAcquireOrStronger = ?; 823 824 // isReleaseOrStronger(cast<AtomicSDNode>(N)->getOrdering()) 825 // !isReleaseOrStronger(cast<AtomicSDNode>(N)->getOrdering()) 826 bit IsAtomicOrderingReleaseOrStronger = ?; 827 828 // cast<LoadSDNode>(N)->getMemoryVT() == MVT::<VT>; 829 // cast<StoreSDNode>(N)->getMemoryVT() == MVT::<VT>; 830 ValueType MemoryVT = ?; 831 // cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::<VT>; 832 // cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::<VT>; 833 ValueType ScalarMemoryVT = ?; 834} 835 836// PatFrag - A version of PatFrags matching only a single fragment. 837class PatFrag<dag ops, dag frag, code pred = [{}], 838 SDNodeXForm xform = NOOP_SDNodeXForm> 839 : PatFrags<ops, [frag], pred, xform>; 840 841// OutPatFrag is a pattern fragment that is used as part of an output pattern 842// (not an input pattern). These do not have predicates or transforms, but are 843// used to avoid repeated subexpressions in output patterns. 844class OutPatFrag<dag ops, dag frag> 845 : PatFrag<ops, frag, [{}], NOOP_SDNodeXForm>; 846 847// PatLeaf's are pattern fragments that have no operands. This is just a helper 848// to define immediates and other common things concisely. 849class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm> 850 : PatFrag<(ops), frag, pred, xform>; 851 852 853// ImmLeaf is a pattern fragment with a constraint on the immediate. The 854// constraint is a function that is run on the immediate (always with the value 855// sign extended out to an int64_t) as Imm. For example: 856// 857// def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>; 858// 859// this is a more convenient form to match 'imm' nodes in than PatLeaf and also 860// is preferred over using PatLeaf because it allows the code generator to 861// reason more about the constraint. 862// 863// If FastIsel should ignore all instructions that have an operand of this type, 864// the FastIselShouldIgnore flag can be set. This is an optimization to reduce 865// the code size of the generated fast instruction selector. 866class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm, 867 SDNode ImmNode = imm> 868 : PatFrag<(ops), (vt ImmNode), [{}], xform> { 869 let ImmediateCode = pred; 870 bit FastIselShouldIgnore = false; 871 872 // Is the data type of the immediate an APInt? 873 bit IsAPInt = false; 874 875 // Is the data type of the immediate an APFloat? 876 bit IsAPFloat = false; 877} 878 879// Convenience wrapper for ImmLeaf to use timm/TargetConstant instead 880// of imm/Constant. 881class TImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm, 882 SDNode ImmNode = timm> : ImmLeaf<vt, pred, xform, ImmNode>; 883 884// An ImmLeaf except that Imm is an APInt. This is useful when you need to 885// zero-extend the immediate instead of sign-extend it. 886// 887// Note that FastISel does not currently understand IntImmLeaf and will not 888// generate code for rules that make use of it. As such, it does not make sense 889// to replace ImmLeaf with IntImmLeaf. However, replacing PatLeaf with an 890// IntImmLeaf will allow GlobalISel to import the rule. 891class IntImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm> 892 : ImmLeaf<vt, pred, xform> { 893 let IsAPInt = true; 894 let FastIselShouldIgnore = true; 895} 896 897// An ImmLeaf except that Imm is an APFloat. 898// 899// Note that FastISel does not currently understand FPImmLeaf and will not 900// generate code for rules that make use of it. 901class FPImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm> 902 : ImmLeaf<vt, pred, xform, fpimm> { 903 let IsAPFloat = true; 904 let FastIselShouldIgnore = true; 905} 906 907// Leaf fragments. 908 909def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>; 910def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>; 911 912// Use ISD::isConstantSplatVectorAllOnes or ISD::isConstantSplatVectorAllZeros 913// to look for the corresponding build_vector or splat_vector. Will look through 914// bitcasts and check for either opcode, except when used as a pattern root. 915// When used as a pattern root, only fixed-length build_vector and scalable 916// splat_vector are supported. 917def immAllOnesV; // ISD::isConstantSplatVectorAllOnes 918def immAllZerosV; // ISD::isConstantSplatVectorAllZeros 919 920// Other helper fragments. 921def not : PatFrag<(ops node:$in), (xor node:$in, -1)>; 922def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; 923def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; 924 925def zanyext : PatFrags<(ops node:$op), 926 [(zext node:$op), 927 (anyext node:$op)]>; 928 929// null_frag - The null pattern operator is used in multiclass instantiations 930// which accept an SDPatternOperator for use in matching patterns for internal 931// definitions. When expanding a pattern, if the null fragment is referenced 932// in the expansion, the pattern is discarded and it is as-if '[]' had been 933// specified. This allows multiclasses to have the isel patterns be optional. 934def null_frag : SDPatternOperator; 935 936// load fragments. 937def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr)> { 938 let IsLoad = true; 939 let IsUnindexed = true; 940} 941def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> { 942 let IsLoad = true; 943 let IsNonExtLoad = true; 944} 945 946// extending load fragments. 947def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> { 948 let IsLoad = true; 949 let IsAnyExtLoad = true; 950} 951def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> { 952 let IsLoad = true; 953 let IsSignExtLoad = true; 954} 955def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> { 956 let IsLoad = true; 957 let IsZeroExtLoad = true; 958} 959 960def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 961 let IsLoad = true; 962 let MemoryVT = i1; 963} 964def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 965 let IsLoad = true; 966 let MemoryVT = i8; 967} 968def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 969 let IsLoad = true; 970 let MemoryVT = i16; 971} 972def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 973 let IsLoad = true; 974 let MemoryVT = i32; 975} 976def extloadf16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 977 let IsLoad = true; 978 let MemoryVT = f16; 979} 980def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 981 let IsLoad = true; 982 let MemoryVT = f32; 983} 984def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 985 let IsLoad = true; 986 let MemoryVT = f64; 987} 988 989def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 990 let IsLoad = true; 991 let MemoryVT = i1; 992} 993def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 994 let IsLoad = true; 995 let MemoryVT = i8; 996} 997def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 998 let IsLoad = true; 999 let MemoryVT = i16; 1000} 1001def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1002 let IsLoad = true; 1003 let MemoryVT = i32; 1004} 1005 1006def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1007 let IsLoad = true; 1008 let MemoryVT = i1; 1009} 1010def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1011 let IsLoad = true; 1012 let MemoryVT = i8; 1013} 1014def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1015 let IsLoad = true; 1016 let MemoryVT = i16; 1017} 1018def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1019 let IsLoad = true; 1020 let MemoryVT = i32; 1021} 1022 1023def extloadvi1 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1024 let IsLoad = true; 1025 let ScalarMemoryVT = i1; 1026} 1027def extloadvi8 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1028 let IsLoad = true; 1029 let ScalarMemoryVT = i8; 1030} 1031def extloadvi16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1032 let IsLoad = true; 1033 let ScalarMemoryVT = i16; 1034} 1035def extloadvi32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1036 let IsLoad = true; 1037 let ScalarMemoryVT = i32; 1038} 1039def extloadvf32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1040 let IsLoad = true; 1041 let ScalarMemoryVT = f32; 1042} 1043def extloadvf64 : PatFrag<(ops node:$ptr), (extload node:$ptr)> { 1044 let IsLoad = true; 1045 let ScalarMemoryVT = f64; 1046} 1047 1048def sextloadvi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1049 let IsLoad = true; 1050 let ScalarMemoryVT = i1; 1051} 1052def sextloadvi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1053 let IsLoad = true; 1054 let ScalarMemoryVT = i8; 1055} 1056def sextloadvi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1057 let IsLoad = true; 1058 let ScalarMemoryVT = i16; 1059} 1060def sextloadvi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> { 1061 let IsLoad = true; 1062 let ScalarMemoryVT = i32; 1063} 1064 1065def zextloadvi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1066 let IsLoad = true; 1067 let ScalarMemoryVT = i1; 1068} 1069def zextloadvi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1070 let IsLoad = true; 1071 let ScalarMemoryVT = i8; 1072} 1073def zextloadvi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1074 let IsLoad = true; 1075 let ScalarMemoryVT = i16; 1076} 1077def zextloadvi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> { 1078 let IsLoad = true; 1079 let ScalarMemoryVT = i32; 1080} 1081 1082// store fragments. 1083def unindexedstore : PatFrag<(ops node:$val, node:$ptr), 1084 (st node:$val, node:$ptr)> { 1085 let IsStore = true; 1086 let IsUnindexed = true; 1087} 1088def store : PatFrag<(ops node:$val, node:$ptr), 1089 (unindexedstore node:$val, node:$ptr)> { 1090 let IsStore = true; 1091 let IsTruncStore = false; 1092} 1093 1094// truncstore fragments. 1095def truncstore : PatFrag<(ops node:$val, node:$ptr), 1096 (unindexedstore node:$val, node:$ptr)> { 1097 let IsStore = true; 1098 let IsTruncStore = true; 1099} 1100def truncstorei8 : PatFrag<(ops node:$val, node:$ptr), 1101 (truncstore node:$val, node:$ptr)> { 1102 let IsStore = true; 1103 let MemoryVT = i8; 1104} 1105def truncstorei16 : PatFrag<(ops node:$val, node:$ptr), 1106 (truncstore node:$val, node:$ptr)> { 1107 let IsStore = true; 1108 let MemoryVT = i16; 1109} 1110def truncstorei32 : PatFrag<(ops node:$val, node:$ptr), 1111 (truncstore node:$val, node:$ptr)> { 1112 let IsStore = true; 1113 let MemoryVT = i32; 1114} 1115def truncstoref16 : PatFrag<(ops node:$val, node:$ptr), 1116 (truncstore node:$val, node:$ptr)> { 1117 let IsStore = true; 1118 let MemoryVT = f16; 1119} 1120def truncstoref32 : PatFrag<(ops node:$val, node:$ptr), 1121 (truncstore node:$val, node:$ptr)> { 1122 let IsStore = true; 1123 let MemoryVT = f32; 1124} 1125def truncstoref64 : PatFrag<(ops node:$val, node:$ptr), 1126 (truncstore node:$val, node:$ptr)> { 1127 let IsStore = true; 1128 let MemoryVT = f64; 1129} 1130 1131def truncstorevi8 : PatFrag<(ops node:$val, node:$ptr), 1132 (truncstore node:$val, node:$ptr)> { 1133 let IsStore = true; 1134 let ScalarMemoryVT = i8; 1135} 1136 1137def truncstorevi16 : PatFrag<(ops node:$val, node:$ptr), 1138 (truncstore node:$val, node:$ptr)> { 1139 let IsStore = true; 1140 let ScalarMemoryVT = i16; 1141} 1142 1143def truncstorevi32 : PatFrag<(ops node:$val, node:$ptr), 1144 (truncstore node:$val, node:$ptr)> { 1145 let IsStore = true; 1146 let ScalarMemoryVT = i32; 1147} 1148 1149// indexed store fragments. 1150def istore : PatFrag<(ops node:$val, node:$base, node:$offset), 1151 (ist node:$val, node:$base, node:$offset)> { 1152 let IsStore = true; 1153 let IsTruncStore = false; 1154} 1155 1156def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset), 1157 (istore node:$val, node:$base, node:$offset), [{ 1158 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 1159 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 1160}]>; 1161 1162def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset), 1163 (ist node:$val, node:$base, node:$offset)> { 1164 let IsStore = true; 1165 let IsTruncStore = true; 1166} 1167def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 1168 (itruncstore node:$val, node:$base, node:$offset), [{ 1169 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 1170 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 1171}]>; 1172def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 1173 (pre_truncst node:$val, node:$base, node:$offset)> { 1174 let IsStore = true; 1175 let MemoryVT = i1; 1176} 1177def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 1178 (pre_truncst node:$val, node:$base, node:$offset)> { 1179 let IsStore = true; 1180 let MemoryVT = i8; 1181} 1182def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 1183 (pre_truncst node:$val, node:$base, node:$offset)> { 1184 let IsStore = true; 1185 let MemoryVT = i16; 1186} 1187def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 1188 (pre_truncst node:$val, node:$base, node:$offset)> { 1189 let IsStore = true; 1190 let MemoryVT = i32; 1191} 1192def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 1193 (pre_truncst node:$val, node:$base, node:$offset)> { 1194 let IsStore = true; 1195 let MemoryVT = f32; 1196} 1197def pre_truncstvi8 : PatFrag<(ops node:$val, node:$base, node:$offset), 1198 (pre_truncst node:$val, node:$base, node:$offset)> { 1199 let IsStore = true; 1200 let ScalarMemoryVT = i8; 1201} 1202def pre_truncstvi16 : PatFrag<(ops node:$val, node:$base, node:$offset), 1203 (pre_truncst node:$val, node:$base, node:$offset)> { 1204 let IsStore = true; 1205 let ScalarMemoryVT = i16; 1206} 1207 1208def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), 1209 (istore node:$val, node:$ptr, node:$offset), [{ 1210 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 1211 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 1212}]>; 1213 1214def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 1215 (itruncstore node:$val, node:$base, node:$offset), [{ 1216 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 1217 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 1218}]>; 1219def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 1220 (post_truncst node:$val, node:$base, node:$offset)> { 1221 let IsStore = true; 1222 let MemoryVT = i1; 1223} 1224def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 1225 (post_truncst node:$val, node:$base, node:$offset)> { 1226 let IsStore = true; 1227 let MemoryVT = i8; 1228} 1229def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 1230 (post_truncst node:$val, node:$base, node:$offset)> { 1231 let IsStore = true; 1232 let MemoryVT = i16; 1233} 1234def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 1235 (post_truncst node:$val, node:$base, node:$offset)> { 1236 let IsStore = true; 1237 let MemoryVT = i32; 1238} 1239def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 1240 (post_truncst node:$val, node:$base, node:$offset)> { 1241 let IsStore = true; 1242 let MemoryVT = f32; 1243} 1244def post_truncstvi8 : PatFrag<(ops node:$val, node:$base, node:$offset), 1245 (post_truncst node:$val, node:$base, node:$offset)> { 1246 let IsStore = true; 1247 let ScalarMemoryVT = i8; 1248} 1249def post_truncstvi16 : PatFrag<(ops node:$val, node:$base, node:$offset), 1250 (post_truncst node:$val, node:$base, node:$offset)> { 1251 let IsStore = true; 1252 let ScalarMemoryVT = i16; 1253} 1254 1255// TODO: Split these into volatile and unordered flavors to enable 1256// selectively legal optimizations for each. (See D66309) 1257def simple_load : PatFrag<(ops node:$ptr), 1258 (load node:$ptr), [{ 1259 return cast<LoadSDNode>(N)->isSimple(); 1260}]>; 1261def simple_store : PatFrag<(ops node:$val, node:$ptr), 1262 (store node:$val, node:$ptr), [{ 1263 return cast<StoreSDNode>(N)->isSimple(); 1264}]>; 1265 1266// nontemporal store fragments. 1267def nontemporalstore : PatFrag<(ops node:$val, node:$ptr), 1268 (store node:$val, node:$ptr), [{ 1269 return cast<StoreSDNode>(N)->isNonTemporal(); 1270}]>; 1271 1272def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 1273 (nontemporalstore node:$val, node:$ptr), [{ 1274 StoreSDNode *St = cast<StoreSDNode>(N); 1275 return St->getAlignment() >= St->getMemoryVT().getStoreSize(); 1276}]>; 1277 1278def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 1279 (nontemporalstore node:$val, node:$ptr), [{ 1280 StoreSDNode *St = cast<StoreSDNode>(N); 1281 return St->getAlignment() < St->getMemoryVT().getStoreSize(); 1282}]>; 1283 1284// nontemporal load fragments. 1285def nontemporalload : PatFrag<(ops node:$ptr), 1286 (load node:$ptr), [{ 1287 return cast<LoadSDNode>(N)->isNonTemporal(); 1288}]>; 1289 1290def alignednontemporalload : PatFrag<(ops node:$ptr), 1291 (nontemporalload node:$ptr), [{ 1292 LoadSDNode *Ld = cast<LoadSDNode>(N); 1293 return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); 1294}]>; 1295 1296// setcc convenience fragments. 1297def setoeq : PatFrag<(ops node:$lhs, node:$rhs), 1298 (setcc node:$lhs, node:$rhs, SETOEQ)>; 1299def setogt : PatFrag<(ops node:$lhs, node:$rhs), 1300 (setcc node:$lhs, node:$rhs, SETOGT)>; 1301def setoge : PatFrag<(ops node:$lhs, node:$rhs), 1302 (setcc node:$lhs, node:$rhs, SETOGE)>; 1303def setolt : PatFrag<(ops node:$lhs, node:$rhs), 1304 (setcc node:$lhs, node:$rhs, SETOLT)>; 1305def setole : PatFrag<(ops node:$lhs, node:$rhs), 1306 (setcc node:$lhs, node:$rhs, SETOLE)>; 1307def setone : PatFrag<(ops node:$lhs, node:$rhs), 1308 (setcc node:$lhs, node:$rhs, SETONE)>; 1309def seto : PatFrag<(ops node:$lhs, node:$rhs), 1310 (setcc node:$lhs, node:$rhs, SETO)>; 1311def setuo : PatFrag<(ops node:$lhs, node:$rhs), 1312 (setcc node:$lhs, node:$rhs, SETUO)>; 1313def setueq : PatFrag<(ops node:$lhs, node:$rhs), 1314 (setcc node:$lhs, node:$rhs, SETUEQ)>; 1315def setugt : PatFrag<(ops node:$lhs, node:$rhs), 1316 (setcc node:$lhs, node:$rhs, SETUGT)>; 1317def setuge : PatFrag<(ops node:$lhs, node:$rhs), 1318 (setcc node:$lhs, node:$rhs, SETUGE)>; 1319def setult : PatFrag<(ops node:$lhs, node:$rhs), 1320 (setcc node:$lhs, node:$rhs, SETULT)>; 1321def setule : PatFrag<(ops node:$lhs, node:$rhs), 1322 (setcc node:$lhs, node:$rhs, SETULE)>; 1323def setune : PatFrag<(ops node:$lhs, node:$rhs), 1324 (setcc node:$lhs, node:$rhs, SETUNE)>; 1325def seteq : PatFrag<(ops node:$lhs, node:$rhs), 1326 (setcc node:$lhs, node:$rhs, SETEQ)>; 1327def setgt : PatFrag<(ops node:$lhs, node:$rhs), 1328 (setcc node:$lhs, node:$rhs, SETGT)>; 1329def setge : PatFrag<(ops node:$lhs, node:$rhs), 1330 (setcc node:$lhs, node:$rhs, SETGE)>; 1331def setlt : PatFrag<(ops node:$lhs, node:$rhs), 1332 (setcc node:$lhs, node:$rhs, SETLT)>; 1333def setle : PatFrag<(ops node:$lhs, node:$rhs), 1334 (setcc node:$lhs, node:$rhs, SETLE)>; 1335def setne : PatFrag<(ops node:$lhs, node:$rhs), 1336 (setcc node:$lhs, node:$rhs, SETNE)>; 1337 1338// We don't have strict FP extended loads as single DAG nodes, but we can 1339// still provide convenience fragments to match those operations. 1340def strict_extloadf32 : PatFrag<(ops node:$ptr), 1341 (strict_fpextend (f32 (load node:$ptr)))>; 1342def strict_extloadf64 : PatFrag<(ops node:$ptr), 1343 (strict_fpextend (f64 (load node:$ptr)))>; 1344 1345// Convenience fragments to match both strict and non-strict fp operations 1346def any_fadd : PatFrags<(ops node:$lhs, node:$rhs), 1347 [(strict_fadd node:$lhs, node:$rhs), 1348 (fadd node:$lhs, node:$rhs)]>; 1349def any_fsub : PatFrags<(ops node:$lhs, node:$rhs), 1350 [(strict_fsub node:$lhs, node:$rhs), 1351 (fsub node:$lhs, node:$rhs)]>; 1352def any_fmul : PatFrags<(ops node:$lhs, node:$rhs), 1353 [(strict_fmul node:$lhs, node:$rhs), 1354 (fmul node:$lhs, node:$rhs)]>; 1355def any_fdiv : PatFrags<(ops node:$lhs, node:$rhs), 1356 [(strict_fdiv node:$lhs, node:$rhs), 1357 (fdiv node:$lhs, node:$rhs)]>; 1358def any_frem : PatFrags<(ops node:$lhs, node:$rhs), 1359 [(strict_frem node:$lhs, node:$rhs), 1360 (frem node:$lhs, node:$rhs)]>; 1361def any_fma : PatFrags<(ops node:$src1, node:$src2, node:$src3), 1362 [(strict_fma node:$src1, node:$src2, node:$src3), 1363 (fma node:$src1, node:$src2, node:$src3)]>; 1364def any_fsqrt : PatFrags<(ops node:$src), 1365 [(strict_fsqrt node:$src), 1366 (fsqrt node:$src)]>; 1367def any_fsin : PatFrags<(ops node:$src), 1368 [(strict_fsin node:$src), 1369 (fsin node:$src)]>; 1370def any_fcos : PatFrags<(ops node:$src), 1371 [(strict_fcos node:$src), 1372 (fcos node:$src)]>; 1373def any_fexp2 : PatFrags<(ops node:$src), 1374 [(strict_fexp2 node:$src), 1375 (fexp2 node:$src)]>; 1376def any_fpow : PatFrags<(ops node:$lhs, node:$rhs), 1377 [(strict_fpow node:$lhs, node:$rhs), 1378 (fpow node:$lhs, node:$rhs)]>; 1379def any_flog2 : PatFrags<(ops node:$src), 1380 [(strict_flog2 node:$src), 1381 (flog2 node:$src)]>; 1382def any_frint : PatFrags<(ops node:$src), 1383 [(strict_frint node:$src), 1384 (frint node:$src)]>; 1385def any_lrint : PatFrags<(ops node:$src), 1386 [(strict_lrint node:$src), 1387 (lrint node:$src)]>; 1388def any_llrint : PatFrags<(ops node:$src), 1389 [(strict_llrint node:$src), 1390 (llrint node:$src)]>; 1391def any_fnearbyint : PatFrags<(ops node:$src), 1392 [(strict_fnearbyint node:$src), 1393 (fnearbyint node:$src)]>; 1394def any_fceil : PatFrags<(ops node:$src), 1395 [(strict_fceil node:$src), 1396 (fceil node:$src)]>; 1397def any_ffloor : PatFrags<(ops node:$src), 1398 [(strict_ffloor node:$src), 1399 (ffloor node:$src)]>; 1400def any_lround : PatFrags<(ops node:$src), 1401 [(strict_lround node:$src), 1402 (lround node:$src)]>; 1403def any_llround : PatFrags<(ops node:$src), 1404 [(strict_llround node:$src), 1405 (llround node:$src)]>; 1406def any_fround : PatFrags<(ops node:$src), 1407 [(strict_fround node:$src), 1408 (fround node:$src)]>; 1409def any_ftrunc : PatFrags<(ops node:$src), 1410 [(strict_ftrunc node:$src), 1411 (ftrunc node:$src)]>; 1412def any_fmaxnum : PatFrags<(ops node:$lhs, node:$rhs), 1413 [(strict_fmaxnum node:$lhs, node:$rhs), 1414 (fmaxnum node:$lhs, node:$rhs)]>; 1415def any_fminnum : PatFrags<(ops node:$lhs, node:$rhs), 1416 [(strict_fminnum node:$lhs, node:$rhs), 1417 (fminnum node:$lhs, node:$rhs)]>; 1418def any_fmaximum : PatFrags<(ops node:$lhs, node:$rhs), 1419 [(strict_fmaximum node:$lhs, node:$rhs), 1420 (fmaximum node:$lhs, node:$rhs)]>; 1421def any_fminimum : PatFrags<(ops node:$lhs, node:$rhs), 1422 [(strict_fminimum node:$lhs, node:$rhs), 1423 (fminimum node:$lhs, node:$rhs)]>; 1424def any_fpround : PatFrags<(ops node:$src), 1425 [(strict_fpround node:$src), 1426 (fpround node:$src)]>; 1427def any_fpextend : PatFrags<(ops node:$src), 1428 [(strict_fpextend node:$src), 1429 (fpextend node:$src)]>; 1430def any_extloadf32 : PatFrags<(ops node:$ptr), 1431 [(strict_extloadf32 node:$ptr), 1432 (extloadf32 node:$ptr)]>; 1433def any_extloadf64 : PatFrags<(ops node:$ptr), 1434 [(strict_extloadf64 node:$ptr), 1435 (extloadf64 node:$ptr)]>; 1436def any_fp_to_sint : PatFrags<(ops node:$src), 1437 [(strict_fp_to_sint node:$src), 1438 (fp_to_sint node:$src)]>; 1439def any_fp_to_uint : PatFrags<(ops node:$src), 1440 [(strict_fp_to_uint node:$src), 1441 (fp_to_uint node:$src)]>; 1442def any_sint_to_fp : PatFrags<(ops node:$src), 1443 [(strict_sint_to_fp node:$src), 1444 (sint_to_fp node:$src)]>; 1445def any_uint_to_fp : PatFrags<(ops node:$src), 1446 [(strict_uint_to_fp node:$src), 1447 (uint_to_fp node:$src)]>; 1448def any_fsetcc : PatFrags<(ops node:$lhs, node:$rhs, node:$pred), 1449 [(strict_fsetcc node:$lhs, node:$rhs, node:$pred), 1450 (setcc node:$lhs, node:$rhs, node:$pred)]>; 1451def any_fsetccs : PatFrags<(ops node:$lhs, node:$rhs, node:$pred), 1452 [(strict_fsetccs node:$lhs, node:$rhs, node:$pred), 1453 (setcc node:$lhs, node:$rhs, node:$pred)]>; 1454 1455multiclass binary_atomic_op_ord<SDNode atomic_op> { 1456 def NAME#_monotonic : PatFrag<(ops node:$ptr, node:$val), 1457 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> { 1458 let IsAtomic = true; 1459 let IsAtomicOrderingMonotonic = true; 1460 } 1461 def NAME#_acquire : PatFrag<(ops node:$ptr, node:$val), 1462 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> { 1463 let IsAtomic = true; 1464 let IsAtomicOrderingAcquire = true; 1465 } 1466 def NAME#_release : PatFrag<(ops node:$ptr, node:$val), 1467 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> { 1468 let IsAtomic = true; 1469 let IsAtomicOrderingRelease = true; 1470 } 1471 def NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$val), 1472 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> { 1473 let IsAtomic = true; 1474 let IsAtomicOrderingAcquireRelease = true; 1475 } 1476 def NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$val), 1477 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> { 1478 let IsAtomic = true; 1479 let IsAtomicOrderingSequentiallyConsistent = true; 1480 } 1481} 1482 1483multiclass ternary_atomic_op_ord<SDNode atomic_op> { 1484 def NAME#_monotonic : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1485 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> { 1486 let IsAtomic = true; 1487 let IsAtomicOrderingMonotonic = true; 1488 } 1489 def NAME#_acquire : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1490 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> { 1491 let IsAtomic = true; 1492 let IsAtomicOrderingAcquire = true; 1493 } 1494 def NAME#_release : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1495 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> { 1496 let IsAtomic = true; 1497 let IsAtomicOrderingRelease = true; 1498 } 1499 def NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1500 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> { 1501 let IsAtomic = true; 1502 let IsAtomicOrderingAcquireRelease = true; 1503 } 1504 def NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1505 (!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> { 1506 let IsAtomic = true; 1507 let IsAtomicOrderingSequentiallyConsistent = true; 1508 } 1509} 1510 1511multiclass binary_atomic_op<SDNode atomic_op, bit IsInt = 1> { 1512 def _8 : PatFrag<(ops node:$ptr, node:$val), 1513 (atomic_op node:$ptr, node:$val)> { 1514 let IsAtomic = true; 1515 let MemoryVT = !if(IsInt, i8, ?); 1516 } 1517 def _16 : PatFrag<(ops node:$ptr, node:$val), 1518 (atomic_op node:$ptr, node:$val)> { 1519 let IsAtomic = true; 1520 let MemoryVT = !if(IsInt, i16, f16); 1521 } 1522 def _32 : PatFrag<(ops node:$ptr, node:$val), 1523 (atomic_op node:$ptr, node:$val)> { 1524 let IsAtomic = true; 1525 let MemoryVT = !if(IsInt, i32, f32); 1526 } 1527 def _64 : PatFrag<(ops node:$ptr, node:$val), 1528 (atomic_op node:$ptr, node:$val)> { 1529 let IsAtomic = true; 1530 let MemoryVT = !if(IsInt, i64, f64); 1531 } 1532 1533 defm NAME#_8 : binary_atomic_op_ord<atomic_op>; 1534 defm NAME#_16 : binary_atomic_op_ord<atomic_op>; 1535 defm NAME#_32 : binary_atomic_op_ord<atomic_op>; 1536 defm NAME#_64 : binary_atomic_op_ord<atomic_op>; 1537} 1538 1539multiclass ternary_atomic_op<SDNode atomic_op> { 1540 def _8 : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1541 (atomic_op node:$ptr, node:$cmp, node:$val)> { 1542 let IsAtomic = true; 1543 let MemoryVT = i8; 1544 } 1545 def _16 : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1546 (atomic_op node:$ptr, node:$cmp, node:$val)> { 1547 let IsAtomic = true; 1548 let MemoryVT = i16; 1549 } 1550 def _32 : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1551 (atomic_op node:$ptr, node:$cmp, node:$val)> { 1552 let IsAtomic = true; 1553 let MemoryVT = i32; 1554 } 1555 def _64 : PatFrag<(ops node:$ptr, node:$cmp, node:$val), 1556 (atomic_op node:$ptr, node:$cmp, node:$val)> { 1557 let IsAtomic = true; 1558 let MemoryVT = i64; 1559 } 1560 1561 defm NAME#_8 : ternary_atomic_op_ord<atomic_op>; 1562 defm NAME#_16 : ternary_atomic_op_ord<atomic_op>; 1563 defm NAME#_32 : ternary_atomic_op_ord<atomic_op>; 1564 defm NAME#_64 : ternary_atomic_op_ord<atomic_op>; 1565} 1566 1567defm atomic_load_add : binary_atomic_op<atomic_load_add>; 1568defm atomic_swap : binary_atomic_op<atomic_swap>; 1569defm atomic_load_sub : binary_atomic_op<atomic_load_sub>; 1570defm atomic_load_and : binary_atomic_op<atomic_load_and>; 1571defm atomic_load_clr : binary_atomic_op<atomic_load_clr>; 1572defm atomic_load_or : binary_atomic_op<atomic_load_or>; 1573defm atomic_load_xor : binary_atomic_op<atomic_load_xor>; 1574defm atomic_load_nand : binary_atomic_op<atomic_load_nand>; 1575defm atomic_load_min : binary_atomic_op<atomic_load_min>; 1576defm atomic_load_max : binary_atomic_op<atomic_load_max>; 1577defm atomic_load_umin : binary_atomic_op<atomic_load_umin>; 1578defm atomic_load_umax : binary_atomic_op<atomic_load_umax>; 1579defm atomic_store : binary_atomic_op<atomic_store>; 1580defm atomic_cmp_swap : ternary_atomic_op<atomic_cmp_swap>; 1581 1582def atomic_load_8 : 1583 PatFrag<(ops node:$ptr), 1584 (atomic_load node:$ptr)> { 1585 let IsAtomic = true; 1586 let MemoryVT = i8; 1587} 1588def atomic_load_16 : 1589 PatFrag<(ops node:$ptr), 1590 (atomic_load node:$ptr)> { 1591 let IsAtomic = true; 1592 let MemoryVT = i16; 1593} 1594def atomic_load_32 : 1595 PatFrag<(ops node:$ptr), 1596 (atomic_load node:$ptr)> { 1597 let IsAtomic = true; 1598 let MemoryVT = i32; 1599} 1600def atomic_load_64 : 1601 PatFrag<(ops node:$ptr), 1602 (atomic_load node:$ptr)> { 1603 let IsAtomic = true; 1604 let MemoryVT = i64; 1605} 1606 1607//===----------------------------------------------------------------------===// 1608// Selection DAG Pattern Support. 1609// 1610// Patterns are what are actually matched against by the target-flavored 1611// instruction selection DAG. Instructions defined by the target implicitly 1612// define patterns in most cases, but patterns can also be explicitly added when 1613// an operation is defined by a sequence of instructions (e.g. loading a large 1614// immediate value on RISC targets that do not support immediates as large as 1615// their GPRs). 1616// 1617 1618class Pattern<dag patternToMatch, list<dag> resultInstrs> { 1619 dag PatternToMatch = patternToMatch; 1620 list<dag> ResultInstrs = resultInstrs; 1621 list<Predicate> Predicates = []; // See class Instruction in Target.td. 1622 int AddedComplexity = 0; // See class Instruction in Target.td. 1623} 1624 1625// Pat - A simple (but common) form of a pattern, which produces a simple result 1626// not needing a full list. 1627class Pat<dag pattern, dag result> : Pattern<pattern, [result]>; 1628 1629//===----------------------------------------------------------------------===// 1630// Complex pattern definitions. 1631// 1632 1633// Complex patterns, e.g. X86 addressing mode, requires pattern matching code 1634// in C++. NumOperands is the number of operands returned by the select function; 1635// SelectFunc is the name of the function used to pattern match the max. pattern; 1636// RootNodes are the list of possible root nodes of the sub-dags to match. 1637// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>; 1638// 1639class ComplexPattern<ValueType ty, int numops, string fn, 1640 list<SDNode> roots = [], list<SDNodeProperty> props = [], 1641 int complexity = -1> { 1642 ValueType Ty = ty; 1643 int NumOperands = numops; 1644 string SelectFunc = fn; 1645 list<SDNode> RootNodes = roots; 1646 list<SDNodeProperty> Properties = props; 1647 int Complexity = complexity; 1648} 1649