1//===-- X86InstrMMX.td - Describe the MMX Instruction Set --*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the X86 MMX instruction set, defining the instructions,
10// and properties of the instructions which are needed for code generation,
11// machine code emission, and analysis.
12//
13// All instructions that use MMX should be in this file, even if they also use
14// SSE.
15//
16//===----------------------------------------------------------------------===//
17
18//===----------------------------------------------------------------------===//
19// MMX Multiclasses
20//===----------------------------------------------------------------------===//
21
22// Alias instruction that maps zero vector to pxor mmx.
23// This is expanded by ExpandPostRAPseudos to an pxor.
24// We set canFoldAsLoad because this can be converted to a constant-pool
25// load of an all-zeros value if folding it would be beneficial.
26let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
27    isPseudo = 1, SchedRW = [WriteZero], Predicates = [HasMMX] in {
28def MMX_SET0 : I<0, Pseudo, (outs VR64:$dst), (ins), "",
29                 [(set VR64:$dst, (x86mmx (MMX_X86movw2d (i32 0))))]>;
30}
31
32let Constraints = "$src1 = $dst" in {
33  // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic.
34  multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
35                               X86FoldableSchedWrite sched, bit Commutable = 0,
36                               X86MemOperand OType = i64mem> {
37    def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
38                 (ins VR64:$src1, VR64:$src2),
39                 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
40                 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>,
41              Sched<[sched]> {
42      let isCommutable = Commutable;
43    }
44    def irm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
45                 (ins VR64:$src1, OType:$src2),
46                 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
47                 [(set VR64:$dst, (IntId VR64:$src1, (load_mmx addr:$src2)))]>,
48                 Sched<[sched.Folded, sched.ReadAfterFold]>;
49  }
50
51  multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
52                                string OpcodeStr, Intrinsic IntId,
53                                Intrinsic IntId2, X86FoldableSchedWrite sched,
54                                X86FoldableSchedWrite schedImm> {
55    def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
56                                  (ins VR64:$src1, VR64:$src2),
57                  !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
58                  [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>,
59             Sched<[sched]>;
60    def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
61                                  (ins VR64:$src1, i64mem:$src2),
62                  !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
63                  [(set VR64:$dst, (IntId VR64:$src1, (load_mmx addr:$src2)))]>,
64                  Sched<[sched.Folded, sched.ReadAfterFold]>;
65    def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
66                                   (ins VR64:$src1, i32u8imm:$src2),
67                    !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
68           [(set VR64:$dst, (IntId2 VR64:$src1, timm:$src2))]>,
69           Sched<[schedImm]>;
70  }
71}
72
73/// Unary MMX instructions requiring SSSE3.
74multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr,
75                               Intrinsic IntId64, X86FoldableSchedWrite sched> {
76  def rr : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
77                 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
78                 [(set VR64:$dst, (IntId64 VR64:$src))]>,
79           Sched<[sched]>;
80
81  def rm : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
82                 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
83                 [(set VR64:$dst, (IntId64 (load_mmx addr:$src)))]>,
84                 Sched<[sched.Folded]>;
85}
86
87/// Binary MMX instructions requiring SSSE3.
88let ImmT = NoImm, Constraints = "$src1 = $dst" in {
89multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr,
90                             Intrinsic IntId64, X86FoldableSchedWrite sched,
91                             bit Commutable = 0> {
92  let isCommutable = Commutable in
93  def rr : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst),
94       (ins VR64:$src1, VR64:$src2),
95        !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
96       [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>,
97      Sched<[sched]>;
98  def rm : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst),
99       (ins VR64:$src1, i64mem:$src2),
100        !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
101       [(set VR64:$dst,
102         (IntId64 VR64:$src1, (load_mmx addr:$src2)))]>,
103      Sched<[sched.Folded, sched.ReadAfterFold]>;
104}
105}
106
107/// PALIGN MMX instructions (require SSSE3).
108multiclass ssse3_palign_mm<string asm, Intrinsic IntId,
109                           X86FoldableSchedWrite sched> {
110  def rri  : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
111      (ins VR64:$src1, VR64:$src2, u8imm:$src3),
112      !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
113      [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 timm:$src3)))]>,
114      Sched<[sched]>;
115  def rmi  : MMXSS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
116      (ins VR64:$src1, i64mem:$src2, u8imm:$src3),
117      !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
118      [(set VR64:$dst, (IntId VR64:$src1, (load_mmx addr:$src2),
119                                          (i8 timm:$src3)))]>,
120      Sched<[sched.Folded, sched.ReadAfterFold]>;
121}
122
123multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
124                         Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
125                         string asm, X86FoldableSchedWrite sched, Domain d> {
126  def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
127                  [(set DstRC:$dst, (Int SrcRC:$src))], d>,
128            Sched<[sched]>;
129  def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
130                  [(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>,
131            Sched<[sched.Folded]>;
132}
133
134multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
135                    RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
136                    PatFrag ld_frag, string asm, Domain d> {
137  def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
138                  (ins DstRC:$src1, SrcRC:$src2), asm,
139                  [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>,
140                  Sched<[WriteCvtI2PS]>;
141  def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst),
142                  (ins DstRC:$src1, x86memop:$src2), asm,
143                  [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], d>,
144                  Sched<[WriteCvtI2PS.Folded]>;
145}
146
147//===----------------------------------------------------------------------===//
148// MMX EMMS Instruction
149//===----------------------------------------------------------------------===//
150
151let SchedRW = [WriteEMMS],
152    Defs = [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
153            ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] in
154def MMX_EMMS  : MMXI<0x77, RawFrm, (outs), (ins), "emms", [(int_x86_mmx_emms)]>;
155
156//===----------------------------------------------------------------------===//
157// MMX Scalar Instructions
158//===----------------------------------------------------------------------===//
159
160// Data Transfer Instructions
161def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
162                        "movd\t{$src, $dst|$dst, $src}",
163                        [(set VR64:$dst,
164                         (x86mmx (MMX_X86movw2d GR32:$src)))]>,
165                        Sched<[WriteVecMoveFromGpr]>;
166def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
167                        "movd\t{$src, $dst|$dst, $src}",
168                        [(set VR64:$dst,
169                          (x86mmx (MMX_X86movw2d (loadi32 addr:$src))))]>,
170                        Sched<[WriteVecLoad]>;
171
172let mayStore = 1 in
173def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
174                        "movd\t{$src, $dst|$dst, $src}", []>,
175                   Sched<[WriteVecStore]>;
176
177def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR64:$src),
178                         "movd\t{$src, $dst|$dst, $src}",
179                         [(set GR32:$dst,
180                          (MMX_X86movd2w (x86mmx VR64:$src)))]>,
181                         Sched<[WriteVecMoveToGpr]>, FoldGenData<"MMX_MOVD64rr">;
182
183let isBitcast = 1 in
184def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
185                             "movq\t{$src, $dst|$dst, $src}",
186                             [(set VR64:$dst, (bitconvert GR64:$src))]>,
187                             Sched<[WriteVecMoveFromGpr]>;
188
189let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
190def MMX_MOVD64to64rm : MMXRI<0x6E, MRMSrcMem, (outs VR64:$dst),
191                             (ins i64mem:$src), "movq\t{$src, $dst|$dst, $src}",
192                             []>, Sched<[SchedWriteVecMoveLS.MMX.RM]>;
193
194let isBitcast = 1 in {
195def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
196                               (outs GR64:$dst), (ins VR64:$src),
197                               "movq\t{$src, $dst|$dst, $src}",
198                               [(set GR64:$dst, (bitconvert VR64:$src))]>,
199                               Sched<[WriteVecMoveToGpr]>;
200let SchedRW = [WriteVecMove], hasSideEffects = 0, isMoveReg = 1 in {
201def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
202                        "movq\t{$src, $dst|$dst, $src}", []>;
203let isCodeGenOnly = 1, ForceDisassemble = 1 in
204def MMX_MOVQ64rr_REV : MMXI<0x7F, MRMDestReg, (outs VR64:$dst), (ins VR64:$src),
205                            "movq\t{$src, $dst|$dst, $src}", []>,
206                            FoldGenData<"MMX_MOVQ64rr">;
207} // SchedRW, hasSideEffects, isMoveReg
208} // isBitcast
209
210def : InstAlias<"movq.s\t{$src, $dst|$dst, $src}",
211                (MMX_MOVQ64rr_REV VR64:$dst, VR64:$src), 0>;
212
213let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
214def MMX_MOVD64from64rm : MMXRI<0x7E, MRMDestMem,
215                               (outs), (ins i64mem:$dst, VR64:$src),
216                               "movq\t{$src, $dst|$dst, $src}", []>,
217                               Sched<[SchedWriteVecMoveLS.MMX.MR]>;
218
219let SchedRW = [SchedWriteVecMoveLS.MMX.RM] in {
220let canFoldAsLoad = 1 in
221def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
222                        "movq\t{$src, $dst|$dst, $src}",
223                        [(set VR64:$dst, (load_mmx addr:$src))]>;
224} // SchedRW
225
226let SchedRW = [SchedWriteVecMoveLS.MMX.MR] in
227def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
228                        "movq\t{$src, $dst|$dst, $src}",
229                        [(store (x86mmx VR64:$src), addr:$dst)]>;
230
231def MMX_X86movdq2q : SDNode<"X86ISD::MOVDQ2Q", SDTypeProfile<1, 1,
232                            [SDTCisVT<0, x86mmx>, SDTCisVT<1, v2i64>]>>;
233def MMX_X86movq2dq : SDNode<"X86ISD::MOVQ2DQ", SDTypeProfile<1, 1,
234                            [SDTCisVT<0, v2i64>, SDTCisVT<1, x86mmx>]>>;
235
236let SchedRW = [SchedWriteVecMoveLS.XMM.RR] in {
237def MMX_MOVDQ2Qrr : MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst),
238                             (ins VR128:$src), "movdq2q\t{$src, $dst|$dst, $src}",
239                             [(set VR64:$dst,
240                               (x86mmx (MMX_X86movdq2q VR128:$src)))]>;
241
242def MMX_MOVQ2DQrr : MMXS2SIi8<0xD6, MRMSrcReg, (outs VR128:$dst),
243                              (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}",
244                              [(set VR128:$dst,
245                                (v2i64 (MMX_X86movq2dq VR64:$src)))]>;
246
247let isCodeGenOnly = 1, hasSideEffects = 1 in {
248def MMX_MOVQ2FR64rr: MMXS2SIi8<0xD6, MRMSrcReg, (outs FR64:$dst),
249                               (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}",
250                               []>;
251
252def MMX_MOVFR642Qrr: MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst),
253                              (ins FR64:$src), "movdq2q\t{$src, $dst|$dst, $src}",
254                              []>;
255}
256} // SchedRW
257
258let Predicates = [HasMMX, HasSSE1] in
259def MMX_MOVNTQmr  : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
260                         "movntq\t{$src, $dst|$dst, $src}",
261                         [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>,
262                         Sched<[SchedWriteVecMoveLSNT.MMX.MR]>;
263
264// Arithmetic Instructions
265defm MMX_PABSB : SS3I_unop_rm_int_mm<0x1C, "pabsb", int_x86_ssse3_pabs_b,
266                                     SchedWriteVecALU.MMX>;
267defm MMX_PABSW : SS3I_unop_rm_int_mm<0x1D, "pabsw", int_x86_ssse3_pabs_w,
268                                     SchedWriteVecALU.MMX>;
269defm MMX_PABSD : SS3I_unop_rm_int_mm<0x1E, "pabsd", int_x86_ssse3_pabs_d,
270                                     SchedWriteVecALU.MMX>;
271// -- Addition
272defm MMX_PADDB : MMXI_binop_rm_int<0xFC, "paddb", int_x86_mmx_padd_b,
273                                   SchedWriteVecALU.MMX, 1>;
274defm MMX_PADDW : MMXI_binop_rm_int<0xFD, "paddw", int_x86_mmx_padd_w,
275                                   SchedWriteVecALU.MMX, 1>;
276defm MMX_PADDD : MMXI_binop_rm_int<0xFE, "paddd", int_x86_mmx_padd_d,
277                                   SchedWriteVecALU.MMX, 1>;
278let Predicates = [HasMMX, HasSSE2] in
279defm MMX_PADDQ : MMXI_binop_rm_int<0xD4, "paddq", int_x86_mmx_padd_q,
280                                   SchedWriteVecALU.MMX, 1>;
281defm MMX_PADDSB  : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b,
282                                     SchedWriteVecALU.MMX, 1>;
283defm MMX_PADDSW  : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w,
284                                     SchedWriteVecALU.MMX, 1>;
285
286defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b,
287                                   SchedWriteVecALU.MMX, 1>;
288defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w,
289                                   SchedWriteVecALU.MMX, 1>;
290
291defm MMX_PHADDW  : SS3I_binop_rm_int_mm<0x01, "phaddw", int_x86_ssse3_phadd_w,
292                                        SchedWritePHAdd.MMX>;
293defm MMX_PHADDD  : SS3I_binop_rm_int_mm<0x02, "phaddd", int_x86_ssse3_phadd_d,
294                                        SchedWritePHAdd.MMX>;
295defm MMX_PHADDSW : SS3I_binop_rm_int_mm<0x03, "phaddsw",int_x86_ssse3_phadd_sw,
296                                        SchedWritePHAdd.MMX>;
297
298// -- Subtraction
299defm MMX_PSUBB : MMXI_binop_rm_int<0xF8, "psubb", int_x86_mmx_psub_b,
300                                   SchedWriteVecALU.MMX>;
301defm MMX_PSUBW : MMXI_binop_rm_int<0xF9, "psubw", int_x86_mmx_psub_w,
302                                   SchedWriteVecALU.MMX>;
303defm MMX_PSUBD : MMXI_binop_rm_int<0xFA, "psubd", int_x86_mmx_psub_d,
304                                   SchedWriteVecALU.MMX>;
305let Predicates = [HasMMX, HasSSE2] in
306defm MMX_PSUBQ : MMXI_binop_rm_int<0xFB, "psubq", int_x86_mmx_psub_q,
307                                   SchedWriteVecALU.MMX>;
308
309defm MMX_PSUBSB  : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b,
310                                   SchedWriteVecALU.MMX>;
311defm MMX_PSUBSW  : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w,
312                                   SchedWriteVecALU.MMX>;
313
314defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b,
315                                   SchedWriteVecALU.MMX>;
316defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w,
317                                   SchedWriteVecALU.MMX>;
318
319defm MMX_PHSUBW  : SS3I_binop_rm_int_mm<0x05, "phsubw", int_x86_ssse3_phsub_w,
320                                        SchedWritePHAdd.MMX>;
321defm MMX_PHSUBD  : SS3I_binop_rm_int_mm<0x06, "phsubd", int_x86_ssse3_phsub_d,
322                                        SchedWritePHAdd.MMX>;
323defm MMX_PHSUBSW : SS3I_binop_rm_int_mm<0x07, "phsubsw",int_x86_ssse3_phsub_sw,
324                                        SchedWritePHAdd.MMX>;
325
326// -- Multiplication
327defm MMX_PMULLW  : MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w,
328                                     SchedWriteVecIMul.MMX, 1>;
329
330defm MMX_PMULHW  : MMXI_binop_rm_int<0xE5, "pmulhw",  int_x86_mmx_pmulh_w,
331                                     SchedWriteVecIMul.MMX, 1>;
332let Predicates = [HasMMX, HasSSE1] in
333defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w,
334                                     SchedWriteVecIMul.MMX, 1>;
335let Predicates = [HasMMX, HasSSE2] in
336defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq,
337                                     SchedWriteVecIMul.MMX, 1>;
338defm MMX_PMULHRSW : SS3I_binop_rm_int_mm<0x0B, "pmulhrsw",
339                                     int_x86_ssse3_pmul_hr_sw,
340                                     SchedWriteVecIMul.MMX, 1>;
341
342// -- Miscellanea
343defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd,
344                                     SchedWriteVecIMul.MMX, 1>;
345
346defm MMX_PMADDUBSW : SS3I_binop_rm_int_mm<0x04, "pmaddubsw",
347                                          int_x86_ssse3_pmadd_ub_sw,
348                                          SchedWriteVecIMul.MMX>;
349let Predicates = [HasMMX, HasSSE1] in {
350defm MMX_PAVGB   : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b,
351                                     SchedWriteVecALU.MMX, 1>;
352defm MMX_PAVGW   : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w,
353                                     SchedWriteVecALU.MMX, 1>;
354
355defm MMX_PMINUB  : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b,
356                                     SchedWriteVecALU.MMX, 1>;
357defm MMX_PMINSW  : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w,
358                                     SchedWriteVecALU.MMX, 1>;
359
360defm MMX_PMAXUB  : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b,
361                                     SchedWriteVecALU.MMX, 1>;
362defm MMX_PMAXSW  : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w,
363                                     SchedWriteVecALU.MMX, 1>;
364
365defm MMX_PSADBW  : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw,
366                                     SchedWritePSADBW.MMX, 1>;
367}
368
369defm MMX_PSIGNB :  SS3I_binop_rm_int_mm<0x08, "psignb", int_x86_ssse3_psign_b,
370                                        SchedWriteVecALU.MMX>;
371defm MMX_PSIGNW :  SS3I_binop_rm_int_mm<0x09, "psignw", int_x86_ssse3_psign_w,
372                                        SchedWriteVecALU.MMX>;
373defm MMX_PSIGND :  SS3I_binop_rm_int_mm<0x0A, "psignd", int_x86_ssse3_psign_d,
374                                        SchedWriteVecALU.MMX>;
375let Constraints = "$src1 = $dst" in
376  defm MMX_PALIGNR : ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b,
377                                     SchedWriteShuffle.MMX>;
378
379// Logical Instructions
380defm MMX_PAND : MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand,
381                                  SchedWriteVecLogic.MMX, 1>;
382defm MMX_POR  : MMXI_binop_rm_int<0xEB, "por" , int_x86_mmx_por,
383                                  SchedWriteVecLogic.MMX, 1>;
384defm MMX_PXOR : MMXI_binop_rm_int<0xEF, "pxor", int_x86_mmx_pxor,
385                                  SchedWriteVecLogic.MMX, 1>;
386defm MMX_PANDN : MMXI_binop_rm_int<0xDF, "pandn", int_x86_mmx_pandn,
387                                   SchedWriteVecLogic.MMX>;
388
389// Shift Instructions
390defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
391                                    int_x86_mmx_psrl_w, int_x86_mmx_psrli_w,
392                                    SchedWriteVecShift.MMX,
393                                    SchedWriteVecShiftImm.MMX>;
394defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
395                                    int_x86_mmx_psrl_d, int_x86_mmx_psrli_d,
396                                    SchedWriteVecShift.MMX,
397                                    SchedWriteVecShiftImm.MMX>;
398defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
399                                    int_x86_mmx_psrl_q, int_x86_mmx_psrli_q,
400                                    SchedWriteVecShift.MMX,
401                                    SchedWriteVecShiftImm.MMX>;
402
403defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
404                                    int_x86_mmx_psll_w, int_x86_mmx_pslli_w,
405                                    SchedWriteVecShift.MMX,
406                                    SchedWriteVecShiftImm.MMX>;
407defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
408                                    int_x86_mmx_psll_d, int_x86_mmx_pslli_d,
409                                    SchedWriteVecShift.MMX,
410                                    SchedWriteVecShiftImm.MMX>;
411defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
412                                    int_x86_mmx_psll_q, int_x86_mmx_pslli_q,
413                                    SchedWriteVecShift.MMX,
414                                    SchedWriteVecShiftImm.MMX>;
415
416defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
417                                    int_x86_mmx_psra_w, int_x86_mmx_psrai_w,
418                                    SchedWriteVecShift.MMX,
419                                    SchedWriteVecShiftImm.MMX>;
420defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
421                                    int_x86_mmx_psra_d, int_x86_mmx_psrai_d,
422                                    SchedWriteVecShift.MMX,
423                                    SchedWriteVecShiftImm.MMX>;
424
425// Comparison Instructions
426defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b,
427                                     SchedWriteVecALU.MMX>;
428defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w,
429                                     SchedWriteVecALU.MMX>;
430defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d,
431                                     SchedWriteVecALU.MMX>;
432
433defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b,
434                                     SchedWriteVecALU.MMX>;
435defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w,
436                                     SchedWriteVecALU.MMX>;
437defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d,
438                                     SchedWriteVecALU.MMX>;
439
440// -- Unpack Instructions
441defm MMX_PUNPCKHBW : MMXI_binop_rm_int<0x68, "punpckhbw",
442                                       int_x86_mmx_punpckhbw,
443                                       SchedWriteShuffle.MMX>;
444defm MMX_PUNPCKHWD : MMXI_binop_rm_int<0x69, "punpckhwd",
445                                       int_x86_mmx_punpckhwd,
446                                       SchedWriteShuffle.MMX>;
447defm MMX_PUNPCKHDQ : MMXI_binop_rm_int<0x6A, "punpckhdq",
448                                       int_x86_mmx_punpckhdq,
449                                       SchedWriteShuffle.MMX>;
450defm MMX_PUNPCKLBW : MMXI_binop_rm_int<0x60, "punpcklbw",
451                                       int_x86_mmx_punpcklbw,
452                                       SchedWriteShuffle.MMX,
453                                       0, i32mem>;
454defm MMX_PUNPCKLWD : MMXI_binop_rm_int<0x61, "punpcklwd",
455                                       int_x86_mmx_punpcklwd,
456                                       SchedWriteShuffle.MMX,
457                                       0, i32mem>;
458defm MMX_PUNPCKLDQ : MMXI_binop_rm_int<0x62, "punpckldq",
459                                       int_x86_mmx_punpckldq,
460                                       SchedWriteShuffle.MMX,
461                                       0, i32mem>;
462
463// -- Pack Instructions
464defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb,
465                                      SchedWriteShuffle.MMX>;
466defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw,
467                                      SchedWriteShuffle.MMX>;
468defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb,
469                                      SchedWriteShuffle.MMX>;
470
471// -- Shuffle Instructions
472defm MMX_PSHUFB : SS3I_binop_rm_int_mm<0x00, "pshufb", int_x86_ssse3_pshuf_b,
473                                       SchedWriteVarShuffle.MMX>;
474
475let Predicates = [HasMMX, HasSSE1] in {
476def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
477                          (outs VR64:$dst), (ins VR64:$src1, u8imm:$src2),
478                          "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
479                          [(set VR64:$dst,
480                             (int_x86_sse_pshuf_w VR64:$src1, timm:$src2))]>,
481                          Sched<[SchedWriteShuffle.MMX]>;
482def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
483                          (outs VR64:$dst), (ins i64mem:$src1, u8imm:$src2),
484                          "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
485                          [(set VR64:$dst,
486                             (int_x86_sse_pshuf_w (load_mmx addr:$src1),
487                                                   timm:$src2))]>,
488                          Sched<[SchedWriteShuffle.MMX.Folded]>;
489}
490
491// -- Conversion Instructions
492defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
493                      f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}",
494                      WriteCvtPS2I, SSEPackedSingle>, PS, SIMD_EXC;
495defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
496                      f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
497                      WriteCvtPD2I, SSEPackedDouble>, PD, SIMD_EXC;
498defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
499                       f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
500                       WriteCvtPS2I, SSEPackedSingle>, PS, SIMD_EXC;
501defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
502                       f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
503                       WriteCvtPD2I, SSEPackedDouble>, PD, SIMD_EXC;
504defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
505                         i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}",
506                         WriteCvtI2PD, SSEPackedDouble>, PD;
507let Constraints = "$src1 = $dst" in {
508  defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
509                         int_x86_sse_cvtpi2ps,
510                         i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
511                         SSEPackedSingle>, PS, SIMD_EXC;
512}
513
514// Extract / Insert
515let Predicates = [HasMMX, HasSSE1] in
516def MMX_PEXTRWrr: MMXIi8<0xC5, MRMSrcReg,
517                     (outs GR32orGR64:$dst), (ins VR64:$src1, i32u8imm:$src2),
518                     "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
519                     [(set GR32orGR64:$dst, (int_x86_mmx_pextr_w VR64:$src1,
520                                             timm:$src2))]>,
521                     Sched<[WriteVecExtract]>;
522let Constraints = "$src1 = $dst" in {
523let Predicates = [HasMMX, HasSSE1] in {
524  def MMX_PINSRWrr : MMXIi8<0xC4, MRMSrcReg,
525                    (outs VR64:$dst),
526                    (ins VR64:$src1, GR32orGR64:$src2, i32u8imm:$src3),
527                    "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
528                    [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
529                                      GR32orGR64:$src2, timm:$src3))]>,
530                    Sched<[WriteVecInsert, ReadDefault, ReadInt2Fpu]>;
531
532  def MMX_PINSRWrm : MMXIi8<0xC4, MRMSrcMem,
533                   (outs VR64:$dst),
534                   (ins VR64:$src1, i16mem:$src2, i32u8imm:$src3),
535                   "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
536                   [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
537                                       (i32 (anyext (loadi16 addr:$src2))),
538                                     timm:$src3))]>,
539                   Sched<[WriteVecInsert.Folded, WriteVecInsert.ReadAfterFold]>;
540}
541}
542
543// Mask creation
544let Predicates = [HasMMX, HasSSE1] in
545def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
546                          (ins VR64:$src),
547                          "pmovmskb\t{$src, $dst|$dst, $src}",
548                          [(set GR32orGR64:$dst,
549                                (int_x86_mmx_pmovmskb VR64:$src))]>,
550                          Sched<[WriteMMXMOVMSK]>;
551
552// Misc.
553let SchedRW = [SchedWriteShuffle.MMX] in {
554let Uses = [EDI], Predicates = [HasMMX, HasSSE1,Not64BitMode] in
555def MMX_MASKMOVQ : MMXI32<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
556                          "maskmovq\t{$mask, $src|$src, $mask}",
557                          [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>;
558let Uses = [RDI], Predicates = [HasMMX, HasSSE1,In64BitMode] in
559def MMX_MASKMOVQ64: MMXI64<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
560                           "maskmovq\t{$mask, $src|$src, $mask}",
561                           [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)]>;
562}
563
564// 64-bit bit convert.
565let Predicates = [HasMMX, HasSSE2] in {
566def : Pat<(f64 (bitconvert (x86mmx VR64:$src))),
567          (MMX_MOVQ2FR64rr VR64:$src)>;
568def : Pat<(x86mmx (bitconvert (f64 FR64:$src))),
569          (MMX_MOVFR642Qrr FR64:$src)>;
570def : Pat<(x86mmx (MMX_X86movdq2q
571                   (bc_v2i64 (v4i32 (X86cvtp2Int (v4f32 VR128:$src)))))),
572          (MMX_CVTPS2PIirr VR128:$src)>;
573def : Pat<(x86mmx (MMX_X86movdq2q
574                   (bc_v2i64 (v4i32 (X86cvttp2si (v4f32 VR128:$src)))))),
575          (MMX_CVTTPS2PIirr VR128:$src)>;
576def : Pat<(x86mmx (MMX_X86movdq2q
577                   (bc_v2i64 (v4i32 (X86cvtp2Int (v2f64 VR128:$src)))))),
578          (MMX_CVTPD2PIirr VR128:$src)>;
579def : Pat<(x86mmx (MMX_X86movdq2q
580                   (bc_v2i64 (v4i32 (X86cvttp2si (v2f64 VR128:$src)))))),
581          (MMX_CVTTPD2PIirr VR128:$src)>;
582}
583