1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3
4---
5name:            add_sext_s32_to_s64
6alignment:       4
7legalized:       true
8regBankSelected: true
9tracksRegLiveness: true
10machineFunctionInfo: {}
11body:             |
12  bb.0:
13    liveins: $w1, $x2
14    ; CHECK-LABEL: name: add_sext_s32_to_s64
15    ; CHECK: liveins: $w1, $x2
16    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
17    ; CHECK: %add_lhs:gpr64sp = COPY $x2
18    ; CHECK: %res:gpr64sp = ADDXrx %add_lhs, [[COPY]], 48
19    ; CHECK: $x3 = COPY %res
20    ; CHECK: RET_ReallyLR implicit $x3
21    %1:gpr(s32) = COPY $w1
22    %ext:gpr(s64) = G_SEXT %1(s32)
23    %add_lhs:gpr(s64) = COPY $x2
24    %res:gpr(s64) = G_ADD %add_lhs, %ext
25    $x3 = COPY %res(s64)
26    RET_ReallyLR implicit $x3
27...
28---
29name:            add_and_s32_to_s64
30alignment:       4
31legalized:       true
32regBankSelected: true
33tracksRegLiveness: true
34machineFunctionInfo: {}
35body:             |
36  bb.0:
37    liveins: $x1, $x2
38    ; CHECK-LABEL: name: add_and_s32_to_s64
39    ; CHECK: liveins: $x1, $x2
40    ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x1
41    ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]].sub_32
42    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]
43    ; CHECK: %add_lhs:gpr64sp = COPY $x2
44    ; CHECK: %res:gpr64sp = ADDXrx %add_lhs, [[COPY2]], 16
45    ; CHECK: $x3 = COPY %res
46    ; CHECK: RET_ReallyLR implicit $x3
47    %1:gpr(s64) = COPY $x1
48    %mask:gpr(s64) = G_CONSTANT i64 4294967295 ; 0xffff
49    %ext:gpr(s64) = G_AND %1(s64), %mask
50    %add_lhs:gpr(s64) = COPY $x2
51    %res:gpr(s64) = G_ADD %add_lhs, %ext
52    $x3 = COPY %res(s64)
53    RET_ReallyLR implicit $x3
54...
55---
56name:            add_sext_s16_to_s32
57alignment:       4
58legalized:       true
59regBankSelected: true
60tracksRegLiveness: true
61machineFunctionInfo: {}
62body:             |
63  bb.0:
64    liveins: $w1, $w2, $x2
65    ; CHECK-LABEL: name: add_sext_s16_to_s32
66    ; CHECK: liveins: $w1, $w2, $x2
67    ; CHECK: %wide_1:gpr32 = COPY $w1
68    ; CHECK: %add_lhs:gpr32sp = COPY $w2
69    ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 40
70    ; CHECK: $w3 = COPY %res
71    ; CHECK: RET_ReallyLR implicit $w3
72    %wide_1:gpr(s32) = COPY $w1
73    %1:gpr(s16) = G_TRUNC %wide_1
74    %ext:gpr(s32) = G_SEXT %1(s16)
75    %add_lhs:gpr(s32) = COPY $w2
76    %res:gpr(s32) = G_ADD %add_lhs, %ext
77    $w3 = COPY %res(s32)
78    RET_ReallyLR implicit $w3
79...
80---
81name:            add_zext_s16_to_s32
82alignment:       4
83legalized:       true
84regBankSelected: true
85tracksRegLiveness: true
86machineFunctionInfo: {}
87body:             |
88  bb.0:
89    liveins: $w1, $w2, $x2
90    ; CHECK-LABEL: name: add_zext_s16_to_s32
91    ; CHECK: liveins: $w1, $w2, $x2
92    ; CHECK: %wide_1:gpr32 = COPY $w1
93    ; CHECK: %add_lhs:gpr32sp = COPY $w2
94    ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 8
95    ; CHECK: $w3 = COPY %res
96    ; CHECK: RET_ReallyLR implicit $w3
97    %wide_1:gpr(s32) = COPY $w1
98    %1:gpr(s16) = G_TRUNC %wide_1
99    %ext:gpr(s32) = G_ZEXT %1(s16)
100    %add_lhs:gpr(s32) = COPY $w2
101    %res:gpr(s32) = G_ADD %add_lhs, %ext
102    $w3 = COPY %res(s32)
103    RET_ReallyLR implicit $w3
104...
105---
106name:            add_anyext_s16_to_s32
107alignment:       4
108legalized:       true
109regBankSelected: true
110tracksRegLiveness: true
111machineFunctionInfo: {}
112body:             |
113  bb.0:
114    liveins: $w1, $w2, $x2
115    ; CHECK-LABEL: name: add_anyext_s16_to_s32
116    ; CHECK: liveins: $w1, $w2, $x2
117    ; CHECK: %wide_1:gpr32 = COPY $w1
118    ; CHECK: %add_lhs:gpr32sp = COPY $w2
119    ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 8
120    ; CHECK: $w3 = COPY %res
121    ; CHECK: RET_ReallyLR implicit $w3
122    %wide_1:gpr(s32) = COPY $w1
123    %1:gpr(s16) = G_TRUNC %wide_1
124    %ext:gpr(s32) = G_ANYEXT %1(s16)
125    %add_lhs:gpr(s32) = COPY $w2
126    %res:gpr(s32) = G_ADD %add_lhs, %ext
127    $w3 = COPY %res(s32)
128    RET_ReallyLR implicit $w3
129...
130---
131name:            add_and_s16_to_s32_uxtb
132alignment:       4
133legalized:       true
134regBankSelected: true
135tracksRegLiveness: true
136machineFunctionInfo: {}
137body:             |
138  bb.0:
139    liveins: $w1, $w2, $x2
140    ; CHECK-LABEL: name: add_and_s16_to_s32_uxtb
141    ; CHECK: liveins: $w1, $w2, $x2
142    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
143    ; CHECK: %add_lhs:gpr32sp = COPY $w2
144    ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 0
145    ; CHECK: $w3 = COPY %res
146    ; CHECK: RET_ReallyLR implicit $w3
147    %1:gpr(s32) = COPY $w1
148    %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff
149    %ext:gpr(s32) = G_AND %1(s32), %mask
150    %add_lhs:gpr(s32) = COPY $w2
151    %res:gpr(s32) = G_ADD %add_lhs, %ext
152    $w3 = COPY %res(s32)
153    RET_ReallyLR implicit $w3
154...
155---
156name:            add_and_s16_to_s32_uxth
157alignment:       4
158legalized:       true
159regBankSelected: true
160tracksRegLiveness: true
161machineFunctionInfo: {}
162body:             |
163  bb.0:
164    liveins: $w1, $w2, $x2
165    ; CHECK-LABEL: name: add_and_s16_to_s32_uxth
166    ; CHECK: liveins: $w1, $w2, $x2
167    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
168    ; CHECK: %add_lhs:gpr32sp = COPY $w2
169    ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 8
170    ; CHECK: $w3 = COPY %res
171    ; CHECK: RET_ReallyLR implicit $w3
172    %1:gpr(s32) = COPY $w1
173    %mask:gpr(s32) = G_CONSTANT i32 65535 ; 0xffff
174    %ext:gpr(s32) = G_AND %1(s32), %mask
175    %add_lhs:gpr(s32) = COPY $w2
176    %res:gpr(s32) = G_ADD %add_lhs, %ext
177    $w3 = COPY %res(s32)
178    RET_ReallyLR implicit $w3
179...
180---
181name:            add_sext_s8_to_s32
182alignment:       4
183legalized:       true
184regBankSelected: true
185tracksRegLiveness: true
186machineFunctionInfo: {}
187body:             |
188  bb.0:
189    liveins: $w1, $w2, $x2
190    ; CHECK-LABEL: name: add_sext_s8_to_s32
191    ; CHECK: liveins: $w1, $w2, $x2
192    ; CHECK: %wide_1:gpr32 = COPY $w1
193    ; CHECK: %add_lhs:gpr32sp = COPY $w2
194    ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 32
195    ; CHECK: $w3 = COPY %res
196    ; CHECK: RET_ReallyLR implicit $w3
197    %wide_1:gpr(s32) = COPY $w1
198    %1:gpr(s8) = G_TRUNC %wide_1
199    %ext:gpr(s32) = G_SEXT %1(s8)
200    %add_lhs:gpr(s32) = COPY $w2
201    %res:gpr(s32) = G_ADD %add_lhs, %ext
202    $w3 = COPY %res(s32)
203    RET_ReallyLR implicit $w3
204...
205---
206name:            add_zext_s8_to_s32
207alignment:       4
208legalized:       true
209regBankSelected: true
210tracksRegLiveness: true
211machineFunctionInfo: {}
212body:             |
213  bb.0:
214    liveins: $w1, $w2, $x2
215    ; CHECK-LABEL: name: add_zext_s8_to_s32
216    ; CHECK: liveins: $w1, $w2, $x2
217    ; CHECK: %wide_1:gpr32 = COPY $w1
218    ; CHECK: %add_lhs:gpr32sp = COPY $w2
219    ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 0
220    ; CHECK: $w3 = COPY %res
221    ; CHECK: RET_ReallyLR implicit $w3
222    %wide_1:gpr(s32) = COPY $w1
223    %1:gpr(s8) = G_TRUNC %wide_1
224    %ext:gpr(s32) = G_ZEXT %1(s8)
225    %add_lhs:gpr(s32) = COPY $w2
226    %res:gpr(s32) = G_ADD %add_lhs, %ext
227    $w3 = COPY %res(s32)
228    RET_ReallyLR implicit $w3
229...
230---
231name:            add_anyext_s8_to_s32
232alignment:       4
233legalized:       true
234regBankSelected: true
235tracksRegLiveness: true
236machineFunctionInfo: {}
237body:             |
238  bb.0:
239    liveins: $w1, $w2, $x2
240    ; CHECK-LABEL: name: add_anyext_s8_to_s32
241    ; CHECK: liveins: $w1, $w2, $x2
242    ; CHECK: %wide_1:gpr32 = COPY $w1
243    ; CHECK: %add_lhs:gpr32sp = COPY $w2
244    ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 0
245    ; CHECK: $w3 = COPY %res
246    ; CHECK: RET_ReallyLR implicit $w3
247    %wide_1:gpr(s32) = COPY $w1
248    %1:gpr(s8) = G_TRUNC %wide_1
249    %ext:gpr(s32) = G_ANYEXT %1(s8)
250    %add_lhs:gpr(s32) = COPY $w2
251    %res:gpr(s32) = G_ADD %add_lhs, %ext
252    $w3 = COPY %res(s32)
253    RET_ReallyLR implicit $w3
254...
255---
256name:            add_sext_with_shl
257alignment:       4
258legalized:       true
259regBankSelected: true
260tracksRegLiveness: true
261machineFunctionInfo: {}
262body:             |
263  bb.0:
264    liveins: $w1, $w2, $x2
265    ; CHECK-LABEL: name: add_sext_with_shl
266    ; CHECK: liveins: $w1, $w2, $x2
267    ; CHECK: %wide_1:gpr32 = COPY $w1
268    ; CHECK: %add_lhs:gpr32sp = COPY $w2
269    ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 43
270    ; CHECK: $w3 = COPY %res
271    ; CHECK: RET_ReallyLR implicit $w3
272    %wide_1:gpr(s32) = COPY $w1
273    %1:gpr(s16) = G_TRUNC %wide_1
274    %ext:gpr(s32) = G_SEXT %1(s16)
275    %imm:gpr(s32) = G_CONSTANT i32 3
276    %shl:gpr(s32) = G_SHL %ext, %imm
277    %add_lhs:gpr(s32) = COPY $w2
278    %res:gpr(s32) = G_ADD %add_lhs, %shl
279    $w3 = COPY %res(s32)
280    RET_ReallyLR implicit $w3
281...
282---
283name:            add_and_with_shl
284alignment:       4
285legalized:       true
286regBankSelected: true
287tracksRegLiveness: true
288machineFunctionInfo: {}
289body:             |
290  bb.0:
291    liveins: $w1, $w2, $x2
292    ; CHECK-LABEL: name: add_and_with_shl
293    ; CHECK: liveins: $w1, $w2, $x2
294    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
295    ; CHECK: %add_lhs:gpr32sp = COPY $w2
296    ; CHECK: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 3
297    ; CHECK: $w3 = COPY %res
298    ; CHECK: RET_ReallyLR implicit $w3
299    %1:gpr(s32) = COPY $w1
300    %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff
301    %ext:gpr(s32) = G_AND %1(s32), %mask
302    %imm:gpr(s32) = G_CONSTANT i32 3
303    %shl:gpr(s32) = G_SHL %ext, %imm
304    %add_lhs:gpr(s32) = COPY $w2
305    %res:gpr(s32) = G_ADD %add_lhs, %shl
306    $w3 = COPY %res(s32)
307    RET_ReallyLR implicit $w3
308...
309---
310name:            dont_fold_invalid_mask
311alignment:       4
312legalized:       true
313regBankSelected: true
314tracksRegLiveness: true
315machineFunctionInfo: {}
316body:             |
317  bb.0:
318    ; Check that we only fold when we have a supported AND mask.
319    liveins: $w1, $w2, $x2
320    ; CHECK-LABEL: name: dont_fold_invalid_mask
321    ; CHECK: liveins: $w1, $w2, $x2
322    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
323    ; CHECK: %mask:gpr32 = MOVi32imm 42
324    ; CHECK: %ext:gpr32 = ANDWrr [[COPY]], %mask
325    ; CHECK: %add_lhs:gpr32 = COPY $w2
326    ; CHECK: %res:gpr32 = ADDWrr %add_lhs, %ext
327    ; CHECK: $w3 = COPY %res
328    ; CHECK: RET_ReallyLR implicit $w3
329    %1:gpr(s32) = COPY $w1
330    %mask:gpr(s32) = G_CONSTANT i32 42
331    %ext:gpr(s32) = G_AND %1(s32), %mask
332    %add_lhs:gpr(s32) = COPY $w2
333    %res:gpr(s32) = G_ADD %add_lhs, %ext
334    $w3 = COPY %res(s32)
335    RET_ReallyLR implicit $w3
336...
337---
338name:            dont_fold_invalid_shl
339alignment:       4
340legalized:       true
341regBankSelected: true
342tracksRegLiveness: true
343machineFunctionInfo: {}
344body:             |
345  bb.0:
346    liveins: $w1, $w2, $x2
347    ; CHECK-LABEL: name: dont_fold_invalid_shl
348    ; CHECK: liveins: $w1, $w2, $x2
349    ; CHECK: %wide_1:gpr32 = COPY $w1
350    ; CHECK: %ext:gpr32 = SBFMWri %wide_1, 0, 15
351    ; CHECK: %add_lhs:gpr32 = COPY $w2
352    ; CHECK: %res:gpr32 = ADDWrs %add_lhs, %ext, 5
353    ; CHECK: $w3 = COPY %res
354    ; CHECK: RET_ReallyLR implicit $w3
355    %wide_1:gpr(s32) = COPY $w1
356    %1:gpr(s16) = G_TRUNC %wide_1
357    %ext:gpr(s32) = G_SEXT %1(s16)
358    %imm:gpr(s32) = G_CONSTANT i32 5
359    %shl:gpr(s32) = G_SHL %ext, %imm
360    %add_lhs:gpr(s32) = COPY $w2
361    %res:gpr(s32) = G_ADD %add_lhs, %shl
362    $w3 = COPY %res(s32)
363    RET_ReallyLR implicit $w3
364...
365---
366name:            sub_sext_s32_to_s64
367alignment:       4
368legalized:       true
369regBankSelected: true
370tracksRegLiveness: true
371machineFunctionInfo: {}
372body:             |
373  bb.0:
374    liveins: $w1, $x2
375    ; CHECK-LABEL: name: sub_sext_s32_to_s64
376    ; CHECK: liveins: $w1, $x2
377    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
378    ; CHECK: %sub_lhs:gpr64sp = COPY $x2
379    ; CHECK: %res:gpr64 = SUBSXrx %sub_lhs, [[COPY]], 48, implicit-def $nzcv
380    ; CHECK: $x3 = COPY %res
381    ; CHECK: RET_ReallyLR implicit $x3
382    %1:gpr(s32) = COPY $w1
383    %ext:gpr(s64) = G_SEXT %1(s32)
384    %sub_lhs:gpr(s64) = COPY $x2
385    %res:gpr(s64) = G_SUB %sub_lhs, %ext
386    $x3 = COPY %res(s64)
387    RET_ReallyLR implicit $x3
388...
389---
390name:            sub_sext_s16_to_s32
391alignment:       4
392legalized:       true
393regBankSelected: true
394tracksRegLiveness: true
395machineFunctionInfo: {}
396body:             |
397  bb.0:
398    liveins: $w1, $w2, $x2
399    ; CHECK-LABEL: name: sub_sext_s16_to_s32
400    ; CHECK: liveins: $w1, $w2, $x2
401    ; CHECK: %wide_1:gpr32 = COPY $w1
402    ; CHECK: %sub_lhs:gpr32sp = COPY $w2
403    ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 40, implicit-def $nzcv
404    ; CHECK: $w3 = COPY %res
405    ; CHECK: RET_ReallyLR implicit $w3
406    %wide_1:gpr(s32) = COPY $w1
407    %1:gpr(s16) = G_TRUNC %wide_1
408    %ext:gpr(s32) = G_SEXT %1(s16)
409    %sub_lhs:gpr(s32) = COPY $w2
410    %res:gpr(s32) = G_SUB %sub_lhs, %ext
411    $w3 = COPY %res(s32)
412    RET_ReallyLR implicit $w3
413...
414---
415name:            sub_zext_s16_to_s32
416alignment:       4
417legalized:       true
418regBankSelected: true
419tracksRegLiveness: true
420machineFunctionInfo: {}
421body:             |
422  bb.0:
423    liveins: $w1, $w2, $x2
424    ; CHECK-LABEL: name: sub_zext_s16_to_s32
425    ; CHECK: liveins: $w1, $w2, $x2
426    ; CHECK: %wide_1:gpr32 = COPY $w1
427    ; CHECK: %sub_lhs:gpr32sp = COPY $w2
428    ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 8, implicit-def $nzcv
429    ; CHECK: $w3 = COPY %res
430    ; CHECK: RET_ReallyLR implicit $w3
431    %wide_1:gpr(s32) = COPY $w1
432    %1:gpr(s16) = G_TRUNC %wide_1
433    %ext:gpr(s32) = G_ZEXT %1(s16)
434    %sub_lhs:gpr(s32) = COPY $w2
435    %res:gpr(s32) = G_SUB %sub_lhs, %ext
436    $w3 = COPY %res(s32)
437    RET_ReallyLR implicit $w3
438...
439---
440name:            sub_anyext_s16_to_s32
441alignment:       4
442legalized:       true
443regBankSelected: true
444tracksRegLiveness: true
445machineFunctionInfo: {}
446body:             |
447  bb.0:
448    liveins: $w1, $w2, $x2
449    ; CHECK-LABEL: name: sub_anyext_s16_to_s32
450    ; CHECK: liveins: $w1, $w2, $x2
451    ; CHECK: %wide_1:gpr32 = COPY $w1
452    ; CHECK: %sub_lhs:gpr32sp = COPY $w2
453    ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 8, implicit-def $nzcv
454    ; CHECK: $w3 = COPY %res
455    ; CHECK: RET_ReallyLR implicit $w3
456    %wide_1:gpr(s32) = COPY $w1
457    %1:gpr(s16) = G_TRUNC %wide_1
458    %ext:gpr(s32) = G_ANYEXT %1(s16)
459    %sub_lhs:gpr(s32) = COPY $w2
460    %res:gpr(s32) = G_SUB %sub_lhs, %ext
461    $w3 = COPY %res(s32)
462    RET_ReallyLR implicit $w3
463...
464---
465name:            sub_and_s16_to_s32_uxtb
466alignment:       4
467legalized:       true
468regBankSelected: true
469tracksRegLiveness: true
470machineFunctionInfo: {}
471body:             |
472  bb.0:
473    liveins: $w1, $w2, $x2
474    ; CHECK-LABEL: name: sub_and_s16_to_s32_uxtb
475    ; CHECK: liveins: $w1, $w2, $x2
476    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
477    ; CHECK: %sub_lhs:gpr32sp = COPY $w2
478    ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 0, implicit-def $nzcv
479    ; CHECK: $w3 = COPY %res
480    ; CHECK: RET_ReallyLR implicit $w3
481    %1:gpr(s32) = COPY $w1
482    %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff
483    %ext:gpr(s32) = G_AND %1(s32), %mask
484    %sub_lhs:gpr(s32) = COPY $w2
485    %res:gpr(s32) = G_SUB %sub_lhs, %ext
486    $w3 = COPY %res(s32)
487    RET_ReallyLR implicit $w3
488...
489---
490name:            sub_and_s16_to_s32_uxth
491alignment:       4
492legalized:       true
493regBankSelected: true
494tracksRegLiveness: true
495machineFunctionInfo: {}
496body:             |
497  bb.0:
498    liveins: $w1, $w2, $x2
499    ; CHECK-LABEL: name: sub_and_s16_to_s32_uxth
500    ; CHECK: liveins: $w1, $w2, $x2
501    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
502    ; CHECK: %sub_lhs:gpr32sp = COPY $w2
503    ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 8, implicit-def $nzcv
504    ; CHECK: $w3 = COPY %res
505    ; CHECK: RET_ReallyLR implicit $w3
506    %1:gpr(s32) = COPY $w1
507    %mask:gpr(s32) = G_CONSTANT i32 65535 ; 0xffff
508    %ext:gpr(s32) = G_AND %1(s32), %mask
509    %sub_lhs:gpr(s32) = COPY $w2
510    %res:gpr(s32) = G_SUB %sub_lhs, %ext
511    $w3 = COPY %res(s32)
512    RET_ReallyLR implicit $w3
513---
514name:            sub_sext_s8_to_s32
515alignment:       4
516legalized:       true
517regBankSelected: true
518tracksRegLiveness: true
519machineFunctionInfo: {}
520body:             |
521  bb.0:
522    liveins: $w1, $w2, $x2
523    %wide_1:gpr(s32) = COPY $w1
524    %1:gpr(s8) = G_TRUNC %wide_1
525    %ext:gpr(s32) = G_SEXT %1(s8)
526    %sub_lhs:gpr(s32) = COPY $w2
527    %res:gpr(s32) = G_SUB %sub_lhs, %ext
528    $w3 = COPY %res(s32)
529    RET_ReallyLR implicit $w3
530...
531---
532name:            sub_zext_s8_to_s32
533alignment:       4
534legalized:       true
535regBankSelected: true
536tracksRegLiveness: true
537machineFunctionInfo: {}
538body:             |
539  bb.0:
540    liveins: $w1, $w2, $x2
541    ; CHECK-LABEL: name: sub_zext_s8_to_s32
542    ; CHECK: liveins: $w1, $w2, $x2
543    ; CHECK: %wide_1:gpr32 = COPY $w1
544    ; CHECK: %sub_lhs:gpr32sp = COPY $w2
545    ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 0, implicit-def $nzcv
546    ; CHECK: $w3 = COPY %res
547    ; CHECK: RET_ReallyLR implicit $w3
548    %wide_1:gpr(s32) = COPY $w1
549    %1:gpr(s8) = G_TRUNC %wide_1
550    %ext:gpr(s32) = G_ZEXT %1(s8)
551    %sub_lhs:gpr(s32) = COPY $w2
552    %res:gpr(s32) = G_SUB %sub_lhs, %ext
553    $w3 = COPY %res(s32)
554    RET_ReallyLR implicit $w3
555...
556---
557name:            sub_anyext_s8_to_s32
558alignment:       4
559legalized:       true
560regBankSelected: true
561tracksRegLiveness: true
562machineFunctionInfo: {}
563body:             |
564  bb.0:
565    liveins: $w1, $w2, $x2
566    ; CHECK-LABEL: name: sub_anyext_s8_to_s32
567    ; CHECK: liveins: $w1, $w2, $x2
568    ; CHECK: %wide_1:gpr32 = COPY $w1
569    ; CHECK: %sub_lhs:gpr32sp = COPY $w2
570    ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 0, implicit-def $nzcv
571    ; CHECK: $w3 = COPY %res
572    ; CHECK: RET_ReallyLR implicit $w3
573    %wide_1:gpr(s32) = COPY $w1
574    %1:gpr(s8) = G_TRUNC %wide_1
575    %ext:gpr(s32) = G_ANYEXT %1(s8)
576    %sub_lhs:gpr(s32) = COPY $w2
577    %res:gpr(s32) = G_SUB %sub_lhs, %ext
578    $w3 = COPY %res(s32)
579    RET_ReallyLR implicit $w3
580---
581...
582---
583name:            sub_sext_with_shl
584alignment:       4
585legalized:       true
586regBankSelected: true
587tracksRegLiveness: true
588machineFunctionInfo: {}
589body:             |
590  bb.0:
591    liveins: $w1, $w2, $x2
592    ; CHECK-LABEL: name: sub_sext_with_shl
593    ; CHECK: liveins: $w1, $w2, $x2
594    ; CHECK: %wide_1:gpr32 = COPY $w1
595    ; CHECK: %sub_lhs:gpr32sp = COPY $w2
596    ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 43, implicit-def $nzcv
597    ; CHECK: $w3 = COPY %res
598    ; CHECK: RET_ReallyLR implicit $w3
599    %wide_1:gpr(s32) = COPY $w1
600    %1:gpr(s16) = G_TRUNC %wide_1
601    %ext:gpr(s32) = G_SEXT %1(s16)
602    %imm:gpr(s32) = G_CONSTANT i32 3
603    %shl:gpr(s32) = G_SHL %ext, %imm
604    %sub_lhs:gpr(s32) = COPY $w2
605    %res:gpr(s32) = G_SUB %sub_lhs, %shl
606    $w3 = COPY %res(s32)
607    RET_ReallyLR implicit $w3
608...
609---
610name:            sub_and_with_shl
611alignment:       4
612legalized:       true
613regBankSelected: true
614tracksRegLiveness: true
615machineFunctionInfo: {}
616body:             |
617  bb.0:
618    liveins: $w1, $w2, $x2
619    ; CHECK-LABEL: name: sub_and_with_shl
620    ; CHECK: liveins: $w1, $w2, $x2
621    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
622    ; CHECK: %sub_lhs:gpr32sp = COPY $w2
623    ; CHECK: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 3, implicit-def $nzcv
624    ; CHECK: $w3 = COPY %res
625    ; CHECK: RET_ReallyLR implicit $w3
626    %1:gpr(s32) = COPY $w1
627    %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff
628    %ext:gpr(s32) = G_AND %1(s32), %mask
629    %imm:gpr(s32) = G_CONSTANT i32 3
630    %shl:gpr(s32) = G_SHL %ext, %imm
631    %sub_lhs:gpr(s32) = COPY $w2
632    %res:gpr(s32) = G_SUB %sub_lhs, %shl
633    $w3 = COPY %res(s32)
634    RET_ReallyLR implicit $w3
635