1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s 3 4define i1 @t32_3_1(i32 %X) nounwind { 5; CHECK-LABEL: t32_3_1: 6; CHECK: // %bb.0: 7; CHECK-NEXT: mov w8, #43691 8; CHECK-NEXT: movk w8, #43690, lsl #16 9; CHECK-NEXT: mov w9, #1431655765 10; CHECK-NEXT: madd w8, w0, w8, w9 11; CHECK-NEXT: cmp w8, w9 12; CHECK-NEXT: cset w0, lo 13; CHECK-NEXT: ret 14 %urem = urem i32 %X, 3 15 %cmp = icmp eq i32 %urem, 1 16 ret i1 %cmp 17} 18 19define i1 @t32_3_2(i32 %X) nounwind { 20; CHECK-LABEL: t32_3_2: 21; CHECK: // %bb.0: 22; CHECK-NEXT: mov w8, #43691 23; CHECK-NEXT: movk w8, #43690, lsl #16 24; CHECK-NEXT: mov w9, #-1431655766 25; CHECK-NEXT: madd w8, w0, w8, w9 26; CHECK-NEXT: mov w9, #1431655765 27; CHECK-NEXT: cmp w8, w9 28; CHECK-NEXT: cset w0, lo 29; CHECK-NEXT: ret 30 %urem = urem i32 %X, 3 31 %cmp = icmp eq i32 %urem, 2 32 ret i1 %cmp 33} 34 35 36define i1 @t32_5_1(i32 %X) nounwind { 37; CHECK-LABEL: t32_5_1: 38; CHECK: // %bb.0: 39; CHECK-NEXT: mov w8, #52429 40; CHECK-NEXT: movk w8, #52428, lsl #16 41; CHECK-NEXT: mov w9, #858993459 42; CHECK-NEXT: madd w8, w0, w8, w9 43; CHECK-NEXT: cmp w8, w9 44; CHECK-NEXT: cset w0, lo 45; CHECK-NEXT: ret 46 %urem = urem i32 %X, 5 47 %cmp = icmp eq i32 %urem, 1 48 ret i1 %cmp 49} 50 51define i1 @t32_5_2(i32 %X) nounwind { 52; CHECK-LABEL: t32_5_2: 53; CHECK: // %bb.0: 54; CHECK-NEXT: mov w8, #52429 55; CHECK-NEXT: movk w8, #52428, lsl #16 56; CHECK-NEXT: mov w9, #1717986918 57; CHECK-NEXT: madd w8, w0, w8, w9 58; CHECK-NEXT: mov w9, #858993459 59; CHECK-NEXT: cmp w8, w9 60; CHECK-NEXT: cset w0, lo 61; CHECK-NEXT: ret 62 %urem = urem i32 %X, 5 63 %cmp = icmp eq i32 %urem, 2 64 ret i1 %cmp 65} 66 67define i1 @t32_5_3(i32 %X) nounwind { 68; CHECK-LABEL: t32_5_3: 69; CHECK: // %bb.0: 70; CHECK-NEXT: mov w8, #52429 71; CHECK-NEXT: movk w8, #52428, lsl #16 72; CHECK-NEXT: mov w9, #-1717986919 73; CHECK-NEXT: madd w8, w0, w8, w9 74; CHECK-NEXT: mov w9, #858993459 75; CHECK-NEXT: cmp w8, w9 76; CHECK-NEXT: cset w0, lo 77; CHECK-NEXT: ret 78 %urem = urem i32 %X, 5 79 %cmp = icmp eq i32 %urem, 3 80 ret i1 %cmp 81} 82 83define i1 @t32_5_4(i32 %X) nounwind { 84; CHECK-LABEL: t32_5_4: 85; CHECK: // %bb.0: 86; CHECK-NEXT: mov w8, #52429 87; CHECK-NEXT: movk w8, #52428, lsl #16 88; CHECK-NEXT: mov w9, #-858993460 89; CHECK-NEXT: madd w8, w0, w8, w9 90; CHECK-NEXT: mov w9, #858993459 91; CHECK-NEXT: cmp w8, w9 92; CHECK-NEXT: cset w0, lo 93; CHECK-NEXT: ret 94 %urem = urem i32 %X, 5 95 %cmp = icmp eq i32 %urem, 4 96 ret i1 %cmp 97} 98 99 100define i1 @t32_6_1(i32 %X) nounwind { 101; CHECK-LABEL: t32_6_1: 102; CHECK: // %bb.0: 103; CHECK-NEXT: mov w8, #43691 104; CHECK-NEXT: movk w8, #43690, lsl #16 105; CHECK-NEXT: mov w9, #1431655765 106; CHECK-NEXT: madd w8, w0, w8, w9 107; CHECK-NEXT: mov w9, #43691 108; CHECK-NEXT: ror w8, w8, #1 109; CHECK-NEXT: movk w9, #10922, lsl #16 110; CHECK-NEXT: cmp w8, w9 111; CHECK-NEXT: cset w0, lo 112; CHECK-NEXT: ret 113 %urem = urem i32 %X, 6 114 %cmp = icmp eq i32 %urem, 1 115 ret i1 %cmp 116} 117 118define i1 @t32_6_2(i32 %X) nounwind { 119; CHECK-LABEL: t32_6_2: 120; CHECK: // %bb.0: 121; CHECK-NEXT: mov w8, #43691 122; CHECK-NEXT: movk w8, #43690, lsl #16 123; CHECK-NEXT: mov w9, #-1431655766 124; CHECK-NEXT: madd w8, w0, w8, w9 125; CHECK-NEXT: mov w9, #43691 126; CHECK-NEXT: ror w8, w8, #1 127; CHECK-NEXT: movk w9, #10922, lsl #16 128; CHECK-NEXT: cmp w8, w9 129; CHECK-NEXT: cset w0, lo 130; CHECK-NEXT: ret 131 %urem = urem i32 %X, 6 132 %cmp = icmp eq i32 %urem, 2 133 ret i1 %cmp 134} 135 136define i1 @t32_6_3(i32 %X) nounwind { 137; CHECK-LABEL: t32_6_3: 138; CHECK: // %bb.0: 139; CHECK-NEXT: mov w8, #43691 140; CHECK-NEXT: movk w8, #43690, lsl #16 141; CHECK-NEXT: mul w8, w0, w8 142; CHECK-NEXT: sub w8, w8, #1 // =1 143; CHECK-NEXT: mov w9, #43691 144; CHECK-NEXT: ror w8, w8, #1 145; CHECK-NEXT: movk w9, #10922, lsl #16 146; CHECK-NEXT: cmp w8, w9 147; CHECK-NEXT: cset w0, lo 148; CHECK-NEXT: ret 149 %urem = urem i32 %X, 6 150 %cmp = icmp eq i32 %urem, 3 151 ret i1 %cmp 152} 153 154define i1 @t32_6_4(i32 %X) nounwind { 155; CHECK-LABEL: t32_6_4: 156; CHECK: // %bb.0: 157; CHECK-NEXT: mov w8, #43691 158; CHECK-NEXT: mov w9, #21844 159; CHECK-NEXT: movk w8, #43690, lsl #16 160; CHECK-NEXT: movk w9, #21845, lsl #16 161; CHECK-NEXT: madd w8, w0, w8, w9 162; CHECK-NEXT: mov w9, #43690 163; CHECK-NEXT: ror w8, w8, #1 164; CHECK-NEXT: movk w9, #10922, lsl #16 165; CHECK-NEXT: cmp w8, w9 166; CHECK-NEXT: cset w0, lo 167; CHECK-NEXT: ret 168 %urem = urem i32 %X, 6 169 %cmp = icmp eq i32 %urem, 4 170 ret i1 %cmp 171} 172 173define i1 @t32_6_5(i32 %X) nounwind { 174; CHECK-LABEL: t32_6_5: 175; CHECK: // %bb.0: 176; CHECK-NEXT: mov w8, #43691 177; CHECK-NEXT: mov w9, #43689 178; CHECK-NEXT: movk w8, #43690, lsl #16 179; CHECK-NEXT: movk w9, #43690, lsl #16 180; CHECK-NEXT: madd w8, w0, w8, w9 181; CHECK-NEXT: mov w9, #43690 182; CHECK-NEXT: ror w8, w8, #1 183; CHECK-NEXT: movk w9, #10922, lsl #16 184; CHECK-NEXT: cmp w8, w9 185; CHECK-NEXT: cset w0, lo 186; CHECK-NEXT: ret 187 %urem = urem i32 %X, 6 188 %cmp = icmp eq i32 %urem, 5 189 ret i1 %cmp 190} 191 192;------------------------------------------------------------------------------- 193; Other widths. 194 195define i1 @t16_3_2(i16 %X) nounwind { 196; CHECK-LABEL: t16_3_2: 197; CHECK: // %bb.0: 198; CHECK-NEXT: mov w9, #43691 199; CHECK-NEXT: and w8, w0, #0xffff 200; CHECK-NEXT: movk w9, #43690, lsl #16 201; CHECK-NEXT: mov w10, #-1431655766 202; CHECK-NEXT: madd w8, w8, w9, w10 203; CHECK-NEXT: mov w9, #1431655765 204; CHECK-NEXT: cmp w8, w9 205; CHECK-NEXT: cset w0, lo 206; CHECK-NEXT: ret 207 %urem = urem i16 %X, 3 208 %cmp = icmp eq i16 %urem, 2 209 ret i1 %cmp 210} 211 212define i1 @t8_3_2(i8 %X) nounwind { 213; CHECK-LABEL: t8_3_2: 214; CHECK: // %bb.0: 215; CHECK-NEXT: mov w9, #43691 216; CHECK-NEXT: and w8, w0, #0xff 217; CHECK-NEXT: movk w9, #43690, lsl #16 218; CHECK-NEXT: mov w10, #-1431655766 219; CHECK-NEXT: madd w8, w8, w9, w10 220; CHECK-NEXT: mov w9, #1431655765 221; CHECK-NEXT: cmp w8, w9 222; CHECK-NEXT: cset w0, lo 223; CHECK-NEXT: ret 224 %urem = urem i8 %X, 3 225 %cmp = icmp eq i8 %urem, 2 226 ret i1 %cmp 227} 228 229define i1 @t64_3_2(i64 %X) nounwind { 230; CHECK-LABEL: t64_3_2: 231; CHECK: // %bb.0: 232; CHECK-NEXT: mov x8, #-6148914691236517206 233; CHECK-NEXT: movk x8, #43691 234; CHECK-NEXT: mov x9, #-6148914691236517206 235; CHECK-NEXT: madd x8, x0, x8, x9 236; CHECK-NEXT: mov x9, #6148914691236517205 237; CHECK-NEXT: cmp x8, x9 238; CHECK-NEXT: cset w0, lo 239; CHECK-NEXT: ret 240 %urem = urem i64 %X, 3 241 %cmp = icmp eq i64 %urem, 2 242 ret i1 %cmp 243} 244