1; RUN: llc < %s -march=amdgcn | FileCheck %s -check-prefix=SI -check-prefix=FUNC
2; RUN: llc < %s -march=amdgcn -mcpu=tonga | FileCheck %s -check-prefix=SI -check-prefix=FUNC
3; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -check-prefix=EG -check-prefix=FUNC
4
5;FUNC-LABEL: test
6;EG: MULADD_IEEE *
7;EG: FRACT *
8;EG: ADD *
9;EG: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
10;EG-NOT: COS
11;SI: v_cos_f32
12;SI-NOT: v_cos_f32
13
14define amdgpu_kernel void @test(float addrspace(1)* %out, float %x) #1 {
15   %cos = call float @llvm.cos.f32(float %x)
16   store float %cos, float addrspace(1)* %out
17   ret void
18}
19
20;FUNC-LABEL: testv
21;EG: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
22;EG: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
23;EG: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
24;EG: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
25;EG-NOT: COS
26;SI: v_cos_f32
27;SI: v_cos_f32
28;SI: v_cos_f32
29;SI: v_cos_f32
30;SI-NOT: v_cos_f32
31
32define amdgpu_kernel void @testv(<4 x float> addrspace(1)* %out, <4 x float> inreg %vx) #1 {
33   %cos = call <4 x float> @llvm.cos.v4f32(<4 x float> %vx)
34   store <4 x float> %cos, <4 x float> addrspace(1)* %out
35   ret void
36}
37
38declare float @llvm.cos.f32(float) readnone
39declare <4 x float> @llvm.cos.v4f32(<4 x float>) readnone
40