1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file is part of the X86 Disassembler Emitter.
10 // It contains the implementation of a single recognizable instruction.
11 // Documentation for the disassembler emitter in general can be found in
12 // X86DisassemblerEmitter.h.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #include "X86RecognizableInstr.h"
17 #include "X86DisassemblerShared.h"
18 #include "X86ModRMFilters.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include <string>
21
22 using namespace llvm;
23 using namespace X86Disassembler;
24
25 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
26 /// Useful for switch statements and the like.
27 ///
28 /// @param init - A reference to the BitsInit to be decoded.
29 /// @return - The field, with the first bit in the BitsInit as the lowest
30 /// order bit.
byteFromBitsInit(BitsInit & init)31 static uint8_t byteFromBitsInit(BitsInit &init) {
32 int width = init.getNumBits();
33
34 assert(width <= 8 && "Field is too large for uint8_t!");
35
36 int index;
37 uint8_t mask = 0x01;
38
39 uint8_t ret = 0;
40
41 for (index = 0; index < width; index++) {
42 if (cast<BitInit>(init.getBit(index))->getValue())
43 ret |= mask;
44
45 mask <<= 1;
46 }
47
48 return ret;
49 }
50
51 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
52 /// name of the field.
53 ///
54 /// @param rec - The record from which to extract the value.
55 /// @param name - The name of the field in the record.
56 /// @return - The field, as translated by byteFromBitsInit().
byteFromRec(const Record * rec,StringRef name)57 static uint8_t byteFromRec(const Record* rec, StringRef name) {
58 BitsInit* bits = rec->getValueAsBitsInit(name);
59 return byteFromBitsInit(*bits);
60 }
61
RecognizableInstr(DisassemblerTables & tables,const CodeGenInstruction & insn,InstrUID uid)62 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
63 const CodeGenInstruction &insn,
64 InstrUID uid) {
65 UID = uid;
66
67 Rec = insn.TheDef;
68 Name = std::string(Rec->getName());
69 Spec = &tables.specForUID(UID);
70
71 if (!Rec->isSubClassOf("X86Inst")) {
72 ShouldBeEmitted = false;
73 return;
74 }
75
76 OpPrefix = byteFromRec(Rec, "OpPrefixBits");
77 OpMap = byteFromRec(Rec, "OpMapBits");
78 Opcode = byteFromRec(Rec, "Opcode");
79 Form = byteFromRec(Rec, "FormBits");
80 Encoding = byteFromRec(Rec, "OpEncBits");
81
82 OpSize = byteFromRec(Rec, "OpSizeBits");
83 AdSize = byteFromRec(Rec, "AdSizeBits");
84 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
85 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
86 HasVEX_W = Rec->getValueAsBit("HasVEX_W");
87 IgnoresVEX_W = Rec->getValueAsBit("IgnoresVEX_W");
88 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
89 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
90 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
91 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
92 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
93 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
94 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
95 CD8_Scale = byteFromRec(Rec, "CD8_Scale");
96
97 Name = std::string(Rec->getName());
98
99 Operands = &insn.Operands.OperandList;
100
101 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
102
103 EncodeRC = HasEVEX_B &&
104 (Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg);
105
106 // Check for 64-bit inst which does not require REX
107 Is32Bit = false;
108 Is64Bit = false;
109 // FIXME: Is there some better way to check for In64BitMode?
110 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
111 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
112 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
113 Predicates[i]->getName().find("In32Bit") != Name.npos) {
114 Is32Bit = true;
115 break;
116 }
117 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
118 Is64Bit = true;
119 break;
120 }
121 }
122
123 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) {
124 ShouldBeEmitted = false;
125 return;
126 }
127
128 // Special case since there is no attribute class for 64-bit and VEX
129 if (Name == "VMASKMOVDQU64") {
130 ShouldBeEmitted = false;
131 return;
132 }
133
134 ShouldBeEmitted = true;
135 }
136
processInstr(DisassemblerTables & tables,const CodeGenInstruction & insn,InstrUID uid)137 void RecognizableInstr::processInstr(DisassemblerTables &tables,
138 const CodeGenInstruction &insn,
139 InstrUID uid)
140 {
141 // Ignore "asm parser only" instructions.
142 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
143 return;
144
145 RecognizableInstr recogInstr(tables, insn, uid);
146
147 if (recogInstr.shouldBeEmitted()) {
148 recogInstr.emitInstructionSpecifier();
149 recogInstr.emitDecodePath(tables);
150 }
151 }
152
153 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
154 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
155 (HasEVEX_KZ ? n##_KZ : \
156 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
157
insnContext() const158 InstructionContext RecognizableInstr::insnContext() const {
159 InstructionContext insnContext;
160
161 if (Encoding == X86Local::EVEX) {
162 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
163 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
164 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
165 }
166 // VEX_L & VEX_W
167 if (!EncodeRC && HasVEX_LPrefix && HasVEX_W) {
168 if (OpPrefix == X86Local::PD)
169 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
170 else if (OpPrefix == X86Local::XS)
171 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
172 else if (OpPrefix == X86Local::XD)
173 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
174 else if (OpPrefix == X86Local::PS)
175 insnContext = EVEX_KB(IC_EVEX_L_W);
176 else {
177 errs() << "Instruction does not use a prefix: " << Name << "\n";
178 llvm_unreachable("Invalid prefix");
179 }
180 } else if (!EncodeRC && HasVEX_LPrefix) {
181 // VEX_L
182 if (OpPrefix == X86Local::PD)
183 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
184 else if (OpPrefix == X86Local::XS)
185 insnContext = EVEX_KB(IC_EVEX_L_XS);
186 else if (OpPrefix == X86Local::XD)
187 insnContext = EVEX_KB(IC_EVEX_L_XD);
188 else if (OpPrefix == X86Local::PS)
189 insnContext = EVEX_KB(IC_EVEX_L);
190 else {
191 errs() << "Instruction does not use a prefix: " << Name << "\n";
192 llvm_unreachable("Invalid prefix");
193 }
194 } else if (!EncodeRC && HasEVEX_L2Prefix && HasVEX_W) {
195 // EVEX_L2 & VEX_W
196 if (OpPrefix == X86Local::PD)
197 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
198 else if (OpPrefix == X86Local::XS)
199 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
200 else if (OpPrefix == X86Local::XD)
201 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
202 else if (OpPrefix == X86Local::PS)
203 insnContext = EVEX_KB(IC_EVEX_L2_W);
204 else {
205 errs() << "Instruction does not use a prefix: " << Name << "\n";
206 llvm_unreachable("Invalid prefix");
207 }
208 } else if (!EncodeRC && HasEVEX_L2Prefix) {
209 // EVEX_L2
210 if (OpPrefix == X86Local::PD)
211 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
212 else if (OpPrefix == X86Local::XD)
213 insnContext = EVEX_KB(IC_EVEX_L2_XD);
214 else if (OpPrefix == X86Local::XS)
215 insnContext = EVEX_KB(IC_EVEX_L2_XS);
216 else if (OpPrefix == X86Local::PS)
217 insnContext = EVEX_KB(IC_EVEX_L2);
218 else {
219 errs() << "Instruction does not use a prefix: " << Name << "\n";
220 llvm_unreachable("Invalid prefix");
221 }
222 }
223 else if (HasVEX_W) {
224 // VEX_W
225 if (OpPrefix == X86Local::PD)
226 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
227 else if (OpPrefix == X86Local::XS)
228 insnContext = EVEX_KB(IC_EVEX_W_XS);
229 else if (OpPrefix == X86Local::XD)
230 insnContext = EVEX_KB(IC_EVEX_W_XD);
231 else if (OpPrefix == X86Local::PS)
232 insnContext = EVEX_KB(IC_EVEX_W);
233 else {
234 errs() << "Instruction does not use a prefix: " << Name << "\n";
235 llvm_unreachable("Invalid prefix");
236 }
237 }
238 // No L, no W
239 else if (OpPrefix == X86Local::PD)
240 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
241 else if (OpPrefix == X86Local::XD)
242 insnContext = EVEX_KB(IC_EVEX_XD);
243 else if (OpPrefix == X86Local::XS)
244 insnContext = EVEX_KB(IC_EVEX_XS);
245 else if (OpPrefix == X86Local::PS)
246 insnContext = EVEX_KB(IC_EVEX);
247 else {
248 errs() << "Instruction does not use a prefix: " << Name << "\n";
249 llvm_unreachable("Invalid prefix");
250 }
251 /// eof EVEX
252 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) {
253 if (HasVEX_LPrefix && HasVEX_W) {
254 if (OpPrefix == X86Local::PD)
255 insnContext = IC_VEX_L_W_OPSIZE;
256 else if (OpPrefix == X86Local::XS)
257 insnContext = IC_VEX_L_W_XS;
258 else if (OpPrefix == X86Local::XD)
259 insnContext = IC_VEX_L_W_XD;
260 else if (OpPrefix == X86Local::PS)
261 insnContext = IC_VEX_L_W;
262 else {
263 errs() << "Instruction does not use a prefix: " << Name << "\n";
264 llvm_unreachable("Invalid prefix");
265 }
266 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix)
267 insnContext = IC_VEX_L_OPSIZE;
268 else if (OpPrefix == X86Local::PD && HasVEX_W)
269 insnContext = IC_VEX_W_OPSIZE;
270 else if (OpPrefix == X86Local::PD)
271 insnContext = IC_VEX_OPSIZE;
272 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS)
273 insnContext = IC_VEX_L_XS;
274 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD)
275 insnContext = IC_VEX_L_XD;
276 else if (HasVEX_W && OpPrefix == X86Local::XS)
277 insnContext = IC_VEX_W_XS;
278 else if (HasVEX_W && OpPrefix == X86Local::XD)
279 insnContext = IC_VEX_W_XD;
280 else if (HasVEX_W && OpPrefix == X86Local::PS)
281 insnContext = IC_VEX_W;
282 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS)
283 insnContext = IC_VEX_L;
284 else if (OpPrefix == X86Local::XD)
285 insnContext = IC_VEX_XD;
286 else if (OpPrefix == X86Local::XS)
287 insnContext = IC_VEX_XS;
288 else if (OpPrefix == X86Local::PS)
289 insnContext = IC_VEX;
290 else {
291 errs() << "Instruction does not use a prefix: " << Name << "\n";
292 llvm_unreachable("Invalid prefix");
293 }
294 } else if (Is64Bit || HasREX_WPrefix || AdSize == X86Local::AdSize64) {
295 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
296 insnContext = IC_64BIT_REXW_OPSIZE;
297 else if (HasREX_WPrefix && AdSize == X86Local::AdSize32)
298 insnContext = IC_64BIT_REXW_ADSIZE;
299 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
300 insnContext = IC_64BIT_XD_OPSIZE;
301 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
302 insnContext = IC_64BIT_XS_OPSIZE;
303 else if (AdSize == X86Local::AdSize32 && OpPrefix == X86Local::PD)
304 insnContext = IC_64BIT_OPSIZE_ADSIZE;
305 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32)
306 insnContext = IC_64BIT_OPSIZE_ADSIZE;
307 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
308 insnContext = IC_64BIT_OPSIZE;
309 else if (AdSize == X86Local::AdSize32)
310 insnContext = IC_64BIT_ADSIZE;
311 else if (HasREX_WPrefix && OpPrefix == X86Local::XS)
312 insnContext = IC_64BIT_REXW_XS;
313 else if (HasREX_WPrefix && OpPrefix == X86Local::XD)
314 insnContext = IC_64BIT_REXW_XD;
315 else if (OpPrefix == X86Local::XD)
316 insnContext = IC_64BIT_XD;
317 else if (OpPrefix == X86Local::XS)
318 insnContext = IC_64BIT_XS;
319 else if (HasREX_WPrefix)
320 insnContext = IC_64BIT_REXW;
321 else
322 insnContext = IC_64BIT;
323 } else {
324 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
325 insnContext = IC_XD_OPSIZE;
326 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
327 insnContext = IC_XS_OPSIZE;
328 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XD)
329 insnContext = IC_XD_ADSIZE;
330 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XS)
331 insnContext = IC_XS_ADSIZE;
332 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::PD)
333 insnContext = IC_OPSIZE_ADSIZE;
334 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16)
335 insnContext = IC_OPSIZE_ADSIZE;
336 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
337 insnContext = IC_OPSIZE;
338 else if (AdSize == X86Local::AdSize16)
339 insnContext = IC_ADSIZE;
340 else if (OpPrefix == X86Local::XD)
341 insnContext = IC_XD;
342 else if (OpPrefix == X86Local::XS)
343 insnContext = IC_XS;
344 else
345 insnContext = IC;
346 }
347
348 return insnContext;
349 }
350
adjustOperandEncoding(OperandEncoding & encoding)351 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) {
352 // The scaling factor for AVX512 compressed displacement encoding is an
353 // instruction attribute. Adjust the ModRM encoding type to include the
354 // scale for compressed displacement.
355 if ((encoding != ENCODING_RM &&
356 encoding != ENCODING_VSIB &&
357 encoding != ENCODING_SIB) ||CD8_Scale == 0)
358 return;
359 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale));
360 assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) ||
361 (encoding == ENCODING_SIB) ||
362 (encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) &&
363 "Invalid CDisp scaling");
364 }
365
handleOperand(bool optional,unsigned & operandIndex,unsigned & physicalOperandIndex,unsigned numPhysicalOperands,const unsigned * operandMapping,OperandEncoding (* encodingFromString)(const std::string &,uint8_t OpSize))366 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
367 unsigned &physicalOperandIndex,
368 unsigned numPhysicalOperands,
369 const unsigned *operandMapping,
370 OperandEncoding (*encodingFromString)
371 (const std::string&,
372 uint8_t OpSize)) {
373 if (optional) {
374 if (physicalOperandIndex >= numPhysicalOperands)
375 return;
376 } else {
377 assert(physicalOperandIndex < numPhysicalOperands);
378 }
379
380 while (operandMapping[operandIndex] != operandIndex) {
381 Spec->operands[operandIndex].encoding = ENCODING_DUP;
382 Spec->operands[operandIndex].type =
383 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
384 ++operandIndex;
385 }
386
387 StringRef typeName = (*Operands)[operandIndex].Rec->getName();
388
389 OperandEncoding encoding = encodingFromString(std::string(typeName), OpSize);
390 // Adjust the encoding type for an operand based on the instruction.
391 adjustOperandEncoding(encoding);
392 Spec->operands[operandIndex].encoding = encoding;
393 Spec->operands[operandIndex].type =
394 typeFromString(std::string(typeName), HasREX_WPrefix, OpSize);
395
396 ++operandIndex;
397 ++physicalOperandIndex;
398 }
399
emitInstructionSpecifier()400 void RecognizableInstr::emitInstructionSpecifier() {
401 Spec->name = Name;
402
403 Spec->insnContext = insnContext();
404
405 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
406
407 unsigned numOperands = OperandList.size();
408 unsigned numPhysicalOperands = 0;
409
410 // operandMapping maps from operands in OperandList to their originals.
411 // If operandMapping[i] != i, then the entry is a duplicate.
412 unsigned operandMapping[X86_MAX_OPERANDS];
413 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
414
415 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
416 if (!OperandList[operandIndex].Constraints.empty()) {
417 const CGIOperandList::ConstraintInfo &Constraint =
418 OperandList[operandIndex].Constraints[0];
419 if (Constraint.isTied()) {
420 operandMapping[operandIndex] = operandIndex;
421 operandMapping[Constraint.getTiedOperand()] = operandIndex;
422 } else {
423 ++numPhysicalOperands;
424 operandMapping[operandIndex] = operandIndex;
425 }
426 } else {
427 ++numPhysicalOperands;
428 operandMapping[operandIndex] = operandIndex;
429 }
430 }
431
432 #define HANDLE_OPERAND(class) \
433 handleOperand(false, \
434 operandIndex, \
435 physicalOperandIndex, \
436 numPhysicalOperands, \
437 operandMapping, \
438 class##EncodingFromString);
439
440 #define HANDLE_OPTIONAL(class) \
441 handleOperand(true, \
442 operandIndex, \
443 physicalOperandIndex, \
444 numPhysicalOperands, \
445 operandMapping, \
446 class##EncodingFromString);
447
448 // operandIndex should always be < numOperands
449 unsigned operandIndex = 0;
450 // physicalOperandIndex should always be < numPhysicalOperands
451 unsigned physicalOperandIndex = 0;
452
453 #ifndef NDEBUG
454 // Given the set of prefix bits, how many additional operands does the
455 // instruction have?
456 unsigned additionalOperands = 0;
457 if (HasVEX_4V)
458 ++additionalOperands;
459 if (HasEVEX_K)
460 ++additionalOperands;
461 #endif
462
463 switch (Form) {
464 default: llvm_unreachable("Unhandled form");
465 case X86Local::PrefixByte:
466 return;
467 case X86Local::RawFrmSrc:
468 HANDLE_OPERAND(relocation);
469 return;
470 case X86Local::RawFrmDst:
471 HANDLE_OPERAND(relocation);
472 return;
473 case X86Local::RawFrmDstSrc:
474 HANDLE_OPERAND(relocation);
475 HANDLE_OPERAND(relocation);
476 return;
477 case X86Local::RawFrm:
478 // Operand 1 (optional) is an address or immediate.
479 assert(numPhysicalOperands <= 1 &&
480 "Unexpected number of operands for RawFrm");
481 HANDLE_OPTIONAL(relocation)
482 break;
483 case X86Local::RawFrmMemOffs:
484 // Operand 1 is an address.
485 HANDLE_OPERAND(relocation);
486 break;
487 case X86Local::AddRegFrm:
488 // Operand 1 is added to the opcode.
489 // Operand 2 (optional) is an address.
490 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
491 "Unexpected number of operands for AddRegFrm");
492 HANDLE_OPERAND(opcodeModifier)
493 HANDLE_OPTIONAL(relocation)
494 break;
495 case X86Local::AddCCFrm:
496 // Operand 1 (optional) is an address or immediate.
497 assert(numPhysicalOperands == 2 &&
498 "Unexpected number of operands for AddCCFrm");
499 HANDLE_OPERAND(relocation)
500 HANDLE_OPERAND(opcodeModifier)
501 break;
502 case X86Local::MRMDestReg:
503 // Operand 1 is a register operand in the R/M field.
504 // - In AVX512 there may be a mask operand here -
505 // Operand 2 is a register operand in the Reg/Opcode field.
506 // - In AVX, there is a register operand in the VEX.vvvv field here -
507 // Operand 3 (optional) is an immediate.
508 assert(numPhysicalOperands >= 2 + additionalOperands &&
509 numPhysicalOperands <= 3 + additionalOperands &&
510 "Unexpected number of operands for MRMDestRegFrm");
511
512 HANDLE_OPERAND(rmRegister)
513 if (HasEVEX_K)
514 HANDLE_OPERAND(writemaskRegister)
515
516 if (HasVEX_4V)
517 // FIXME: In AVX, the register below becomes the one encoded
518 // in ModRMVEX and the one above the one in the VEX.VVVV field
519 HANDLE_OPERAND(vvvvRegister)
520
521 HANDLE_OPERAND(roRegister)
522 HANDLE_OPTIONAL(immediate)
523 break;
524 case X86Local::MRMDestMem:
525 case X86Local::MRMDestMemFSIB:
526 // Operand 1 is a memory operand (possibly SIB-extended)
527 // Operand 2 is a register operand in the Reg/Opcode field.
528 // - In AVX, there is a register operand in the VEX.vvvv field here -
529 // Operand 3 (optional) is an immediate.
530 assert(numPhysicalOperands >= 2 + additionalOperands &&
531 numPhysicalOperands <= 3 + additionalOperands &&
532 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
533
534 HANDLE_OPERAND(memory)
535
536 if (HasEVEX_K)
537 HANDLE_OPERAND(writemaskRegister)
538
539 if (HasVEX_4V)
540 // FIXME: In AVX, the register below becomes the one encoded
541 // in ModRMVEX and the one above the one in the VEX.VVVV field
542 HANDLE_OPERAND(vvvvRegister)
543
544 HANDLE_OPERAND(roRegister)
545 HANDLE_OPTIONAL(immediate)
546 break;
547 case X86Local::MRMSrcReg:
548 // Operand 1 is a register operand in the Reg/Opcode field.
549 // Operand 2 is a register operand in the R/M field.
550 // - In AVX, there is a register operand in the VEX.vvvv field here -
551 // Operand 3 (optional) is an immediate.
552 // Operand 4 (optional) is an immediate.
553
554 assert(numPhysicalOperands >= 2 + additionalOperands &&
555 numPhysicalOperands <= 4 + additionalOperands &&
556 "Unexpected number of operands for MRMSrcRegFrm");
557
558 HANDLE_OPERAND(roRegister)
559
560 if (HasEVEX_K)
561 HANDLE_OPERAND(writemaskRegister)
562
563 if (HasVEX_4V)
564 // FIXME: In AVX, the register below becomes the one encoded
565 // in ModRMVEX and the one above the one in the VEX.VVVV field
566 HANDLE_OPERAND(vvvvRegister)
567
568 HANDLE_OPERAND(rmRegister)
569 HANDLE_OPTIONAL(immediate)
570 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
571 break;
572 case X86Local::MRMSrcReg4VOp3:
573 assert(numPhysicalOperands == 3 &&
574 "Unexpected number of operands for MRMSrcReg4VOp3Frm");
575 HANDLE_OPERAND(roRegister)
576 HANDLE_OPERAND(rmRegister)
577 HANDLE_OPERAND(vvvvRegister)
578 break;
579 case X86Local::MRMSrcRegOp4:
580 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 &&
581 "Unexpected number of operands for MRMSrcRegOp4Frm");
582 HANDLE_OPERAND(roRegister)
583 HANDLE_OPERAND(vvvvRegister)
584 HANDLE_OPERAND(immediate) // Register in imm[7:4]
585 HANDLE_OPERAND(rmRegister)
586 HANDLE_OPTIONAL(immediate)
587 break;
588 case X86Local::MRMSrcRegCC:
589 assert(numPhysicalOperands == 3 &&
590 "Unexpected number of operands for MRMSrcRegCC");
591 HANDLE_OPERAND(roRegister)
592 HANDLE_OPERAND(rmRegister)
593 HANDLE_OPERAND(opcodeModifier)
594 break;
595 case X86Local::MRMSrcMem:
596 case X86Local::MRMSrcMemFSIB:
597 // Operand 1 is a register operand in the Reg/Opcode field.
598 // Operand 2 is a memory operand (possibly SIB-extended)
599 // - In AVX, there is a register operand in the VEX.vvvv field here -
600 // Operand 3 (optional) is an immediate.
601
602 assert(numPhysicalOperands >= 2 + additionalOperands &&
603 numPhysicalOperands <= 4 + additionalOperands &&
604 "Unexpected number of operands for MRMSrcMemFrm");
605
606 HANDLE_OPERAND(roRegister)
607
608 if (HasEVEX_K)
609 HANDLE_OPERAND(writemaskRegister)
610
611 if (HasVEX_4V)
612 // FIXME: In AVX, the register below becomes the one encoded
613 // in ModRMVEX and the one above the one in the VEX.VVVV field
614 HANDLE_OPERAND(vvvvRegister)
615
616 HANDLE_OPERAND(memory)
617 HANDLE_OPTIONAL(immediate)
618 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
619 break;
620 case X86Local::MRMSrcMem4VOp3:
621 assert(numPhysicalOperands == 3 &&
622 "Unexpected number of operands for MRMSrcMem4VOp3Frm");
623 HANDLE_OPERAND(roRegister)
624 HANDLE_OPERAND(memory)
625 HANDLE_OPERAND(vvvvRegister)
626 break;
627 case X86Local::MRMSrcMemOp4:
628 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 &&
629 "Unexpected number of operands for MRMSrcMemOp4Frm");
630 HANDLE_OPERAND(roRegister)
631 HANDLE_OPERAND(vvvvRegister)
632 HANDLE_OPERAND(immediate) // Register in imm[7:4]
633 HANDLE_OPERAND(memory)
634 HANDLE_OPTIONAL(immediate)
635 break;
636 case X86Local::MRMSrcMemCC:
637 assert(numPhysicalOperands == 3 &&
638 "Unexpected number of operands for MRMSrcMemCC");
639 HANDLE_OPERAND(roRegister)
640 HANDLE_OPERAND(memory)
641 HANDLE_OPERAND(opcodeModifier)
642 break;
643 case X86Local::MRMXrCC:
644 assert(numPhysicalOperands == 2 &&
645 "Unexpected number of operands for MRMXrCC");
646 HANDLE_OPERAND(rmRegister)
647 HANDLE_OPERAND(opcodeModifier)
648 break;
649 case X86Local::MRMr0:
650 // Operand 1 is a register operand in the R/M field.
651 HANDLE_OPERAND(roRegister)
652 break;
653 case X86Local::MRMXr:
654 case X86Local::MRM0r:
655 case X86Local::MRM1r:
656 case X86Local::MRM2r:
657 case X86Local::MRM3r:
658 case X86Local::MRM4r:
659 case X86Local::MRM5r:
660 case X86Local::MRM6r:
661 case X86Local::MRM7r:
662 // Operand 1 is a register operand in the R/M field.
663 // Operand 2 (optional) is an immediate or relocation.
664 // Operand 3 (optional) is an immediate.
665 assert(numPhysicalOperands >= 0 + additionalOperands &&
666 numPhysicalOperands <= 3 + additionalOperands &&
667 "Unexpected number of operands for MRMnr");
668
669 if (HasVEX_4V)
670 HANDLE_OPERAND(vvvvRegister)
671
672 if (HasEVEX_K)
673 HANDLE_OPERAND(writemaskRegister)
674 HANDLE_OPTIONAL(rmRegister)
675 HANDLE_OPTIONAL(relocation)
676 HANDLE_OPTIONAL(immediate)
677 break;
678 case X86Local::MRMXmCC:
679 assert(numPhysicalOperands == 2 &&
680 "Unexpected number of operands for MRMXm");
681 HANDLE_OPERAND(memory)
682 HANDLE_OPERAND(opcodeModifier)
683 break;
684 case X86Local::MRMXm:
685 case X86Local::MRM0m:
686 case X86Local::MRM1m:
687 case X86Local::MRM2m:
688 case X86Local::MRM3m:
689 case X86Local::MRM4m:
690 case X86Local::MRM5m:
691 case X86Local::MRM6m:
692 case X86Local::MRM7m:
693 // Operand 1 is a memory operand (possibly SIB-extended)
694 // Operand 2 (optional) is an immediate or relocation.
695 assert(numPhysicalOperands >= 1 + additionalOperands &&
696 numPhysicalOperands <= 2 + additionalOperands &&
697 "Unexpected number of operands for MRMnm");
698
699 if (HasVEX_4V)
700 HANDLE_OPERAND(vvvvRegister)
701 if (HasEVEX_K)
702 HANDLE_OPERAND(writemaskRegister)
703 HANDLE_OPERAND(memory)
704 HANDLE_OPTIONAL(relocation)
705 break;
706 case X86Local::RawFrmImm8:
707 // operand 1 is a 16-bit immediate
708 // operand 2 is an 8-bit immediate
709 assert(numPhysicalOperands == 2 &&
710 "Unexpected number of operands for X86Local::RawFrmImm8");
711 HANDLE_OPERAND(immediate)
712 HANDLE_OPERAND(immediate)
713 break;
714 case X86Local::RawFrmImm16:
715 // operand 1 is a 16-bit immediate
716 // operand 2 is a 16-bit immediate
717 HANDLE_OPERAND(immediate)
718 HANDLE_OPERAND(immediate)
719 break;
720 case X86Local::MRM0X:
721 case X86Local::MRM1X:
722 case X86Local::MRM2X:
723 case X86Local::MRM3X:
724 case X86Local::MRM4X:
725 case X86Local::MRM5X:
726 case X86Local::MRM6X:
727 case X86Local::MRM7X:
728 #define MAP(from, to) case X86Local::MRM_##from:
729 X86_INSTR_MRM_MAPPING
730 #undef MAP
731 HANDLE_OPTIONAL(relocation)
732 break;
733 }
734
735 #undef HANDLE_OPERAND
736 #undef HANDLE_OPTIONAL
737 }
738
emitDecodePath(DisassemblerTables & tables) const739 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
740 // Special cases where the LLVM tables are not complete
741
742 #define MAP(from, to) \
743 case X86Local::MRM_##from:
744
745 llvm::Optional<OpcodeType> opcodeType;
746 switch (OpMap) {
747 default: llvm_unreachable("Invalid map!");
748 case X86Local::OB: opcodeType = ONEBYTE; break;
749 case X86Local::TB: opcodeType = TWOBYTE; break;
750 case X86Local::T8: opcodeType = THREEBYTE_38; break;
751 case X86Local::TA: opcodeType = THREEBYTE_3A; break;
752 case X86Local::XOP8: opcodeType = XOP8_MAP; break;
753 case X86Local::XOP9: opcodeType = XOP9_MAP; break;
754 case X86Local::XOPA: opcodeType = XOPA_MAP; break;
755 case X86Local::ThreeDNow: opcodeType = THREEDNOW_MAP; break;
756 }
757
758 std::unique_ptr<ModRMFilter> filter;
759 switch (Form) {
760 default: llvm_unreachable("Invalid form!");
761 case X86Local::Pseudo: llvm_unreachable("Pseudo should not be emitted!");
762 case X86Local::RawFrm:
763 case X86Local::AddRegFrm:
764 case X86Local::RawFrmMemOffs:
765 case X86Local::RawFrmSrc:
766 case X86Local::RawFrmDst:
767 case X86Local::RawFrmDstSrc:
768 case X86Local::RawFrmImm8:
769 case X86Local::RawFrmImm16:
770 case X86Local::AddCCFrm:
771 case X86Local::PrefixByte:
772 filter = std::make_unique<DumbFilter>();
773 break;
774 case X86Local::MRMDestReg:
775 case X86Local::MRMSrcReg:
776 case X86Local::MRMSrcReg4VOp3:
777 case X86Local::MRMSrcRegOp4:
778 case X86Local::MRMSrcRegCC:
779 case X86Local::MRMXrCC:
780 case X86Local::MRMXr:
781 filter = std::make_unique<ModFilter>(true);
782 break;
783 case X86Local::MRMDestMem:
784 case X86Local::MRMDestMemFSIB:
785 case X86Local::MRMSrcMem:
786 case X86Local::MRMSrcMemFSIB:
787 case X86Local::MRMSrcMem4VOp3:
788 case X86Local::MRMSrcMemOp4:
789 case X86Local::MRMSrcMemCC:
790 case X86Local::MRMXmCC:
791 case X86Local::MRMXm:
792 filter = std::make_unique<ModFilter>(false);
793 break;
794 case X86Local::MRM0r: case X86Local::MRM1r:
795 case X86Local::MRM2r: case X86Local::MRM3r:
796 case X86Local::MRM4r: case X86Local::MRM5r:
797 case X86Local::MRM6r: case X86Local::MRM7r:
798 filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r);
799 break;
800 case X86Local::MRM0X: case X86Local::MRM1X:
801 case X86Local::MRM2X: case X86Local::MRM3X:
802 case X86Local::MRM4X: case X86Local::MRM5X:
803 case X86Local::MRM6X: case X86Local::MRM7X:
804 filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0X);
805 break;
806 case X86Local::MRMr0:
807 filter = std::make_unique<ExtendedRMFilter>(true, Form - X86Local::MRMr0);
808 break;
809 case X86Local::MRM0m: case X86Local::MRM1m:
810 case X86Local::MRM2m: case X86Local::MRM3m:
811 case X86Local::MRM4m: case X86Local::MRM5m:
812 case X86Local::MRM6m: case X86Local::MRM7m:
813 filter = std::make_unique<ExtendedFilter>(false, Form - X86Local::MRM0m);
814 break;
815 X86_INSTR_MRM_MAPPING
816 filter = std::make_unique<ExactFilter>(0xC0 + Form - X86Local::MRM_C0);
817 break;
818 } // switch (Form)
819
820 uint8_t opcodeToSet = Opcode;
821
822 unsigned AddressSize = 0;
823 switch (AdSize) {
824 case X86Local::AdSize16: AddressSize = 16; break;
825 case X86Local::AdSize32: AddressSize = 32; break;
826 case X86Local::AdSize64: AddressSize = 64; break;
827 }
828
829 assert(opcodeType && "Opcode type not set");
830 assert(filter && "Filter not set");
831
832 if (Form == X86Local::AddRegFrm || Form == X86Local::MRMSrcRegCC ||
833 Form == X86Local::MRMSrcMemCC || Form == X86Local::MRMXrCC ||
834 Form == X86Local::MRMXmCC || Form == X86Local::AddCCFrm) {
835 unsigned Count = Form == X86Local::AddRegFrm ? 8 : 16;
836 assert(((opcodeToSet % Count) == 0) && "ADDREG_FRM opcode not aligned");
837
838 uint8_t currentOpcode;
839
840 for (currentOpcode = opcodeToSet; currentOpcode < opcodeToSet + Count;
841 ++currentOpcode)
842 tables.setTableFields(*opcodeType, insnContext(), currentOpcode, *filter,
843 UID, Is32Bit, OpPrefix == 0,
844 IgnoresVEX_L || EncodeRC,
845 IgnoresVEX_W, AddressSize);
846 } else {
847 tables.setTableFields(*opcodeType, insnContext(), opcodeToSet, *filter, UID,
848 Is32Bit, OpPrefix == 0, IgnoresVEX_L || EncodeRC,
849 IgnoresVEX_W, AddressSize);
850 }
851
852 #undef MAP
853 }
854
855 #define TYPE(str, type) if (s == str) return type;
typeFromString(const std::string & s,bool hasREX_WPrefix,uint8_t OpSize)856 OperandType RecognizableInstr::typeFromString(const std::string &s,
857 bool hasREX_WPrefix,
858 uint8_t OpSize) {
859 if(hasREX_WPrefix) {
860 // For instructions with a REX_W prefix, a declared 32-bit register encoding
861 // is special.
862 TYPE("GR32", TYPE_R32)
863 }
864 if(OpSize == X86Local::OpSize16) {
865 // For OpSize16 instructions, a declared 16-bit register or
866 // immediate encoding is special.
867 TYPE("GR16", TYPE_Rv)
868 } else if(OpSize == X86Local::OpSize32) {
869 // For OpSize32 instructions, a declared 32-bit register or
870 // immediate encoding is special.
871 TYPE("GR32", TYPE_Rv)
872 }
873 TYPE("i16mem", TYPE_M)
874 TYPE("i16imm", TYPE_IMM)
875 TYPE("i16i8imm", TYPE_IMM)
876 TYPE("GR16", TYPE_R16)
877 TYPE("GR16orGR32orGR64", TYPE_R16)
878 TYPE("i32mem", TYPE_M)
879 TYPE("i32imm", TYPE_IMM)
880 TYPE("i32i8imm", TYPE_IMM)
881 TYPE("GR32", TYPE_R32)
882 TYPE("GR32orGR64", TYPE_R32)
883 TYPE("i64mem", TYPE_M)
884 TYPE("i64i32imm", TYPE_IMM)
885 TYPE("i64i8imm", TYPE_IMM)
886 TYPE("GR64", TYPE_R64)
887 TYPE("i8mem", TYPE_M)
888 TYPE("i8imm", TYPE_IMM)
889 TYPE("u4imm", TYPE_UIMM8)
890 TYPE("u8imm", TYPE_UIMM8)
891 TYPE("i16u8imm", TYPE_UIMM8)
892 TYPE("i32u8imm", TYPE_UIMM8)
893 TYPE("i64u8imm", TYPE_UIMM8)
894 TYPE("GR8", TYPE_R8)
895 TYPE("VR128", TYPE_XMM)
896 TYPE("VR128X", TYPE_XMM)
897 TYPE("f128mem", TYPE_M)
898 TYPE("f256mem", TYPE_M)
899 TYPE("f512mem", TYPE_M)
900 TYPE("FR128", TYPE_XMM)
901 TYPE("FR64", TYPE_XMM)
902 TYPE("FR64X", TYPE_XMM)
903 TYPE("f64mem", TYPE_M)
904 TYPE("sdmem", TYPE_M)
905 TYPE("FR32", TYPE_XMM)
906 TYPE("FR32X", TYPE_XMM)
907 TYPE("f32mem", TYPE_M)
908 TYPE("ssmem", TYPE_M)
909 TYPE("RST", TYPE_ST)
910 TYPE("RSTi", TYPE_ST)
911 TYPE("i128mem", TYPE_M)
912 TYPE("i256mem", TYPE_M)
913 TYPE("i512mem", TYPE_M)
914 TYPE("i64i32imm_brtarget", TYPE_REL)
915 TYPE("i16imm_brtarget", TYPE_REL)
916 TYPE("i32imm_brtarget", TYPE_REL)
917 TYPE("ccode", TYPE_IMM)
918 TYPE("AVX512RC", TYPE_IMM)
919 TYPE("brtarget32", TYPE_REL)
920 TYPE("brtarget16", TYPE_REL)
921 TYPE("brtarget8", TYPE_REL)
922 TYPE("f80mem", TYPE_M)
923 TYPE("lea64_32mem", TYPE_M)
924 TYPE("lea64mem", TYPE_M)
925 TYPE("VR64", TYPE_MM64)
926 TYPE("i64imm", TYPE_IMM)
927 TYPE("anymem", TYPE_M)
928 TYPE("opaquemem", TYPE_M)
929 TYPE("sibmem", TYPE_MSIB)
930 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
931 TYPE("DEBUG_REG", TYPE_DEBUGREG)
932 TYPE("CONTROL_REG", TYPE_CONTROLREG)
933 TYPE("srcidx8", TYPE_SRCIDX)
934 TYPE("srcidx16", TYPE_SRCIDX)
935 TYPE("srcidx32", TYPE_SRCIDX)
936 TYPE("srcidx64", TYPE_SRCIDX)
937 TYPE("dstidx8", TYPE_DSTIDX)
938 TYPE("dstidx16", TYPE_DSTIDX)
939 TYPE("dstidx32", TYPE_DSTIDX)
940 TYPE("dstidx64", TYPE_DSTIDX)
941 TYPE("offset16_8", TYPE_MOFFS)
942 TYPE("offset16_16", TYPE_MOFFS)
943 TYPE("offset16_32", TYPE_MOFFS)
944 TYPE("offset32_8", TYPE_MOFFS)
945 TYPE("offset32_16", TYPE_MOFFS)
946 TYPE("offset32_32", TYPE_MOFFS)
947 TYPE("offset32_64", TYPE_MOFFS)
948 TYPE("offset64_8", TYPE_MOFFS)
949 TYPE("offset64_16", TYPE_MOFFS)
950 TYPE("offset64_32", TYPE_MOFFS)
951 TYPE("offset64_64", TYPE_MOFFS)
952 TYPE("VR256", TYPE_YMM)
953 TYPE("VR256X", TYPE_YMM)
954 TYPE("VR512", TYPE_ZMM)
955 TYPE("VK1", TYPE_VK)
956 TYPE("VK1WM", TYPE_VK)
957 TYPE("VK2", TYPE_VK)
958 TYPE("VK2WM", TYPE_VK)
959 TYPE("VK4", TYPE_VK)
960 TYPE("VK4WM", TYPE_VK)
961 TYPE("VK8", TYPE_VK)
962 TYPE("VK8WM", TYPE_VK)
963 TYPE("VK16", TYPE_VK)
964 TYPE("VK16WM", TYPE_VK)
965 TYPE("VK32", TYPE_VK)
966 TYPE("VK32WM", TYPE_VK)
967 TYPE("VK64", TYPE_VK)
968 TYPE("VK64WM", TYPE_VK)
969 TYPE("VK1Pair", TYPE_VK_PAIR)
970 TYPE("VK2Pair", TYPE_VK_PAIR)
971 TYPE("VK4Pair", TYPE_VK_PAIR)
972 TYPE("VK8Pair", TYPE_VK_PAIR)
973 TYPE("VK16Pair", TYPE_VK_PAIR)
974 TYPE("vx64mem", TYPE_MVSIBX)
975 TYPE("vx128mem", TYPE_MVSIBX)
976 TYPE("vx256mem", TYPE_MVSIBX)
977 TYPE("vy128mem", TYPE_MVSIBY)
978 TYPE("vy256mem", TYPE_MVSIBY)
979 TYPE("vx64xmem", TYPE_MVSIBX)
980 TYPE("vx128xmem", TYPE_MVSIBX)
981 TYPE("vx256xmem", TYPE_MVSIBX)
982 TYPE("vy128xmem", TYPE_MVSIBY)
983 TYPE("vy256xmem", TYPE_MVSIBY)
984 TYPE("vy512xmem", TYPE_MVSIBY)
985 TYPE("vz256mem", TYPE_MVSIBZ)
986 TYPE("vz512mem", TYPE_MVSIBZ)
987 TYPE("BNDR", TYPE_BNDR)
988 TYPE("TILE", TYPE_TMM)
989 errs() << "Unhandled type string " << s << "\n";
990 llvm_unreachable("Unhandled type string");
991 }
992 #undef TYPE
993
994 #define ENCODING(str, encoding) if (s == str) return encoding;
995 OperandEncoding
immediateEncodingFromString(const std::string & s,uint8_t OpSize)996 RecognizableInstr::immediateEncodingFromString(const std::string &s,
997 uint8_t OpSize) {
998 if(OpSize != X86Local::OpSize16) {
999 // For instructions without an OpSize prefix, a declared 16-bit register or
1000 // immediate encoding is special.
1001 ENCODING("i16imm", ENCODING_IW)
1002 }
1003 ENCODING("i32i8imm", ENCODING_IB)
1004 ENCODING("AVX512RC", ENCODING_IRC)
1005 ENCODING("i16imm", ENCODING_Iv)
1006 ENCODING("i16i8imm", ENCODING_IB)
1007 ENCODING("i32imm", ENCODING_Iv)
1008 ENCODING("i64i32imm", ENCODING_ID)
1009 ENCODING("i64i8imm", ENCODING_IB)
1010 ENCODING("i8imm", ENCODING_IB)
1011 ENCODING("u4imm", ENCODING_IB)
1012 ENCODING("u8imm", ENCODING_IB)
1013 ENCODING("i16u8imm", ENCODING_IB)
1014 ENCODING("i32u8imm", ENCODING_IB)
1015 ENCODING("i64u8imm", ENCODING_IB)
1016 // This is not a typo. Instructions like BLENDVPD put
1017 // register IDs in 8-bit immediates nowadays.
1018 ENCODING("FR32", ENCODING_IB)
1019 ENCODING("FR64", ENCODING_IB)
1020 ENCODING("FR128", ENCODING_IB)
1021 ENCODING("VR128", ENCODING_IB)
1022 ENCODING("VR256", ENCODING_IB)
1023 ENCODING("FR32X", ENCODING_IB)
1024 ENCODING("FR64X", ENCODING_IB)
1025 ENCODING("VR128X", ENCODING_IB)
1026 ENCODING("VR256X", ENCODING_IB)
1027 ENCODING("VR512", ENCODING_IB)
1028 ENCODING("TILE", ENCODING_IB)
1029 errs() << "Unhandled immediate encoding " << s << "\n";
1030 llvm_unreachable("Unhandled immediate encoding");
1031 }
1032
1033 OperandEncoding
rmRegisterEncodingFromString(const std::string & s,uint8_t OpSize)1034 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
1035 uint8_t OpSize) {
1036 ENCODING("RST", ENCODING_FP)
1037 ENCODING("RSTi", ENCODING_FP)
1038 ENCODING("GR16", ENCODING_RM)
1039 ENCODING("GR16orGR32orGR64",ENCODING_RM)
1040 ENCODING("GR32", ENCODING_RM)
1041 ENCODING("GR32orGR64", ENCODING_RM)
1042 ENCODING("GR64", ENCODING_RM)
1043 ENCODING("GR8", ENCODING_RM)
1044 ENCODING("VR128", ENCODING_RM)
1045 ENCODING("VR128X", ENCODING_RM)
1046 ENCODING("FR128", ENCODING_RM)
1047 ENCODING("FR64", ENCODING_RM)
1048 ENCODING("FR32", ENCODING_RM)
1049 ENCODING("FR64X", ENCODING_RM)
1050 ENCODING("FR32X", ENCODING_RM)
1051 ENCODING("VR64", ENCODING_RM)
1052 ENCODING("VR256", ENCODING_RM)
1053 ENCODING("VR256X", ENCODING_RM)
1054 ENCODING("VR512", ENCODING_RM)
1055 ENCODING("VK1", ENCODING_RM)
1056 ENCODING("VK2", ENCODING_RM)
1057 ENCODING("VK4", ENCODING_RM)
1058 ENCODING("VK8", ENCODING_RM)
1059 ENCODING("VK16", ENCODING_RM)
1060 ENCODING("VK32", ENCODING_RM)
1061 ENCODING("VK64", ENCODING_RM)
1062 ENCODING("VK1PAIR", ENCODING_RM)
1063 ENCODING("VK2PAIR", ENCODING_RM)
1064 ENCODING("VK4PAIR", ENCODING_RM)
1065 ENCODING("VK8PAIR", ENCODING_RM)
1066 ENCODING("VK16PAIR", ENCODING_RM)
1067 ENCODING("BNDR", ENCODING_RM)
1068 ENCODING("TILE", ENCODING_RM)
1069 errs() << "Unhandled R/M register encoding " << s << "\n";
1070 llvm_unreachable("Unhandled R/M register encoding");
1071 }
1072
1073 OperandEncoding
roRegisterEncodingFromString(const std::string & s,uint8_t OpSize)1074 RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
1075 uint8_t OpSize) {
1076 ENCODING("GR16", ENCODING_REG)
1077 ENCODING("GR16orGR32orGR64",ENCODING_REG)
1078 ENCODING("GR32", ENCODING_REG)
1079 ENCODING("GR32orGR64", ENCODING_REG)
1080 ENCODING("GR64", ENCODING_REG)
1081 ENCODING("GR8", ENCODING_REG)
1082 ENCODING("VR128", ENCODING_REG)
1083 ENCODING("FR128", ENCODING_REG)
1084 ENCODING("FR64", ENCODING_REG)
1085 ENCODING("FR32", ENCODING_REG)
1086 ENCODING("VR64", ENCODING_REG)
1087 ENCODING("SEGMENT_REG", ENCODING_REG)
1088 ENCODING("DEBUG_REG", ENCODING_REG)
1089 ENCODING("CONTROL_REG", ENCODING_REG)
1090 ENCODING("VR256", ENCODING_REG)
1091 ENCODING("VR256X", ENCODING_REG)
1092 ENCODING("VR128X", ENCODING_REG)
1093 ENCODING("FR64X", ENCODING_REG)
1094 ENCODING("FR32X", ENCODING_REG)
1095 ENCODING("VR512", ENCODING_REG)
1096 ENCODING("VK1", ENCODING_REG)
1097 ENCODING("VK2", ENCODING_REG)
1098 ENCODING("VK4", ENCODING_REG)
1099 ENCODING("VK8", ENCODING_REG)
1100 ENCODING("VK16", ENCODING_REG)
1101 ENCODING("VK32", ENCODING_REG)
1102 ENCODING("VK64", ENCODING_REG)
1103 ENCODING("VK1Pair", ENCODING_REG)
1104 ENCODING("VK2Pair", ENCODING_REG)
1105 ENCODING("VK4Pair", ENCODING_REG)
1106 ENCODING("VK8Pair", ENCODING_REG)
1107 ENCODING("VK16Pair", ENCODING_REG)
1108 ENCODING("VK1WM", ENCODING_REG)
1109 ENCODING("VK2WM", ENCODING_REG)
1110 ENCODING("VK4WM", ENCODING_REG)
1111 ENCODING("VK8WM", ENCODING_REG)
1112 ENCODING("VK16WM", ENCODING_REG)
1113 ENCODING("VK32WM", ENCODING_REG)
1114 ENCODING("VK64WM", ENCODING_REG)
1115 ENCODING("BNDR", ENCODING_REG)
1116 ENCODING("TILE", ENCODING_REG)
1117 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1118 llvm_unreachable("Unhandled reg/opcode register encoding");
1119 }
1120
1121 OperandEncoding
vvvvRegisterEncodingFromString(const std::string & s,uint8_t OpSize)1122 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
1123 uint8_t OpSize) {
1124 ENCODING("GR32", ENCODING_VVVV)
1125 ENCODING("GR64", ENCODING_VVVV)
1126 ENCODING("FR32", ENCODING_VVVV)
1127 ENCODING("FR128", ENCODING_VVVV)
1128 ENCODING("FR64", ENCODING_VVVV)
1129 ENCODING("VR128", ENCODING_VVVV)
1130 ENCODING("VR256", ENCODING_VVVV)
1131 ENCODING("FR32X", ENCODING_VVVV)
1132 ENCODING("FR64X", ENCODING_VVVV)
1133 ENCODING("VR128X", ENCODING_VVVV)
1134 ENCODING("VR256X", ENCODING_VVVV)
1135 ENCODING("VR512", ENCODING_VVVV)
1136 ENCODING("VK1", ENCODING_VVVV)
1137 ENCODING("VK2", ENCODING_VVVV)
1138 ENCODING("VK4", ENCODING_VVVV)
1139 ENCODING("VK8", ENCODING_VVVV)
1140 ENCODING("VK16", ENCODING_VVVV)
1141 ENCODING("VK32", ENCODING_VVVV)
1142 ENCODING("VK64", ENCODING_VVVV)
1143 ENCODING("VK1PAIR", ENCODING_VVVV)
1144 ENCODING("VK2PAIR", ENCODING_VVVV)
1145 ENCODING("VK4PAIR", ENCODING_VVVV)
1146 ENCODING("VK8PAIR", ENCODING_VVVV)
1147 ENCODING("VK16PAIR", ENCODING_VVVV)
1148 ENCODING("TILE", ENCODING_VVVV)
1149 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1150 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1151 }
1152
1153 OperandEncoding
writemaskRegisterEncodingFromString(const std::string & s,uint8_t OpSize)1154 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
1155 uint8_t OpSize) {
1156 ENCODING("VK1WM", ENCODING_WRITEMASK)
1157 ENCODING("VK2WM", ENCODING_WRITEMASK)
1158 ENCODING("VK4WM", ENCODING_WRITEMASK)
1159 ENCODING("VK8WM", ENCODING_WRITEMASK)
1160 ENCODING("VK16WM", ENCODING_WRITEMASK)
1161 ENCODING("VK32WM", ENCODING_WRITEMASK)
1162 ENCODING("VK64WM", ENCODING_WRITEMASK)
1163 errs() << "Unhandled mask register encoding " << s << "\n";
1164 llvm_unreachable("Unhandled mask register encoding");
1165 }
1166
1167 OperandEncoding
memoryEncodingFromString(const std::string & s,uint8_t OpSize)1168 RecognizableInstr::memoryEncodingFromString(const std::string &s,
1169 uint8_t OpSize) {
1170 ENCODING("i16mem", ENCODING_RM)
1171 ENCODING("i32mem", ENCODING_RM)
1172 ENCODING("i64mem", ENCODING_RM)
1173 ENCODING("i8mem", ENCODING_RM)
1174 ENCODING("ssmem", ENCODING_RM)
1175 ENCODING("sdmem", ENCODING_RM)
1176 ENCODING("f128mem", ENCODING_RM)
1177 ENCODING("f256mem", ENCODING_RM)
1178 ENCODING("f512mem", ENCODING_RM)
1179 ENCODING("f64mem", ENCODING_RM)
1180 ENCODING("f32mem", ENCODING_RM)
1181 ENCODING("i128mem", ENCODING_RM)
1182 ENCODING("i256mem", ENCODING_RM)
1183 ENCODING("i512mem", ENCODING_RM)
1184 ENCODING("f80mem", ENCODING_RM)
1185 ENCODING("lea64_32mem", ENCODING_RM)
1186 ENCODING("lea64mem", ENCODING_RM)
1187 ENCODING("anymem", ENCODING_RM)
1188 ENCODING("opaquemem", ENCODING_RM)
1189 ENCODING("sibmem", ENCODING_SIB)
1190 ENCODING("vx64mem", ENCODING_VSIB)
1191 ENCODING("vx128mem", ENCODING_VSIB)
1192 ENCODING("vx256mem", ENCODING_VSIB)
1193 ENCODING("vy128mem", ENCODING_VSIB)
1194 ENCODING("vy256mem", ENCODING_VSIB)
1195 ENCODING("vx64xmem", ENCODING_VSIB)
1196 ENCODING("vx128xmem", ENCODING_VSIB)
1197 ENCODING("vx256xmem", ENCODING_VSIB)
1198 ENCODING("vy128xmem", ENCODING_VSIB)
1199 ENCODING("vy256xmem", ENCODING_VSIB)
1200 ENCODING("vy512xmem", ENCODING_VSIB)
1201 ENCODING("vz256mem", ENCODING_VSIB)
1202 ENCODING("vz512mem", ENCODING_VSIB)
1203 errs() << "Unhandled memory encoding " << s << "\n";
1204 llvm_unreachable("Unhandled memory encoding");
1205 }
1206
1207 OperandEncoding
relocationEncodingFromString(const std::string & s,uint8_t OpSize)1208 RecognizableInstr::relocationEncodingFromString(const std::string &s,
1209 uint8_t OpSize) {
1210 if(OpSize != X86Local::OpSize16) {
1211 // For instructions without an OpSize prefix, a declared 16-bit register or
1212 // immediate encoding is special.
1213 ENCODING("i16imm", ENCODING_IW)
1214 }
1215 ENCODING("i16imm", ENCODING_Iv)
1216 ENCODING("i16i8imm", ENCODING_IB)
1217 ENCODING("i32imm", ENCODING_Iv)
1218 ENCODING("i32i8imm", ENCODING_IB)
1219 ENCODING("i64i32imm", ENCODING_ID)
1220 ENCODING("i64i8imm", ENCODING_IB)
1221 ENCODING("i8imm", ENCODING_IB)
1222 ENCODING("u8imm", ENCODING_IB)
1223 ENCODING("i16u8imm", ENCODING_IB)
1224 ENCODING("i32u8imm", ENCODING_IB)
1225 ENCODING("i64u8imm", ENCODING_IB)
1226 ENCODING("i64i32imm_brtarget", ENCODING_ID)
1227 ENCODING("i16imm_brtarget", ENCODING_IW)
1228 ENCODING("i32imm_brtarget", ENCODING_ID)
1229 ENCODING("brtarget32", ENCODING_ID)
1230 ENCODING("brtarget16", ENCODING_IW)
1231 ENCODING("brtarget8", ENCODING_IB)
1232 ENCODING("i64imm", ENCODING_IO)
1233 ENCODING("offset16_8", ENCODING_Ia)
1234 ENCODING("offset16_16", ENCODING_Ia)
1235 ENCODING("offset16_32", ENCODING_Ia)
1236 ENCODING("offset32_8", ENCODING_Ia)
1237 ENCODING("offset32_16", ENCODING_Ia)
1238 ENCODING("offset32_32", ENCODING_Ia)
1239 ENCODING("offset32_64", ENCODING_Ia)
1240 ENCODING("offset64_8", ENCODING_Ia)
1241 ENCODING("offset64_16", ENCODING_Ia)
1242 ENCODING("offset64_32", ENCODING_Ia)
1243 ENCODING("offset64_64", ENCODING_Ia)
1244 ENCODING("srcidx8", ENCODING_SI)
1245 ENCODING("srcidx16", ENCODING_SI)
1246 ENCODING("srcidx32", ENCODING_SI)
1247 ENCODING("srcidx64", ENCODING_SI)
1248 ENCODING("dstidx8", ENCODING_DI)
1249 ENCODING("dstidx16", ENCODING_DI)
1250 ENCODING("dstidx32", ENCODING_DI)
1251 ENCODING("dstidx64", ENCODING_DI)
1252 errs() << "Unhandled relocation encoding " << s << "\n";
1253 llvm_unreachable("Unhandled relocation encoding");
1254 }
1255
1256 OperandEncoding
opcodeModifierEncodingFromString(const std::string & s,uint8_t OpSize)1257 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s,
1258 uint8_t OpSize) {
1259 ENCODING("GR32", ENCODING_Rv)
1260 ENCODING("GR64", ENCODING_RO)
1261 ENCODING("GR16", ENCODING_Rv)
1262 ENCODING("GR8", ENCODING_RB)
1263 ENCODING("ccode", ENCODING_CC)
1264 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1265 llvm_unreachable("Unhandled opcode modifier encoding");
1266 }
1267 #undef ENCODING
1268