1 //===-- RegisterContextDarwin_arm64.cpp -----------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "RegisterContextDarwin_arm64.h"
10 #include "RegisterContextDarwinConstants.h"
11
12 #include "lldb/Target/Process.h"
13 #include "lldb/Target/Thread.h"
14 #include "lldb/Utility/DataBufferHeap.h"
15 #include "lldb/Utility/DataExtractor.h"
16 #include "lldb/Utility/Endian.h"
17 #include "lldb/Utility/Log.h"
18 #include "lldb/Utility/RegisterValue.h"
19 #include "lldb/Utility/Scalar.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/Support/Compiler.h"
22
23 #include "Plugins/Process/Utility/InstructionUtils.h"
24
25 #include <memory>
26
27 #if defined(__APPLE__) && (defined(__arm64__) || defined(__aarch64__))
28 #include <sys/types.h>
29 #include <sys/sysctl.h>
30 #endif
31
32 #include "Utility/ARM64_DWARF_Registers.h"
33
34 using namespace lldb;
35 using namespace lldb_private;
36
37 #define GPR_OFFSET(idx) ((idx)*8)
38 #define GPR_OFFSET_NAME(reg) \
39 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::GPR, reg))
40
41 #define FPU_OFFSET(idx) ((idx)*16 + sizeof(RegisterContextDarwin_arm64::GPR))
42 #define FPU_OFFSET_NAME(reg) \
43 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::FPU, reg))
44
45 #define EXC_OFFSET_NAME(reg) \
46 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::EXC, reg) + \
47 sizeof(RegisterContextDarwin_arm64::GPR) + \
48 sizeof(RegisterContextDarwin_arm64::FPU))
49 #define DBG_OFFSET_NAME(reg) \
50 (LLVM_EXTENSION offsetof(RegisterContextDarwin_arm64::DBG, reg) + \
51 sizeof(RegisterContextDarwin_arm64::GPR) + \
52 sizeof(RegisterContextDarwin_arm64::FPU) + \
53 sizeof(RegisterContextDarwin_arm64::EXC))
54
55 #define DEFINE_DBG(reg, i) \
56 #reg, NULL, \
57 sizeof(((RegisterContextDarwin_arm64::DBG *) NULL)->reg[i]), \
58 DBG_OFFSET_NAME(reg[i]), eEncodingUint, eFormatHex, \
59 {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
60 LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
61 LLDB_INVALID_REGNUM }, \
62 NULL, NULL, NULL, 0
63 #define REG_CONTEXT_SIZE \
64 (sizeof(RegisterContextDarwin_arm64::GPR) + \
65 sizeof(RegisterContextDarwin_arm64::FPU) + \
66 sizeof(RegisterContextDarwin_arm64::EXC))
67
68 // Include RegisterInfos_arm64 to declare our g_register_infos_arm64 structure.
69 #define DECLARE_REGISTER_INFOS_ARM64_STRUCT
70 #include "RegisterInfos_arm64.h"
71 #undef DECLARE_REGISTER_INFOS_ARM64_STRUCT
72
73 // General purpose registers
74 static uint32_t g_gpr_regnums[] = {
75 gpr_x0, gpr_x1, gpr_x2, gpr_x3, gpr_x4, gpr_x5, gpr_x6,
76 gpr_x7, gpr_x8, gpr_x9, gpr_x10, gpr_x11, gpr_x12, gpr_x13,
77 gpr_x14, gpr_x15, gpr_x16, gpr_x17, gpr_x18, gpr_x19, gpr_x20,
78 gpr_x21, gpr_x22, gpr_x23, gpr_x24, gpr_x25, gpr_x26, gpr_x27,
79 gpr_x28, gpr_fp, gpr_lr, gpr_sp, gpr_pc, gpr_cpsr};
80
81 // Floating point registers
82 static uint32_t g_fpu_regnums[] = {
83 fpu_v0, fpu_v1, fpu_v2, fpu_v3, fpu_v4, fpu_v5, fpu_v6,
84 fpu_v7, fpu_v8, fpu_v9, fpu_v10, fpu_v11, fpu_v12, fpu_v13,
85 fpu_v14, fpu_v15, fpu_v16, fpu_v17, fpu_v18, fpu_v19, fpu_v20,
86 fpu_v21, fpu_v22, fpu_v23, fpu_v24, fpu_v25, fpu_v26, fpu_v27,
87 fpu_v28, fpu_v29, fpu_v30, fpu_v31, fpu_fpsr, fpu_fpcr};
88
89 // Exception registers
90
91 static uint32_t g_exc_regnums[] = {exc_far, exc_esr, exc_exception};
92
93 static size_t k_num_register_infos =
94 llvm::array_lengthof(g_register_infos_arm64_le);
95
RegisterContextDarwin_arm64(Thread & thread,uint32_t concrete_frame_idx)96 RegisterContextDarwin_arm64::RegisterContextDarwin_arm64(
97 Thread &thread, uint32_t concrete_frame_idx)
98 : RegisterContext(thread, concrete_frame_idx), gpr(), fpu(), exc() {
99 uint32_t i;
100 for (i = 0; i < kNumErrors; i++) {
101 gpr_errs[i] = -1;
102 fpu_errs[i] = -1;
103 exc_errs[i] = -1;
104 }
105 }
106
107 RegisterContextDarwin_arm64::~RegisterContextDarwin_arm64() = default;
108
InvalidateAllRegisters()109 void RegisterContextDarwin_arm64::InvalidateAllRegisters() {
110 InvalidateAllRegisterStates();
111 }
112
GetRegisterCount()113 size_t RegisterContextDarwin_arm64::GetRegisterCount() {
114 assert(k_num_register_infos == k_num_registers);
115 return k_num_registers;
116 }
117
118 const RegisterInfo *
GetRegisterInfoAtIndex(size_t reg)119 RegisterContextDarwin_arm64::GetRegisterInfoAtIndex(size_t reg) {
120 assert(k_num_register_infos == k_num_registers);
121 if (reg < k_num_registers)
122 return &g_register_infos_arm64_le[reg];
123 return nullptr;
124 }
125
GetRegisterInfosCount()126 size_t RegisterContextDarwin_arm64::GetRegisterInfosCount() {
127 return k_num_register_infos;
128 }
129
GetRegisterInfos()130 const RegisterInfo *RegisterContextDarwin_arm64::GetRegisterInfos() {
131 return g_register_infos_arm64_le;
132 }
133
134 // Number of registers in each register set
135 const size_t k_num_gpr_registers = llvm::array_lengthof(g_gpr_regnums);
136 const size_t k_num_fpu_registers = llvm::array_lengthof(g_fpu_regnums);
137 const size_t k_num_exc_registers = llvm::array_lengthof(g_exc_regnums);
138
139 // Register set definitions. The first definitions at register set index of
140 // zero is for all registers, followed by other registers sets. The register
141 // information for the all register set need not be filled in.
142 static const RegisterSet g_reg_sets[] = {
143 {
144 "General Purpose Registers", "gpr", k_num_gpr_registers, g_gpr_regnums,
145 },
146 {"Floating Point Registers", "fpu", k_num_fpu_registers, g_fpu_regnums},
147 {"Exception State Registers", "exc", k_num_exc_registers, g_exc_regnums}};
148
149 const size_t k_num_regsets = llvm::array_lengthof(g_reg_sets);
150
GetRegisterSetCount()151 size_t RegisterContextDarwin_arm64::GetRegisterSetCount() {
152 return k_num_regsets;
153 }
154
GetRegisterSet(size_t reg_set)155 const RegisterSet *RegisterContextDarwin_arm64::GetRegisterSet(size_t reg_set) {
156 if (reg_set < k_num_regsets)
157 return &g_reg_sets[reg_set];
158 return nullptr;
159 }
160
161 // Register information definitions for arm64
GetSetForNativeRegNum(int reg)162 int RegisterContextDarwin_arm64::GetSetForNativeRegNum(int reg) {
163 if (reg < fpu_v0)
164 return GPRRegSet;
165 else if (reg < exc_far)
166 return FPURegSet;
167 else if (reg < k_num_registers)
168 return EXCRegSet;
169 return -1;
170 }
171
ReadGPR(bool force)172 int RegisterContextDarwin_arm64::ReadGPR(bool force) {
173 int set = GPRRegSet;
174 if (force || !RegisterSetIsCached(set)) {
175 SetError(set, Read, DoReadGPR(GetThreadID(), set, gpr));
176 }
177 return GetError(GPRRegSet, Read);
178 }
179
ReadFPU(bool force)180 int RegisterContextDarwin_arm64::ReadFPU(bool force) {
181 int set = FPURegSet;
182 if (force || !RegisterSetIsCached(set)) {
183 SetError(set, Read, DoReadFPU(GetThreadID(), set, fpu));
184 }
185 return GetError(FPURegSet, Read);
186 }
187
ReadEXC(bool force)188 int RegisterContextDarwin_arm64::ReadEXC(bool force) {
189 int set = EXCRegSet;
190 if (force || !RegisterSetIsCached(set)) {
191 SetError(set, Read, DoReadEXC(GetThreadID(), set, exc));
192 }
193 return GetError(EXCRegSet, Read);
194 }
195
ReadDBG(bool force)196 int RegisterContextDarwin_arm64::ReadDBG(bool force) {
197 int set = DBGRegSet;
198 if (force || !RegisterSetIsCached(set)) {
199 SetError(set, Read, DoReadDBG(GetThreadID(), set, dbg));
200 }
201 return GetError(DBGRegSet, Read);
202 }
203
WriteGPR()204 int RegisterContextDarwin_arm64::WriteGPR() {
205 int set = GPRRegSet;
206 if (!RegisterSetIsCached(set)) {
207 SetError(set, Write, -1);
208 return KERN_INVALID_ARGUMENT;
209 }
210 SetError(set, Write, DoWriteGPR(GetThreadID(), set, gpr));
211 SetError(set, Read, -1);
212 return GetError(GPRRegSet, Write);
213 }
214
WriteFPU()215 int RegisterContextDarwin_arm64::WriteFPU() {
216 int set = FPURegSet;
217 if (!RegisterSetIsCached(set)) {
218 SetError(set, Write, -1);
219 return KERN_INVALID_ARGUMENT;
220 }
221 SetError(set, Write, DoWriteFPU(GetThreadID(), set, fpu));
222 SetError(set, Read, -1);
223 return GetError(FPURegSet, Write);
224 }
225
WriteEXC()226 int RegisterContextDarwin_arm64::WriteEXC() {
227 int set = EXCRegSet;
228 if (!RegisterSetIsCached(set)) {
229 SetError(set, Write, -1);
230 return KERN_INVALID_ARGUMENT;
231 }
232 SetError(set, Write, DoWriteEXC(GetThreadID(), set, exc));
233 SetError(set, Read, -1);
234 return GetError(EXCRegSet, Write);
235 }
236
WriteDBG()237 int RegisterContextDarwin_arm64::WriteDBG() {
238 int set = DBGRegSet;
239 if (!RegisterSetIsCached(set)) {
240 SetError(set, Write, -1);
241 return KERN_INVALID_ARGUMENT;
242 }
243 SetError(set, Write, DoWriteDBG(GetThreadID(), set, dbg));
244 SetError(set, Read, -1);
245 return GetError(DBGRegSet, Write);
246 }
247
ReadRegisterSet(uint32_t set,bool force)248 int RegisterContextDarwin_arm64::ReadRegisterSet(uint32_t set, bool force) {
249 switch (set) {
250 case GPRRegSet:
251 return ReadGPR(force);
252 case FPURegSet:
253 return ReadFPU(force);
254 case EXCRegSet:
255 return ReadEXC(force);
256 case DBGRegSet:
257 return ReadDBG(force);
258 default:
259 break;
260 }
261 return KERN_INVALID_ARGUMENT;
262 }
263
WriteRegisterSet(uint32_t set)264 int RegisterContextDarwin_arm64::WriteRegisterSet(uint32_t set) {
265 // Make sure we have a valid context to set.
266 if (RegisterSetIsCached(set)) {
267 switch (set) {
268 case GPRRegSet:
269 return WriteGPR();
270 case FPURegSet:
271 return WriteFPU();
272 case EXCRegSet:
273 return WriteEXC();
274 case DBGRegSet:
275 return WriteDBG();
276 default:
277 break;
278 }
279 }
280 return KERN_INVALID_ARGUMENT;
281 }
282
LogDBGRegisters(Log * log,const DBG & dbg)283 void RegisterContextDarwin_arm64::LogDBGRegisters(Log *log, const DBG &dbg) {
284 if (log) {
285 for (uint32_t i = 0; i < 16; i++)
286 LLDB_LOGF(log,
287 "BVR%-2u/BCR%-2u = { 0x%8.8" PRIu64 ", 0x%8.8" PRIu64
288 " } WVR%-2u/WCR%-2u "
289 "= { 0x%8.8" PRIu64 ", 0x%8.8" PRIu64 " }",
290 i, i, dbg.bvr[i], dbg.bcr[i], i, i, dbg.wvr[i], dbg.wcr[i]);
291 }
292 }
293
ReadRegister(const RegisterInfo * reg_info,RegisterValue & value)294 bool RegisterContextDarwin_arm64::ReadRegister(const RegisterInfo *reg_info,
295 RegisterValue &value) {
296 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
297 int set = RegisterContextDarwin_arm64::GetSetForNativeRegNum(reg);
298
299 if (set == -1)
300 return false;
301
302 if (ReadRegisterSet(set, false) != KERN_SUCCESS)
303 return false;
304
305 switch (reg) {
306 case gpr_x0:
307 case gpr_x1:
308 case gpr_x2:
309 case gpr_x3:
310 case gpr_x4:
311 case gpr_x5:
312 case gpr_x6:
313 case gpr_x7:
314 case gpr_x8:
315 case gpr_x9:
316 case gpr_x10:
317 case gpr_x11:
318 case gpr_x12:
319 case gpr_x13:
320 case gpr_x14:
321 case gpr_x15:
322 case gpr_x16:
323 case gpr_x17:
324 case gpr_x18:
325 case gpr_x19:
326 case gpr_x20:
327 case gpr_x21:
328 case gpr_x22:
329 case gpr_x23:
330 case gpr_x24:
331 case gpr_x25:
332 case gpr_x26:
333 case gpr_x27:
334 case gpr_x28:
335 value.SetUInt64(gpr.x[reg - gpr_x0]);
336 break;
337 case gpr_fp:
338 value.SetUInt64(gpr.fp);
339 break;
340 case gpr_sp:
341 value.SetUInt64(gpr.sp);
342 break;
343 case gpr_lr:
344 value.SetUInt64(gpr.lr);
345 break;
346 case gpr_pc:
347 value.SetUInt64(gpr.pc);
348 break;
349 case gpr_cpsr:
350 value.SetUInt64(gpr.cpsr);
351 break;
352
353 case gpr_w0:
354 case gpr_w1:
355 case gpr_w2:
356 case gpr_w3:
357 case gpr_w4:
358 case gpr_w5:
359 case gpr_w6:
360 case gpr_w7:
361 case gpr_w8:
362 case gpr_w9:
363 case gpr_w10:
364 case gpr_w11:
365 case gpr_w12:
366 case gpr_w13:
367 case gpr_w14:
368 case gpr_w15:
369 case gpr_w16:
370 case gpr_w17:
371 case gpr_w18:
372 case gpr_w19:
373 case gpr_w20:
374 case gpr_w21:
375 case gpr_w22:
376 case gpr_w23:
377 case gpr_w24:
378 case gpr_w25:
379 case gpr_w26:
380 case gpr_w27:
381 case gpr_w28: {
382 ProcessSP process_sp(m_thread.GetProcess());
383 if (process_sp.get()) {
384 DataExtractor regdata(&gpr.x[reg - gpr_w0], 8, process_sp->GetByteOrder(),
385 process_sp->GetAddressByteSize());
386 offset_t offset = 0;
387 uint64_t retval = regdata.GetMaxU64(&offset, 8);
388 uint32_t retval_lower32 = static_cast<uint32_t>(retval & 0xffffffff);
389 value.SetUInt32(retval_lower32);
390 }
391 } break;
392
393 case fpu_v0:
394 case fpu_v1:
395 case fpu_v2:
396 case fpu_v3:
397 case fpu_v4:
398 case fpu_v5:
399 case fpu_v6:
400 case fpu_v7:
401 case fpu_v8:
402 case fpu_v9:
403 case fpu_v10:
404 case fpu_v11:
405 case fpu_v12:
406 case fpu_v13:
407 case fpu_v14:
408 case fpu_v15:
409 case fpu_v16:
410 case fpu_v17:
411 case fpu_v18:
412 case fpu_v19:
413 case fpu_v20:
414 case fpu_v21:
415 case fpu_v22:
416 case fpu_v23:
417 case fpu_v24:
418 case fpu_v25:
419 case fpu_v26:
420 case fpu_v27:
421 case fpu_v28:
422 case fpu_v29:
423 case fpu_v30:
424 case fpu_v31:
425 value.SetBytes(fpu.v[reg - fpu_v0].bytes, reg_info->byte_size,
426 endian::InlHostByteOrder());
427 break;
428
429 case fpu_s0:
430 case fpu_s1:
431 case fpu_s2:
432 case fpu_s3:
433 case fpu_s4:
434 case fpu_s5:
435 case fpu_s6:
436 case fpu_s7:
437 case fpu_s8:
438 case fpu_s9:
439 case fpu_s10:
440 case fpu_s11:
441 case fpu_s12:
442 case fpu_s13:
443 case fpu_s14:
444 case fpu_s15:
445 case fpu_s16:
446 case fpu_s17:
447 case fpu_s18:
448 case fpu_s19:
449 case fpu_s20:
450 case fpu_s21:
451 case fpu_s22:
452 case fpu_s23:
453 case fpu_s24:
454 case fpu_s25:
455 case fpu_s26:
456 case fpu_s27:
457 case fpu_s28:
458 case fpu_s29:
459 case fpu_s30:
460 case fpu_s31: {
461 ProcessSP process_sp(m_thread.GetProcess());
462 if (process_sp.get()) {
463 DataExtractor regdata(&fpu.v[reg - fpu_s0], 4, process_sp->GetByteOrder(),
464 process_sp->GetAddressByteSize());
465 offset_t offset = 0;
466 value.SetFloat(regdata.GetFloat(&offset));
467 }
468 } break;
469
470 case fpu_d0:
471 case fpu_d1:
472 case fpu_d2:
473 case fpu_d3:
474 case fpu_d4:
475 case fpu_d5:
476 case fpu_d6:
477 case fpu_d7:
478 case fpu_d8:
479 case fpu_d9:
480 case fpu_d10:
481 case fpu_d11:
482 case fpu_d12:
483 case fpu_d13:
484 case fpu_d14:
485 case fpu_d15:
486 case fpu_d16:
487 case fpu_d17:
488 case fpu_d18:
489 case fpu_d19:
490 case fpu_d20:
491 case fpu_d21:
492 case fpu_d22:
493 case fpu_d23:
494 case fpu_d24:
495 case fpu_d25:
496 case fpu_d26:
497 case fpu_d27:
498 case fpu_d28:
499 case fpu_d29:
500 case fpu_d30:
501 case fpu_d31: {
502 ProcessSP process_sp(m_thread.GetProcess());
503 if (process_sp.get()) {
504 DataExtractor regdata(&fpu.v[reg - fpu_d0], 8, process_sp->GetByteOrder(),
505 process_sp->GetAddressByteSize());
506 offset_t offset = 0;
507 value.SetDouble(regdata.GetDouble(&offset));
508 }
509 } break;
510
511 case fpu_fpsr:
512 value.SetUInt32(fpu.fpsr);
513 break;
514
515 case fpu_fpcr:
516 value.SetUInt32(fpu.fpcr);
517 break;
518
519 case exc_exception:
520 value.SetUInt32(exc.exception);
521 break;
522 case exc_esr:
523 value.SetUInt32(exc.esr);
524 break;
525 case exc_far:
526 value.SetUInt64(exc.far);
527 break;
528
529 default:
530 value.SetValueToInvalid();
531 return false;
532 }
533 return true;
534 }
535
WriteRegister(const RegisterInfo * reg_info,const RegisterValue & value)536 bool RegisterContextDarwin_arm64::WriteRegister(const RegisterInfo *reg_info,
537 const RegisterValue &value) {
538 const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
539 int set = GetSetForNativeRegNum(reg);
540
541 if (set == -1)
542 return false;
543
544 if (ReadRegisterSet(set, false) != KERN_SUCCESS)
545 return false;
546
547 switch (reg) {
548 case gpr_x0:
549 case gpr_x1:
550 case gpr_x2:
551 case gpr_x3:
552 case gpr_x4:
553 case gpr_x5:
554 case gpr_x6:
555 case gpr_x7:
556 case gpr_x8:
557 case gpr_x9:
558 case gpr_x10:
559 case gpr_x11:
560 case gpr_x12:
561 case gpr_x13:
562 case gpr_x14:
563 case gpr_x15:
564 case gpr_x16:
565 case gpr_x17:
566 case gpr_x18:
567 case gpr_x19:
568 case gpr_x20:
569 case gpr_x21:
570 case gpr_x22:
571 case gpr_x23:
572 case gpr_x24:
573 case gpr_x25:
574 case gpr_x26:
575 case gpr_x27:
576 case gpr_x28:
577 case gpr_fp:
578 case gpr_sp:
579 case gpr_lr:
580 case gpr_pc:
581 case gpr_cpsr:
582 gpr.x[reg - gpr_x0] = value.GetAsUInt64();
583 break;
584
585 case fpu_v0:
586 case fpu_v1:
587 case fpu_v2:
588 case fpu_v3:
589 case fpu_v4:
590 case fpu_v5:
591 case fpu_v6:
592 case fpu_v7:
593 case fpu_v8:
594 case fpu_v9:
595 case fpu_v10:
596 case fpu_v11:
597 case fpu_v12:
598 case fpu_v13:
599 case fpu_v14:
600 case fpu_v15:
601 case fpu_v16:
602 case fpu_v17:
603 case fpu_v18:
604 case fpu_v19:
605 case fpu_v20:
606 case fpu_v21:
607 case fpu_v22:
608 case fpu_v23:
609 case fpu_v24:
610 case fpu_v25:
611 case fpu_v26:
612 case fpu_v27:
613 case fpu_v28:
614 case fpu_v29:
615 case fpu_v30:
616 case fpu_v31:
617 ::memcpy(fpu.v[reg - fpu_v0].bytes, value.GetBytes(),
618 value.GetByteSize());
619 break;
620
621 case fpu_fpsr:
622 fpu.fpsr = value.GetAsUInt32();
623 break;
624
625 case fpu_fpcr:
626 fpu.fpcr = value.GetAsUInt32();
627 break;
628
629 case exc_exception:
630 exc.exception = value.GetAsUInt32();
631 break;
632 case exc_esr:
633 exc.esr = value.GetAsUInt32();
634 break;
635 case exc_far:
636 exc.far = value.GetAsUInt64();
637 break;
638
639 default:
640 return false;
641 }
642 return WriteRegisterSet(set) == KERN_SUCCESS;
643 }
644
ReadAllRegisterValues(lldb::DataBufferSP & data_sp)645 bool RegisterContextDarwin_arm64::ReadAllRegisterValues(
646 lldb::DataBufferSP &data_sp) {
647 data_sp = std::make_shared<DataBufferHeap>(REG_CONTEXT_SIZE, 0);
648 if (ReadGPR(false) == KERN_SUCCESS && ReadFPU(false) == KERN_SUCCESS &&
649 ReadEXC(false) == KERN_SUCCESS) {
650 uint8_t *dst = data_sp->GetBytes();
651 ::memcpy(dst, &gpr, sizeof(gpr));
652 dst += sizeof(gpr);
653
654 ::memcpy(dst, &fpu, sizeof(fpu));
655 dst += sizeof(gpr);
656
657 ::memcpy(dst, &exc, sizeof(exc));
658 return true;
659 }
660 return false;
661 }
662
WriteAllRegisterValues(const lldb::DataBufferSP & data_sp)663 bool RegisterContextDarwin_arm64::WriteAllRegisterValues(
664 const lldb::DataBufferSP &data_sp) {
665 if (data_sp && data_sp->GetByteSize() == REG_CONTEXT_SIZE) {
666 const uint8_t *src = data_sp->GetBytes();
667 ::memcpy(&gpr, src, sizeof(gpr));
668 src += sizeof(gpr);
669
670 ::memcpy(&fpu, src, sizeof(fpu));
671 src += sizeof(gpr);
672
673 ::memcpy(&exc, src, sizeof(exc));
674 uint32_t success_count = 0;
675 if (WriteGPR() == KERN_SUCCESS)
676 ++success_count;
677 if (WriteFPU() == KERN_SUCCESS)
678 ++success_count;
679 if (WriteEXC() == KERN_SUCCESS)
680 ++success_count;
681 return success_count == 3;
682 }
683 return false;
684 }
685
ConvertRegisterKindToRegisterNumber(RegisterKind kind,uint32_t reg)686 uint32_t RegisterContextDarwin_arm64::ConvertRegisterKindToRegisterNumber(
687 RegisterKind kind, uint32_t reg) {
688 if (kind == eRegisterKindGeneric) {
689 switch (reg) {
690 case LLDB_REGNUM_GENERIC_PC:
691 return gpr_pc;
692 case LLDB_REGNUM_GENERIC_SP:
693 return gpr_sp;
694 case LLDB_REGNUM_GENERIC_FP:
695 return gpr_fp;
696 case LLDB_REGNUM_GENERIC_RA:
697 return gpr_lr;
698 case LLDB_REGNUM_GENERIC_FLAGS:
699 return gpr_cpsr;
700 default:
701 break;
702 }
703 } else if (kind == eRegisterKindDWARF) {
704 switch (reg) {
705 case arm64_dwarf::x0:
706 return gpr_x0;
707 case arm64_dwarf::x1:
708 return gpr_x1;
709 case arm64_dwarf::x2:
710 return gpr_x2;
711 case arm64_dwarf::x3:
712 return gpr_x3;
713 case arm64_dwarf::x4:
714 return gpr_x4;
715 case arm64_dwarf::x5:
716 return gpr_x5;
717 case arm64_dwarf::x6:
718 return gpr_x6;
719 case arm64_dwarf::x7:
720 return gpr_x7;
721 case arm64_dwarf::x8:
722 return gpr_x8;
723 case arm64_dwarf::x9:
724 return gpr_x9;
725 case arm64_dwarf::x10:
726 return gpr_x10;
727 case arm64_dwarf::x11:
728 return gpr_x11;
729 case arm64_dwarf::x12:
730 return gpr_x12;
731 case arm64_dwarf::x13:
732 return gpr_x13;
733 case arm64_dwarf::x14:
734 return gpr_x14;
735 case arm64_dwarf::x15:
736 return gpr_x15;
737 case arm64_dwarf::x16:
738 return gpr_x16;
739 case arm64_dwarf::x17:
740 return gpr_x17;
741 case arm64_dwarf::x18:
742 return gpr_x18;
743 case arm64_dwarf::x19:
744 return gpr_x19;
745 case arm64_dwarf::x20:
746 return gpr_x20;
747 case arm64_dwarf::x21:
748 return gpr_x21;
749 case arm64_dwarf::x22:
750 return gpr_x22;
751 case arm64_dwarf::x23:
752 return gpr_x23;
753 case arm64_dwarf::x24:
754 return gpr_x24;
755 case arm64_dwarf::x25:
756 return gpr_x25;
757 case arm64_dwarf::x26:
758 return gpr_x26;
759 case arm64_dwarf::x27:
760 return gpr_x27;
761 case arm64_dwarf::x28:
762 return gpr_x28;
763
764 case arm64_dwarf::fp:
765 return gpr_fp;
766 case arm64_dwarf::sp:
767 return gpr_sp;
768 case arm64_dwarf::lr:
769 return gpr_lr;
770 case arm64_dwarf::pc:
771 return gpr_pc;
772 case arm64_dwarf::cpsr:
773 return gpr_cpsr;
774
775 case arm64_dwarf::v0:
776 return fpu_v0;
777 case arm64_dwarf::v1:
778 return fpu_v1;
779 case arm64_dwarf::v2:
780 return fpu_v2;
781 case arm64_dwarf::v3:
782 return fpu_v3;
783 case arm64_dwarf::v4:
784 return fpu_v4;
785 case arm64_dwarf::v5:
786 return fpu_v5;
787 case arm64_dwarf::v6:
788 return fpu_v6;
789 case arm64_dwarf::v7:
790 return fpu_v7;
791 case arm64_dwarf::v8:
792 return fpu_v8;
793 case arm64_dwarf::v9:
794 return fpu_v9;
795 case arm64_dwarf::v10:
796 return fpu_v10;
797 case arm64_dwarf::v11:
798 return fpu_v11;
799 case arm64_dwarf::v12:
800 return fpu_v12;
801 case arm64_dwarf::v13:
802 return fpu_v13;
803 case arm64_dwarf::v14:
804 return fpu_v14;
805 case arm64_dwarf::v15:
806 return fpu_v15;
807 case arm64_dwarf::v16:
808 return fpu_v16;
809 case arm64_dwarf::v17:
810 return fpu_v17;
811 case arm64_dwarf::v18:
812 return fpu_v18;
813 case arm64_dwarf::v19:
814 return fpu_v19;
815 case arm64_dwarf::v20:
816 return fpu_v20;
817 case arm64_dwarf::v21:
818 return fpu_v21;
819 case arm64_dwarf::v22:
820 return fpu_v22;
821 case arm64_dwarf::v23:
822 return fpu_v23;
823 case arm64_dwarf::v24:
824 return fpu_v24;
825 case arm64_dwarf::v25:
826 return fpu_v25;
827 case arm64_dwarf::v26:
828 return fpu_v26;
829 case arm64_dwarf::v27:
830 return fpu_v27;
831 case arm64_dwarf::v28:
832 return fpu_v28;
833 case arm64_dwarf::v29:
834 return fpu_v29;
835 case arm64_dwarf::v30:
836 return fpu_v30;
837 case arm64_dwarf::v31:
838 return fpu_v31;
839
840 default:
841 break;
842 }
843 } else if (kind == eRegisterKindEHFrame) {
844 switch (reg) {
845 case arm64_ehframe::x0:
846 return gpr_x0;
847 case arm64_ehframe::x1:
848 return gpr_x1;
849 case arm64_ehframe::x2:
850 return gpr_x2;
851 case arm64_ehframe::x3:
852 return gpr_x3;
853 case arm64_ehframe::x4:
854 return gpr_x4;
855 case arm64_ehframe::x5:
856 return gpr_x5;
857 case arm64_ehframe::x6:
858 return gpr_x6;
859 case arm64_ehframe::x7:
860 return gpr_x7;
861 case arm64_ehframe::x8:
862 return gpr_x8;
863 case arm64_ehframe::x9:
864 return gpr_x9;
865 case arm64_ehframe::x10:
866 return gpr_x10;
867 case arm64_ehframe::x11:
868 return gpr_x11;
869 case arm64_ehframe::x12:
870 return gpr_x12;
871 case arm64_ehframe::x13:
872 return gpr_x13;
873 case arm64_ehframe::x14:
874 return gpr_x14;
875 case arm64_ehframe::x15:
876 return gpr_x15;
877 case arm64_ehframe::x16:
878 return gpr_x16;
879 case arm64_ehframe::x17:
880 return gpr_x17;
881 case arm64_ehframe::x18:
882 return gpr_x18;
883 case arm64_ehframe::x19:
884 return gpr_x19;
885 case arm64_ehframe::x20:
886 return gpr_x20;
887 case arm64_ehframe::x21:
888 return gpr_x21;
889 case arm64_ehframe::x22:
890 return gpr_x22;
891 case arm64_ehframe::x23:
892 return gpr_x23;
893 case arm64_ehframe::x24:
894 return gpr_x24;
895 case arm64_ehframe::x25:
896 return gpr_x25;
897 case arm64_ehframe::x26:
898 return gpr_x26;
899 case arm64_ehframe::x27:
900 return gpr_x27;
901 case arm64_ehframe::x28:
902 return gpr_x28;
903 case arm64_ehframe::fp:
904 return gpr_fp;
905 case arm64_ehframe::sp:
906 return gpr_sp;
907 case arm64_ehframe::lr:
908 return gpr_lr;
909 case arm64_ehframe::pc:
910 return gpr_pc;
911 case arm64_ehframe::cpsr:
912 return gpr_cpsr;
913 }
914 } else if (kind == eRegisterKindLLDB) {
915 return reg;
916 }
917 return LLDB_INVALID_REGNUM;
918 }
919
NumSupportedHardwareWatchpoints()920 uint32_t RegisterContextDarwin_arm64::NumSupportedHardwareWatchpoints() {
921 #if defined(__APPLE__) && (defined(__arm64__) || defined(__aarch64__))
922 // autodetect how many watchpoints are supported dynamically...
923 static uint32_t g_num_supported_hw_watchpoints = UINT32_MAX;
924 if (g_num_supported_hw_watchpoints == UINT32_MAX) {
925 size_t len;
926 uint32_t n = 0;
927 len = sizeof(n);
928 if (::sysctlbyname("hw.optional.watchpoint", &n, &len, NULL, 0) == 0) {
929 g_num_supported_hw_watchpoints = n;
930 }
931 }
932 return g_num_supported_hw_watchpoints;
933 #else
934 // TODO: figure out remote case here!
935 return 2;
936 #endif
937 }
938
SetHardwareWatchpoint(lldb::addr_t addr,size_t size,bool read,bool write)939 uint32_t RegisterContextDarwin_arm64::SetHardwareWatchpoint(lldb::addr_t addr,
940 size_t size,
941 bool read,
942 bool write) {
943 // if (log) log->Printf
944 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint(addr = %8.8p,
945 // size = %u, read = %u, write = %u)", addr, size, read, write);
946
947 const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints();
948
949 // Can't watch zero bytes
950 if (size == 0)
951 return LLDB_INVALID_INDEX32;
952
953 // We must watch for either read or write
954 if (!read && !write)
955 return LLDB_INVALID_INDEX32;
956
957 // Can't watch more than 4 bytes per WVR/WCR pair
958 if (size > 4)
959 return LLDB_INVALID_INDEX32;
960
961 // We can only watch up to four bytes that follow a 4 byte aligned address
962 // per watchpoint register pair. Since we have at most so we can only watch
963 // until the next 4 byte boundary and we need to make sure we can properly
964 // encode this.
965 uint32_t addr_word_offset = addr % 4;
966 // if (log) log->Printf
967 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint() -
968 // addr_word_offset = 0x%8.8x", addr_word_offset);
969
970 uint32_t byte_mask = ((1u << size) - 1u) << addr_word_offset;
971 // if (log) log->Printf
972 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint() - byte_mask =
973 // 0x%8.8x", byte_mask);
974 if (byte_mask > 0xfu)
975 return LLDB_INVALID_INDEX32;
976
977 // Read the debug state
978 int kret = ReadDBG(false);
979
980 if (kret == KERN_SUCCESS) {
981 // Check to make sure we have the needed hardware support
982 uint32_t i = 0;
983
984 for (i = 0; i < num_hw_watchpoints; ++i) {
985 if ((dbg.wcr[i] & WCR_ENABLE) == 0)
986 break; // We found an available hw breakpoint slot (in i)
987 }
988
989 // See if we found an available hw breakpoint slot above
990 if (i < num_hw_watchpoints) {
991 // Make the byte_mask into a valid Byte Address Select mask
992 uint32_t byte_address_select = byte_mask << 5;
993 // Make sure bits 1:0 are clear in our address
994 dbg.wvr[i] = addr & ~((lldb::addr_t)3);
995 dbg.wcr[i] = byte_address_select | // Which bytes that follow the IMVA
996 // that we will watch
997 S_USER | // Stop only in user mode
998 (read ? WCR_LOAD : 0) | // Stop on read access?
999 (write ? WCR_STORE : 0) | // Stop on write access?
1000 WCR_ENABLE; // Enable this watchpoint;
1001
1002 kret = WriteDBG();
1003 // if (log) log->Printf
1004 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint()
1005 // WriteDBG() => 0x%8.8x.", kret);
1006
1007 if (kret == KERN_SUCCESS)
1008 return i;
1009 } else {
1010 // if (log) log->Printf
1011 // ("RegisterContextDarwin_arm64::EnableHardwareWatchpoint():
1012 // All hardware resources (%u) are in use.",
1013 // num_hw_watchpoints);
1014 }
1015 }
1016 return LLDB_INVALID_INDEX32;
1017 }
1018
ClearHardwareWatchpoint(uint32_t hw_index)1019 bool RegisterContextDarwin_arm64::ClearHardwareWatchpoint(uint32_t hw_index) {
1020 int kret = ReadDBG(false);
1021
1022 const uint32_t num_hw_points = NumSupportedHardwareWatchpoints();
1023 if (kret == KERN_SUCCESS) {
1024 if (hw_index < num_hw_points) {
1025 dbg.wcr[hw_index] = 0;
1026 // if (log) log->Printf
1027 // ("RegisterContextDarwin_arm64::ClearHardwareWatchpoint( %u )
1028 // - WVR%u = 0x%8.8x WCR%u = 0x%8.8x",
1029 // hw_index,
1030 // hw_index,
1031 // dbg.wvr[hw_index],
1032 // hw_index,
1033 // dbg.wcr[hw_index]);
1034
1035 kret = WriteDBG();
1036
1037 if (kret == KERN_SUCCESS)
1038 return true;
1039 }
1040 }
1041 return false;
1042 }
1043